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CM2 Manual

INTRODUCTION

As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurements and simulation, communications, Ethernet switch, and SBC functions. Our CM2 combination module offers users the functionality of two COSA® smart function modules in one physical module. Based on NAI’s AR1 and DT4 modules, the CM2 module provides eight ARINC 429/575 and twelve Discrete I/O channels in a single smart function module. This user manual is designed to help you get the most out of our CM2 smart function module.

For a brief description of the module and complete list of specifications, click here for the CM2 data sheet.

CM2 Overview

NAI’s CM2 module offers a range of features designed to suit a variety of system requirements, including:

Discrete I/O (DT4 Module-Type) Features

12 Channels of Programmable Discrete Input/Output: The DT4 function features 12 channels programmable for either discrete input or output that provide the following:

Input - voltage or contact sensing with programmable, pull-up/pull-down current sources, eliminating the need for external resistors or mechanical jumpers.
Output - programmable current source (high-side), sink (low-side) or push-pull switching up to 500 mA per channel from an applied 3- 60V external VCC source (or sink to ISO-GND).

Current Sharing: The DT4 function enables current sharing* by connecting multiple outputs in parallel, capable of sinking or sourcing up to 2A per bank, enhancing your system’s capacity and reliability.

(*) Current Share: The maximum output load per-channel is ±0.5A. Channels can be connected and operated in parallel to provide > 0.5A to act as a single channel. The load current between paralleled channels cannot be effectively characterized and is not expected to be equal due to factors including:

Channel/bank position, module position, motherboard/system platform configuration, operating temperature range including external application/configuration influences (e.g., external cabling).

Therefore, when operating in shared current (parallel channel) configuration, it is recommended to de-rate the per-channel maximum current output to at least 66% (or 333 mA/channel) to ensure that no single channel is overburdened by handling most of the load current.

For example: If the maximum continuous load current is expected to be 1A: 1/0.33 ≅ 3 channels (minimum).

Inrush Current Handling: The DT4 function can efficiently handle high inrush current loads, such as connecting two #327 incandescent lamps in parallel, without compromising performance.

Dual Turn-On Application Support: The DT4 function supports 'dual turn-on' applications, such as dual series 'key' missile launch control, providing seamless control in critical operations.

Debounce Circuitry: Programmable debounce circuitry with selectable time delay eliminates false signals caused by relay contact bounce, ensuring accurate data acquisition.

Background Built-In-Test (BIT): All channels have continuous background Built-In-Test (BIT), which provides real-time channel health to ensure reliable operation in mission-critical systems. This feature runs in the background and is transparent in normal operations.

Input Diagnostics: The DT4 function can sense broken input connections and detect if inputs are shorted to +V or ground, allowing for early detection and troubleshooting.

Voltage and Current Readings: The DT4 function offers the ability to read I/O voltage and output current, facilitating improved diagnostics and load status identification (indicates if load is connected).

Enhanced Functionality Features: In addition to offering the same functionality as the DT1 standard function (SF) module, the DT4 includes the following enhanced features:

Enhanced Input Mode - Pulse Measurements, Transition Timestamps, Transition Counters, Period Measurement, and Frequency Measurement.
Enhanced Output Mode - PWM Output and Pattern Generator Output.

ARINC 429/575 (AR1 Module-Type) Features

ARINC 429: ARINC 429 is a widely adopted data transfer standard, serving as an alternative to MIL-STD-1553. It utilizes a self-clocking, self-synchronizing data bus protocol with separate transmit and receive ports. The physical connection consists of twisted pairs carrying balanced differential signaling. Each data word is 32 bits in length, with most messages containing a single data word. Messages are transmitted at either 12.5 or 100 kbps, allowing other system elements to monitor the bus messages. The transmitter continuously transmits 32-bit data words or the NULL state. A single-wire pair can accommodate one transmitter and up to 20 receivers. Notably, the receiver end of the protocol enables self-clocking, eliminating the need for transmitting clocking data.

ARINC 575: In addition to ARINC 429, the AR1 function also supports ARINC 575, a data transfer protocol specifically used for the Digital Air Data System (DADS) on commercial and transport aircraft. ARINC 575 defines a digital data bus that distributes crucial air-data information to displays, autopilots, and flight control instrumentation.

While there are minor differences between the digital data bus of ARINC 575 and ARINC 429, the most significant distinction lies in the usage of bit 32. In ARINC 429, bit 32 is reserved for parity, whereas ARINC 575 can utilize bit 32 for either parity (when using BNR encoding) or data (when using BCD encoding).

Receive/Transmit Mode Programmability: Each channel of the AR1 function can be programmed to operate in either receive or transmit mode according to your specific application needs.

Flexible Operation: The AR1 function supports both 100 kHz and 12.5 kHz operation per channel, allowing you to choose the appropriate speed for your communication requirements.

Transmit Capabilities: Enjoy the convenience of a 255 message FIFO or scheduled transmits per channel, allowing you to efficiently manage and control the transmission of messages. Additionally, asynchronous transmits can be performed alongside scheduled transmits.

Receive Capabilities: Benefit from a 255 message FIFO or mailbox buffering per channel, providing ample storage for incoming messages. This ensures reliable reception and efficient handling of data.

Message Validation: The AR1 function supports SDI/Label Filtering, enabling you to validate received messages based on specific criteria per channel. This feature enhances the overall data integrity and ensures only relevant information is processed.

Hardware Parity: You have the option to enable selectable hardware parity generation/checking, which adds an extra layer of data integrity verification during transmission and reception.

Receive Time Stamping: Gain valuable insight into message reception with the functions’s receive time stamping feature. This allows precise timing analysis and synchronization in your communication system.

Continuous Built-In Test (BIT): The AR1 function incorporates continuous BIT functionality, providing self-diagnostics and monitoring capabilities to ensure reliable operation and easy troubleshooting.

Loop-Back Test: Verify the integrity of the AR1 function by performing loop-back tests. This feature allows you to validate the communication path and confirm proper functionality.

Tri-State Outputs: The AR1 function’s outputs support tri-state functionality, allowing you to control the state of the outputs as needed. This enables seamless integration with other system components.

High and Low-Speed Slew Rate Outputs: The AR1 function offers both high and low-speed slew rate outputs, providing flexibility in meeting the requirements of various communication interfaces.

DISCRETE I/O FUNCTION

The Discrete I/O communications function is like the standard DT4 communications function module (DT4 may be used as a reference/guide within the context of this document).

Principle of Operation

The CM2 provides up to twelve (12) channels of individual digital (DT4 module-type) I/O with BIT fault detection, which enables flagging of non-compliant outputs or inconsistent input readings between dual input measurements

When channels are programmed as inputs, they can be used for either voltage or contact sensing. Channels set for contact sensing (e.g., sensing a relay contact position; OPEN-CLOSED) can be configured with a programmable “pull-up” or “pull-down” (current source or sink) which effectively provides the proper voltage level change to sense the open state of the contact. This unique design eliminates the need for external resistors or mechanical jumpers. Instead, this design offers a current source/sink (in banks of 6 channels) that the user programs to a desired current (0-5 mA) level.

When programmed as outputs, each channel can be set for high-side (current-source), low-side (current-sink) or push-pull (current-source-sink) operation. The load impedance determines the delivered switched output current drive (up to 500 mA per channel). Diode clamping is provided (useful for inductive loads, such as relays) and thermal protection.

Overcurrent protection is implemented using current sensing technology. When the current exceeds a programmed threshold of 650 mA steady-state, or a higher short duration, the overcurrent/short-circuit protection is triggered, shutting down the output drivers for safety. The overcurrent fault status will be indicated for the affected channels and will require a reset operation to restore output. To reset this condition, a reset command needs to be issued to the Overcurrent Reset register, which will restore drive output and allow the latched status to be reset. This is separate from the reset for the Overcurrent Interrupt Enable register on this module. It is recommended that a reset command is done whenever status is cleared to avoid a non-apparent output reset condition.

The 12 channels are configured as 2 banks of 6 channels. Each bank is provided with a separate external input VCC and a ground return (GND) pin. The GND pins are common within the module but are isolated from system (power) GND.

Operational requirements/assumptions:

An external source VCC supply must be wired for proper:
- Output operation as a current source.
- Input operation when requiring a programmed pull-up current (i.e., programmed “pull-up” for input contact sense; OPEN/GND detect/state change).
An external source Ground/Return must be wired for all I/O configurations. The Ground/Return must be the input signal or the load current sink ground/reference.

Input/Output Interface

Each channel can be configured as an input or one of three types of outputs.

Output

When configured as an output, the interface can act as a “High-Side”, “Low-Side” or “Push-Pull” drive, providing up to 500 mA per channel or 1 A when two channels are connected in parallel. The total output per module is 8 A (2 A per bank).

Note	Maximum source current 'rules' for rear I/O connectors still apply - see specifications.

Input

When configured as an input, output drivers are disabled. The I/O interface can act as a constant current source, current sink or voltage sensing circuit. For contact sensing, each channel may be set for pull-up or pull-down using the Select Pull-Up or Pull-Down register and by entering the appropriate current level in the Pull-Up/Down Current register. Contact closure and hysteresis may be defined using the Upper Voltage and Lower Voltage Threshold registers. No additional resistors or hardware are required to provide for current flow. A current value of zero disables the current source/sink circuits and configures the module for voltage sensing. Default is voltage sensing. Level or contact sensing can be mixed within a channel bank, if the contact sensing channels are externally pulled up or pulled down.

Note	If this module supplies the current for the contact sensing, then level and contact sensing cannot be mixed within a channel bank.

All four threshold levels must be programmed in monotonic, increasing order of: Minimum Low, Lower, Upper and Maximum High. For input and output, threshold levels define logic state. For output, threshold levels are used in BIT test (wrap-around) signal monitoring. A pair of drive FETs and current circuits are provided at each I/O pin. See the functional representation of the drivers in the I/O Circuits interface diagram below.

Input/Output Circuits

Discrete I/O Threshold Programming

Four threshold levels (Max High Voltage Threshold, Upper Voltage Threshold, Lower Voltage Threshold, and Min Low Voltage Threshold) offer maximum user flexibility. All four threshold levels must be programmed. For input or output, the threshold levels will define the logic states. For proper operation, the threshold values should be programmed such that:

Max High Voltage Threshold > Upper Voltage Threshold > Lower Voltage Threshold > Min Low Voltage Threshold

Program Upper and Lower Voltage Thresholds, keeping the 0.25 V min. differential in mind, and then add debounce time as required. When the input signal exceeds the Upper Voltage Threshold, a logic high 1 is maintained until the input signal falls below the Lower Voltage Threshold. Conversely, when the input signal falls below the Lower Voltage Threshold, a logic low 0 is maintained until the input signal rises above the Upper Voltage Threshold.

Debounce Programming

The Debounce register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Once a signal level is a logic voltage level period longer than the Debounce Time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed Debounce Time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state.

Automatic Background Built-In Test (BIT)/Diagnostic Capability

The Discrete module supports automatic background BIT testing that verifies channel processing. The testing is totally transparent to the user, requires no external programming and has no effect on the operation of the module. This capability is accomplished by an additional test comparator that is incorporated into each module. The test comparator checks each channel and is compared against the operational channel. Depending upon the configuration, the Input data read, or Output logic written of the operational channel and test comparator must agree or a fault is indicated with the results available in the associated status register. The results of the tests are stored in the BIT Dynamic Status and BIT Latched Status registers.

The technique used by the continuous background BIT (CBIT) test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. Note, the interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g., BIT faults would register when sustained; i.e., at a ten second interval, not a 10-millisecond interval). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state.

In addition to BIT, the Discrete module tests for overcurrent conditions and provides Above Max High Voltage, Below Min Low Voltage, and Mid-Range Voltage statuses for threshold signal transitioning.

Status and Interrupts

The Discrete I/O function provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

Module Common Registers

The Discrete I/O function includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

Unit Conversions

The Discrete I/O function Threshold and Measurement registers can be programmed to be utilized as a single precision floating point value (IEEE-754) or as a 32-bit integer value. The purpose for providing this feature is to offload the processing that is normally performed by the mission processor to convert the integer values to floating-point values.

When the Enable Floating Point Mode register is set to 1 (Floating Point Mode) the following registers are formatted as Single Precision Floating Point Value (IEEE-754):

Voltage Reading (Volts)
Current Reading (mA)
VCC Voltage Reading (Volts)
Max High Voltage Threshold (Volts)*
Upper Voltage Threshold (Volts)*
Lower Voltage Threshold (Volts)*
Min Low Voltage Threshold (Volts)*
Pull-Up/Down Current (mA)*

*When the Enable Floating Point Mode register is set to 1, it is important that these registers are updated with the Single Precision Floating Point (IEEE-754) representation of the value for proper operation of the channel. Conversely, when the Enable Floating Point Mode register is set to 0, these registers must be updated with the Integer 32-bit representation of the value.

Note	When changing the Enable Floating Point Mode from Integer Mode to Floating Point Mode or vice versa, the following steps are followed to avoid faults from falsely being generated:

Set the Enable Floating Point Mode register to the desired mode (Integer or Floating Point).
The application waits for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete. Data registers will be converted to the units specified and can be read in that specified format.

User Watchdog Timer Capability

The Discrete I/O function provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the Principle of Operation description.

Enhanced Functionality

The Discrete I/O function (DT4-type) provides enhanced input and output mode functionality. For incoming signals (inputs), the Discrete I/O enhanced modes include Pulse Measurements, Transition Timestamps, Transition Counters, Period Measurement and Frequency Measurement. For outputs, the Discrete I/O enhanced modes include PWM (Pulse Width Modulation) Outputs and Pattern Generator Outputs.

Refer to “Enhanced Discrete I/O, Digital I/O Functionality - Module Manual” for the Principle of Operation description.

Register Description

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Discrete Input/Output Registers

Each channel can be configured as an input or one of three types of outputs. The I/O Format registers are used to set each channel input/output configuration. The Write Outputs register controls the output channels to either a High (1) or Low (0) state, and the Read I/O register contains the discrete channel’s state (High (1) or Low (0)) as specified by the channel’s threshold configurations.

I/O Format Ch1-12

Function:

Sets channels 1-12 as inputs or outputs.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x00FF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

Write integer 0 for input; 1, 2 or 3 for specific output format.

Integer	D_H	D_L	(2 bits per channel)
0	0	0	Input
1	0	1	Output, Low-side switched, with/without current pull up
2	1	0	Output, High-side switched, with/without current pull down
3	1	1	Output, push-pull

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Ch12

Ch11

Ch10

Ch9

D15

D14

D13

D12

D11

D10

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Write Outputs

Function:

Drives output channels High 1 or Low 0

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

Write 1 to drive output high. Write 0 to drive output low.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Input/Output State

Function:

Reads High 1 or Low 0 inputs or outputs as defined by internal channel threshold values.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

Initialized Value:

N/A

Operational Settings:

Bit-mapped per channel.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Discrete Input/Output Voltage Threshold Programming Registers

Four threshold levels (Max High Voltage Threshold, Upper Voltage Threshold, Lower Voltage Threshold, and Min Low Voltage Threshold) are programmable for each Discrete channel in the module.

Max High Voltage Threshold (Enable Floating Point Mode: Integer Mode)

Upper Voltage Threshold (Enable Floating Point Mode: Integer Mode)

Lower Voltage Threshold (Enable Floating Point Mode: Integer Mode)

Min Low Voltage Threshold (Enable Floating Point Mode: Integer Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Max High Voltage Threshold (Enable Floating Point Mode: Floating Point Mode)

Upper Voltage Threshold (Enable Floating Point Mode: Floating Point Mode)

Lower Voltage Threshold (Enable Floating Point Mode: Floating Point Mode)

Min Low Voltage Threshold (Enable Floating Point Mode: Floating Point Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Max High Voltage Threshold

Function:

Sets the maximum high voltage threshold value. Programmable per channel from 0 VDC to 60 VDC.

Type:

unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)
0x0000 0000 to 0x0000 0258

Enable Floating Point Mode: 1 (Floating Point Mode)
Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

0x32

Operational Settings:

Assumes that the programmed level is the minimum voltage used to indicate a Max High Voltage Threshold. If a signal is greater than the Max High Voltage Threshold value, a flag is set in the Max High Voltage Threshold Status register. The Max High Voltage Threshold register may be used to monitor any type of high signal voltage condition or threshold such as a “Short to +V” as it applies to input measurement as well as contact sensing applications.

Integer Mode: LSB is 0.1 VDC. For example: to program 5.0 VDC, 5.0 / 0.1 = 50 (binary equivalent for 50 is 0x0000 0032).

Floating Point Mode: Set Max High Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 5.0V, enter 5.0 as a single precision floating point value (IEEE-754) (binary equivalent 5.0 is 0x40A0 0000).

Upper Voltage Threshold

Function:

Sets the upper voltage threshold value. Programmable per channel from 0 VDC to 60 VDC.

Type:

unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)
0x0000 0000 to 0x0000 0258

Enable Floating Point Mode: 1 (Floating Point Mode)
Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

0x28

Operational Settings:

A signal is considered logic High 1 when its value exceeds the Upper Voltage Threshold and does not consequently fall below the Upper Voltage Threshold in less than the programmed Debounce Time

Integer Mode: LSB is 0.1 VDC. For example: to program 3.5 VDC, 3.5 / 0.1 = 35 (binary equivalent for 35 is 0x0000 0023).

Floating Point Mode: Set Upper Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 3.5 V, enter 3.5 as a single precision floating point value (IEEE-754) (binary equivalent 3.5 is 0x4060 0000).

Lower Voltage Threshold

Function:

Sets the lower voltage threshold value. Programmable per channel from 0 VDC to 60 VDC.

Type:

unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)
0x0000 0000 to 0x0000 0258

Enable Floating Point Mode: 1 (Floating Point Mode)
Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

0x10

Operational Settings:

A signal is considered logic Low 0 when its value falls below the Lower Voltage Threshold and does not consequently rise above the Lower Voltage Threshold in less than the programmed Debounce Time.

Integer Mode: LSB is 0.1 VDC. For example: to program 1.5 VDC, 1.5 / 0.1 = 15 (binary equivalent for 15 is 0x0000 000F).

Floating Point Mode: Set Lower Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 1.5 V, enter 1.5 as a single precision floating point value (IEEE-754) (binary equivalent 1.5 is 0x3FC0 0000).

Min Low Voltage Threshold

Function:

Sets the minimum low voltage threshold. Programmable per channel 0 VDC to 60 VDC.

Type:

unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode) 0x0000 0000 to 0x0000 0258

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

0xA

Operational Settings:

Assumes that the programmed level is the voltage used to indicate a Minimum Low Voltage Threshold. If a signal is less than the Min Low Voltage Threshold value, a flag is set in the Min Low Voltage Threshold Status register. The Min Low Voltage Threshold register may be used to monitor any type of low signal voltage condition or threshold such as a “Short to Ground” as it applies to input measurement as well as contact sensing applications.

Integer Mode: LSB is 0.1 VDC. For example: to program 0.5 VDC, 0.5 / 0.1 = 5 (binary equivalent for 5 is 0x0000 0005).

Floating Point Mode: Set Min Low Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 0.5 V, enter 0.5 as a single precision floating point value (IEEE-754) (binary equivalent 0.5 is 0x3F00 0000).

Discrete Input/Output Measurement Registers

The measured voltage and current at the I/O pin for each channel can be read from the Voltage Reading and Current Reading registers.

Voltage Reading

Function:

Reads actual voltage at I/O pin per individual channel.

Type:

unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)
0x0000 0000 to 0x0000 0258

Enable Floating Point Mode: 1 (Floating Point Mode)
Single Precision Floating Point Value (IEEE-754)

Read/Write:

Initialized Value:

N/A

Operational Settings:

Integer Mode: LSB is 0.1 VDC. If the register value is 261 (binary equivalent for 261 is 0x0000 0105), conversion to the voltage value is 261 * 0.1 = 26.1 V.

Floating Point Mode: Read as a Single Precision Floating Point Value (IEEE-754). For example, if the register value is 0x41D0 CCCD, this is equivalent to is 26.1, which represent 26.1 V.

Voltage Reading (Enable Floating Point Mode: Integer Mode)``

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Voltage Reading (Enable Floating Point Mode: Floating Point Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Current Reading

Function:

Reads actual output current through I/O pin per channel.

Type:

signed binary word (32-bit (only lower 16-bit is used)) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)
(2’s compliment. 16-bit value sign extended to 32 bits)
0x0000 0000 to 0x0000 00D0 (positive) or 0x0000 FF30 (negative)

Enable Floating Point Mode: 1 (Floating Point Mode)
Single Precision Floating Point Value (IEEE-754)

Read/Write:

Initialized Value:

N/A

Operational Settings:

Integer Mode: LSB is 3.0 mA. Value is signed binary 16-bit word. Read as 2’s complement value for positive and negative current readings. For example, if the register value is 50 (binary equivalent for 50 is 0x0000 0032), the conversion to the current value is 50 * 3.0 = 150 mA. If register value is -50 (binary equivalent for -150 is 0x0000 FFCE), the conversion to the current value is -50 * 3.0 = -150 mA.

Floating Point Mode: Read as a Single Precision Floating Point Value (IEEE-754). The value will represent a positive or negative current reading. For example, if the register value is 0x4316 0000, this is equivalent to 150, which represent 150 mA. If the register value is 0xC316 0000, this is equivalent to -150, which represents -150 mA.

Current Reading (Enable Floating Point Mode: Integer Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Current Reading (Enable Floating Point Mode: Floating Point Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

VCC Bank Registers

There are two VCC banks where each bank controls 6 discrete channels. Configuration for each bank involves specifying if the bank is configured for pull-up or pull-down and the current for source/sink. The measured voltage for each VCC bank can be read from the VCC Voltage Reading register.

Select Pull-Up or Pull-Down

Function:

Configures Pull-up or Pull-down configuration per 6-channel bank

Type:

unsigned binary word (32-bit)

Data Range:

0 to 0x0000 0003

Read/Write:

R/W

Initialized Value:

Operational Settings:

Set bit to 1 to configure channel bank to Pull-up. Set bit to 0 to configure channel bank to Pull-down. Each data bit configures entire bank of 6 channels.

Note	For contact (switch closure) applications, a current supply (Vcc) is required for internal pull-up.

Bit(s)

Name

Description

D31:D2

Reserved

Set Reserved bits to 0.

Configure Bank 2 (Ch 07-12)

1=Pull-Up, 0=Pull-Down

Configure Bank 1 (Ch 01-06)

1=Pull-Up, 0=Pull-Down

Pull-Up/Down Current

Function:

Sets current for pull-up/down per 6-channel bank. Programmable from 0 to 5 mA.

Type:

unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)
0x0000 0000 to 0x0000 0032

Enable Floating Point Mode: 1 (Floating Point Mode)
Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

Operational Settings:

A current of zero disables the current pull-down circuits and configures for voltage sensing.

Integer Mode: LSB is 0.1 mA. For example: to program 5 mA, 5 / 0.1 = 50 (binary equivalent for 50 is 0x0000 0032).

Floating Point Mode: Set the current for pull-up/down as a Single Precision Floating Point Value (IEEE-754). For example, to program 5 mA, enter 5.0 as a Single Precision Floating Point Value (IEEE-754) (binary equivalent for 5.0 is 0x40A0 0000).

Pull-Up/Down Current (Enable Floating Point Mode: Integer Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Pull-Up/Down Current (Enable Floating Point Mode: Floating Point Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

VCC Voltage Reading

Function:

Read the VCC bank voltage.

Type:

unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)
0x0000 0000 to 0x0000 0258

Enable Floating Point Mode: 1 (Floating Point Mode)
Single Precision Floating Point Value (IEEE-754)

Read/Write:

Initialized Value:

N/A

Operational Settings:

Integer Mode: LSB is 0.1 VDC. If the register value is 260 (binary equivalent for this value is 0x0000 0104), conversion to the voltage value is 260 * 0.1 = 26.0 V.

Floating Point Mode: Read as a Single Precision Floating Point Value (IEEE-754). For example, the binary equivalent for 0x41D0 0000 is 26.0 which represent 26.0 V.

VCC Voltage Reading (Enable Floating Point Mode: Integer Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

VCC Voltage Reading (Enable Floating Point Mode: Floating Point Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Discrete Input/Output Control Registers

Control of the Discrete I/O channels include specifying the Debounce time for each input channel and resetting the I/O channel on an overcurrent condition.

Debounce Time

Function:

When set for inputs, the input signal will have the debounce filtering applied based on this programmed value. This is selectable for each channel.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

The Debounce Time register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Enter required Debounce Time into appropriate channel registers. LSB weight is 10 µs/bit (register may be programmed from 0x0000 0000 (debounce filter inactive) through a maximum of 0xFFFF FFFF (2^32 * 10µs). (full scale w/ 10 µs resolution). Once a signal level is a logic voltage level period longer than the debounce time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed Debounce Time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state. Enter a value of 0 to disable debounce filtering.

Overcurrent Reset

Function:

Resets disabled channels in Overcurrent Latched Status register following an overcurrent condition as measured by the Current Reading register.

Type:

unsigned binary word (32-bit)

Data Range:

0 or 1

Read/Write:

Initialized Value:

Operational Settings:

1 is written to reset disabled channels. Processor will write a 0 back to the Overcurrent Reset register when reset process is complete.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Unit Conversion Programming Registers

The Enable Floating Point register provides the ability to set the Threshold values as floating-point values and read the Voltage Reading and Current Reading registers as floating-point values. The purpose for this feature is to offload the processing that is normally performed by the mission processor to convert the integer values to floating-point values.

Enable Floating Point Mode

Function:

Sets all channels for floating point mode or integer module.

Type:

unsigned binary word (32-bit)

Data Range:

0 to 1

Read/Write:

R/W

Initialized Value:

Operational Settings:

Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode. Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Floating Point State

Function:

Indicates the state of the mode selected (Integer or Floating Point).

Type:

unsigned binary word (32-bit)

Data Range:

0 to 1

Read/Write:

Initialized Value:

Operational Settings:

Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Background BIT Threshold Programming Registers

The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The BIT Count Clear register provides the ability to reset the BIT counter used in CBIT.

Background BIT Threshold

Function:

Sets BIT Threshold value (in milliseconds) to use for all channels for BIT failure indication.

Type:

unsigned binary word (32-bit)

Data Range:

1 ms to 2^32 ms

Read/Write:

R/W

Initialized Value:

5 ms

Operational Settings:

The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module.

BIT Count Clear

Function:

Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

Initialized Value:

Operational Settings:

Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

User Watchdog Timer Programming Registers

Refer to “User Watchdog Timer Module Manual” for the Register descriptions.

Module Common Registers

Refer to “Module Common Registers Module Manual” for the register descriptions.

Status and Interrupt Registers

The Discrete I/O function provides status registers for BIT, Low-to-High Transition, High-to-Low Transition, Overcurrent, Above Max High Voltage, Below Min Low Voltage, and Mid-Range Voltage

Channel Status Enable

Function:

Determines whether to update the status for the channels. This feature can be used to “mask” status bits of unused channels in status registers that are bitmapped by channel.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF (Channel Status)

Read/Write:

R/W

Initialized Value:

0x0000 0FFF

Operational Settings:

When the bit corresponding to a given channel in the Channel Status Enable register is not enabled (0) the status will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status, Low-to-High Transition Status, High-to-Low Transition Status, Overcurrent Status, Above Max High Voltage Status, Below Min Low Voltage Status, Mid-Range Voltage and Summary Status).

Note	Background BIT will continue to run even if the Channel Status Enable is set to 0.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Note	When a BIT fault is detected, reading the Voltage Reading Error and the Driver Error register will provide additional diagnostics on the cause of the BIT fault.

BIT Status

Function:

Sets the corresponding bit associated with the channel’s BIT error.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x000F 0FFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Note	Discrete faults are detected (associated channel(s) bit set to 1) within 10 ms.

Note	BIT Status is a shared register between the AR1 and DT4 functions. Bits D11:D0 are dedicated to the DT4 function and bits D19:D12 are dedicated to the AR1 function.

BIT Dynamic Status

BIT Latched Status

BIT Interrupt Enable

BIT Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

AR1
Ch8

AR1
Ch7

AR1
Ch6

AR1
Ch5

D15

D14

D13

D12

D11

D10

AR1
Ch4

AR1
Ch3

AR1
Ch2

AR1
Ch1

DT4
Ch12

DT4
Ch11

DT4 Ch10

DT4
Ch9

DT4
Ch8

DT4
Ch7

DT4
Ch6

DT4
Ch5

DT4
Ch4

DT4
Ch3

DT4
Ch2

DT4
Ch1

Voltage Reading Error

Function:

The Voltage Reading Error register is set when a redundant voltage measurement is inconsistent with the input voltage level detected.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

Initialized Value:

Operational Settings:

1 is read when a fault is detected. 0 indicates no fault detected.

Note	Faults are detected (associated channel(s) bit set to 1) within 10 ms.

Note	Clearing the latched BIT status will also clear this error register.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Driver Error

Function:

The Driver Error register is set when the voltage reading mismatches active driver measurement and is inconsistent with the input driver level detected (Note: requires programming of thresholds).

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

Initialized Value:

Operational Settings:

1 is read when a fault is detected. 0 indicates no fault detected.

Note	Faults are detected (associated channel(s) bit set to 1) within 10 ms.

Note	Clearing the latched BIT status will also clear this error register.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Low-to-High Transition Status

There are four registers associated with the High-to-Low Transition Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Low-to-High Transition Status

Function:

Sets the corresponding bit associated with the channel’s Low-to-High Transition event.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Note	Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.

Note	Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.

Note	Transition status follows the value read by the Input/Output State register.

Low-to-High Transition Dynamic Status

Low-to-High Transition Latched Status

Low-to-High Transition Interrupt Enable

Low-to-High Transition Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

High-to-Low Transition Status

There are four registers associated with the High-to-Low Transition Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

High-to-Low Transition Status

Function:

Sets the corresponding bit associated with the channel’s High-to-Low Transition event.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Note	Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.

Note	Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 s.

Note	Transition status follows the value read by the Input/Output State register.

High-to-Low Transition Dynamic Status

High-to-Low Transition Latched Status

High-to-Low Transition Interrupt Enable

High-to-Low Transition Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Overcurrent Status

There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Overcurrent Status

Function:

Sets the corresponding bit associated with the channel’s Overcurrent error.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Note	Status is indicated (associated channel(s) bit set to 1), within 80 ms.

Note	Latched Status is indicated (associated channel(s) bit set to 1), within 80 ms.

Note	Channel(s) shut down by overcurrent sensed can be reset by writing to the Overcurrent Clear register.

Overcurrent Dynamic Status

Overcurrent Latched Status

Overcurrent Interrupt Enable

Overcurrent Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Above Max High Voltage Status

There are four registers associated with the Above Max High Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.

Above Max High Voltage Status

Function:

Sets the corresponding bit associated with the channel’s Above Max High Voltage event.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Above Max High Voltage Dynamic Status

Above Max High Voltage Latched Status

Above Max High Voltage Interrupt Enable

Above Max High Voltage Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Below Min Low Voltage Status

There are four registers associated with the Below Min Low Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.

Below Min Low Voltage Status

Function:

Sets the corresponding bit associated with the channel’s Below Min Low Voltage event.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Below Min Low Voltage Dynamic Status

Below Min Low Voltage Latched Status

Below Min Low Voltage Interrupt Enable

Below Min Low Voltage Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Mid-Range Voltage Status

There are four registers associated with the Mid-Range Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.

Mid-Range Voltage Status

Function:

Sets the corresponding bit associated with the channel’s Mid-Range Voltage error.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Note	Voltage level needs to be between the upper and lower thresholds for the debounce time for this status to assert.

Note	In the event this status is asserted, the Input/Output state will hold its previous state.

Mid-Range Voltage Dynamic Status

Mid-Range Voltage Latched Status

Mid-Range Voltage Interrupt Enable

Mid-Range Voltage Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

User Watchdog Timer Fault Status

The Discrete I/O function provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status Register descriptions.

Inter-FPGA Failure Status

Data is periodically transferred between the Lattice FPGA and the Xilinx FPGA. A CRC value is calculated and verified with each data transfer. A CRC error flag is sent from the Lattice FPGA to the Xilinx FPGA if a CRC error is detected. The Xilinx FPGA contains a counter that will increase by two when a CRC error is flagged and decremented by one when there is no CRC error. If the counter reaches ten, the Xilinx FPGA will set the Inter-FPGA Failure status bit and shut down the isolated power supply. To recover from an Inter-FPGA Failure, the module needs to be reset and re-initialized.

There are four registers associated with the Inter-FPGA Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. 0 = Normal; 0xFFF = Inter-FPGA Communication Failure. The status represents the status for

Inter-FPGA Failure Status

Function:

Sets the corresponding bit associated with the channel’s Inter-FPGA Failure error.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0FFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Inter-FPGA Failure Dynamic Status

Inter-FPGA Failure Latched Status

Inter-FPGA Failure Interrupt Enable

Inter-FPGA Failure Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Interrupt Vector and Steering

In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note	The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector

Function:

Set an identifier for the interrupt.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering

Function:

Sets where to direct the interrupt.

Type:

unsigned binary word (32-bit)

Data Range:

See table Read/Write: R/W

Initialized Value:

Operational Settings:

When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME	1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)	2
Direct Interrupt to PCIe Bus	5
Direct Interrupt to cPCI Bus	6

Enhanced Functionality Registers

Refer to “Enhanced Discrete I/O, Digital I/O Functionality - Module Manual” for the Register descriptions.

Function Register Map

KEY

Configuration/Control

Measurement/Status

DISCRETE INPUT/OUTPUT REGISTERS

NOTE: Base Address - 0x4000 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x1038

I/O Format Ch1-12

R/W

0x1000

I/O State

0x1024

Write Outputs

R/W

DISCRETE INPUT/OUTPUT THRESHOLD PROGRAMMING REGISTERS

NOTE: Base Address - 0x4000 0000

**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x20C0

Max High Voltage Threshold Ch 1**

R/W

0x20C4

Upper Voltage Threshold Ch 1**

R/W

0x2140

Max High Voltage Threshold Ch 2**

R/W

0x2144

Upper Voltage Threshold Ch 2**

R/W

0x21C0

Max High Voltage Threshold Ch 3**

R/W

0x21C4

Upper Voltage Threshold Ch 3**

R/W

0x2240

Max High Voltage Threshold Ch 4**

R/W

0x2244

Upper Voltage Threshold Ch 4**

R/W

0x22C0

Max High Voltage Threshold Ch 5**

R/W

0x22C4

Upper Voltage Threshold Ch 5**

R/W

0x2340

Max High Voltage Threshold Ch 6**

R/W

0x2344

Upper Voltage Threshold Ch 6**

R/W

0x23C0

Max High Voltage Threshold Ch 7**

R/W

0x23C4

Upper Voltage Threshold Ch 7**

R/W

0x2440

Max High Voltage Threshold Ch 8**

R/W

0x2444

Upper Voltage Threshold Ch 8**

R/W

0x24C0

Max High Voltage Threshold Ch 9**

R/W

0x24C4

Upper Voltage Threshold Ch 9**

R/W

0x2540

Max High Voltage Threshold Ch 10**

R/W

0x2544

Upper Voltage Threshold Ch 10**

R/W

0x25C0

Max High Voltage Threshold Ch 11**

R/W

0x25C4

Upper Voltage Threshold Ch 11**

R/W

0x2640

Max High Voltage Threshold Ch 12**

R/W

0x2644

Upper Voltage Threshold Ch 12**

R/W

0x20C8

Lower Voltage Threshold Ch 1**

R/W

0x20CC

Min Low Voltage Threshold Ch 1**

R/W

0x2148

Lower Voltage Threshold Ch 2**

R/W

0x214C

Min Low Voltage Threshold Ch 2**

R/W

0x21C8

Lower Voltage Threshold Ch 3**

R/W

0x21CC

Min Low Voltage Threshold Ch 3**

R/W

0x2248

Lower Voltage Threshold Ch 4**

R/W

0x224C

Min Low Voltage Threshold Ch 4**

R/W

0x22C8

Lower Voltage Threshold Ch 5**

R/W

0x22CC

Min Low Voltage Threshold Ch 5**

R/W

0x2348

Lower Voltage Threshold Ch 6**

R/W

0x234C

Min Low Voltage Threshold Ch 6**

R/W

0x23C8

Lower Voltage Threshold Ch 7**

R/W

0x23CC

Min Low Voltage Threshold Ch 7**

R/W

0x2448

Lower Voltage Threshold Ch 8**

R/W

0x244C

Min Low Voltage Threshold Ch 8**

R/W

0x24C8

Lower Voltage Threshold Ch 9**

R/W

0x24CC

Min Low Voltage Threshold Ch 9**

R/W

0x2548

Lower Voltage Threshold Ch 10**

R/W

0x254C

Min Low Voltage Threshold Ch 10**

R/W

0x25C8

Lower Voltage Threshold Ch 11**

R/W

0x25CC

Min Low Voltage Threshold Ch 11**

R/W

0x2648

Lower Voltage Threshold Ch 12**

R/W

0x264C

Min Low Voltage Threshold Ch 12**

R/W

DISCRETE INPUT/OUTPUT MEASUREMENT REGISTERS

NOTE: Base Address - 0x4000 0000

**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x20E0

Voltage Reading Ch 1**

0x20E4

Current Reading Ch 1**

0x2160

Voltage Reading Ch 2**

0x2164

Current Reading Ch 2**

0x21E0

Voltage Reading Ch 3**

0x21E4

Current Reading Ch 3**

0x2260

Voltage Reading Ch 4**

0x2264

Current Reading Ch 4**

0x22E0

Voltage Reading Ch 5**

0x22E4

Current Reading Ch 5**

0x2360

Voltage Reading Ch 6**

0x2364

Current Reading Ch 6**

0x23E0

Voltage Reading Ch 7**

0x23E4

Current Reading Ch 7**

0x2460

Voltage Reading Ch 8**

0x2464

Current Reading Ch 8**

0x24E0

Voltage Reading Ch 9**

0x24E4

Current Reading Ch 9**

0x2560

Voltage Reading Ch 10**

0x2564

Current Reading Ch 10**

0x25E0

Voltage Reading Ch 11**

0x25E4

Current Reading Ch 11**

0x2660

Voltage Reading Ch 12**

0x2664

Current Reading Ch 12**

VCC BANK REGISTERS

NOTE: Base Address - 0x4000 0000

**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x1104

Select Pullup or Pulldown

R/W

0x20D0

Pull-Up/Down Current Bank 1 (Ch1-6)**

R/W

0x20EC

VCC Voltage Reading Bank 1 (Ch 1-6)**

0x2150

Pull-Up/Down Current Bank 2 (Ch7-12)**

R/W

0x216C

VCC Voltage Reading Bank 2 (Ch 7-12)**

DISCRETE INPUT/OUTPUT CONTROL REGISTERS

NOTE: Base Address - 0x4000 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x20D4

Debounce Time Ch 1

R/W

0x2154

Debounce Time Ch 2

R/W

0x21D4

Debounce Time Ch 3

R/W

0x2254

Debounce Time Ch 4

R/W

0x22D4

Debounce Time Ch 5

R/W

0x2354

Debounce Time Ch 6

R/W

0x23D4

Debounce Time Ch 7

R/W

0x2454

Debounce Time Ch 8

R/W

0x24D4

Debounce Time Ch 9

R/W

0x2554

Debounce Time Ch 10

R/W

0x25D4

Debounce Time Ch 11

R/W

0x2654

Debounce Time Ch 12

R/W

0x1100

Overcurrent Reset

UNIT CONVERSION PROGRAMMING REGISTERS

NOTE: Base Address - 0x4000 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x02B4

Enable Floating Point

R/W

USER WATCHDOG TIMER PROGRAMMING REGISTERS

Refer to 'User Watchdog Timer Module Manual' for the User Watchdog Timer Status Function Register Map.

MODULE COMMON REGISTERS

Refer to 'Module Common Registers Module Manual' for the Module Common Registers Function Register Map.

CHANNEL STATUS REGISTER

NOTE: Base Address - 0x4000 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x02B0

Channel Status Enable

R/W

BIT REGISTERs

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).

NOTE: Base Address - 0x4000 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0800

Dynamic Status

0x0804

Latched Status*

R/W

0x0808

Interrupt Enable

R/W

0x080C

Set Edge/Level Interrupt

R/W

0x1200

Voltage Reading Error Dynamic

0x1208

Driver Error Dynamic

0x1204

Voltage Reading Error Latched*

R/W

0x120C

Driver Error Latched*

R/W

0x0248

Test Enabled

R/W

0x02AC

Power-on BIT Complete⁺⁺

0x02B8

Background BIT Threshold

R/W

0x02BC

BIT Count Clear

⁺⁺After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.

STATUS REGISTERS

NOTE: Base Address - 0x4000 0000

Low-to-High Transition

High-to-Low Transition

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0810

Dynamic Status

0x0820

Dynamic Status

0x0814

Latched Status*

R/W

0x0824

Latched Status*

R/W

0x0818

Interrupt Enable

R/W

0x0828

Interrupt Enable

R/W

0x081C

Set Edge/Level Interrupt

R/W

0x082C

Set Edge/Level Interrupt

R/W

Overcurrent

Above Max High Voltage

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0830

Dynamic Status

0x0840

Dynamic Status

0x0834

Latched Status*

R/W

0x0844

Latched Status*

R/W

0x0838

Interrupt Enable

R/W

0x0848

Interrupt Enable

R/W

0x083C

Set Edge/Level Interrupt

R/W

0x084C

Set Edge/Level Interrupt

R/W

Below Min Low Voltage

Mid-Range Voltage

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0850

Dynamic Status

0x0860

Dynamic Status

0x0854

Latched Status*

R/W

0x0864

Latched Status*

R/W

0x0858

Interrupt Enable

R/W

0x0868

Interrupt Enable

R/W

0x085C

Set Edge/Level Interrupt

R/W

0x086C

Set Edge/Level Interrupt

R/W

User Watchdog Timer Fault/Inter-FPGA Failure

The Discrete Modules provide registers that support User Watchdog Timer capability. Refer to 'Appendix C: Inboard Discrete I/O User Watchdog Timer Functionality' for the User Watchdog Timer Fault Status Function Register Map.

ENHANCED FUNCTIONALITY REGISTERS

Refer to 'Enhanced Discrete I/O, Digital I/O Functionality Module Manual' for the Function Register Map.

INTERRUPT REGISTERS

The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below. NOTE: Vector/Steering 1-7, 9, & 28 are allocated for the Discrete I/O function; vector/steering 17-24 are allocated for the ARINC Function; vector/steering 1 is shared between the two functions

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0500

Module 1 Interrupt Vector 1 - BIT

R/W

0x0600

Module 1 Interrupt Steering 1 - BIT

R/W

0x0504

Module 1 Interrupt Vector 2 - Low-High

R/W

0x0604

Module 1 Interrupt Steering 2 - Low-High

R/W

0x0508

Module 1 Interrupt Vector 3 - High-Low

R/W

0x0608

Module 1 Interrupt Steering 3 - High-Low

R/W

0x050C

Module 1 Interrupt Vector 4 - Overcurrent

R/W

0x060C

Module 1 Interrupt Steering 4 - Overcurrent

R/W

0x0510

Module 1 Interrupt Vector 5 - Max-High

R/W

0x0610

Module 1 Interrupt Steering 5 - Max-High

R/W

0x0514

Module 1 Interrupt Vector 6 - Min-Low

R/W

0x0614

Module 1 Interrupt Steering 6 - Min-Low

R/W

0x0518

Module 1 Interrupt Vector 7 - Mid Range

R/W

0x0618

Module 1 Interrupt Steering 7 - Mid Range

R/W

0x051C

Module 1 Interrupt Vector 8 - Reserved

R/W

0x061C

Module 1 Interrupt Steering 8 - Reserved

R/W

0x0520

Module 1 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x0620

Module 1 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0524 to 0x053C

Module 1 Interrupt Vector 10 to 16 - Reserved

R/W

0x0624 to 0x063C

Module 1 Interrupt Steering 10 to 16 - Reserved

R/W

0x0540

Module 1 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x0640

Module 1 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0544

Module 1 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x0644

Module 1 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0548

Module 1 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x0648

Module 1 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x054C

Module 1 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x064C

Module 1 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0550

Module 1 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x0650

Module 1 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0554

Module 1 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x0654

Module 1 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0558

Module 1 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x0658

Module 1 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x055C

Module 1 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x065C

Module 1 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0560 to 0x0568

Module 1 Interrupt Vector 25 to 27 - Reserved

R/W

0x0660 to 0x0668

Module 1 Interrupt Steering 25 to 27 - Reserved

R/W

0x056C

Module 1 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x066C

Module 1 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0570 to 0x057C

Module 1 Interrupt Vector 29 to 32 - Reserved

R/W

0x0670 to 0x067C

Module 1 Interrupt Steering 29 to 32 - Reserved

R/W

0x0700

Module 2 Interrupt Vector 1 - BIT

R/W

0x0800

Module 2 Interrupt Steering 1 - BIT

R/W

0x0704

Module 2 Interrupt Vector 2 - Low-High

R/W

0x0804

Module 2 Interrupt Steering 2 - Low-High

R/W

0x0708

Module 2 Interrupt Vector 3 - High-Low

R/W

0x0808

Module 2 Interrupt Steering 3 - High-Low

R/W

0x070C

Module 2 Interrupt Vector 4 - Overcurrent

R/W

0x080C

Module 2 Interrupt Steering 4 - Overcurrent

R/W

0x0710

Module 2 Interrupt Vector 5 - Max-High

R/W

0x0810

Module 2 Interrupt Steering 5 - Max-High

R/W

0x0714

Module 2 Interrupt Vector 6 - Min-Low

R/W

0x0814

Module 2 Interrupt Steering 6 - Min-Low

R/W

0x0718

Module 2 Interrupt Vector 7 - Mid Range

R/W

0x0818

Module 2 Interrupt Steering 7 - Mid Range

R/W

0x071C

Module 2 Interrupt Vector 8 - Reserved

R/W

0x081C

Module 2 Interrupt Steering 8 - Reserved

R/W

0x0720

Module 2 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x0820

Module 2 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0724 to 0x073C

Module 2 Interrupt Vector 10 to 16 - Reserved

R/W

0x0824 to 0x083C

Module 2 Interrupt Steering 10 to 16 - Reserved

R/W

0x0740

Module 2 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x0840

Module 2 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0744

Module 2 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x0844

Module 2 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0748

Module 2 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x0848

Module 2 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x074C

Module 2 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x084C

Module 2 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0750

Module 2 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x0850

Module 2 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0754

Module 2 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x0854

Module 2 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0758

Module 2 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x0858

Module 2 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x075C

Module 2 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x085C

Module 2 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0760 to 0x0768

Module 2 Interrupt Vector 25 to 27 - Reserved

R/W

0x0860 to 0x0868

Module 2 Interrupt Steering 25 to 27 - Reserved

R/W

0x076C

Module 2 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x086C

Module 2 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0770 to 0x077C

Module 2 Interrupt Vector 29 to 32 - Reserved

R/W

0x0870 to 0x087C

Module 2 Interrupt Steering 29 to 32 - Reserved

R/W

0x0900

Module 3 Interrupt Vector 1 - BIT

R/W

0x0A00

Module 3 Interrupt Steering 1 - BIT

R/W

0x0904

Module 3 Interrupt Vector 2 - Low-High

R/W

0x0A04

Module 3 Interrupt Steering 2 - Low-High

R/W

0x0908

Module 3 Interrupt Vector 3 - High-Low

R/W

0x0A08

Module 3 Interrupt Steering 3 - High-Low

R/W

0x090C

Module 3 Interrupt Vector 4 - Overcurrent

R/W

0x0A0C

Module 3 Interrupt Steering 4 - Overcurrent

R/W

0x0910

Module 3 Interrupt Vector 5 - Max-High

R/W

0x0A10

Module 3 Interrupt Steering 5 - Max-High

R/W

0x0914

Module 3 Interrupt Vector 6 - Min-Low

R/W

0x0A14

Module 3 Interrupt Steering 6 - Min-Low

R/W

0x0918

Module 3 Interrupt Vector 7 - Mid Range

R/W

0x0A18

Module 3 Interrupt Steering 7 - Mid Range

R/W

0x091C

Module 3 Interrupt Vector 8 - Reserved

R/W

0x0A1C

Module 3 Interrupt Steering 8 - Reserved

R/W

0x0920

Module 3 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x0A20

Module 3 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0924 to 0x093C

Module 3 Interrupt Vector 10 to 16 - Reserved

R/W

0x0A24 to 0x0A3C

Module 3 Interrupt Steering 10 to 16 - Reserved

R/W

0x0940

Module 3 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x0A40

Module 3 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0944

Module 3 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x0A44

Module 3 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0948

Module 3 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x0A48

Module 3 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x094C

Module 3 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x0A4C

Module 3 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0950

Module 3 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x0A50

Module 3 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0954

Module 3 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x0A54

Module 3 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0958

Module 3 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x0A58

Module 3 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x095C

Module 3 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x0A5C

Module 3 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0960 to 0x0968

Module 3 Interrupt Vector 25 to 27 - Reserved

R/W

0x0A60 to 0x0A68

Module 3 Interrupt Steering 25 to 27 - Reserved

R/W

0x096C

Module 3 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x0A6C

Module 3 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0970 to 0x097C

Module 3 Interrupt Vector 29 to 32 - Reserved

R/W

0x0A70 to 0x0A7C

Module 3 Interrupt Steering 29 to 32 - Reserved

R/W

0x0B00

Module 4 Interrupt Vector 1 - BIT

R/W

0x0C00

Module 4 Interrupt Steering 1 - BIT

R/W

0x0B04

Module 4 Interrupt Vector 2 - Low-High

R/W

0x0C04

Module 4 Interrupt Steering 2 - Low-High

R/W

0x0B08

Module 4 Interrupt Vector 3 - High-Low

R/W

0x0C08

Module 4 Interrupt Steering 3 - High-Low

R/W

0x0B0C

Module 4 Interrupt Vector 4 - Overcurrent

R/W

0x0C0C

Module 4 Interrupt Steering 4 - Overcurrent

R/W

0x0B10

Module 4 Interrupt Vector 5 - Max-High

R/W

0x0C10

Module 4 Interrupt Steering 5 - Max-High

R/W

0x0B14

Module 4 Interrupt Vector 6 - Min-Low

R/W

0x0C14

Module 4 Interrupt Steering 6 - Min-Low

R/W

0x0B18

Module 4 Interrupt Vector 7 - Mid Range

R/W

0x0C18

Module 4 Interrupt Steering 7 - Mid Range

R/W

0x0B1C

Module 4 Interrupt Vector 8 - Reserved

R/W

0x0C1C

Module 4 Interrupt Steering 8 - Reserved

R/W

0x0B20

Module 4 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x0C20

Module 4 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0B24 to 0x0B3C

Module 4 Interrupt Vector 10 to 16 - Reserved

R/W

0x0C24 to 0x0C3C

Module 4 Interrupt Steering 10 to 16 - Reserved

R/W

0x0B40

Module 4 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x0C40

Module 4 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0B44

Module 4 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x0C44

Module 4 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0B48

Module 4 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x0C48

Module 4 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x0B4C

Module 4 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x0C4C

Module 4 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0B50

Module 4 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x0C50

Module 4 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0B54

Module 4 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x0C54

Module 4 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0B58

Module 4 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x0C58

Module 4 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x0B5C

Module 4 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x0C5C

Module 4 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0B60 to 0x0B68

Module 4 Interrupt Vector 25 to 27 - Reserved

R/W

0x0C60 to 0x0C68

Module 4 Interrupt Steering 25 to 27 - Reserved

R/W

0x0B6C

Module 4 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x0C6C

Module 4 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0B70 to 0x0B7C

Module 4 Interrupt Vector 29 to 32 - Reserved

R/W

0x0C70 to 0x0C7C

Module 4 Interrupt Steering 29 to 32 - Reserved

R/W

0x0D00

Module 5 Interrupt Vector 1 - BIT

R/W

0x0E00

Module 5 Interrupt Steering 1 - BIT

R/W

0x0D04

Module 5 Interrupt Vector 2 - Low-High

R/W

0x0E04

Module 5 Interrupt Steering 2 - Low-High

R/W

0x0D08

Module 5 Interrupt Vector 3 - High-Low

R/W

0x0E08

Module 5 Interrupt Steering 3 - High-Low

R/W

0x0D0C

Module 5 Interrupt Vector 4 - Overcurrent

R/W

0x0E0C

Module 5 Interrupt Steering 4 - Overcurrent

R/W

0x0D10

Module 5 Interrupt Vector 5 - Max-High

R/W

0x0E10

Module 5 Interrupt Steering 5 - Max-High

R/W

0x0D14

Module 5 Interrupt Vector 6 - Min-Low

R/W

0x0E14

Module 5 Interrupt Steering 6 - Min-Low

R/W

0x0D18

Module 5 Interrupt Vector 7 - Mid Range

R/W

0x0E18

Module 5 Interrupt Steering 7 - Mid Range

R/W

0x0D1C

Module 5 Interrupt Vector 8 - Reserved

R/W

0x0E1C

Module 5 Interrupt Steering 8 - Reserved

R/W

0x0D20

Module 5 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x0E20

Module 5 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0D24 to 0x0D3C

Module 5 Interrupt Vector 10 to 16 - Reserved

R/W

0x0E24 to 0x0E3C

Module 5 Interrupt Steering 10 to 16 - Reserved

R/W

0x0D40

Module 5 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x0E40

Module 5 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0D44

Module 5 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x0E44

Module 5 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0D48

Module 5 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x0E48

Module 5 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x0D4C

Module 5 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x0E4C

Module 5 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0D50

Module 5 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x0E50

Module 5 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0D54

Module 5 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x0E54

Module 5 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0D58

Module 5 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x0E58

Module 5 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x0D5C

Module 5 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x0E5C

Module 5 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0D60 to 0x0D68

Module 5 Interrupt Vector 25 to 27 - Reserved

R/W

0x0E60 to 0x0E68

Module 5 Interrupt Steering 25 to 27 - Reserved

R/W

0x0D6C

Module 5 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x0E6C

Module 5 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0D70 to 0x0D7C

Module 5 Interrupt Vector 29 to 32 - Reserved

R/W

0x0E70 to 0x0E7C

Module 5 Interrupt Steering 29 to 32 - Reserved

R/W

0x0F00

Module 6 Interrupt Vector 1 - BIT

R/W

0x1000

Module 6 Interrupt Steering 1 - BIT

R/W

0x0F04

Module 6 Interrupt Vector 2 - Low-High

R/W

0x1004

Module 6 Interrupt Steering 2 - Low-High

R/W

0x0F08

Module 6 Interrupt Vector 3 - High-Low

R/W

0x1008

Module 6 Interrupt Steering 3 - High-Low

R/W

0x0F0C

Module 6 Interrupt Vector 4 - Overcurrent

R/W

0x100C

Module 6 Interrupt Steering 4 - Overcurrent

R/W

0x0F10

Module 6 Interrupt Vector 5 - Max-High

R/W

0x1010

Module 6 Interrupt Steering 5 - Max-High

R/W

0x0F14

Module 6 Interrupt Vector 6 - Min-Low

R/W

0x1014

Module 6 Interrupt Steering 6 - Min-Low

R/W

0x0F18

Module 6 Interrupt Vector 7 - Mid Range

R/W

0x1018

Module 6 Interrupt Steering 7 - Mid Range

R/W

0x0F1C

Module 6 Interrupt Vector 8 - Reserved

R/W

0x101C

Module 6 Interrupt Steering 8 - Reserved

R/W

0x0F20

Module 6 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x1020

Module 6 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0F24 to 0x0F3C

Module 6 Interrupt Vector 10 to 16 - Reserved

R/W

0x1024 to 0x103C

Module 6 Interrupt Steering 10 to 16 - Reserved

R/W

0x0F40

Module 6 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x1040

Module 6 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0F44

Module 6 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x1044

Module 6 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0F48

Module 6 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x1048

Module 6 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x0F4C

Module 6 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x104C

Module 6 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0F50

Module 6 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x1050

Module 6 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0F54

Module 6 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x1054

Module 6 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0F58

Module 6 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x1058

Module 6 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x0F5C

Module 6 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x105C

Module 6 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0F60 to 0x0F68

Module 6 Interrupt Vector 25 to 27 - Reserved

R/W

0x1060 to 0x1068

Module 6 Interrupt Steering 25 to 27 - Reserved

R/W

0x106C

Module 6 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x106C

Module 6 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0F70 to 0x0F7C

Module 6 Interrupt Vector 29 to 32 - Reserved

R/W

0x1070 to 0x107C

Module 6 Interrupt Steering 29 to 32 - Reserved

R/W

ARINC 429/575 FUNCTION

The ARINC 429/575 communications function is like the standard communications function module (AR1 may be used as a reference/guide within the context of this document).

Principle of Operation

The CM2 provides (8) channels of programmable ARINC-429 communication buses (AR1 module-type). Each channel is software selectable for transmit and/or receive, high or low speed, and odd or no parity. Therefore, AR1 can support multiple ARINC 429 and 575 channels simultaneously.

Receive Operation

Serial BRZ data is decoded for logic states: one, zero or null. Once Word Gap is detected (4 null states) the receiver waits for either a zero or one state to start the serial-to-parallel shift function. If a waveform timing fault is detected before the serial/parallel function is complete, operation is terminated and the receiver returns to waiting for Word Gap detection. The serial-to-parallel output data is validated for odd parity, Label and Serial-to-Digital Interface (SDI).

If message validation (filtering) is enabled, the module compares the SDI/Label of incoming ARINC messages to a list of desired SDI/Labels in validation (match) memory and only stores messages with an SDI/Label in the list. The message is stored in the receive FIFO or mailbox, depending if the channel is in FIFO receive mode or mailbox receive mode. In FIFO Receive Mode, received ARINC messages / words are stored with an associated status word and an optional time-stamp value in the channel’s receive FIFO. Additionally, the Rx FIFO can be set for either bounded or circular mode, which determines FIFO behavior when it is full. In bounded mode, newly received ARINC messages are discarded if the FIFO is full whereas in circular mode, new ARINC messages overwrite the oldest messages in the FIFO. In mailbox mode, received ARINC words are stored in mailboxes or records in RAM that are indexed by the SDI/Label of the ARINC word. Each mailbox contains a status word associated with the message, the ARINC message / word, and an optional 32-bit timestamp value. The status word indicates parity error and new message status.

Transmit Operation

Transmitters are tri-stated when TX is not enabled. Transmit operates in one of three modes: Immediate FIFO, Triggered FIFO, and Scheduled. In immediate mode, ARINC data is sent as soon as data is written to the transmit FIFO. In Triggered FIFO mode, a write to the Transmit Trigger register is needed to start transmission of the transmit FIFO contents. Transmission continues until the FIFO is empty. To transmit more data after the FIFO empties out, issue a new trigger after filling the transmit FIFO with new data.

For either FIFO mode, a transmit FIFO Rate register is provided to control rate of transmission. The contents of this register specify the gap time between transmitted words from the FIFO. The default is the minimum ARINC gap time of 4-bit times.

Schedule mode transmits ARINC data words according to a prebuilt schedule table in Transmit Schedule RAM. In the Schedule table, various commands define what messages are sent and the duration of gaps between each message. Note that a Gap (Gap or Fixed Gap) command must be explicitly added in between each Message command otherwise a gap will not be inserted between messages. The ARINC data words and gap times are stored in the Transmit Message RAM and can be updated on the fly as the schedule executes. A write to the Transmit Trigger register initiates the schedule and commands are executed starting from the first command (address 0x0) in the Schedule RAM. While a schedule is running, an ARINC word can be transmitted asynchronously by writing the async data word to the Async Transmit Data register. After it has transmitted, the Async Data Available bit will be cleared from the Channel Status register and the Async Data Sent Interrupt will be set if enabled. The Async Data Available bit in Channel Status also gets cleared by a Stop Cmd in a schedule or if a Transmit Stop command is issued from the Transmit Stop register. Use the Fixed Gap command instead of the Gap command to disable async transmissions during the schedule gap time. Gap and Fixed Gap commands can both be used when building the transmit schedule.

Schedule Transmit Commands

ARINC 429/575 scheduling is controlled by commands that are written to the Transmit Schedule RAM. The available commands are:

Message
Gap
Fixed Gap
Pause
Schedule Interrupt
Jump
Stop

Table 1. Schedule Transmit Commands
Command Name	Description
Message	This command takes a parameter that specifies the location in Transmit Message memory containing the ARINC data word to be sent. The word is transmitted when the Message command is executed. This ARINC word can be modified in Tx Message memory while the schedule is running.
Gap	This command takes a parameter that specifies the location in Transmit Message memory containing a 20-bit gap time value. Values less than 4 are invalid. If the previous command was a Message, then that message is transmitted and then the transmitter waits out the specified gap time transmitting nulls. An exception to this is if there is an async data word available. If the gap time is greater or equal to 40 bit times (4-bit gap time plus one ARINC word plus another 4-bit gap time) an async data word, if available, will be transmitted during this time. If a new async data word is made available and the remaining gap time is large enough to accommodate another async data word transmission, then the new async data word will be transmitted after a 4-bit gap time. Multiple async data word transmissions can thus occur as long as the remaining gap time is large enough to accommodate a message and the required minimum 4-bit gap time. Otherwise, the transmitter waits out the remaining gap time before executing the next command.
Fixed Gap	This command takes a parameter that specifies the location in Transmit Message memory containing a 20-bit gap time value. Values less than 4 are invalid. If the previous command was a Message, then that message is transmitted with the specified gap time appended. If the previous command was not a Message, then the transmitter waits for the specified gap time before executing the next command. The difference between the Fixed Gap and Gap command is that Fixed Gap will prevent the transmission of async data words during the gap time. Use Fixed Gap to only allow nulls to be transmitted during the gap time.
Pause	This command causes the transmitter to pause execution of the schedule after transmitting the current word. Either a Transmit Trigger command is issued to resume execution, or a Transmit Stop command is issued to halt execution.
Interrupt	This command causes the Schedule Interrupt to be set if Schedule Interrupt is enabled. An unlatched version of this flag is also visible in the channel status register
Jump	Jumps to the 9-bit address in Schedule memory pointed to by this command and resumes execution there.
Stop	This command causes the transmitter to stop execution of the schedule after transmitting the current word.

ARINC 429/575 Built-in Test

The AR1 function supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are logically ORed together and stored in the BIT Dynamic Status and BIT Latched Status registers.

Power-On Self-Test (POST) / Power-on BIT (PBIT) / Start-up BIT(SBIT)

The power-on self-test is performed on each channel automatically when power is applied and reports the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.

Continuous Background Built-In Test

The background Built-In-Test or Continuous BIT (CBIT) runs in the background for each enabled channel. In Transmit operations, internal transmit data is compared to loop-back data received by the ARINC receivers. When the channel is configured for Receive operation, receive data is continuously monitored via a secondary parallel path circuit and compared to the primary input receive data. If the data does not match, the technique used by the automatic background BIT test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state. Results of the Continuous BIT are stored in the BIT Dynamic Status and BIT Latched Status register.

Initiated Built-In Test

The Initiated Built-In-Test (IBIT) is an internal loopback available for each channel of the AR1 module. The test is initiated by setting the bit for the associated channel in the Test Enabled register to a 1. Once enabled, they must wait at least 3 msec before checking to see if the bit for the associated channel in the Test Enabled register reads a 0. When the AR1 clears the bit, it means that the test has completed, and its results can be checked. The results of the IBIT is stored in the BIT Dynamic Status and BIT Latched Status registers, a 0 indicates that the channel has passed and a 1 indicates that it failed.

Loop-Back Operation

Transmit and receive operation of an AR1 channel can be verified internally by enabling both Tx and Rx on the same channel. Tx Scheduling is not supported when the channel is placed in this mode.

Transient Protection

Transmit and receive operation of an AR1 channel can be verified internally by enabling both Tx and Rx on the same channel. Tx Scheduling is not supported when the channel is placed in this mode.

Status and Interrupts

The AR1 function of the combination module provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

Module Common Registers

The AR1 function of the combination module includes module common registers that provide access to module-level bare metal/FPGA revisions and compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for detailed information.

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Receive Registers

The registers listed are associated with data that is received on the AR1 channels. Two modes of message storage are supported: Receive FIFO and Receive Mailbox.

Receive FIFO Mode Registers

The Receive FIFO Mode Registers contain information about ARINC messages that are received via the Receive FIFO buffer on the AR1 channel. The registers associated with this feature are:

Receive FIFO Message Buffer
Receive FIFO Message Count
Receive FIFO Almost Full Threshold
Receive FIFO Size

Receive FIFO Message Buffer

Function:

In FIFO receive mode, the received ARINC messages are stored in this buffer.

Type:

unsigned binary word (32-bit)

Range:

0 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Operational Settings:

Perform two reads from this register to retrieve the Status word and the ARINC data word, respectively. If Time Stamping is enabled, perform one more read to retrieve the timestamp.

Message Status Word

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Data Word

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Timestamp Word (*if enabled)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

PE = Parity Error

1 - Calculated parity does not match the received parity bit.

N = New message

1 - Message has not been read yet.

Receive FIFO Message Count

Function:

Contains the number of ARINC messages in the receive FIFO in Receive FIFO mode.

Type:

unsigned binary word (32-bit)

Range:

0 to 255

Read/Write:

Initialized Value:

Operational Settings:

A received message consists of the message status word and the ARINC data word. If time stamping is enabled, a 32-bit timestamp is also included in the message. For example, if this register reads 1, indicating one message is loaded in the receive FIFO, perform two reads from the Receive FIFO Message Buffer register to retrieve the full message (status word and ARINC data word) if time stamping is disabled or perform three reads from the Receive FIFO Message Buffer register to retrieve the full message (status word, ARINC data word and timestamp word) if time stamping is enabled.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Receive FIFO Almost Full Threshold

Function:

Specifies the level of the receive FIFO buffer, equal or above, at which the Rx FIFO Almost Full Status bit D1 in the Channel Status register, is flagged (High True).

Type:

unsigned binary word (32-bit)

Range:

0 to 255

Read/Write:

R/W

Initialized Value:

128 (0x0080)

Operational Settings:

If the Interrupt Enable register interrupt is enabled, a SYSTEM interrupt will be generated when the receive FIFO level increases and reaches the threshold level. This register does NOT get reset by a channel reset.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Receive FIFO Size

Function:

Specifies the size of the Rx FIFO buffer. The default size is 255 messages.

Type:

unsigned binary word (32-bit)

Range:

1 to 255

Read/Write:

R/W

Initialized Value:

255 (0xFF)

Operational Settings:

This setting affects the Rx FIFO size when the Rx FIFO is configured in either Rx FIFO Bounded or Circular mode.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Receive Mailbox Mode Registers

The Receive Mailbox Mode Registers contain information about ARINC messages that are received via mailboxes on the AR1 channel. The registers associated with this feature are:

Receive FIFO SDI/Label Buffer
Receive FIFO SDI/Label Count
Receive FIFO Almost Full Threshold
Receive FIFO Size
Mailbox Status Data
Mailbox Message Data
Mailbox Timestamp Data

Receive FIFO SDI/Label Buffer

Function:

In Mailbox receive mode, SDI/Label of received messages are stored in this buffer.

Type:

unsigned binary word (32-bit)

Range:

0 to 0x0000 03FF

Read/Write:

Initialized Value:

N/A

Operational Settings:

In Mailbox receive mode, this FIFO contains the 10-bit SDI/Label of newly received messages. This provides a list to the user showing which mailboxes contain new messages since the last time this FIFO was read.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

A10

A8-A1

Label (A8 is MSB and A1 is LSB)

A10-A9

SDI

Receive FIFO SDI/Label Count

Function:

Contains the number of newly received SDI/Labels in the receive FIFO in Receive Mailbox mode.

Type:

unsigned binary word (32-bit)

Range:

0 to 255

Read/Write:

Initialized Value:

Operational Settings:

In Mailbox receive mode, this register contains the number of newly received SDI/Labels in the receive FIFO. The user may perform this number of reads on the Receive FIFO SDI/Label Buffer register to retrieve all SDI/Labels.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Receive FIFO Almost Full Threshold

Function:

Specifies the level of the receive FIFO buffer, equal or above, at which the Rx FIFO Almost Full Status bit D1 in the Channel Status register, is flagged (High True).

Type:

unsigned binary word (32-bit)

Range:

0 to 255

Read/Write:

R/W

Initialized Value:

128 (0x0080)

Operational Settings:

If the Interrupt Enable register interrupt is enabled, a SYSTEM interrupt will be generated when the receive FIFO level increases and reaches the threshold level. This register does NOT get reset by a channel reset.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Receive FIFO Size

Function:

Specifies the size of the Rx FIFO buffer. The default size is 255 SDI/Labels.

Type:

unsigned binary word (32-bit)

Range:

1 to 255

Read/Write:

R/W

Initialized Value:

255 (0xFF)

Operational Settings:

This setting affects the Rx FIFO size when the Rx FIFO is configured in either Rx FIFO Bounded or Circular mode.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Mailbox Status Data

Function:

Stores ARINC Status data word.

Type:

unsigned binary word (32-bit)

Range:

0 to 0x0000 0003

Read/Write:

Initialized Value:

Operational Settings:

This is a 32-bit value that contains status information associated with the received ARINC word. D1 of 1 indicates that the received ARINC word is a new message. D0 of 1 indicates a parity error is present in the ARINC message. There are 1024 Mailbox Status Data registers, one for each SDI/Label. The user can determine which Mailbox Status Data registers contain new data based on newly received SDI/Labels in the receive FIFO.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	N	PE

PE = Parity Error

1 - Calculated parity does not match the received parity bit.

N = New message

1 - This is a new ARINC message.

Mailbox Message Data

Function:

Stores ARINC Message data word.

Type:

unsigned binary word (32-bit)

Range:

0 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Operational Settings:

This is the 32-bit ARINC data word. There are 1024 Mailbox Message Data registers, one for each SDI/Label. The user can determine which Mailbox Message Data registers contain new data based on newly received SDI/Labels in the receive FIFO.

Mailbox Timestamp Data

Function:

Stores ARINC Timestamp data word.

Type:

unsigned binary word (32-bit)

Range:

0 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Operational Settings:

This is the 32-bit timestamp associated with the received ARINC word. There are 1024 Mailbox Timestamp Data registers, one for each SDI/Label. The user can determine which Mailbox Timestamp Data registers contain new data based on newly received SDI/Labels in the receive FIFO.

Timestamp Registers

Timestamp Control

Function:

Determines the resolution of the timestamp counter.

Type:

unsigned binary word (32-bit)

Range:

0 to 0x0000 0007

Read/Write:

R/W

Initialized Value:

0 (1 µsec)

Operational Settings:

The LSB can have one of four time values. Set bit D2 to zero out the timestamp counter.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Z	D	D

Timestamp Control Register

Bit(s)

Name

Description

D31:D3

Reserved

Set Reserved bits to 0.

Zero Timestamp

Set the bit to zero out the timestamp counter.

D1:D0

Resolution

The following sets the Resolution:

(0:0) 1 µs
(0:1) 10 µs
(1:0) 100 µs
(1:1) 1 ms

Timestamp Value

Function:

Reads the current 32-bit timestamp.

Type:

unsigned binary word (32-bit)

Range:

0 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Operational Settings:

The time value of each LSB is determined by the resolution set in the Timestamp Control register.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Message Validation Registers

Match Enable

Function:

Enables or disables reception of ARINC words containing the associated SDI/Label.

Type:

unsigned binary word (32-bit)

Range:

0 to 1

Read/Write:

R/W

Initialized Value:

Operational Settings:

D0 set to 1' enables reception of ARINC words containing the SDI/Label that is associated with the register. This register only takes effect if the MATCH ENABLE bit is set to 1 in the Channel Control Register. There are 1024 Match Enable Data Registers and each register is indexed by the SDI/Label. Note that bit D1 is a reserved bit and is fixed to 1.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	D

Transmit Registers

The registers listed are associated with data that is to be transmitted from the AR1 channels. Two modes of message storage are supported: Transmit FIFO and Transmit Scheduling.

Transmit FIFO Registers

The Transmit FIFO Mode Registers contain information about ARINC messages that are to be transmitted via the Transmit FIFO buffer on the AR1 channel. The registers associated with this feature are:

Transmit FIFO Message Buffer
Transmit FIFO Message Count
Transmit FIFO Almost Empty Threshold
Transmit FIFO Rate

Transmit FIFO Message Buffer

Function:

In immediate or triggered FIFO modes, ARINC messages are placed here prior to transmission.

Type:

unsigned binary word (32-bit)

Range:

0 to 0xFFFF FFFF

Read/Write:

Initialized Value:

N/A

Operational Settings:

ARINC data words are 32-bits. This memory is shared with the Tx Message memory and is only available in Tx FIFO modes.

Transmit FIFO Message Count

Function:

Contains the number of ARINC 32-bit words in the transmit FIFO.

Type:

unsigned binary word (32-bit)

Range:

0 to 255

Read/Write:

Initialized Value:

Operational Settings:

Used only in the FIFO transmit modes.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Transmit FIFO Almost Empty Threshold

Function:

Specifies the level of the transmit buffer, equal or below, at which the Tx FIFO Almost Empty Status bit D5 in the Channel Status register, is flagged (High True).

Type:

unsigned binary word (32-bit)

Range:

0 to 255

Read/Write:

R/W

Initialized Value:

32 decimal (0x0020)

Operational Settings:

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Transmit FIFO Rate

Function:

Determines the Gap time between transmitted ARINC messages in FIFO transmit modes.

Type:

unsigned binary word (32-bit)

Range:

0-0x000F FFFF

Read/Write:

R/W

Initialized Value:

Mode:

FIFO

Operational Settings:

Each LSB is 1 bit time. Rates less than 4 are not valid. This register does NOT get reset by a channel reset.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Transmit Scheduling Registers

The Transmit Scheduling Registers are utilized when the channel is set up to run a Transmit Schedule. The memories/registers associated with this feature are:

Transmit Schedule RAM
Transmit Message RAM
Async Transmit Data Register

Transmit Schedule RAM Command Format

Function:

The Transmit Schedule RAM consists of 256 32-bit words that are used to set up a self-running transmit schedule. These are the valid command formats for the Transmit Schedule RAM.

Type:

unsigned binary word (32-bit)

Range:

0 to 0x0000 FFFF

Read/Write:

R/W

Initialized Value:

N/A

Operational Settings:

Only bits 0 to 15 are utilized for schedule commands. Bits 12 to 15 specify the command type and bits 0 to 7 or 8 specify the command parameter. Only the Message, Gap, Fixed Gap and Jump commands utilize a command parameter. When the schedule starts, commands are executed sequentially starting from schedule RAM address 0x0.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

STOP CMD

D15

D14

D13

D12

D11

D10

FUNCTION

MA7

MA6

MA5

MA4

MA3

MA2

MA1

MA0

MESSAGE CMD¹

D15

D14

D13

D12

D11

D10

FUNCTION

MA7

MA6

MA5

MA4

MA3

MA2

MA1

MA0

GAP CMD¹

D15

D14

D13

D12

D11

D10

FUNCTION

MA7

MA6

MA5

MA4

MA3

MA2

MA1

MA0

FIXED GAP CMD¹

D15

D14

D13

D12

D11

D10

FUNCTION

PAUSE CMD

D15

D14

D13

D12

D11

D10

FUNCTION

SCH INTERRUPT CMD

D15

D14

D13

D12

D11

D10

FUNCTION

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

JUMP CMD²

D15

D14

D13

D12

D11

D10

FUNCTION

RESERVED

D15

D14

D13

D12

D11

D10

FUNCTION

RESERVED

¹ MA7-MA0

Address of Tx Message memory organized as 256 x 32.

² SA8-SA0

Address of next command in Tx Schedule memory organized as 256 x 32.

Transmit Message RAM Data Format

Function:

The Transmit Message RAM consists of 256 32-bit words that are used by the transmit schedule for ARINC message and gap time word storage.

Type:

unsigned binary word (32-bit)

Range:

0 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

N/A

Operational Settings:

Words that are stored in Transmit Message RAM are utilized by Message, Gap, and Fixed Gap commands in the Transmit Schedule. In the case of Message commands, the command parameter specifies an address in Transmit Message RAM that contains the 32-bit ARINC message to transmit. In the case of Gap or Fixed Gap commands, the command parameter specifies an address in Transmit Message RAM that contains the gap time value.

Async Transmit Data

Function:

This memory location is the transmit async buffer.

Type:

unsigned binary word (32-bit)

Range:

0 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

While a schedule is running, a single 32-bit ARINC message that is intended to be transmitted asynchronously must be written to this register. When an async data word is written to this register, the Async Data Available status bit will get set until the async data word is transmitted. If a gap (not fixed gap) time is greater or equal to 40 bit times (4-bit gap time plus one ARINC word plus another 4-bit gap time) the async data word, if available, will be transmitted during this time.

Transmit Control Registers

Control of the transmission of ARINC messages includes the ability to start/resume, pause and stop the transmission of the message.

Transmit Trigger

Function:

Sends a trigger command to the transmitter and is used to start transmission in Triggered FIFO or Scheduled Transmit modes.

Type:

unsigned binary word (32-bit)

Range:

0 to 0x0000 0FFF

Read/Write:

Initialized Value:

Operational Settings:

Set bit to 1 for the channel to resume transmission after a scheduled pause or Transmit pause command.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Transmit Pause

Function:

Sends a command to pause the transmitter after the current word and gap time has finished transmitting.

Type:

unsigned binary word (32-bit)

Range:

0 to 0x0000 0FFF

Read/Write:

Initialized Value:

Modes Affected:

Triggered FIFO and Schedule Transmit

Operational Settings:

Set bit to 1 for the channel to pause transmission in Triggered FIFO or Scheduled Transmit modes. Issue a Transmit Trigger command to resume transmission or issue a Transmit Stop command to halt transmission.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Transmit Stop

Function:

Sends a command to stop the transmitter after the current word and gap time has been transmitted.

Type:

unsigned binary word (32-bit)

Range:

0 to 0x0000 0FFF

Read/Write:

Initialized Value:

Modes Affected:

All Transmit modes

Operational Settings:

Set bit to 1 for the channel to stop transmission.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Control Registers

The AR1 function control registers provide the ability to reset all the channels in the AR1 module and configuring and controlling individual AR1 channels.

Channel Control

Function:

Used to configure and control the channels.

Type:

unsigned binary word (32-bit)

Range:

See table

Read/Write:

R/W

Initialized Value:

Operational Settings:

When writing to this register, the configuration bits must be maintained when setting the control bits.

Bit(s)

CONTROL FUNCTIONS

Description

D31:D22

RESERVED

Set RESERVED bits to 0.

D21

SCHEDULE INTERRUPT CLEAR

When the SCHEDULE INTERRUPT CLEAR bit is set to 1 by the user, the Schedule Interrupt bit (D10) in the Channel Status register can be cleared.

D20

RESERVED

Set RESERVED bits to 0.

D19

CHANNEL RESET

When the CHANNEL RESET bit is set to 1 by the user, the channel is held in reset until the user sets the bit to 0. The channel reset causes Tx and Rx FIFO buffers to clear out but channel configuration settings remain unchanged.

D18

MATCH MEMORY CLEAR

When the MATCH MEMORY CLEAR bit is set to 1 by the user and if MATCH ENABLE bit is set to 1, all 1024 SDI/Labels will be disabled in Rx Match Memory, which means all received ARINC messages will be filtered out and discarded. This is a self-clearing bit. After setting the bit, allow 100 us to complete.

D17

RECEIVE FIFO CLEAR

When the RECEIVE FIFO CLEAR bit is set to 1 then set to 0 by the user, the Rx FIFO buffer is cleared out and the Rx FIFO count goes to zero.

D16

TRANSMIT FIFO CLEAR

When the TRANSMIT FIFO CLEAR bit is set to 1 then set to 0 by the user, the Tx FIFO buffer is cleared out and the Tx FIFO count goes to zero.

Bit(s)

CONFIGURATION FUNCTIONS

Description/Values

D15:D11

RESERVED

Set RESERVED bits to 0.

D10

STORE ON ERROR DISABLE

If the STORE ON ERROR DISABLE bit is cleared (0) and odd parity is enabled, received words that contain a parity error will be stored in the receive buffer or mailbox.

When the STORE ON ERROR DISABLE bit is set (1) and odd parity is enabled, received words that contain a parity error will NOT be stored in the receive buffer or mailbox.

RESERVED

Set RESERVED bits to 0.

TIMESTAMP ENABLE

When TIMESTAMP ENABLE bit is set to 1, the receiver will store a 32-bit time stamp value along with the received ARINC word. There is one time stamp counter per module, and it is used across all 8 channels. It has 4 selectable resolutions and can be reset via the Time Stamp Control register. It is recommended to clear the Receive FIFOs whenever the Receive mode or Time Stamp Enable mode is changed to ensure that extraneous data is not leftover from a previous receive operation.

MATCH ENABLE

When the MATCH ENABLE bit is set to 1, the receiver will only store ARINC words which match the SDI/Labels enabled in Rx Match memory.

PARITY DISABLE

The PARITY DISABLE bit when set to 0, causes ARINC bit 32 to be treated as an odd parity bit. The transmitter calculates the ARINC odd parity bit and transmits it as bit 32. The receiver will check the received ARINC word for odd parity and will flag an error if is not. When the PARITY DISABLE bit is set to 1, parity generation and checking will be disabled, and both the transmitter and receiver will treat ARINC bit 32 as data and pass it on unchanged.

HIGH SPEED

The HIGH SPEED bit is used to select the data rate.

12.5 kHz = 0
100 kHz = 1

D4:D3

TRANSMIT MODE

The TRANSMIT MODE bits are used to select the Transmit Mode.

(0:0) = Immediate FIFO mode
(0:1) = Schedule mode
(1:0) = Triggered FIFO mode
(1:1) = Invalid mode

TRANSMIT ENABLE

The TRANSMIT ENABLE bit should be set after all transmit parameters have been set up. This is especially important in Immediate FIFO Transmit mode since this mode will start transmitting as soon as data is put into the Tx FIFO.

RECEIVE MODE

The RECEIVE MODE bit is used to select the storage mode (FIFO or Mailbox) of received messages.

FIFO = 0
MBOX = 1

RECEIVER ENABLE

The RECEIVER ENABLE bit should be set after all receive parameters and filters have been set up. After setting this bit, the module will look for a minimum 4-bit gap time before decoding any ARINC bits to prevent it from receiving a partial ARINC word.

Module Reset

Function:

Sends a command to reset the entire 12-channel module to power up conditions.

Type:

unsigned binary word (32-bit)

Range:

0 or 1

Read/Write:

Initialized Value:

Operational Settings:

All FIFOs are cleared. However, it does not clear out any memories. Set D0 to 1 to reset the module then set to 0 to bring it out of reset.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1

ARINC 429/575 Test Registers

The AR1 function provides the ability to run an initiated test (IBIT). Writing a 1 to the bit associated with the channel in the Test Enabled register.

Test Enabled

Function:

Set the bit corresponding to the channel you want to run Initiated Built-In-Test.

Type:

unsigned binary word (32-bit)

Data Range:

0 to 0x0000 0FFF

Read/Write:

R/W

Initialized Value:

0x0

Operational Settings:

Set bit to 1 for channel to run an Initiated BIT test. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects failures. Bit is self-clearing and does so upon completion of the test. Allow at least 3 ms per channel for the test enabled bits to clear after enabling. Note that running Initiated BIT test on a channel will interrupt operation of the channel and all FIFOs will get cleared. The system implementation should take this behavior into consideration.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Background BIT Threshold Programming Registers

The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The Reset BIT register provides the ability to reset the BIT counter used in CBIT.

Background BIT Threshold

Function:

Sets background BIT Threshold value to use for all channels for BIT failure indication.

Data Range:

1 to 65,535

Read/Write:

R/W

Initialized Value:

Operational Settings:

This value represents the background BIT error “count” that, when surpassed, will cause the BIT status to indicate failure.

BIT Count Clear

Function:

Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.

Type:

unsigned binary word (32-bit)

Data Range:

0 to 0x0000 0FFF

Read/Write:

Initialized Value:

Operational Settings:

Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Module Common Registers

Refer to “Module Common Registers Module Manual” for the register descriptions.

Status and Interrupt Registers

The AR1 function provides status registers for BIT and Channel.

Channel Status Enable

Function:

Determines whether to update the status for the channels. Does NOT prevent BIT from executing; only prevents the update of results to the status registers. This feature can be used to “mask” status bit updates of unused channels in status registers that are bitmapped by channel.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 00FF (Channel Status)

Read/Write:

R/W

Initialized Value:

0x0000 00FF

Operational Settings:

When the bit corresponding to a given channel in the Channel Status Enabled register is not enabled (0) the status update will be masked. This applies to all statuses that are bitmapped by channel (BIT Status and Summary Status).

Note	Background BIT will continue to run even if the Channel Status Enabled is set to 0.

Note	If latched status has been set for any channel bit, disabling the channel status update will NOT clear the latched status bit. To clear latched bits and disable their status updates, follow these steps:

Disable channels in Channel Status Enable register.
Read the Latched Status register.
Clear the Latched Status register with the value read from step 2.
Read the Latched Status register; should not read any errors (0) on channels that have been disabled.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

BIT Status

Function:

Sets the corresponding bit associated with the channel’s BIT register.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x000F FFFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Note	BIT Status is a shared register between the AR1 and DT4 functions. Bits D11:D0 are dedicated to the DT4 functions and bits D19:D12 are dedicated to the AR1 function.

BIT Dynamic Status

BIT Latched Status

BIT Interrupt Enable

BIT Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

AR1
Ch8

AR1
Ch7

AR1
Ch6

AR1
Ch5

D15

D14

D13

D12

D11

D10

AR1
Ch4

AR1
Ch3

AR1
Ch2

AR1
Ch1

DT4
Ch12

DT4
Ch11

DT4 Ch10

DT4
Ch9

DT4
Ch8

DT4
Ch7

DT4
Ch6

DT4
Ch5

DT4
Ch4

DT4
Ch3

DT4
Ch2

DT4
Ch1

Channel Status

There are four registers associated with the Channel Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Use this register to read current or real-time status. The Built-In-Test Error bit is latched and will stay set once an error is detected. It can be cleared by reading the BIT Status register. The Schedule Interrupt bit can be cleared by reading the Interrupt Status register when enabled or it can be cleared via the Channel Control register. See specific registers for function description and programming.

The Rx Data Available bit is set when the receive FIFO is not empty. The Rx FIFO Overflow bit will set whenever the receiver must discard data because the receive FIFO was full and new data was received. The Async Data Available bit in Channel Status also gets cleared by a Stop Cmd in a schedule or if a Transmit Stop command is issued from the Transmit Stop register. The Tx Run bit is set whenever the transmitter is executing a schedule or actively transmitting the contents of the transmit FIFO. The Tx Pause bit is set whenever the transmitter has been paused in schedule mode. Some events are NOT latched. They are dynamic.

Channel Status

Function:

Sets the corresponding bit associated with the event type. There are separate registers for each channel.

Function:

Sets the corresponding bit associated with the event type. There are separate registers for each channel.

Type:

unsigned binary word (32-bit)

Range:

0 to 0x0000 3FFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

N/A

Channel Dynamic Status

Channel Latched Status

Channel Interrupt Enable

Channel Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Bit

Description

Configurable?

Configuration Register

Rx Data Available

Rx FIFO Almost Full

Yes

Receive FIFO Almost Full Threshold

Rx FIFO Full

Yes

Receive FIFO Size

Rx FIFO Overflow

Yes

Receive FIFO Size

Tx FIFO Empty

Tx FIFO Almost Empty

Yes

Transmit FIFO Almost Empty Threshold

Tx FIFO Full

Parity Error

Receive Error

Built-in-Test Error

D10

Schedule Interrupt

D11

Async Data Available

D12

Tx Run

D13

Tx Pause

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note	The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector

Function:

Set an identifier for the interrupt.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering

Function:

Sets where to direct the interrupt.

Type:

unsigned binary word (32-bit)

Data Range:

See table Read/Write: R/W

Initialized Value:

Operational Settings:

When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME	1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)	2
Direct Interrupt to PCIe Bus	5
Direct Interrupt to cPCI Bus	6

Function Register Map

KEY

Configuration/Control

Status

Incoming Data

Outgoing Data

RECEIVE FIFO MODE REGISTERS

NOTE: Base Address - 0x4010 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x1104

Receive FIFO Message Buffer Ch 1

0x1110

Receive FIFO Message Count Ch 1

0x1204

Receive FIFO Message Buffer Ch 2

0x1210

Receive FIFO Message Count Ch 2

0x1304

Receive FIFO Message Buffer Ch 3

0x1310

Receive FIFO Message Count Ch 3

0x1404

Receive FIFO Message Buffer Ch 4

0x1410

Receive FIFO Message Count Ch 4

0x1504

Receive FIFO Message Buffer Ch 5

0x1510

Receive FIFO Message Count Ch 5

0x1604

Receive FIFO Message Buffer Ch 6

0x1610

Receive FIFO Message Count Ch 6

0x1704

Receive FIFO Message Buffer Ch 7

0x1710

Receive FIFO Message Count Ch 7

0x1804

Receive FIFO Message Buffer Ch 8

0x1810

Receive FIFO Message Count Ch 8

0x1108

Receive FIFO Almost Full Threshold Ch 1

R/W

0x1124

Receive FIFO Size Ch 1

R/W

0x1208

Receive FIFO Almost Full Threshold Ch 2

R/W

0x1224

Receive FIFO Size Ch 2

R/W

0x1308

Receive FIFO Almost Full Threshold Ch 3

R/W

0x1324

Receive FIFO Size Ch 3

R/W

0x1408

Receive FIFO Almost Full Threshold Ch 4

R/W

0x1424

Receive FIFO Size Ch 4

R/W

0x1508

Receive FIFO Almost Full Threshold Ch 5

R/W

0x1524

Receive FIFO Size Ch 5

R/W

0x1608

Receive FIFO Almost Full Threshold Ch 6

R/W

0x1624

Receive FIFO Size Ch 6

R/W

0x1708

Receive FIFO Almost Full Threshold Ch 7

R/W

0x1724

Receive FIFO Size Ch 7

R/W

0x1808

Receive FIFO Almost Full Threshold Ch 8

R/W

0x1824

Receive FIFO Size Ch 8

R/W

RECEIVE MAILBOX MODE REGISTERS

NOTE: Base Address - 0x4010 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x1104

Receive FIFO SDI/Label Buffer Ch 1

0x1110

Receive FIFO SDI/Label Count Ch 1

0x1204

Receive FIFO SDI/Label Buffer Ch 2

0x1210

Receive FIFO SDI/Label Count Ch 2

0x1304

Receive FIFO SDI/Label Buffer Ch 3

0x1310

Receive FIFO SDI/Label Count Ch 3

0x1404

Receive FIFO SDI/Label Buffer Ch 4

0x1410

Receive FIFO SDI/Label Count Ch 4

0x1504

Receive FIFO SDI/Label Buffer Ch 5

0x1510

Receive FIFO SDI/Label Count Ch 5

0x1604

Receive FIFO SDI/Label Buffer Ch 6

0x1610

Receive FIFO SDI/Label Count Ch 6

0x1704

Receive FIFO SDI/Label Buffer Ch 7

0x1710

Receive FIFO SDI/Label Count Ch 7

0x1804

Receive FIFO SDI/Label Buffer Ch 8

0x1810

Receive FIFO SDI/Label Count Ch 8

0x1108

Receive FIFO Almost Full Threshold Ch 1

R/W

0x1124

Receive FIFO Size Ch 1

R/W

0x1208

Receive FIFO Almost Full Threshold Ch 2

R/W

0x1224

Receive FIFO Size Ch 2

R/W

0x1308

Receive FIFO Almost Full Threshold Ch 3

R/W

0x1324

Receive FIFO Size Ch 3

R/W

0x1408

Receive FIFO Almost Full Threshold Ch 4

R/W

0x1424

Receive FIFO Size Ch 4

R/W

0x1508

Receive FIFO Almost Full Threshold Ch 5

R/W

0x1524

Receive FIFO Size Ch 5

R/W

0x1608

Receive FIFO Almost Full Threshold Ch 6

R/W

0x1624

Receive FIFO Size Ch 6

R/W

0x1708

Receive FIFO Almost Full Threshold Ch 7

R/W

0x1724

Receive FIFO Size Ch 7

R/W

0x1808

Receive FIFO Almost Full Threshold Ch 8

R/W

0x1824

Receive FIFO Size Ch 8

R/W

CM2 Arinc img01

TIMESTAMP REGISTERS

NOTE: Base Address - 0x4010 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x100C

Timestamp Control

R/W

0x1010

Timestamp Value

MESSAGE VALIDATION REGISTERS

CM2 Arinc img02

TRANSMIT FIFO REGISTERS

NOTE: Base Address - 0x4010 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x1100

Transmit FIFO Message Buffer Ch 1

0x1114

Transmit FIFO Message Count Ch 1

0x1200

Transmit FIFO Message Buffer Ch 2

0x1214

Transmit FIFO Message Count Ch 2

0x1300

Transmit FIFO Message Buffer Ch 3

0x1314

Transmit FIFO Message Count Ch 3

0x1400

Transmit FIFO Message Buffer Ch 4

0x1414

Transmit FIFO Message Count Ch 4

0x1500

Transmit FIFO Message Buffer Ch 5

0x1514

Transmit FIFO Message Count Ch 5

0x1600

Transmit FIFO Message Buffer Ch 6

0x1614

Transmit FIFO Message Count Ch 6

0x1700

Transmit FIFO Message Buffer Ch 7

0x1714

Transmit FIFO Message Count Ch 7

0x1800

Transmit FIFO Message Buffer Ch 8

0x1814

Transmit FIFO Message Count Ch 8

0x110C

Transmit FIFO Almost Empty Threshold Ch 1

R/W

0x111C

Transmit FIFO Rate Ch 1

R/W

0x120C

Transmit FIFO Almost Empty Threshold Ch 2

R/W

0x121C

Transmit FIFO Rate Ch 2

R/W

0x130C

Transmit FIFO Almost Empty Threshold Ch 3

R/W

0x131C

Transmit FIFO Rate Ch 3

R/W

0x140C

Transmit FIFO Almost Empty Threshold Ch 4

R/W

0x141C

Transmit FIFO Rate Ch 4

R/W

0x150C

Transmit FIFO Almost Empty Threshold Ch 5

R/W

0x151C

Transmit FIFO Rate Ch 5

R/W

0x160C

Transmit FIFO Almost Empty Threshold Ch 6

R/W

0x161C

Transmit FIFO Rate Ch 6

R/W

0x170C

Transmit FIFO Almost Empty Threshold Ch 7

R/W

0x171C

Transmit FIFO Rate Ch 7

R/W

0x180C

Transmit FIFO Almost Empty Threshold Ch 8

R/W

0x181C

Transmit FIFO Rate Ch 8

R/W

TRANSMIT SCHEDULING REGISTERS

NOTE: Base Address - 0x4010 0000

CM2 Arinc img03

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x1120

Async Transmit Data Ch 1

R/W

0x1220

Async Transmit Data Ch 2

R/W

0x1320

Async Transmit Data Ch 3

R/W

0x1420

Async Transmit Data Ch 4

R/W

0x1520

Async Transmit Data Ch 5

R/W

0x1620

Async Transmit Data Ch 6

R/W

0x1720

Async Transmit Data Ch 7

R/W

0x1820

Async Transmit Data Ch 8

R/W

TRANSMIT CONTROL REGISTERS

NOTE: Base Address - 0x4010 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x1000

Tx Trigger

R/W

0x1004

Tx Pause

R/W

0x1008

Tx Stop

R/W

CONTROL REGISTERS

NOTE: Base Address - 0x4010 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x1118

Channel Control Ch 1

R/W

0x1014

Module Reset

0x1218

Channel Control Ch 2

R/W

0x1318

Channel Control Ch 3

R/W

0x1418

Channel Control Ch 4

R/W

0x1158

Channel Control Ch 5

R/W

0x1618

Channel Control Ch 6

R/W

0x1718

Channel Control Ch 7

R/W

0x1818

Channel Control Ch 8

R/W

BIT REGISTERS

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a '1' back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).

NOTE: Base Address - 0x4010 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0800

Dynamic Status

0x0804

Latched Status*

R/W

0x0808

Interrupt Enable

R/W

0x080C

Set Edge/Level Interrupt

R/W

NOTE: Base Address - 0x4010 0000

0x02B8

Background BIT Threshold

R/W

0x02BC

BIT Count Clear

CHANNEL STATUS REGISTERS

NOTE: Base Address - 0x4010 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x02B0

Channel Status Enable

R/W

NOTE: Base Address - 0x4010 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0870

Dynamic Status Ch 1

0x0880

Dynamic Status Ch 2

0x0874

Latched Status Ch 1*

R/W

0x0884

Latched Status Ch 2*

R/W

0x0878

Interrupt Enable Ch 1

R/W

0x0888

Interrupt Enable Ch 2

R/W

0x087C

Set Edge/Level Interrupt Ch 1

R/W

0x088C

Set Edge/Level Interrupt Ch 2

R/W

0x0890

Dynamic Status Ch 3

0x08A0

Dynamic Status Ch 4

0x0894

Latched Status Ch 3*

R/W

0x08A4

Latched Status Ch 4*

R/W

0x0898

Interrupt Enable Ch 3

R/W

0x08A8

Interrupt Enable Ch 4

R/W

0x089C

Set Edge/Level Interrupt Ch 3

R/W

0x08AC

Set Edge/Level Interrupt Ch 4

R/W

0x08B0

Dynamic Status Ch 5

0x08C0

Dynamic Status Ch 6

0x08B4

Latched Status Ch 5*

R/W

0x08C4

Latched Status Ch 6*

R/W

0x08B8

Interrupt Enable Ch 5

R/W

0x08C8

Interrupt Enable Ch 6

R/W

0x08BC

Set Edge/Level Interrupt Ch 5

R/W

0x08CC

Set Edge/Level Interrupt Ch 6

R/W

0x08D0

Dynamic Status Ch 7

0x08E0

Dynamic Status Ch 8

0x08D4

Latched Status Ch 7*

R/W

0x08E4

Latched Status Ch 8*

R/W

0x08D8

Interrupt Enable Ch 7

R/W

0x08E8

Interrupt Enable Ch 8

R/W

0x08DC

Set Edge/Level Interrupt Ch 7

R/W

0x08EC

Set Edge/Level Interrupt Ch 8

R/W

INTERRUPT REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0500

Module 1 Interrupt Vector 1 - BIT

R/W

0x0600

Module 1 Interrupt Steering 1 - BIT

R/W

0x0504

Module 1 Interrupt Vector 2 - Low-High

R/W

0x0604

Module 1 Interrupt Steering 2 - Low-High

R/W

0x0508

Module 1 Interrupt Vector 3 - High-Low

R/W

0x0608

Module 1 Interrupt Steering 3 - High-Low

R/W

0x050C

Module 1 Interrupt Vector 4 - Overcurrent

R/W

0x060C

Module 1 Interrupt Steering 4 - Overcurrent

R/W

0x0510

Module 1 Interrupt Vector 5 - Max-High

R/W

0x0610

Module 1 Interrupt Steering 5 - Max-High

R/W

0x0514

Module 1 Interrupt Vector 6 - Min-Low

R/W

0x0614

Module 1 Interrupt Steering 6 - Min-Low

R/W

0x0518

Module 1 Interrupt Vector 7 - Mid Range

R/W

0x0618

Module 1 Interrupt Steering 7 - Mid Range

R/W

0x051C

Module 1 Interrupt Vector 8 - Reserved

R/W

0x061C

Module 1 Interrupt Steering 8 - Reserved

R/W

0x0520

Module 1 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x0620

Module 1 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0524 to 0x053C

Module 1 Interrupt Vector 10 to 16 - Reserved

R/W

0x0624 to 0x063C

Module 1 Interrupt Steering 10 to 16 - Reserved

R/W

0x0540

Module 1 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x0640

Module 1 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0544

Module 1 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x0644

Module 1 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0548

Module 1 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x0648

Module 1 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x054C

Module 1 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x064C

Module 1 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0550

Module 1 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x0650

Module 1 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0554

Module 1 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x0654

Module 1 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0558

Module 1 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x0658

Module 1 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x055C

Module 1 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x065C

Module 1 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0560 to 0x0568

Module 1 Interrupt Vector 25 to 27 - Reserved

R/W

0x0660 to 0x0668

Module 1 Interrupt Steering 25 to 27 - Reserved

R/W

0x056C

Module 1 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x066C

Module 1 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0570 to 0x057C

Module 1 Interrupt Vector 29 to 32 - Reserved

R/W

0x0670 to 0x067C

Module 1 Interrupt Steering 29 to 32 - Reserved

R/W

0x0700

Module 2 Interrupt Vector 1 - BIT

R/W

0x0800

Module 2 Interrupt Steering 1 - BIT

R/W

0x0704

Module 2 Interrupt Vector 2 - Low-High

R/W

0x0804

Module 2 Interrupt Steering 2 - Low-High

R/W

0x0708

Module 2 Interrupt Vector 3 - High-Low

R/W

0x0808

Module 2 Interrupt Steering 3 - High-Low

R/W

0x070C

Module 2 Interrupt Vector 4 - Overcurrent

R/W

0x080C

Module 2 Interrupt Steering 4 - Overcurrent

R/W

0x0710

Module 2 Interrupt Vector 5 - Max-High

R/W

0x0810

Module 2 Interrupt Steering 5 - Max-High

R/W

0x0714

Module 2 Interrupt Vector 6 - Min-Low

R/W

0x0814

Module 2 Interrupt Steering 6 - Min-Low

R/W

0x0718

Module 2 Interrupt Vector 7 - Mid Range

R/W

0x0818

Module 2 Interrupt Steering 7 - Mid Range

R/W

0x071C

Module 2 Interrupt Vector 8 - Reserved

R/W

0x081C

Module 2 Interrupt Steering 8 - Reserved

R/W

0x0720

Module 2 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x0820

Module 2 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0724 to 0x073C

Module 2 Interrupt Vector 10 to 16 - Reserved

R/W

0x0824 to 0x083C

Module 2 Interrupt Steering 10 to 16 - Reserved

R/W

0x0740

Module 2 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x0840

Module 2 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0744

Module 2 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x0844

Module 2 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0748

Module 2 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x0848

Module 2 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x074C

Module 2 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x084C

Module 2 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0750

Module 2 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x0850

Module 2 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0754

Module 2 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x0854

Module 2 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0758

Module 2 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x0858

Module 2 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x075C

Module 2 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x085C

Module 2 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0760 to 0x0768

Module 2 Interrupt Vector 25 to 27 - Reserved

R/W

0x0860 to 0x0868

Module 2 Interrupt Steering 25 to 27 - Reserved

R/W

0x076C

Module 2 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x086C

Module 2 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0770 to 0x077C

Module 2 Interrupt Vector 29 to 32 - Reserved

R/W

0x0870 to 0x087C

Module 2 Interrupt Steering 29 to 32 - Reserved

R/W

0x0900

Module 3 Interrupt Vector 1 - BIT

R/W

0x0A00

Module 3 Interrupt Steering 1 - BIT

R/W

0x0904

Module 3 Interrupt Vector 2 - Low-High

R/W

0x0A04

Module 3 Interrupt Steering 2 - Low-High

R/W

0x0908

Module 3 Interrupt Vector 3 - High-Low

R/W

0x0A08

Module 3 Interrupt Steering 3 - High-Low

R/W

0x090C

Module 3 Interrupt Vector 4 - Overcurrent

R/W

0x0A0C

Module 3 Interrupt Steering 4 - Overcurrent

R/W

0x0910

Module 3 Interrupt Vector 5 - Max-High

R/W

0x0A10

Module 3 Interrupt Steering 5 - Max-High

R/W

0x0914

Module 3 Interrupt Vector 6 - Min-Low

R/W

0x0A14

Module 3 Interrupt Steering 6 - Min-Low

R/W

0x0918

Module 3 Interrupt Vector 7 - Mid Range

R/W

0x0A18

Module 3 Interrupt Steering 7 - Mid Range

R/W

0x091C

Module 3 Interrupt Vector 8 - Reserved

R/W

0x0A1C

Module 3 Interrupt Steering 8 - Reserved

R/W

0x0920

Module 3 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x0A20

Module 3 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0924 to 0x093C

Module 3 Interrupt Vector 10 to 16 - Reserved

R/W

0x0A24 to 0x0A3C

Module 3 Interrupt Steering 10 to 16 - Reserved

R/W

0x0940

Module 3 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x0A40

Module 3 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0944

Module 3 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x0A44

Module 3 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0948

Module 3 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x0A48

Module 3 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x094C

Module 3 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x0A4C

Module 3 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0950

Module 3 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x0A50

Module 3 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0954

Module 3 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x0A54

Module 3 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0958

Module 3 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x0A58

Module 3 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x095C

Module 3 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x0A5C

Module 3 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0960 to 0x0968

Module 3 Interrupt Vector 25 to 27 - Reserved

R/W

0x0A60 to 0x0A68

Module 3 Interrupt Steering 25 to 27 - Reserved

R/W

0x096C

Module 3 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x0A6C

Module 3 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0970 to 0x097C

Module 3 Interrupt Vector 29 to 32 - Reserved

R/W

0x0A70 to 0x0A7C

Module 3 Interrupt Steering 29 to 32 - Reserved

R/W

0x0B00

Module 4 Interrupt Vector 1 - BIT

R/W

0x0C00

Module 4 Interrupt Steering 1 - BIT

R/W

0x0B04

Module 4 Interrupt Vector 2 - Low-High

R/W

0x0C04

Module 4 Interrupt Steering 2 - Low-High

R/W

0x0B08

Module 4 Interrupt Vector 3 - High-Low

R/W

0x0C08

Module 4 Interrupt Steering 3 - High-Low

R/W

0x0B0C

Module 4 Interrupt Vector 4 - Overcurrent

R/W

0x0C0C

Module 4 Interrupt Steering 4 - Overcurrent

R/W

0x0B10

Module 4 Interrupt Vector 5 - Max-High

R/W

0x0C10

Module 4 Interrupt Steering 5 - Max-High

R/W

0x0B14

Module 4 Interrupt Vector 6 - Min-Low

R/W

0x0C14

Module 4 Interrupt Steering 6 - Min-Low

R/W

0x0B18

Module 4 Interrupt Vector 7 - Mid Range

R/W

0x0C18

Module 4 Interrupt Steering 7 - Mid Range

R/W

0x0B1C

Module 4 Interrupt Vector 8 - Reserved

R/W

0x0C1C

Module 4 Interrupt Steering 8 - Reserved

R/W

0x0B20

Module 4 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x0C20

Module 4 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0B24 to 0x0B3C

Module 4 Interrupt Vector 10 to 16 - Reserved

R/W

0x0C24 to 0x0C3C

Module 4 Interrupt Steering 10 to 16 - Reserved

R/W

0x0B40

Module 4 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x0C40

Module 4 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0B44

Module 4 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x0C44

Module 4 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0B48

Module 4 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x0C48

Module 4 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x0B4C

Module 4 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x0C4C

Module 4 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0B50

Module 4 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x0C50

Module 4 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0B54

Module 4 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x0C54

Module 4 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0B58

Module 4 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x0C58

Module 4 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x0B5C

Module 4 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x0C5C

Module 4 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0B60 to 0x0B68

Module 4 Interrupt Vector 25 to 27 - Reserved

R/W

0x0C60 to 0x0C68

Module 4 Interrupt Steering 25 to 27 - Reserved

R/W

0x0B6C

Module 4 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x0C6C

Module 4 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0B70 to 0x0B7C

Module 4 Interrupt Vector 29 to 32 - Reserved

R/W

0x0C70 to 0x0C7C

Module 4 Interrupt Steering 29 to 32 - Reserved

R/W

0x0D00

Module 5 Interrupt Vector 1 - BIT

R/W

0x0E00

Module 5 Interrupt Steering 1 - BIT

R/W

0x0D04

Module 5 Interrupt Vector 2 - Low-High

R/W

0x0E04

Module 5 Interrupt Steering 2 - Low-High

R/W

0x0D08

Module 5 Interrupt Vector 3 - High-Low

R/W

0x0E08

Module 5 Interrupt Steering 3 - High-Low

R/W

0x0D0C

Module 5 Interrupt Vector 4 - Overcurrent

R/W

0x0E0C

Module 5 Interrupt Steering 4 - Overcurrent

R/W

0x0D10

Module 5 Interrupt Vector 5 - Max-High

R/W

0x0E10

Module 5 Interrupt Steering 5 - Max-High

R/W

0x0D14

Module 5 Interrupt Vector 6 - Min-Low

R/W

0x0E14

Module 5 Interrupt Steering 6 - Min-Low

R/W

0x0D18

Module 5 Interrupt Vector 7 - Mid Range

R/W

0x0E18

Module 5 Interrupt Steering 7 - Mid Range

R/W

0x0D1C

Module 5 Interrupt Vector 8 - Reserved

R/W

0x0E1C

Module 5 Interrupt Steering 8 - Reserved

R/W

0x0D20

Module 5 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x0E20

Module 5 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0D24 to 0x0D3C

Module 5 Interrupt Vector 10 to 16 - Reserved

R/W

0x0E24 to 0x0E3C

Module 5 Interrupt Steering 10 to 16 - Reserved

R/W

0x0D40

Module 5 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x0E40

Module 5 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0D44

Module 5 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x0E44

Module 5 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0D48

Module 5 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x0E48

Module 5 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x0D4C

Module 5 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x0E4C

Module 5 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0D50

Module 5 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x0E50

Module 5 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0D54

Module 5 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x0E54

Module 5 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0D58

Module 5 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x0E58

Module 5 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x0D5C

Module 5 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x0E5C

Module 5 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0D60 to 0x0D68

Module 5 Interrupt Vector 25 to 27 - Reserved

R/W

0x0E60 to 0x0E68

Module 5 Interrupt Steering 25 to 27 - Reserved

R/W

0x0D6C

Module 5 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x0E6C

Module 5 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0D70 to 0x0D7C

Module 5 Interrupt Vector 29 to 32 - Reserved

R/W

0x0E70 to 0x0E7C

Module 5 Interrupt Steering 29 to 32 - Reserved

R/W

0x0F00

Module 6 Interrupt Vector 1 - BIT

R/W

0x1000

Module 6 Interrupt Steering 1 - BIT

R/W

0x0F04

Module 6 Interrupt Vector 2 - Low-High

R/W

0x1004

Module 6 Interrupt Steering 2 - Low-High

R/W

0x0F08

Module 6 Interrupt Vector 3 - High-Low

R/W

0x1008

Module 6 Interrupt Steering 3 - High-Low

R/W

0x0F0C

Module 6 Interrupt Vector 4 - Overcurrent

R/W

0x100C

Module 6 Interrupt Steering 4 - Overcurrent

R/W

0x0F10

Module 6 Interrupt Vector 5 - Max-High

R/W

0x1010

Module 6 Interrupt Steering 5 - Max-High

R/W

0x0F14

Module 6 Interrupt Vector 6 - Min-Low

R/W

0x1014

Module 6 Interrupt Steering 6 - Min-Low

R/W

0x0F18

Module 6 Interrupt Vector 7 - Mid Range

R/W

0x1018

Module 6 Interrupt Steering 7 - Mid Range

R/W

0x0F1C

Module 6 Interrupt Vector 8 - Reserved

R/W

0x101C

Module 6 Interrupt Steering 8 - Reserved

R/W

0x0F20

Module 6 Interrupt Vector 9 - Inter-FPGA Failure

R/W

0x1020

Module 6 Interrupt Steering 9 - Inter-FPGA Failure

R/W

0x0F24 to 0x0F3C

Module 6 Interrupt Vector 10 to 16 - Reserved

R/W

0x1024 to 0x103C

Module 6 Interrupt Steering 10 to 16 - Reserved

R/W

0x0F40

Module 6 Interrupt Vector 17 - Channel Status Ch 1

R/W

0x1040

Module 6 Interrupt Steering 17 - Channel Status Ch 1

R/W

0x0F44

Module 6 Interrupt Vector 18 - Channel Status Ch 2

R/W

0x1044

Module 6 Interrupt Steering 18 - Channel Status Ch 2

R/W

0x0F48

Module 6 Interrupt Vector 19 - Channel Status Ch 3

R/W

0x1048

Module 6 Interrupt Steering 19 - Channel Status Ch 3

R/W

0x0F4C

Module 6 Interrupt Vector 20 - Channel Status Ch 4

R/W

0x104C

Module 6 Interrupt Steering 20 - Channel Status Ch 4

R/W

0x0F50

Module 6 Interrupt Vector 21 - Channel Status Ch 5

R/W

0x1050

Module 6 Interrupt Steering 21 - Channel Status Ch 5

R/W

0x0F54

Module 6 Interrupt Vector 22 - Channel Status Ch 6

R/W

0x1054

Module 6 Interrupt Steering 22 - Channel Status Ch 6

R/W

0x0F58

Module 6 Interrupt Vector 23 - Channel Status Ch 7

R/W

0x1058

Module 6 Interrupt Steering 23 - Channel Status Ch 7

R/W

0x0F5C

Module 6 Interrupt Vector 24 - Channel Status Ch 8

R/W

0x105C

Module 6 Interrupt Steering 24 - Channel Status Ch 8

R/W

0x0F60 to 0x0F68

Module 6 Interrupt Vector 25 to 27 - Reserved

R/W

0x1060 to 0x1068

Module 6 Interrupt Steering 25 to 27 - Reserved

R/W

0x106C

Module 6 Interrupt Vector 28 - User Watchdog Timer Fault

R/W

0x106C

Module 6 Interrupt Steering 28 - User Watchdog Timer Fault

R/W

0x0F70 to 0x0F7C

Module 6 Interrupt Vector 29 to 32 - Reserved

R/W

0x1070 to 0x107C

Module 6 Interrupt Steering 29 to 32 - Reserved

R/W

APPENDIX: PIN-OUT DETAILS

Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals.

Module Signal (Ref Only)	44-Pin I/O	50-Pin I/O (Mod Slot 1-J3)	50-Pin I/O (Mod Slot 2-J4)	50-Pin I/O (Mod Slot 3-J3)	50-Pin I/O (Mod Slot 3-J4)	8 CH ARINC-429 & 12 CH Discrete I/O (CM2)
DATIO1	2	10	1	2		IO-CH01
DATIO2	24	35	26	27		IO-CH02
DATIO3	3	11	2	3		IO-CH03
DATIO4	25	36	27	28		IO-CH04
DATIO5	5	13	4	5		VCC1 (1-6)
DATIO6	27	38	29	30		DT-IO-GND
DATIO7	7	14	5	6		IO-CH07
DATIO8	29	39	30	31		IO-CH08
DATIO9	8	15	6	7		IO-CH09
DATIO10	30	40	31	32		IO-CH10
DATIO11	10	17	8	9		VCC2 (7-12)
DATIO12	32	42	33	34		DT-IO-GND
DATIO13	12	18	9		17	AR429-A-CH01
DATIO14	34	43	34		42	AR429-B-CH01
DATIO15	13	19	10		18	AR429-A-CH02
DATIO16	35	44	35		43	AR429-B-CH02
DATIO17	15	21	12		20	AR429-A-CH04
DATIO18	37	46	37		45	AR429-B-CH04
DATIO19	17	22	13		21	AR429-A-CH05
DATIO20	39	47	38		46	AR429-B-CH05
DATIO21	18	23	14		22	AR429-A-CH06
DATIO22	40	48	39		47	AR429-B-CH06
DATIO23	20	25	16		24	AR429-A-CH08
DATIO24	42	50	41		49	AR429-B-CH08
DATIO25	4	12	3	4		IO-CH05
DATIO26	26	37	28	29		IO-CH06
DATIO27	9	16	7	8		IO-CH11
DATIO28	31	41	32	33		IO-CH12
DATIO29	14	20	11		19	AR429-A-CH03
DATIO30	36	45	36		44	AR429-B-CH03
DATIO31	19	24	15		23	AR429-A-CH07
DATIO32	41	49	40		48	AR429-B-CH07
DATIO33	6
DATIO34	28
DATIO35	11
DATIO36	33
DATIO37	16
DATIO38	38
DATIO39	21
DATIO40	43
N/A

DOCS.NAII REVISIONS

Revision Date

Description

2026-04-30

Initial release of CM2 manual.

STATUS AND INTERRUPTS

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Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.

For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.

Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.

Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).

Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.

Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).

Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edge-triggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Interrupt Trigger Types

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

Dynamic and Latched Status Registers Examples

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

No Clearing of Latched Status

Clearing of Latched Status (Edge-Triggered)

Clearing of Latched Status(Level-Triggered)

Time

Dynamic Status

Latched Status

Action

Latched Status

Action

Latched

0x0

Read Latched Register

0x0

Read Latched Register

0x0

0x1

Read Latched Register

0x1

Write 0x1 to Latched Register

0x1

0x0

0x1

0x0

0x1

Read Latched Register

0x0

Read Latched Register

0x1

0x0

0x1

Read Latched Register

0x0

Write 0x1 to Latched Register

0x0

0x1

Read Latched Register

0x0

0x0

0x2

0x3

Read Latched Register

0x2

Read Latched Register

0x2

0x3

Write 0x2 to Latched Register

0x2

0x3

0x0

0x2

0x2

0x3

Read Latched Register

0x1

Read Latched Register

0x3

0x2

0x3

Write 0x1 to Latched Register

Write 0x3 to Latched Register

0x2

0x3

0x0

0x2

0xC

0xF

Read Latched Register

0xC

Read Latched Register

0xE

0xC

0xF

Write 0xC to Latched Register

Write 0xE to Latched Register

0xC

0xF

0x0

0xC

0xC

0xF

Read Latched Register

0x0

Read Latched

0xC

0xF

Read Latched Register

0x0

Write 0xC to Latched Register

0xC

0xF

Read Latched Register

0x0

0xC

0x4

0xF

Read Latched Register

0x0

Read Latched Register

0xC

0x4

0xF

Read Latched Register

0x0

Write 0xC to Latched Register

0x4

0xF

Read Latched Register

0x0

0x4

0x4

0xF

Read Latched Register

0x0

Read Latched Register

0x4

Interrupt Examples

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

Time

Latched Status (Edge-Triggered - Clear Multi-Channel)

Latched Status (Edge-Triggered - Clear Single Channel)

Latched Status (Level-Triggered - Clear Multi-Channel)

Action

Latched

Action

Latched

Action

Latched

T1 (Int 1)

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

T1 (Int 1)

Write 0x1 to Latched Register

T1 (Int 1)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T2.

0x1

T3 (Int 2)

Interrupt Generated Read Latched Registers

0x2

Interrupt Generated Read Latched Registers

0x2

Interrupt Generated Read Latched Registers

0x2

T3 (Int 2)

Write 0x2 to Latched Register

T3 (Int 2)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.

0x2

T4 (Int 3)

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x3

T4 (Int 3)

Write 0x1 to Latched Register

Write 0x3 to Latched Register

T4 (Int 3)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.

0x3

T4 (Int 3)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.

0x2

T6 (Int 4)

Interrupt Generated Read Latched Registers

0xC

Interrupt Generated Read Latched Registers

0xC

Interrupt Generated Read Latched Registers

0xE

T6 (Int 4)

Write 0xC to Latched Register

Write 0x4 to Latched Register

Write 0xE to Latched Register

T6 (Int 4)

0x0

Interrupt re-triggers Write 0x8 to Latched Register

0x8

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.

0xE

T6 (Int 4)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.

0xC

T6 (Int 4)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.

0x4

REVISION HISTORY

Motherboard Manual - Status and Interrupts Revision History

Revision

Revision Date

Description

2021-11-30

C08896; Transition manual to docbuilder format - no technical info change.

DOCS.NAII REVISIONS

Revision Date

Description

2026-03-02

Formatting updates to document; no technical changes.

USER WATCHDOG TIMER MODULE MANUAL

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User Watchdog Timer Capability

The User Watchdog Timer (UWDT) Capability is available on the following modules:

AC Reference Source Modules
- AC1 - 1 Channel, 2-115 Vrms, 47 Hz - 20kHz
- AC2 - 2 Channels, 2-28 Vrms, 47 Hz - 20kHz
- AC3 - 1 Channel, 28-115 Vrms, 47 Hz - 2.5 kHz
Differential Transceiver Modules
- DF1/DF2 - 16 Channels Differential I/O
Digital-to-Analog (D/A) Modules
- DA1 - 12 Channels, ±10 VDC @ 25 mA, Voltage or Current Control Modes
- DA2 - 16 Channels, ±10 VDC @ 10 mA
- DA3 - 4 Channels, ±40 VDC @ ±100 mA, Voltage or Current Control Modes
- DA4 - 4 Channels, ±80 VDC @ 10 mA
- DA5 - 4 Channels, ±65 VDC or ±2 A, Voltage or Current Control Modes
Digital-to-Synchro/Resolver (D/S) or Digital-to-L( R )VDT (D/LV) Modules
- (Not supported)
Discrete I/O Modules
- DT1/DT4 - 24 Channels, Programmable for either input or output, output up to 500 mA per channel from an applied external 3 - 60 VCC source.
- DT2/DT5 - 16 Channels, Programmable for either input voltage measurements (±80 V) or as a bi-directional current switch (up to 500 mA per channel).
- DT3/DT6 - 4 Channels, Programmable for either input voltage measurements (±100 V) or as a bi-directional current switch (up to 3 A per channel).
TTL/CMOS Modules
- TL1-TL8 - 24 Channels, Programmable for either input or output.

Principle of Operation

The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.

The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:

The application must not strobe during the Quiet time.
The application must strobe within the Window time.
The application must not strobe more than once in a single window time.

A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.

The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.

The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.

WDT Diagram Fig1

Figure 1. User Watchdog Timer Overview

WDT Diagram Example Fig2

Figure 2. User Watchdog Timer Example

WDT Diagram Errors Fig3

Figure 3. User Watchdog Timer Failures

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

User Watchdog Timer Registers

The registers associated with the User Watchdog Timer provide the ability to specify the UWDT Quiet Time and the UWDT Window that will be monitored to ensure that EXACTLY ONE User Watchdog Timer (UWDT) Strobe is written within the window.

UWDT Quiet Time

Function:

Sets Quiet Time value (in microseconds) to use for the User Watchdog Timer Frame.

Type:

unsigned binary word (32-bit)

Data Range:

0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)

Read/Write:

R/W

Initialized Value:

0x0

Operational Settings:

LSB = 1 µsec. The application must NOT write a strobe in the time between the previous strobe and the end of the Quiet time interval. In addition, the application must write in the UWDT Window EXACTLY ONCE.

UWDT Window

Function:

Writes the window value (in microseconds) to be used for the User Watchdog Timer Frame.

Type:

unsigned binary word (32-bit)

Data Range:

0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)

Read/Write:

R/W

Initialized Value:

0x0

Operational Settings:

LSB = 1 µsec. The application must write the strobe once within the Window time after the end of the Quiet time interval. The application must write in the UWDT Window EXACTLY ONCE. This setting must be initialized to a non-zero value for operation and should allow sufficient tolerance for strobe timing by the application.

UWDT Strobe

Function:

Writes the strobe value to be use for the User Watchdog Timer Frame.

Type:

unsigned binary word (32-bit)

Data Range:

0x55AA

Read/Write:

Initialized Value:

0x0

Operational Settings:

At startup, the user watchdog is disabled. Write the value of 0x55AA to this register to start the user watchdog timer monitoring after initial power on or a reset. To prevent a disablement, the application must periodically write the strobe based on the user watchdog timer rules.

Status and Interrupt

The modules that are capable of User Watchdog Timer support provide status registers for the User Watchdog Timer.

User Watchdog Timer Status

The status register that contains the User Watchdog Timer Fault information is also used to indicate channel Inter-FPGA failures on modules that have communication between FPGA components. There are four registers associated with the User Watchdog Timer Fault/Inter-FPGA Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Function:

Sets the corresponding bit (D31) associated with the channel’s User Watchdog Timer Fault error.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)

Initialized Value:

User Watchdog Timer Fault/Inter-FPGA Failure Dynamic Status

User Watchdog Timer Fault/Inter-FPGA Failure Latched Status

User Watchdog Timer Fault/Inter-FPGA Failure Interrupt Enable

User Watchdog Timer Fault/Inter-FPGA Failure Set Edge/Level Interrupt

Bit(s)

Status

Description

D31

User Watchdog Timer Fault Status

0 = No Fault
1 = User Watchdog Timer Fault

D30:D0

Reserved for Inter-FPGA Failure Status

Channel bit-mapped indicating channel inter FPGA communication failure detection.

Interrupt Vector and Steering

In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note	the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector

Function:

Set an identifier for the interrupt.

Type:

unsigned binary word (32-bit)

Data Range:

0 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering

Function:

Sets where to direct the interrupt.

Type:

unsigned binary word (32-bit)

Data Range:

See table

Read/Write:

R/W

Initialized Value:

Operational Settings:

When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME	1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)	2
Direct Interrupt to PCIe Bus	5
Direct Interrupt to cPCI Bus	6

Function Register Map

KEY

Configuration/Control

Measurement/Status

USER WATCHDOG TIMER REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x01C0

UWDT Quiet Time

R/W

0x01C4

UWDT Window

R/W

0x01C8

UWDT Strobe

R/W

STATUS REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x09B0

Dynamic Status

0x09B4

Latched Status*

R/W

0x09B8

Interrupt Enable

R/W

0x09BC

Set Edge/Level Interrupt

R/W

INTERRUPT REGISTERS

The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x056C

Module 1 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x066C

Module 1 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x076C

Module 2 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x086C

Module 2 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x096C

Module 3 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0A6C

Module 3 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0B6C

Module 4 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0C6C

Module 4 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0D6C

Module 5 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0E6C

Module 5 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0F6C

Module 6 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x106C

Module 6 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

REVISION HISTORY

Motherboard Manual - Status and Interrupts Revision History

Revision

Revision Date

Description

2021-11-30

C08896; Transition manual to docbuilder format - no technical info change.

DOCS.NAII REVISIONS

Revision Date

Description

2026-03-02

Formatting updates to document; no technical changes.

MODULE COMMON REGISTERS

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The registers described in this document are common to all NAI Generation 5 modules.

Module Information Registers

The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.

FPGA Version Registers

The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.

FPGA Revision

Function:

FPGA firmware revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the revision of the board’s FPGA

Operational Settings:

The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

FPGA Compile Timestamp

Function:

Compile Timestamp for the FPGA firmware.

Type:

unsigned binary word (32-bit)

Data Range:

N/A

Read/Write:

Initialized Value:

Value corresponding to the compile timestamp of the board’s FPGA

Operational Settings:

The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

day (5-bits)

month (4-bits)

year (6-bits)

D15

D14

D13

D12

D11

D10

hour (5-bits)

minutes (6-bits)

seconds (6-bits)

FPGA SerDes Revision

Function:

FPGA SerDes revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the SerDes revision of the board’s FPGA

Operational Settings:

The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

FPGA Template Revision

Function:

FPGA Template revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the template revision of the board’s FPGA

Operational Settings:

The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

FPGA Zynq Block Revision

Function:

FPGA Zynq Block revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the Zynq block revision of the board’s FPGA

Operational Settings:

The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

Bare Metal Version Registers

The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.

Bare Metal Revision

Function:

Bare Metal firmware revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the revision of the board’s Bare Metal

Operational Settings:

The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

Bare Metal Compile Time

Function:

Provides an ASCII representation of the Date/Time for the Bare Metal compile time.

Type:

24-character ASCII string - Six (6) unsigned binary word (32-bit)

Data Range:

N/A

Read/Write:

Initialized Value:

Value corresponding to the ASCII representation of the compile time of the board’s Bare Metal

Operational Settings:

The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Note	little-endian order of ASCII values

Word 1 (Ex. 0x2079614D)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Month ('y' - 0x79)

D15

D14

D13

D12

D11

D10

Month ('a' - 0x61)

Month ('M' - 0x4D)

Word 2 (Ex. 0x32203731)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Year ('2' - 0x32)

Space (0x20)

D15

D14

D13

D12

D11

D10

Day ('7' - 0x37)

Day ('1' - 0x31)

Word 3 (Ex. 0x20393130)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Year ('9' - 0x39)

D15

D14

D13

D12

D11

D10

Year ('1' - 0x31)

Year ('0' - 0x30)

Word 4 (Ex. 0x31207461)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Hour ('1' - 0x31)

Space (0x20)

D15

D14

D13

D12

D11

D10

'a' (0x74)

't' (0x61)

Word 5 (Ex. 0x38333A35)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Minute ('8' - 0x38)

Minute ('3' - 0x33)

D15

D14

D13

D12

D11

D10

':' (0x3A)

Hour ('5' - 0x35)

Word 6 (Ex. 0x0032333A)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

NULL (0x00)

Seconds ('2' - 0x32)

D15

D14

D13

D12

D11

D10

Seconds ('3' - 0x33)

':' (0x3A)

FSBL Version Registers

The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).

FSBL Revision

Function:

FSBL firmware revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the revision of the board’s FSBL

Operational Settings:

The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

FSBL Compile Time

Function:

Provides an ASCII representation of the Date/Time for the FSBL compile time.

Type:

24-character ASCII string - Six (6) unsigned binary word (32-bit)

Data Range:

N/A

Read/Write:

Initialized Value:

Value corresponding to the ASCII representation of the Compile Time of the board’s FSBL

Operational Settings:

The six 32-bit words provide an ASCII representation of the Date/Time.

The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Note	little-endian order of ASCII values

Word 1 (Ex. 0x2079614D)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Month ('y' - 0x79)

D15

D14

D13

D12

D11

D10

Month ('a' - 0x61)

Month ('M' - 0x4D)

Word 2 (Ex. 0x32203731)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Year ('2' - 0x32)

Space (0x20)

D15

D14

D13

D12

D11

D10

Day ('7' - 0x37)

Day ('1' - 0x31)

Word 3 (Ex. 0x20393130)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Year ('9' - 0x39)

D15

D14

D13

D12

D11

D10

Year ('1' - 0x31)

Year ('0' - 0x30)

Word 4 (Ex. 0x31207461)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Hour ('1' - 0x31)

Space (0x20)

D15

D14

D13

D12

D11

D10

'a' (0x74)

't' (0x61)

Word 5 (Ex. 0x38333A35)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Minute ('8' - 0x38)

Minute ('3' - 0x33)

D15

D14

D13

D12

D11

D10

':' (0x3A)

Hour ('5' - 0x35)

Word 6 (Ex. 0x0032333A)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

NULL (0x00)

Seconds ('2' - 0x32)

D15

D14

D13

D12

D11

D10

Seconds ('3' - 0x33)

':' (0x3A)

Module Serial Number Registers

The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.

Interface Board Serial Number

Function:

Unique 128-bit identifier used to identify the interface board.

Type:

16-character ASCII string - Four (4) unsigned binary words (32-bit)

Data Range:

N/A

Read/Write:

Initialized Value:

Serial number of the interface board

Operational Settings:

This register is for information purposes only.

Functional Board Serial Number

Function:

Unique 128-bit identifier used to identify the functional board.

Type:

16-character ASCII string - Four (4) unsigned binary words (32-bit)

Data Range:

N/A

Read/Write:

Initialized Value:

Serial number of the functional board

Operational Settings:

This register is for information purposes only.

Module Capability

Function:

Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0107

Read/Write:

Initialized Value:

0x0000 0107

Operational Settings:

A “1” in the bit associated with the capability indicates that it is supported.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	Flt-Pt	0	0	0	0	0	Pack	FIFO Blk	Blk

Module Memory Map Revision

Function:

Module Memory Map revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the Module Memory Map Revision

Operational Settings:

The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

Module Measurement Registers

The registers in this section provide module temperature measurement information.

Temperature Readings Registers

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.

Interface Board Current Temperature

Function:

Measured PCB and Zynq Core temperatures on Interface Board.

Type:

signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range:

0x0000 0000 to 0x0000 FFFF

Read/Write:

Initialized Value:

Value corresponding to the measured PCB and Zynq core temperatures based on the table below

Operational Settings:

The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

PCB Temperature

Zynq Core Temperature

Functional Board Current Temperature

Function:

Measured PCB temperature on Functional Board.

Type:

signed byte (8-bits) for PCB

Data Range:

0x0000 0000 to 0x0000 00FF

Read/Write:

Initialized Value:

Value corresponding to the measured PCB on the table below

Operational Settings:

The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Interface Board Maximum Temperature

Function:

Maximum PCB and Zynq Core temperatures on Interface Board since power-on.

Type:

signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range:

0x0000 0000 to 0x0000 FFFF

Read/Write:

Initialized Value:

Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below

Operational Settings:

The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

PCB Temperature

Zynq Core Temperature

Interface Board Minimum Temperature

Function:

Minimum PCB and Zynq Core temperatures on Interface Board since power-on.

Type:

signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range:

0x0000 0000 to 0x0000 FFFF

Read/Write:

Initialized Value:

Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below

Operational Settings:

The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

PCB Temperature

Zynq Core Temperature

Functional Board Maximum Temperature

Function:

Maximum PCB temperature on Functional Board since power-on.

Type:

signed byte (8-bits) for PCB

Data Range:

0x0000 0000 to 0x0000 00FF

Read/Write:

Initialized Value:

Value corresponding to the measured PCB on the table below

Operational Settings:

The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Functional Board Minimum Temperature

Function:

Minimum PCB temperature on Functional Board since power-on.

Type:

signed byte (8-bits) for PCB

Data Range:

0x0000 0000 to 0x0000 00FF

Read/Write:

Initialized Value:

Value corresponding to the measured PCB on the table below

Operational Settings:

The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Higher Precision Temperature Readings Registers

These registers provide higher precision readings of the current Zynq and PCB temperatures.

Higher Precision Zynq Core Temperature

Function:

Higher precision measured Zynq Core temperature on Interface Board.

Type:

signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Measured Zynq Core temperature on Interface Board

Operational Settings:

The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

Fractional Part of Temperature

Higher Precision Interface PCB Temperature

Function:

Higher precision measured Interface PCB temperature.

Type:

signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Measured Interface PCB temperature

Operational Settings:

The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

Fractional Part of Temperature

Higher Precision Functional PCB Temperature

Function:

Higher precision measured Functional PCB temperature.

Type:

signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Measured Functional PCB temperature

Operational Settings:

The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

Fractional Part of Temperature

Module Health Monitoring Registers

The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.

Module Sensor Summary Status

Function:

The corresponding sensor bit is set if the sensor has crossed any of its thresholds.

Type:

unsigned binary word (32-bits)

Data Range:

See table below

Read/Write:

Initialized Value:

Operational Settings:

This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.

Bit(s)

Sensor

D31:D6

Reserved

Functional Board PCB Temperature

Interface Board PCB Temperature

D3:D0

Reserved

Module Sensor Registers

The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.

Sensor Threshold Status

Function:

Reflects which threshold has been crossed

Type:

unsigned binary word (32-bits)

Data Range:

See table below

Read/Write:

Initialized Value:

Operational Settings:

The associated bit is set when the sensor reading exceed the corresponding threshold settings.

Bit(s)

Description

D31:D4

Reserved

Exceeded Upper Critical Threshold

Exceeded Upper Warning Threshold

Exceeded Lower Critical Threshold

Exceeded Lower Warning Threshold

Sensor Current Reading

Function:

Reflects current reading of temperature sensor

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

Initialized Value:

N/A

Operational Settings:

The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Minimum Reading

Function:

Reflects minimum value of temperature sensor since power up

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

Initialized Value:

N/A

Operational Settings:

The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Maximum Reading

Function:

Reflects maximum value of temperature sensor since power up

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

Initialized Value:

N/A

Operational Settings:

The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Lower Warning Threshold

Function:

Reflects lower warning threshold of temperature sensor

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

Default lower warning threshold (value dependent on specific sensor)

Operational Settings:

The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.

Sensor Lower Critical Threshold

Function:

Reflects lower critical threshold of temperature sensor

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

Default lower critical threshold (value dependent on specific sensor)

Operational Settings:

The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.

Sensor Upper Warning Threshold

Function:

Reflects upper warning threshold of temperature sensor

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

Default upper warning threshold (value dependent on specific sensor)

Operational Settings:

The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.

Sensor Upper Critical Threshold

Function:

Reflects upper critical threshold of temperature sensor

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

Default upper critical threshold (value dependent on specific sensor)

Operational Settings:

The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.

FUNCTION REGISTER MAP

KEY

Configuration/Control

Measurement/Status/Board Information

MODULE INFORMATION REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x003C

FPGA Revision

0x0074

Bare Metal Revision

0x0030

FPGA Compile Timestamp

0x0080

Bare Metal Compile Time (Bit 0-31)

0x0034

FPGA SerDes Revision

0x0084

Bare Metal Compile Time (Bit 32-63)

0x0038

FPGA Template Revision

0x0088

Bare Metal Compile Time (Bit 64-95)

0x0040

FPGA Zynq Block Revision

0x008C

Bare Metal Compile Time (Bit 96-127)

0x0090

Bare Metal Compile Time (Bit 128-159)

0x0094

Bare Metal Compile Time (Bit 160-191)

0x007C

FSBL Revision

0x00B0

FSBL Compile Time (Bit 0-31)

0x00B4

FSBL Compile Time (Bit 32-63)

0x00B8

FSBL Compile Time (Bit 64-95)

0x00BC

FSBL Compile Time (Bit 96-127)

0x00C0

FSBL Compile Time (Bit 128-159)

0x00C4

FSBL Compile Time (Bit 160-191)

0x0000

Interface Board Serial Number (Bit 0-31)

0x0010

Functional Board Serial Number (Bit 0-31)

0x0034

Interface Board Serial Number (Bit 32-63)

0x0014

Functional Board Serial Number (Bit 32-63)

0x0008

Interface Board Serial Number (Bit 64-95)

0x0018

Functional Board Serial Number (Bit 64-95)

0x000C

Interface Board Serial Number (Bit 96-127)

0x001C

Functional Board Serial Number (Bit 96-127)

0x0070

Module Capability

0x01FC

Module Memory Map Revision

MODULE MEASUREMENTS REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0200

Interface Board PCB/Zynq Current Temp

0x0208

Functional Board PCB Current Temp

0x0218

Interface Board PCB/Zynq Max Temp

0x0228

Functional Board PCB Max Temp

0x0220

Interface Board PCB/Zynq Min Temp

0x0230

Functional Board PCB Min Temp

0x02C0

Higher Precision Zynq Core Temperature

0x02C4

Higher Precision Interface PCB Temperature

0x02E0

Higher Precision Functional PCB Temperature

MODULE HEALTH MONITORING REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x07F8

Module Sensor Summary Status

Module Sensor Registers Memory Map

REVISION HISTORY

Motherboard Manual - Module Common Registers Revision History

Revision

Revision Date

Description

2023-08-11

ECO C10649, initial release of module common registers manual.

2024-05-15

ECO C11522, removed Zynq Core/Aux/DDR Voltage register descriptions from Module Measurement Registers. Pg.16, updated Module Sensor Summary Status register to add PS references; updated Bit Table to change voltage/current bits to 'reserved'. Pg.16, updated Module/Power Supply Sensor Registers description to better describe register functionality and to add figure. Pg.17, added 'Exceeded' to threshold bit descriptions. Pg.17-18, removed voltage/current references from sensor descriptions. Pg.20, removed Zynq Core/Aux/DDR Voltage register offsets from Module Measurement Registers. Pg.20, updated Module Health Monitoring Registers offset tables.

2024-07-10

ECO C11701, pg.16, updated Module Sensor Summary Status register to remove PS references;updated Bit Table to change PS temperature bits to 'reserved'. Pg.16, updated Module SensorRegisters description to remove PS references. Pg.20, updated Module Health MonitoringRegisters offset tables to remove PS temperature register offsets.

DOCS.NAII REVISIONS

Revision Date

Description

2025-11-05

Corrected register offsets for Interface Board Min Temp and Function Board Min & Max Temps.

2026-03-02

Formatting updates to document; no technical changes.

ENHANCED INPUT/OUTPUT FUNCTIONALITY CAPABILITY

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The Enhanced Input/Output Functionality Capability is available on the following modules:

Differential Transceiver Modules
- DF2 - 16 Channels Differential I/O
Discrete I/O Modules
- DT4 - 24 Channels, Programmable for either input or output, output up to 500 mA per channel from an applied external 3 – 60 VCC source.
- DT5 - 16 Channels, Programmable for either input voltage measurements (±80 V) or as a bi-directional current switch (up to 500 mA per channel).
- DT6 - 4 Channels, Programmable for either input voltage measurements (±100 V) or as a bi-directional current switch (up to 3 A per channel).
TTL/CMOS Modules
- TL2, TL4, TL6 and TL8 - 24 Channels, Programmable for either input or output.

PRINCIPLE OF OPERATION

The modules listed in Enhanced Input/Output Functionality Capability provide enhanced input and output mode functionality. For incoming signals (inputs), the enhanced modes include Pulse, Frequency and Period measurements. For outputs, the enhanced modes include PWM (Pulse Width Modulation) and Pattern Generation.

Input Modes

All input modes may be configured with debounce capability. Debounce capability allows configurable filtering of noisy signals and transients. Each channel may be set to an individual debounce time value. When a debounce time is set to a non-zero value, the signal reading after a transition must remain at the same level for the debounce interval before it is propagated through, otherwise it is rejected.

The waveform shown in Figure 1 will be used to illustrate the behavior for each input mode.

Figure 1. Incoming Signal Example Used to illustrate Input Modes

Pulse Measurements

There are two Pulse Measurements features available - High Time Pulse Measurements and Low Time Pulse Measurements. The Pulse Measurement data is stored in the FIFO Buffer.

High Time Pulse Measurements

In this input mode, the data in the FIFO buffer is the measurement for each rising transition to the next falling one. Timing measurements record the time interval (in 10 µs ticks) from a pair of transitions.

Figure 2 - High Time Pulse Measurement Input Mode

For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs):

1500 (0x0000 05DC)
2500 (0x0000 09C4)
1000 (0x0000 03E8)

Time Interval

Calculations

High Time Pulse Measurements

1500 counts * 10 µsec = 15000 µsec = 15.0 msec

15.0 msec

2500 counts * 10 µsec = 25000 µsec = 25.0 msec

25.0 msec

1000 counts * 10 µsec = 10000 µsec = 10.0 msec

10.0 msec

Low Time Pulse Measurements

In this mode, the data in the FIFO buffer is the measurement for each falling edge to the next rising edge. Timing measurements record the time interval (in 10 µs ticks) from a pair of transitions.

Figure 3. Low Time Pulse Measurement Input Mode

For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs):

2000 (0x0000 07D0)
500 (0x0000 01F4)
1500 (0x0000 05DC)

Time Interval

Calculations

Low Time Pulse Measurements

2000 counts * 10 µsec = 2000 µsec = 20.0 msec

20.0 msec

500 counts * 10 µsec = 5000 µsec = 5.0 msec

5.0 msec

1500 counts * 10 µsec = 15000 µsec = 15.0 msec

15.0 msec

Transition Timestamps

There are three Transition Timestamp Measurements features available - Transition Timestamp for All Rising Edges, Transition Timestamp for All Falling Edges, and Transition Timestamp for All Edges. The Transition Timestamps Measurement data are store in the FIFO Buffer.

Transition Timestamp of All Rising Edges

In this mode, the data in the FIFO buffer is the Rising Edge Timestamp. The timestamp is a 32-bit counter that is incremented at the rate of 100 kHz (in other words, counter is incremented every 10 µsec). The timestamp is can be reset by the application at any time.

Figure 4. Transition Timestamp of All Rising Edges Input Mode

For this example, the FIFO Word Count register will be set to 4 and the FIFO Buffer Data register will contain the following four values (counts of 10 µs):

1000 (0x0000 03E8)
4500 (0x0000 1194)
7500 (0x0000 1D4C)
10000 (0x000 2710)

This data can be interpreted as follows:

Time Interval

Calculations

Time Between Rising Edges

1 to 2

4500 counts * 10 µsec = 35000 µsec = 35.0 msec

35.0 msec

2 to 3

7500 counts * 10 µsec = 30000 µsec = 30.0 msec

30.0 msec

3 to 4

10000 counts * 10 µsec = 25000 µsec = 25.0 msec

25.0 msec

Transition Timestamp of All Falling Edges

In this mode, the data in the FIFO buffer is the Falling Edge Timestamp. The timestamp is a 32-bit counter that is incremented at the rate of 100 kHz (in other words, counter is incremented every 10 µsec). The timestamp is can be reset by the application at any time.

Figure 5. Transition Timestamp of All Falling Edges Input Mode

For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs):

2500 (0x0000 09C4)
7000 (0x0000 1B58)
8500 (0x0000 2134)

This data can be interpreted as follows:

Time Interval

Calculations

Time Between Falling Edges

1 to 2

7000 - 2500 = 4500 counts = 4500 * 10 µsec = 45000 µsec = 45.0 msec

45.0 msec

2 to 3

8500 - 7000 = 1500 counts = 1500 * 10 µsec = 15000 µsec = 15.0 msec

15.0 msec

Transition Timestamp of All Edges

In this mode, the data in the FIFO buffer is the Rising and Falling Edge Timestamp. The timestamp is a 32-bit counter that is incremented at the rate of 100 kHz (in other words, counter is incremented every 10 µsec). The timestamp is can be reset by the application at any time.

Figure 6. Transition Timestamp for All Edges Input Mode

For this example, the FIFO Word Count register will be set to 7 and the FIFO Buffer Data register will contain the following seven values (counts of 10 µs):

1000 (0x0000 03E8)
2500 (0x0000 09C4)
4500 (0x0000 1194)
7000 (0x0000 1B58)
7500 (0x0000 1D4C)
8500 (0x0000 2134)
10000 (0x000 2710)

This data can be interpreted as follows:

Time Interval

Calculations

Time Between Edges

1 to 2

2500 - 1000 = 1500 counts = 1500 * 10 µsec = 15000 µsec = 15.0 msec

15.0 msec

2 to 3

4500 - 2500 = 2000 counts = 2000 * 10 µsec = 20000 µsec = 20.0 msec

20.0 msec

3 to 4

7000 - 4500 = 2500 counts = 2500 * 10 µsec = 25000 µsec = 25.0 msec

25.0 msec

4 to 5

7500 - 7000 = 500 counts = 500 * 10 µsec = 5000 µsec = 5.0 msec

5.0 msec

5 to 6

8500 - 7500 = 1000 counts = 1000 * 10 µsec = 10000 µsec = 10.0 msec

10.0 msec

6 to 7

10000 - 8500 = 1500 counts = 1500 * 10 µsec = 15000 µsec = 15.0 msec

15.0 msec

Transition Counter

There are three Transition Counter features available - Rising Edge Transition Counter, Falling Edge Transition Counter and All Edge Transition Counter.

Rising Edges Transition Counter

In this mode, the count of the number of Rising Edges is recorded. The counter is a 32-bit counter. The counter is can be reset by the application at any time.

Figure 7. Rising Edges Transition Counter Input Mode

For this example, the Transition Count register will be set to 4.

Falling Edges Transition Counter

In this mode, the count of the number of Falling Edges is recorded. The counter is a 32-bit counter. The counter is can be reset by the application at any time

Figure 8. Falling Edges Transition Counter Input Mode

For this example, the Transition Count register will be set to 3.

All Edges Transition Counter

In this mode, the count of the number of Rising and Falling Edges is recorded. The counter is a 32-bit counter. The counter is can be reset by the application at any time.

Figure 9. All Edges Transition Counter Input Mode

For this example, the Transition Count register will be set to 7.

Period Measurement

In this input mode, the data in the FIFO buffer is the measurement for each rising edge transition to the next rising edge transition. Timing measurements record the time interval (in 10 µs ticks).

Figure 10. Period Measurement Input Mode

For this example, the FIFO Word Count register will be set to 4 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs):

2000 (0x0000 07D0)
2000 (0x0000 07D0)
2000 (0x0000 07D0)
2000 (0x0000 07D0)

Time Interval

Calculations

Period Measurements

2000 counts * 10 µsec = 20000 µsec = 20.0 msec

20.0 msec

2000 counts * 10 µsec = 20000 µsec = 20.0 msec

20.0 msec

2000 counts * 10 µsec = 20000 µsec = 20.0 msec

20.0 msec

2000 counts * 10 µsec = 20000 µsec = 20.0 msec

20.0 msec

Frequency Measurement

In this input mode, the data in the FIFO buffer is the number of rising edge transitions for the programmable time interval programmed in the Frequency Measurement Period register.

For this example, set the Frequency Measurement Period register = 4000 (4000 * 10 µs = 40000 µs = 40 msec)

Figure 11. Frequency Measurement Input Mode

For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (number of rising edges:

2 (0x0000 0002)
2 (0x0000 0002)
2 (0x0000 0002)

Time Interval

Calculations

Frequency Measurements

2 counts/40 msec = 2 counts/0.04 seconds = 50 Hz

50 Hz

2 counts/40 msec = 2 counts/0.04 seconds = 50 Hz

50 Hz

2 counts/40 msec = 2 counts/0.04 seconds = 50 Hz

50 Hz

Output Modes

There are three Enhanced Output Functionality modes: two PWM outputs and one Pattern Generator Output mode.

PWM Output

There are two PWM output modes, PWM Continuous and PWM Burst. The PWM timing is very precise with low jitter. In PWM Output mode, the Mode Select register is set to either “PWM Continuous or PWM Burst”. The value written to the PWM Period register specifies the period to output the PWM signal, the value written to the PWM Pulse Width register specifies the time for the “ON” state, and the value written to the PWM Output Polarity register specifies the initial edge of the output. For PWM Burst mode, the PWM Number of Cycles register specifies the number of cycles to output the signal. Note, there may be an initial “OFF” state level delay based on the Period time before the initial pulse is output.

PWM Continuous

Figure 12 and Figure 13 illustrate the PWM Continuous Output signal, one configured with PWM Output Polarity = Positive (0) and one configured with PWM Output Polarity = Negative (1). The configured PWM output is enabled and disabled with the Enable Measurements/Outputs register.

Figure 12. PWM Continuous Output (PWM Period = 15 msec, PWM Pulse Width = 10 msec, PWM Output Polarity = Positive (0))

Figure 13. PWM Continuous Output (PWM Period = 15 msec, PWM Pulse Width = 10 msec, PWM Output Polarity = Negative (1))

PWM Burst

Figure 14 and Figure 15 illustrate the PWM Burst Output signal with the PWM Number of Cycles = 5 pulses, one configured with PWM Output Polarity = Positive (0) and one configured with PWM Output Polarity = Negative (1). The configured PWM output is enabled with the Enable Measurements/Outputs register. Once the number of pulses that were requested is outputted, the value in the Enable Measurements/Outputs register will be reset (self-clearing) to allow for the output to be re-enabled.

Figure 14. PWM Burst Output (PWM Period = 15 msec, PWM Pulse Width = 10 msec, PWM Output Polarity = Positive (0), PWM Number of Cycles = 5)

Figure 15. PWM Burst Output (PWM Period = 15 msec, PWM Pulse Width = 10 msec, PWM Output Polarity = Negative (1), PWM Number of Cycles = 5)

Pattern Generator

For the Pattern Generator mode, there is 64K block of unsigned 32-bit words allocated to specify the data pattern for the output channels. The data in each 32-bit word is bit-mapped per channel. The Pattern RAM Start Address and Pattern RAM End Address registers specify the starting and ending address in the 64K block to use as the data to output for each channel configured for Pattern Generator mode. The Pattern RAM Period register specifies the pattern rate. The Pattern RAM Control and Pattern RAM Number of Cycles control the Pattern Generator output - Continuous, Burst with a specified number of cycles, Pause, or External Trigger from input from Channel 1.

Note	When any channel is configured for External Trigger Pattern Generator mode, Channel 1 MUST be set as an input.

Figure 16 illustrates the output of the 24 channels for the DT4 module all configured in Pattern Generator mode

Figure 16. Pattern Generator

REGISTER DESCRIPTIONS

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

Enhanced Input/Output Functionality Registers

The onboard Discrete I/O option provides enhanced input and output mode functionality. The Mode Select and Enable Output/Measurement registers are general control registers for the different enhanced input and output modes.

Mode Select

Function:

Configures the Enhanced Functionality Modes to apply to the channel.

Type:

unsigned binary word (32-bit)

Data Range:

See table

Read/Write:

R/W

Initialized Value:

Operational Settings:

It is important that the channel is correctly configured to either input or output in the Input/Output Format registers to correspond to the Enhanced Functionality Mode selected. Setting a 0 to this register will configure that channel to normal operation.

Mode Select Value (Decimal)

Mode Select Value (Hexadecimal)

Description

0x0000 0000

Enhanced Functionality Disabled

Input Enhanced Functionality Mode

0x0000 0001

High Time Pulse Measurements

0x0000 0002

Low Time Pulse Measurements

0x0000 0003

Transition Timestamp of All Rising Edges

0x0000 0004

Transition Timestamp of All Falling Edges

0x0000 0005

Transition Timestamp of All Edges

0x0000 0006

Rising Edges Transition Counter

0x0000 0007

Falling Edges Transition Counter

0x0000 0008

All Edges Transition Counter

0x0000 0009

Period Measurement

0x0000 000A

Frequency Measurement

Output Enhanced Functionality Mode

0x0000 0020

PWM Continuous

0x0000 0021

PWM Burst

0x0000 0022

Pattern Generator

Enable Measurements/Outputs

Function:

Enables/starts the measurements or outputs based on the Mode Select for the channel.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x00FF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

Setting the bit for the associated channel to a 1 will start the measurement or output depending on the Mode Select configuration for that channel. Setting the bit for the associated channel to 0 will stop the measurements/outputs.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Ch24

Ch23

Ch22

Ch21

Ch20

Ch19

Ch18

Ch17

D15

D14

D13

D12

D11

D10

Ch16

Ch15

Ch14

Ch13

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Input Mode Registers

After configuring the Mode Select register, write a 1 to the Reset Timer/Counter register resets the channel’s timestamp and counter used for input modes. Write a 1 to the Enable Measurements/Outputs register to begin the measurement of the input signal. Write a 0 to the Enable Measurements/Outputs register to stop the measurement of the input signal. The data can be read either while the measurements are being made on input signals or after stopping the measurements.

Reset Timer/Counter

Function:

Resets the measurement timestamp and counter for the channel.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x00FF FFFF

Read/Write:

Initialized Value:

Operational Settings:

Setting the bit for the associated channel to a 1 will:

* reset the timestamp used for the Pulse Measurements mode (1-2), Transition Timestamp mode (3-5), and Period Measurement mode (9) and Frequency Measurement mode (10)

* reset the counter used for Transition Counter mode (6-8)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Ch24

Ch23

Ch22

Ch21

Ch20

Ch19

Ch18

Ch17

D15

D14

D13

D12

D11

D10

Ch16

Ch15

Ch14

Ch13

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

FIFO Registers

The FIFO registers are used for the following input modes:

Pulse Measurements mode (1-2)
Transition Timestamp mode (3-5)
Period Measurement mode (9)
Frequency Measurement mode (10)

FIFO Buffer Data

Function:

The data stored in the FIFO Buffer Data is dependent on the input mode.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

N/A

Operational Settings:

Refer to examples in Input Modes.

FIFO Word Count

Function:

This is a counter that reports the number of 32-bit words stored in the FIFO buffer.

Type:

unsigned binary word (32-bit)

Data Range:

0 - 255 (0x0000 0000 to 0x0000 00FF)

Read/Write:

Initialized Value:

Operational Settings:

Every time a read operation is made from the FIFO Buffer Data register, the value in the FIFO Word Count register will be decremented by one. The maximum number of words that can be stored in the FIFO is 255.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Clear FIFO

Function:

Clears FIFO by resetting the FIFO Word Count register.

Type:

unsigned binary word (32-bit)

Data Range:

0 or 1

Read/Write:

Initialized Value:

N/A

Operational Settings:

Write a 1 to resets the Words in FIFO to zero; Clear FIFO register does not clear data in the buffer. A read to the buffer data will give “aged” data.

Bit

Description

D31:D1

Reserved. Set to 0

Set to 1 to reset the FIFO Word Count value to zero.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

FIFO Status

Function:

Sets the corresponding bit associated with the FIFO status type; there is a separate register for each channel.

Type:

unsigned binary word (32-bit)

Data Range:

See table

Read/Write:

Initialized Value:

Bit

Name

Description

D31:D4

Reserved

Set to 0

Empty

Set to 1 when FIFO Word Count = 0

Almost Empty

Set to 1 when FIFO Word Count ⇐ 63 (25%)

Almost Full

Set to 1 when FIFO Word Count >= 191 (75%)

Full

Set to 1 when FIFO Word Count = 255

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

Transition Count Registers

The Transition Count register are used for the following input modes:

Transition Counter mode (6-8)

Transition Count

Function:

Contains the count of the transitions depending on the configuration in the Mode Select register - Rising Edges, Falling Edges or All Edges.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Operational Settings:

Refer to examples in Transition Counter.

Frequency Measurement Registers

For the Frequency Measurement mode, the period to perform the frequency measurements must be specified in the Frequency Measurement Period register.

Frequency Measurement Period

Function:

When the Mode Select register is programmed for Frequency Measurement mode (10), the value in the Frequency Measurement Period is used as the time interval for counting the number of rising edge transitions within that interval.

Type:

unsigned binary word (32-bit)

Data Range:

0x0 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

Set the Frequency Measurement Period (LSB = 10 µs). Refer to examples in Frequency Measurement.

Output Modes Registers

After configuring the Mode Select register, write a 1 to the Enable Measurements/Outputs register to outputting the signal. Write a 0 to the Enable Measurements/Outputs register to stop the output signal.

PWM Registers

The PWM Period, PWM Pulse Width and PWM Output Polarity registers configure the PWM output signal. When the Mode Select register is configured for PWM Burst mode, the PWM Number of Cycles register is used to specify the number of cycles to repeat for the burst.

PWM Period

Function:

When the Mode Select register is programmed for PWM Continuous or PWM Burst mode (32-33), the value in the PWM Period is used as the time interval for outputting the PWM signal.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0001 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

Set the PWM Period (LSB = 10 µs). The PWM Period must be greater than the value set in the PWM Pulse Width register. Refer to examples in PWM Output.

PWM Pulse Width

Function:

When the Mode Select register is programmed for PWM Continuous or PWM Burst mode (32-33), the value in the PWM Pulse Width is used as the time interval of the “ON” state for outputting the PWM signal.

Type:

unsigned binary word (32-bit)

Data Range:

0x0 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

Set the PWM Pulse Width (LSB = 10 µs). The PWM Pulse Width must be less than the value set in the PWM Pulse Width register. Refer to examples in PWM Output.

PWM Output Polarity

Function:

When the Mode Select register is programmed for PWM Continuous or PWM Burst mode (32-33), the value in the PWM Output Polarity is used to specify whether the PWM output signal starts with a rising edge (Positive (0)), or a falling edge (Negative (1)).

Type:

unsigned binary word (32-bit)

Data Range:

0x0 to 0x00FF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

The PWM Output Polarity register is used to program the starting edge of the PWM Pulse Period (rising or falling). When the PWM output Polarity is set to Positive (0), the output will start with a rising edge, when it’s set to Negative (1), the output will start with a falling edge. The default is Positive (0), which is set when the PWM Polarity bit is 0. Refer to examples in PWM Output.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Ch24

Ch23

Ch22

Ch21

Ch20

Ch19

Ch18

Ch17

D15

D14

D13

D12

D11

D10

Ch16

Ch15

Ch14

Ch13

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

PWM Number of Cycles

Function:

When the Mode Select register is programmed for PWM Burst mode (33), the value in the PWM Number of Cycles is used to specify the number of times to repeat the PWM output signal.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0001 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

Set the number of times to output the PWM signal. Refer to examples in PWM Output.

Pattern Generator Registers

The Pattern RAM registers are a 64K block of unsigned 32-bit words allocated to specify the data pattern for the output channels. The Pattern RAM Start Address, Pattern RAM End Address, Pattern RAM Period and Pattern RAM Control registers configure the Pattern Generator output signals. When the Pattern RAM Control register is configured for Burst, the Pattern RAM Number of Cycles specify the number of cycles to repeat the pattern for the burst.

Pattern RAM

Function:

Pattern Generator Memory Block from 0x40000 to 0x7FFFC.

Type:

unsigned binary word (32-bit)

Address Range:

0x0000 0000 to 0x00FF FFFF

Read/Write: R

Initialized Value:

Operational Settings:

64K block of unsigned 32-bit words. The data in each 32-bit word is bit-mapped per channel.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Ch24

Ch23

Ch22

Ch21

Ch20

Ch19

Ch18

Ch17

D15

D14

D13

D12

D11

D10

Ch16

Ch15

Ch14

Ch13

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Pattern RAM Start Address

Function:

When the Mode Select register is programmed for Pattern Generator mode (34), the Pattern RAM Start Address register specifies the starting address within the Pattern RAM block registers to use for the output.

Type:

unsigned binary word (32-bit)

Data Range:

0x0004 0000 to 0x0007 FFFC

Read/Write:

R/W

Initialized Value:

Operational Settings:

The value in the Pattern RAM Start Address must be LESS than the value in the Pattern RAM End Address.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Pattern RAM End Address

Function:

When the Mode Select register is programmed for Pattern Generator mode (34), the Pattern RAM End Address register specifies the end address within the Pattern RAM block registers to use for the output.

Type:

unsigned binary word (32-bit)

Data Range:

0x40000 to 0x7FFFC

Read/Write:

R/W

Initialized Value:

Operational Settings:

The value in the Pattern RAM End Address must be GREATER than the value in the Pattern RAM Start Address.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Pattern RAM Period

Function:

When the Mode Select register is programmed for Pattern Generator mode (34), the value in the Pattern RAM Period is used as the time interval for outputting the Pattern Generator signals.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0001 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

Set the Pattern RAM Period (LSB = 10 µs).

Pattern RAM Control

Function:

When the Mode Select register is programmed for Pattern Generator mode (34), the value in the Pattern RAM Control is used to control the outputting of the Pattern Generator signals.

Type:

unsigned binary word (32-bit)

Data Range:

See table

Read/Write:

R/W

Initialized Value:

Operational Settings:

Configures the Pattern Generator for Continuous, Burst with a specified number of cycles, Pause, or External Trigger from input from Channel 1.

Note	When any channel is configured for External Trigger Pattern Generator mode, Channel 1 MUST be set as an input.

Bits

Description

D31-D5

Reserved. Set to 0

Falling Edge External Trigger - Channel 1 used as the input for the trigger

Rising Edge External Trigger - Channel 1 used as the input for the trigger

Pause

Burst Mode - value in Pattern RAM Number of Cycles register defines number of cycles to output

Enable Pattern Generator

Values

Description

0x0000

Disable Pattern Generator, Continuous Mode, No External Trigger

0x0001

Enable Pattern Generator, Continuous Mode, No External Trigger

0x0002

Disable Pattern Generator, Burst Mode, No External Trigger

0x0003

Enable Pattern Generator, Burst Mode, No External Trigger

0x0005

Enable Pattern Generator, Continuous Mode, Pause, No External Trigger

0x0007

Enable Pattern Generator, Burst Mode, Pause, No External Trigger

0x0008

Disable Pattern Generator, Continuous Mode, Rising External Trigger

0x0009

Enable Pattern Generator, Continuous Mode, Rising External Trigger

0x000A

Disable Pattern Generator, Burst Mode, Rising External Trigger

0x000B

Enable Pattern Generator, Burst Mode, Rising External Trigger

0x000D

Enable Pattern Generator, Continuous Mode, Pause, Rising External Trigger

0x000F

Enable Pattern Generator, Burst Mode, Pause, Rising External Trigger

0x1000

Disable Pattern Generator, Continuous Mode, Falling External Trigger

0x1001

Enable Pattern Generator, Continuous Mode, Falling External Trigger

0x1002

Disable Pattern Generator, Burst Mode, Falling External Trigger

0x1003

Enable Pattern Generator, Burst Mode, Falling External Trigger

0x1005

Enable Pattern Generator, Continuous Mode, Pause, Falling External Trigger

0x1007

Enable Pattern Generator, Burst Mode, Pause, Falling External Trigger

0x0004, 0x0006, 0x000C, 0x000E, 0x1004, 0x1006, 0x1008-0x100F

Invalid

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

Pattern RAM Number of Cycles

Function:

When the Mode Select register is programmed for Pattern Generator mode (34) and the Pattern RAM Control register is set for Burst mode, the value in the Pattern RAM Number of Cycles is used to specify the number of times to repeat the pattern output signal.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0001 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

Set the number of times to output the pattern.

FUNCTION REGISTER MAP

Key:

Configuration/Control

Status

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a '1' to a bit set to '1' will set the bit to '0').

MODE SELECT REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x300C

Mode Select Ch 1

R/W

0x308C

Mode Select Ch 2

R/W

0x310C

Mode Select Ch 3

R/W

0x318C

Mode Select Ch 4

R/W

0x320C

Mode Select Ch 5

R/W

0x328C

Mode Select Ch 6

R/W

0x330C

Mode Select Ch 7

R/W

0x338C

Mode Select Ch 8

R/W

0x340C

Mode Select Ch 9

R/W

0x348C

Mode Select Ch 10

R/W

0x350C

Mode Select Ch 11

R/W

0x358C

Mode Select Ch 12

R/W

0x360C

Mode Select Ch 13

R/W

0x368C

Mode Select Ch 14

R/W

0x370C

Mode Select Ch 15

R/W

0x378C

Mode Select Ch 16

R/W

0x380C

Mode Select Ch 17

R/W

0x388C

Mode Select Ch 18

R/W

0x390C

Mode Select Ch 19

R/W

0x398C

Mode Select Ch 20

R/W

0x3A0C

Mode Select Ch 21

R/W

0x3A8C

Mode Select Ch 22

R/W

0x3B0C

Mode Select Ch 23

R/W

0x3B8C

Mode Select Ch 24

R/W

0x2000

Enable Measurements/Outputs

R/W

INPUT MODES REGISTER

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x2004

Reset Timer/Counter

FIFO REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x3000

FIFO Buffer Data Ch 1

0x3004

FIFO Word Count Ch 1

0x3080

FIFO Buffer Data Ch 2

0x3084

FIFO Word Count Ch 2

0x3100

FIFO Buffer Data Ch 3

0x3104

FIFO Word Count Ch 3

0x3180

FIFO Buffer Data Ch 4

0x3184

FIFO Word Count Ch 4

0x3200

FIFO Buffer Data Ch 5

0x3204

FIFO Word Count Ch 5

0x3280

FIFO Buffer Data Ch 6

0x3284

FIFO Word Count Ch 6

0x3300

FIFO Buffer Data Ch 7

0x3304

FIFO Word Count Ch 7

0x3380

FIFO Buffer Data Ch 8

0x3384

FIFO Word Count Ch 8

0x3400

FIFO Buffer Data Ch 9

0x3404

FIFO Word Count Ch 9

0x3480

FIFO Buffer Data Ch 10

0x3484

FIFO Word Count Ch 10

0x3500

FIFO Buffer Data Ch 11

0x3504

FIFO Word Count Ch 11

0x3580

FIFO Buffer Data Ch 12

0x3584

FIFO Word Count Ch 12

0x3600

FIFO Buffer Data Ch 13

0x3604

FIFO Word Count Ch 13

0x3680

FIFO Buffer Data Ch 14

0x3684

FIFO Word Count Ch 14

0x3700

FIFO Buffer Data Ch 15

0x3704

FIFO Word Count Ch 15

0x3780

FIFO Buffer Data Ch 16

0x3784

FIFO Word Count Ch 16

0x3800

FIFO Buffer Data Ch 17

0x3804

FIFO Word Count Ch 17

0x3880

FIFO Buffer Data Ch 18

0x3884

FIFO Word Count Ch 18

0x3900

FIFO Buffer Data Ch 19

0x3904

FIFO Word Count Ch 19

0x3980

FIFO Buffer Data Ch 20

0x3984

FIFO Word Count Ch 20

0x3A00

FIFO Buffer Data Ch 21

0x3A04

FIFO Word Count Ch 21

0x3A80

FIFO Buffer Data Ch 22

0x3A84

FIFO Word Count Ch 22

0x3B00

FIFO Buffer Data Ch 23

0x3B04

FIFO Word Count Ch 23

0x3B80

FIFO Buffer Data Ch 24

0x3B84

FIFO Word Count Ch 24

0x3008

FIFO Status Ch 1

0x3088

FIFO Status Ch 2

0x3108

FIFO Status Ch 3

0x3188

FIFO Status Ch 4

0x3208

FIFO Status Ch 5

0x3288

FIFO Status Ch 6

0x3308

FIFO Status Ch 7

0x3388

FIFO Status Ch 8

0x3408

FIFO Status Ch 9

0x3488

FIFO Status Ch 10

0x3508

FIFO Status Ch 11

0x3588

FIFO Status Ch 12

0x3608

FIFO Status Ch 13

0x3688

FIFO Status Ch 14

0x3708

FIFO Status Ch 15

0x3788

FIFO Status Ch 16

0x3808

FIFO Status Ch 17

0x3888

FIFO Status Ch 18

0x3908

FIFO Status Ch 19

0x3988

FIFO Status Ch 20

0x3A08

FIFO Status Ch 21

0x3A88

FIFO Status Ch 22

0x3B08

FIFO Status Ch 23

0x3B88

FIFO Status Ch 24

0x2008

Reset FIFO

TRANSITION COUNT REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x3000

Transition Count Ch 1

0x3080

Transition Count Ch 2

0x3100

Transition Count Ch 3

0x3180

Transition Count Ch 4

0x3200

Transition Count Ch 5

0x3280

Transition Count Ch 6

0x3300

Transition Count Ch 7

0x3380

Transition Count Ch 8

0x3400

Transition Count Ch 9

0x3480

Transition Count Ch 10

0x3500

Transition Count Ch 11

0x3580

Transition Count Ch 12

0x3600

Transition Count Ch 13

0x3680

Transition Count Ch 14

0x3700

Transition Count Ch 15

0x3780

Transition Count Ch 16

0x3800

Transition Count Ch 17

0x3880

Transition Count Ch 18

0x3900

Transition Count Ch 19

0x3980

Transition Count Ch 20

0x3A00

Transition Count Ch 21

0x3A80

Transition Count Ch 22

0x3B00

Transition Count Ch 23

0x3B80

Transition Count Ch 24

FREQUENCY MEASUREMENT REGISTERS

NOTE: Base Address - 0x9010 C000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x3014

Frequency Measurement Period Ch 1

R/W

0x3094

Frequency Measurement Period Ch 2

R/W

0x3114

Frequency Measurement Period Ch 3

R/W

0x3194

Frequency Measurement Period Ch 4

R/W

0x3214

Frequency Measurement Period Ch 5

R/W

0x3294

Frequency Measurement Period Ch 6

R/W

0x3314

Frequency Measurement Period Ch 7

R/W

0x3394

Frequency Measurement Period Ch 8

R/W

0x3414

Frequency Measurement Period Ch 9

R/W

0x3494

Frequency Measurement Period Ch 10

R/W

0x3514

Frequency Measurement Period Ch 11

R/W

0x3594

Frequency Measurement Period Ch 12

R/W

0x3614

Frequency Measurement Period Ch 13

R/W

0x3694

Frequency Measurement Period Ch 14

R/W

0x3714

Frequency Measurement Period Ch 15

R/W

0x3794

Frequency Measurement Period Ch 16

R/W

0x3814

Frequency Measurement Period Ch 17

R/W

0x3894

Frequency Measurement Period Ch 18

R/W

0x3914

Frequency Measurement Period Ch 19

R/W

0x3994

Frequency Measurement Period Ch 20

R/W

0x3A14

Frequency Measurement Period Ch 21

R/W

0x3A94

Frequency Measurement Period Ch 22

R/W

0x3B14

Frequency Measurement Period Ch 23

R/W

0x3B94

Frequency Measurement Period Ch 24

R/W

PWM REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x3014

PWM Period Ch 1

R/W

0x3010

PWM Pulse Width Ch 1

R/W

0x3094

PWM Period Ch 2

R/W

0x3090

PWM Pulse Width Ch 2

R/W

0x3114

PWM Period Ch 3

R/W

0x3110

PWM Pulse Width Ch 3

R/W

0x3194

PWM Period Ch 4

R/W

0x3190

PWM Pulse Width Ch 4

R/W

0x3214

PWM Period Ch 5

R/W

0x3210

PWM Pulse Width Ch 5

R/W

0x3294

PWM Period Ch 6

R/W

0x3290

PWM Pulse Width Ch 6

R/W

0x3314

PWM Period Ch 7

R/W

0x3310

PWM Pulse Width Ch 7

R/W

0x3394

PWM Period Ch 8

R/W

0x3390

PWM Pulse Width Ch 8

R/W

0x3414

PWM Period Ch 9

R/W

0x3410

PWM Pulse Width Ch 9

R/W

0x3494

PWM Period Ch 10

R/W

0x3490

PWM Pulse Width Ch 10

R/W

0x3514

PWM Period Ch 11

R/W

0x3510

PWM Pulse Width Ch 11

R/W

0x3594

PWM Period Ch 12

R/W

0x3590

PWM Pulse Width Ch 12

R/W

0x3614

PWM Period Ch 13

R/W

0x3610

PWM Pulse Width Ch 13

R/W

0x3694

PWM Period Ch 14

R/W

0x3690

PWM Pulse Width Ch 14

R/W

0x3714

PWM Period Ch 15

R/W

0x3710

PWM Pulse Width Ch 15

R/W

0x3794

PWM Period Ch 16

R/W

0x3790

PWM Pulse Width Ch 16

R/W

0x3814

PWM Period Ch 17

R/W

0x3810

PWM Pulse Width Ch 17

R/W

0x3894

PWM Period Ch 18

R/W

0x3890

PWM Pulse Width Ch 18

R/W

0x3914

PWM Period Ch 19

R/W

0x3910

PWM Pulse Width Ch 19

R/W

0x3994

PWM Period Ch 20

R/W

0x3990

PWM Pulse Width Ch 20

R/W

0x3A14

PWM Period Ch 21

R/W

0x3A10

PWM Pulse Width Ch 21

R/W

0x3A94

PWM Period Ch 22

R/W

0x3A90

PWM Pulse Width Ch 22

R/W

0x3B14

PWM Period Ch 23

R/W

0x3B10

PWM Pulse Width Ch 23

R/W

0x3B94

PWM Period Ch 24

R/W

0x3B90

PWM Pulse Width Ch 24

R/W

0x3018

PWM Number of Cycles Ch 1

R/W

0x3098

PWM Number of Cycles Ch 2

R/W

0x3118

PWM Number of Cycles Ch 3

R/W

0x3198

PWM Number of Cycles Ch 4

R/W

0x3218

PWM Number of Cycles Ch 5

R/W

0x3298

PWM Number of Cycles Ch 6

R/W

0x3318

PWM Number of Cycles Ch 7

R/W

0x3398

PWM Number of Cycles Ch 8

R/W

0x3418

PWM Number of Cycles Ch 9

R/W

0x3498

PWM Number of Cycles Ch 10

R/W

0x3518

PWM Number of Cycles Ch 11

R/W

0x3598

PWM Number of Cycles Ch 12

R/W

0x3618

PWM Number of Cycles Ch 13

R/W

0x3698

PWM Number of Cycles Ch 14

R/W

0x3718

PWM Number of Cycles Ch 15

R/W

0x3798

PWM Number of Cycles Ch 16

R/W

0x3818

PWM Number of Cycles Ch 17

R/W

0x3898

PWM Number of Cycles Ch 18

R/W

0x3918

PWM Number of Cycles Ch 19

R/W

0x3998

PWM Number of Cycles Ch 20

R/W

0x3A18

PWM Number of Cycles Ch 21

R/W

0x3A98

PWM Number of Cycles Ch 22

R/W

0x3B18

PWM Number of Cycles Ch 23

R/W

0x3B98

PWM Number of Cycles Ch 24

R/W

0x200C

PWM Output Polarity

R/W

PATTERN GENERATOR REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0004_0000 to 0x0007_FFFC

Pattern RAM

R/W

0x2010

Pattern RAM Period

R/W

0x2014

Pattern RAM Start Address

R/W

0x2018

Pattern RAM End Address

R/W

0x201C

Pattern RAM Control

R/W

0x2020

Pattern RAM Number of Cycles

R/W

REVISION HISTORY

Module Manual - Enhanced IO Functionality Revision History

Revision

Revision Date

Description

2021-11-30

C08896; Transition manual to docbuilder format - no technical info change.

DOCS.NAII REVISIONS

Revision Date

Description

2026-03-02

Formatting updates to document; no technical changes.

NAI Cares

Edit this on GitLab

North Atlantic Industries (NAI) is a leading independent supplier of Embedded I/O Boards, Single Board Computers, Rugged Power Supplies, Embedded Systems and Motion Simulation and Measurement Instruments for the Military, Aerospace and Industrial Industries. We accelerate our clients’ time-to-mission with a unique approach based on a Configurable Open Systems Architecture™ (COSA®) that delivers the best of both worlds: custom solutions from standard COTS components.

We have built a reputation by listening to our customers, understanding their needs, and designing, testing and delivering board and system-level products for their most demanding air, land and sea requirements. If you have any applications or questions regarding the use of our products, please contact us for an expedient solution.

Please visit us at: www.naii.com or select one of the following for immediate assistance:

Call Us

(631) 567-1100

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	N	PE

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Z	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	N	PE

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Z	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

CM2 Manual

Table of Contents

Integrator Resources

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	N	PE

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Z	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D