Integrator Resources

The official home for NAI Support

Not sure where to start? Try Quick Start Guide or ask a question below!

Toggle Components with Visual Button
JavaScript Form Processing

High-Density Synchro Simulator

INTRODUCTION

Modules DS and DR are Synchro/Resolver Simulation Modules. Synchros and Resolvers are transformer-type voltage/current transducers that convert a shaft or other rotating device’s angular position and/or velocity to a multi-wire AC electrical signal. Both deliver signals proportional to the Sine and/or Cosine of the shaft angle. A Digital-to-Synchro or Digital-to-Resolver simulator is used to generate digital representations of angle/ commands to corresponding Synchro/Resolver AC signals.

A wide variety of DS and DR modules are available to cover the range of excitation voltages/frequency, include extensive field-parameter programmability, and provide a full operating envelope choice for simulating virtually any type Synchro or Resolver. By eliminating the need for external transformers and operating with lower AC reference frequencies, these solid-state designs offer huge space savings.

See Model Designations table below for a description of the available DS and DR configurations.

Module ID

No. of Channels

Full Scale Output Voltage (RMS VL-L)

Output Load

Frequency Range (Hz)

Synchro

Resolver

DS1

DR1

1*

2-28

3 VA @ 28 VRMS

47-1k

DS2

DR2

1*

2-28

3 VA @ 28 VRMS

1k-5k

DS3

DR3

1*

2-28

3 VA @ 28 VRMS

5k-10k

DS4

DR4

1*

2-28

3 VA @ 28 VRMS

10k-20k

DS5

DR5

1*

28-90

3 VA @ 90 VRMS

47-1k

DS8

1

90

8 VA @ 90 VRMS

400

DSA

DRA

2

2-28

1.5 VA @ 28 VRMS

47-1k

DSB

DRB

2

2-28

1.5 VA @ 28 VRMS

1k-5k

DSC

DRC

2

2-28

1.5 VA @ 28 VRMS

5k-10k

DSD

DRD

2

2-28

1.5 VA @ 28 VRMS

10k-20k

DSE

DRE

2

28-90

2.2 VA @ 90 VRMS

47-1k

DSJ

DRJ

3

2-28

0.5 VA @ 28 VRMS

47-1k

DSK

DRK

3

2-28

0.5 VA @ 28 VRMS

1k-5k

DSL

DRL

3

2-28

0.5 VA @ 28 VRMS

5k-10k

DSM

DRM

3

2-28

0.5 VA @ 28 VRMS

10k-20k

DSN

DRN

3

28-90

0.5 VA @ 90 VRMS

47-1k

There are three types of D/S and D/R modules:

  • 3-Channel Modules: These high-density modules have a lower power output drive (0.5 VA per channel, maximum). The lower power output drive is ideal for driving solid-state input instruments, gauges, and Synchro Booster Amplifiers (SBAs).

  • 2-Channel Modules: The 2-channel modules have a standard power output of 2.2 VA (28-90 VLL or 1.5 VA (2-28 VLL) per channel, maximum.

  • Single-Channel Modules: The single-channel modules have a high-power output drive capability (3 VA per channel, maximum).

          * Contact factory for single channel availability

PRINCIPLE OF OPERATION

The Digital-to-Synchro/Resolver module includes optional format selections (synchro or resolver). A background calibration feature (pending), that is totally transparent to the operation of the channels, maintains outputs for all load and environmental conditions. Each channel can be programmed for a different line-to-line voltage, which can be programmed for either ratio or fixed output mode. When set to ratio mode, each channel utilizes a transformation ratio (TR) which sets the maximum output signal voltage in relation to the input reference voltage (TR = Max Output Voltage/Reference Voltage). This ratiometric design eliminates errors caused by variations in reference voltage by allowing the output voltage to adjust with it. When set to fixed mode, the output voltage is absolute and does not change with reference voltage variations. Module power ON/OFF capability provided for shutting down channels.

Built-In Test (BIT)/Diagnostic Capability

The board supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are logically ORed together and stored in the BIT Dynamic Status and BIT Latched Status registers.

Power-On Self-Test (POST)/Power-on BIT (PBIT)/Start-up BIT (SBIT)

This board features a power-on self-test that will do an accuracy check of each channel and report the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Latched Status.

Continuous Background Built-In Test

The background Built-In-Test or Continuous BIT (CBIT) (“D2”) runs in the background where each channel is checked to a test accuracy of 0.2% FS. The testing is totally transparent to the user, requires no external programming, and has no effect on the operation of the module or card.

The technique used by the continuous background BIT (CBIT) test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. Note, the interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained; i.e. at a ten second interval, not a 10-millisecond interval). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and a fail state.

Initiate Built-In Test

The DS and DR modules supports an off-line Initiated Built-In Test (IBIT) (“D3”).

IBIT test starts an initiated BIT test that utilizes an internal stimulus to generate and test the full-scale positional range to a default test accuracy of 0.1% full scale range. IBIT test cycle is completed within 30 seconds and the result can be read from the BIT status registers when IBIT bit changes from 1 to 0.

Status and Interrupts

The DS (DR) Simulation Module provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

Module Common Registers

The DS (DR) Simulation Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

REGISTER DESCRIPTIONS

The register descriptions provide the register name, Function Address Offset, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Control Registers

Power On/Off

Function: Turns on the selected channel and initiates output.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 - 0x0000 0007 (for supporting up to 3 channels)

Read/Write: R/W

Initialized Value: 0x0000 0000

Operational Settings: To turn on the selected channel, set the bit to 1.

Table 1. Power On/Off

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

Ch3

Ch2

Ch1

DS Set Angle

Function: Sets synchro or resolver angle data in each channel for single-speed or multi-speed applications.

Type: unsigned binary word (32-bit)

Range: 0 to 359.9999 degrees

Read/Write: R/W

Initialized Value: 0°

Operational Settings: For single-speed applications (Ratio=1), write a 32-bit integer to the corresponding channel D/S Data Register.

          WORD = Angle / (360/ 2^32)

LSB is 360/232 or approximately 0.00000008382 degrees. The upper 24 bits define the angle, while the lower 8 bits are at zero.

The module can automatically simulate two-speed applications (applies only to multiple channel modules. By entering a ratio in the DS Ratio Mode Ch ½ register, the fine channel (channel 2) will automatically output an angle proportional to the programmed coarse channel (channel 1) angle, multiplied by the ratio programmed.

Table 2. DS Set Angle

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

180

90

45

22.5

11.25

5.625

2.813

1.406

.703

.352

.176

.088

.044

.022

.011

.0055

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

.00274

.00137

.00068

.00034

.00017

.00008

.00004

.00002

0

0

0

0

0

0

0

0

DS Set Voltage

Function: Sets signal voltage “VL-L” to a corresponding register.

Type: unsigned binary word (32-bit)

Range: 2-28 or 28-90 VL-L depending on model

Read/Write: R/W

Initialized Value: 26 VL-L for low voltage modules and 90 VL-L for high voltage modules.

Operational Settings: The output voltage is set with a resolution of 10 mVRMS. The setting is in integer decimal format.

For example, if channel 1 Signal (VL-L) voltage is to be 11.8 VRMS, the set word to the corresponding register would be 1180.

DS Expected Reference

Function: Sets reference voltage “VREF” to a corresponding register.

Type: unsigned binary word (32-bit)

Range: 26 VREF for low voltage module or 115 VREF for high voltage module

Read/Write: R/W

Initialized Value: 2 or 28 VL-L depending on model

Operational Settings: The input voltage is set with a resolution of 10 mVRMS. The setting is in integer decimal format.

For example, if channel 1 expected input REF voltage is 26.0 VRMS, the set word to the corresponding register would be 2600.

DS Set Phase Offset

Function: Enables setting the phase (in degrees) of each channel to an offset of the Reference.

Type: unsigned binary word (32-bit)

Range: ± 90°

Read/Write: R/W

Initialized Value: 0°

Operational Settings: The phase offset has 24-bit resolution put into the MSBs of the 32-bit word.

Word = Phase / (360/2^32%).

Table 3. DS Set Phase Offset

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

180

90

45

22.5

11.25

5.625

2.813

1.406

.703

.352

.176

.088

.044

.022

.011

.0055

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

.00274

.00137

.00068

.00034

.00017

.00008

.00004

.00002

0

0

0

0

0

0

0

0

DS Output Mode (Ratio/Fixed)

Function: Enables selection of either ratiometric (ratio) or absolute (fixed) mode output voltages.

Type: unsigned binary word (32-bit)

Range: NA

Read/Write: R/W

Initialized Value: 0 = Ratiometric

Operational Settings: Ratiometric Mode, when selected, will cause the output signal voltage of the channel to vary with the input Reference Voltage. Fixed Mode, when selected, will cause the output signal voltage of the channel NOT to vary with the input Reference Voltage. Set corresponding channel bit to 0 for Ratiometric Mode. Set corresponding channel bit to 1 for Fixed Mode.

Table 4. DS Output Mode (Ratio/Fixed)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

Ch3

Ch2

Ch1

Rotation Mode - Continuous or Start/Stop

Function: Sets channel for continuous or start/stop rotation.

Type: unsigned binary word (32-bit)

Range: NA

Read/Write: R/W

Initialized Value: NA

Operational Settings: For continuous rotation, set the corresponding channel bit to 0. For rotation to cease at a designated stop angle, set the bit to 1. For 2-speed applications, only the odd (coarse) channel needs to be programmed (Ch1).

Table 5. Rotation Mode - Continuous, Start/Stop

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

Ch3

Ch2

Ch1

Stop Angle

Function: Stops rotation on selected channel when desired stop angle is reached.

Type: unsigned binary word (32-bit)

Range: 0 to 359.9999 degrees

Read/Write: R/W

Initialized Value: 0

Operational Settings: Word = Angle /(360/232)

Rotation Rate+_

Function: Sets rotation rate for selected channel.

Type: signed binary word (32-bit)

Range: +/-9.999 dps

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 2’s complement number representing the desired rotation rate. LSB = 0.015°/sec.

For example, 12 RPS = (12 x 360°/0.015° = 288000 = 46500h), -12 RPS = (-12 x 360°/0.015° = -288000 = FFFB9B00h)

Start Rotation

Function: Set this register after Rotation Rate register has been set. Will start rotating in continuous or start/stop rotation mode.

Type: unsigned binary word (32-bit)

Range: NA

Read/Write: R/W

Initialized Value: 0

Operational Settings: To start rotation for the corresponding channel, write a 1 to the corresponding channel.

Table 6. Start Rotation

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

Ch3

Ch2

Ch1

Stop Rotation

Function: Stops a channel from rotating when a 1 is written to the corresponding bit location.

Type: unsigned binary word (32-bit)

Range: NA

Read/Write: R/W

Initialized Value: 0

Operational Settings: To stop rotation for the corresponding channel, write a 1 to the corresponding channel.

Table 7. Stop Rotation

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

Ch3

Ch2

Ch1

DS Ratio Mode Ch 1/2

Function: Sets the ratio from the coarse channel (channel 1) to the fine channel (channel 2).

Type: unsigned binary word (32-bit)

Range: 1 to 255

Read/Write: R/W

Initialized Value: 1

Operational Settings: Set desired ratio between coarse (channel 1) and fine (channel 2) channels to be used as a two-speed channel.

Example 1: In single speed mode, set this register to 1. This will allow channel 2 to be controlled by its own set angle register.

Example 2: For a 36:1 ratio, set this register to 36. Now, the set angle for channel 2 will be equal to the set angle of channel 1, multiplied by 36.

Measurement Registers

Wrap Angle

Function: Measures the output angle.

Type: unsigned binary word (32-bit)

Range: 0-359.9999

Read/Write: R

Initialized Value: 0

Operational Settings: Measured angle in degrees = value * (360/232).

Table 8. Wrap Angle

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

180

90

45

22.5

11.25

5.625

2.813

1.406

.703

.352

.176

.088

.044

.022

.011

.0055

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

.00274

.00137

.00068

.00034

.00017

.00008

.00004

.00002

0

0

0

0

0

0

0

0

Velocity

Function: Reads CW and CCW velocity of each channel in degrees per second (dps).

Type: unsigned binary word (32-bit)

Range: ±10,000 dps

Read/Write: R

Initialized Value: 0

Operational Settings: Velocity registers of each channel are read as a two’s complement word, with 0x7FFFh FFFF being maximum CW rotation, and 0x8000 0000 being maximum CCW rotation. LSB = 0.015°/sec.

To convert a velocity word to dps: Velocity in dps = value * 0.015 (0.015 degree/second resolution)

Table 9. Velocity

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

Measured Frequency

Function: Reads each channel’s input reference frequency.

Type: unsigned binary word (32-bit)

Range: Depends on model

Read/Write: R

Initialized Value: 0 Hz

Operational Settings: The input reference frequency is reported to a resolution of 1 Hz. The output is in integer decimal format. For example, if channel 1 input excitation is 400 Hz, the output measurement word from the corresponding register would be 400.

Measured Signal Voltage

Function: Reads each channel’s output signal voltage VL-L.

Type: 32-bit unsigned integer

Range: unsigned binary word (32-bit)

Read/Write: R

Initialized Value: 0 VLL

Operational Settings: The output voltage is reported to a resolution of 10 mVRMS. The output is in integer decimal format. For example, if channel 1 output signal voltage is 11.8 VRMS, the output measurement word from the corresponding register would be 1180.

Measured Reference Voltage

Function: Reads each channel’s input signal reference voltage (VREF).

Type: 32-bit unsigned integer

Range: unsigned binary word (32-bit)

Read/Write: R

Initialized Value: 0 VREF on power up

Operational Settings: The input voltage is reported to a resolution of 10 mVRMS. The output is in integer decimal format. For example, if channel 1 input VREF voltage is 26.0 VRMS, the output measurement word from the corresponding register would be 2600.

Measured Current

Function: Displays the measured current on the channel’s output.

Type: unsigned binary word (32-bit)

Range: NA

Read/Write: R

Initialized Value: 0

Operational Settings: Measures current in milliamps.

Threshold Programming Registers

Signal Loss Threshold

Function: Programmable status threshold to indicate when the measured VLL falls below this value.

Type: unsigned binary word (32-bit)

Range: 0 to 90 VL-L

Read/Write: R/W Initialized Value: 80% of default DS output voltage.

Operational Settings: The signal loss detection circuitry can be tailored to report a signal loss (at Signal Loss Status register) at a user defined threshold. This threshold can be set to a resolution of 10 mVL-L. Program the threshold by writing the value of the voltage threshold in integer decimal format. For example, if Channel 1 signal loss voltage threshold is to be 7 VL-L, the programmed word to the corresponding register would be 700 (2BCh).

Reference Loss Threshold

Function: Programmable status threshold to indicate when the measured VREF falls below this value.

Type: unsigned binary word (32-bit)

Range: 0 to 115 Vrms

Read/Write: R/W

Initialized Value: 80% of the default expected reference

Operational Settings: The reference loss detection circuitry can be tailored to report a reference loss at a user defined threshold. This threshold can be set to a resolution of 10 mVrms. Program the threshold by writing the value of the voltage threshold in integer decimal format. For example, if channel 1 input reference loss voltage threshold is to be 20 VRMS, the programmed word to the corresponding register would be 2000 (7D0h).

Test Registers

This module features a power-on self-test that will perform an accuracy check on each channel. In addition, two different tests, one on-line (CBIT) and one off-line (IBIT), can be selected. External reference voltage is not required for any of these tests.

Test Enabled

Function: Set bit in this register to enable associated Built-In Self-Test IBIT and CBIT.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 to 0x000D

Read/Write: R/W

Initialized Value: 0x4 (CBIT Test Enabled)

Operational Settings: BIT tests include an on-line (CBIT) test and an off-line (IBIT) test. Failures in the BIT tests are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects a failure.

Table 10. Test Enabled

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

IBIT Test D

CBIT Test 1

0

0

Test CBIT Verify

Function: Allows user to verify if the CBIT test is running.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: User can write any value to this register. If CBIT test is running, after a minimum of 10ms the value read back will be 0x0000 0055, otherwise the value read back will be the value written.

Module Common Registers

Refer to “Module Common Registers Module Manual” for the register descriptions.

Status and Interrupt Registers

The DS (DR) Simulation Module provides status registers for BIT, Signal Loss, Reference Loss, Phase Lock, DS Rotation and Overcurrent.

Channel Status Enabled

Function: Determines whether to update the status for the channels. The feature can be used to “mask' status bits of unused channels in status registers that are bitmapped by channel

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 - 0x0000 FFFF

Read/Write: R/W

Initialized Value: 0x0000 FFFF

Operational Settings: When the bit corresponding to a given channel in the Channel Status Enabled register is not enabled (0), the statuses will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status, Signal Loss Status, Reference Loss Status, Phase Lock Status, DS Rotation Status and Overcurrent Status). When the bit corresponding to a given channel is enabled (1), it will allow the statuses for that channel to be updated.

Table 11. Channel Status Enabled

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 12. BIT Status

BIT Dynamic Status

BIT Latched Status

BIT Interrupt Enable

BIT Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

CH3

CH2

CH1

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0007

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Signal Loss Status

There are four registers associated with the Signal Loss Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 13. Signal Loss Status

Signal Loss Dynamic Status

Signal Loss Latched Status

Signal Loss Interrupt Enable

Signal Loss Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

CH3

CH2

CH1

Function: Sets the corresponding bit associated with the channel’s Signal Loss error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0007

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Reference Loss Status

There are four registers associated with the Reference Loss Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 14. Reference Loss Status

Reference Loss Dynamic Status

Reference Loss Latched Status

Reference Loss Interrupt Enable

Reference Loss Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

CH3

CH2

CH1

Function: Sets the corresponding bit associated with the channel’s Reference Fault Low error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0007

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Phase Lock Status

There are four registers associated with the Phase Lock Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 15. Phase Lock Status

Phase Lock Dynamic Status

Phase Lock Latched Status

Phase Lock Interrupt Enable

Phase Lock Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

CH3

CH2

CH1

Function: Sets the corresponding bit associated with the channel’s Phase Lock error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0007

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

DS Rotation Status

There are four registers associated with the DS Rotation Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 16. DS Rotation Status

DS Rotation Dynamic Status

DS Rotation Latched Status

DS Rotation Interrupt Enable

DS Rotation Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

CH3

CH2

CH1

Function: Sets the corresponding bit associated with the channel’s DS Rotation error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0007

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Overcurrent Status

There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 17. Overcurrent Status

Overcurrent Dynamic Status

Overcurrent Latched Status

Overcurrent Interrupt Enable

Overcurrent Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

CH3

CH2

CH1

Function: Sets the corresponding bit associated with the channel’s Overcurrent error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0007

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector

Function: Set an identifier for the interrupt.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering

Function: Sets where to direct the interrupt.

Type: unsigned binary word (32-bit)

Data Range: See table Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME

1

Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)

2

Direct Interrupt to PCIe Bus

5

Direct Interrupt to cPCI Bus

6

FUNCTION REGISTER MAP

Key:

Bold Italic = Configuration/Control

Bold Underline = Measurement/Status

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a '1' to a bit set to '1' will set the bit to '0').

~ Data is always in Floating Point.

Control Registers

0x0250

Power On/Off++

R/W

++After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.

0x1000

DS Set Angle Ch 1

R/W

0x1004

DS Set Angle Ch 2

R/W

0x1008

DS Set Angle Ch 3

R/W.

0x1010

DS Set Angle Ch 1

R/W

0x1014

DS Set Angle Ch 2

R/W

0x1018

DS Set Angle Ch 3

R/W

0x1020

DS Expected Reference Ch 1

R/W

0x1024

DS Expected Reference Ch 2

R/W

0x1028

DS Expected Reference Ch 3

R/W

0x1030

DS Set Phase Offset Ch 1

R/W

0x1034

DS Set Phase Offset Ch 2

R/W

0x1038

DS Set Phase Offset Ch 3

R/W

0x1040

DS Output Mode (Ratio/Fixed) Ch 1

R/W

0x1044

DS Output Mode (Ratio/Fixed) Ch 2

R/W

0x1048

DS Output Mode (Ratio/Fixed) Ch 3

R/W

0x10F0

Rotation Mode - Continuous Start/Stop Ch 1

R/W

0x10F4

Rotation Mode - Continuous Start/Stop Ch 2

R/W

0x10F8

Rotation Mode - Continuous Start/Stop Ch 3

R/W

0x1100

Stop Angle Ch 1

R/W

0x1104

Stop Angle Ch 2

R/W

0x1108

Stop Angle Ch 3

R/W

0x1110

Rotation Rate Ch 1

R/W

0x1114

Rotation Rate Ch 2

R/W

0x1118

Rotation Rate Ch 3

R/W

0x1120

Start Rotation Ch 1-3

R/W

0x1124

Stop Rotation Rate Ch 1-3

R/W

0x1140

DS Ratio Mode Ch 1/2

R/W

Measurement Registers

0x1050

Wrap Angle Ch 1

R

0x1054

Wrap Angle Ch 2

R

0x1058

Wrap Angle Ch 3

R

0x1160

Velocity Ch 1

R

0x1164

Velocity Ch 2

R

0x1168

Velocity Ch 3

R

0x1070

Measured Frequency Ch 1

R

0x1074

Measured Frequency Ch 2

R

0x1078

Measured Frequency Ch 3

R

0x1080

Measured Signal Voltage Ch 1

R

0x1084

Measured Signal Voltage Ch 2

R

0x1088

Measured Signal Voltage Ch 3

R

0x1090

Measured Reference Voltage Ch 1

R

0x1094

Measured Reference Voltage Ch 2

R

0x1098

Measured Reference Voltage Ch 3

R

0x10A0

Measured Current Ch 1

R

0x10A4

Measured Current Ch 2

R

0x10A8

Measured Current Ch 3

R

Threshold Programming Registers

0x10B0

Signal Loss Threshold Ch 1

R/W

0x10B4

Signal Loss Threshold Ch 2

R/W

0x10B8

Signal Loss Threshold Ch 3

R/W

0x10C0

Reference Loss Threshold Ch 1

R/W

0x10C4

Reference Loss Threshold Ch 2

R/W

0x10C8

Reference Loss Threshold Ch 3

R/W

Module Common Registers

Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.

Status and Interrupt Registers

0x02B0

Channel Status Enabled

R/W

Test Registers

0x0248

Test Enabled

R/W

0x024C

Test Verify

R/W

Status Registers

Bit Status

0x0800

Dynamic Status

R

0x0804

Latched Status*

R/W

0x0808

Interrupt Enable

R/W

0x080C

Set Edge/Level Interrupt

R/W

Signal Loss Status

0x0810

Dynamic Status

R

0x0814

Latched Status*

R/W

0x0818

Interrupt Enable

R/W

0x081C

Set Edge/Level Interrupt

R/W

Reference Loss Status

0x0820

Dynamic Status

R

0x0824

Latched Status*

R/W

0x0828

Interrupt Enable

R/W

0x082C

Set Edge/Level Interrupt

R/W

Phase Lock Status

0x0830

Dynamic Status

R

0x0834

Latched Status*

R/W

0x0838

Interrupt Enable

R/W

0x083C

Set Edge/Level Interrupt

R/W

DS Rotation Status

0x0840

Dynamic Status

R

0x0844

Latched Status*

R/W

0x0848

Interrupt Enable

R/W

0x084C

Set Edge/Level Interrupt

R/W

Overcurrent Status

0x0850

Dynamic Status

R

0x0854

Latched Status*

R/W

0x0858

Interrupt Enable

R/W

0x085C

Set Edge/Level Interrupt

R/W

Interrupt Registers

The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.

0x0500

Module 1 Interrupt Vector 1 - BIT

R/W

0x0504

Module 1 Interrupt Vector 2 - Signal Loss

R/W

0x0508

Module 1 Interrupt Vector 3 - Reference Loss

R/W

0x050C

Module 1 Interrupt Vector 4 - Phase Lock

R/W

0x0510

Module 1 Interrupt Vector 5 - DS Rotation

R/W

0x0514

Module 1 Interrupt Vector 6 - Overcurrent

R/W

0x0518 to 0x057C

Module 1 Interrupt Vector 7-32 - Reserved

R/W

0x0600

Module 1 Interrupt Steering 1 - BIT

R/W

0x0604

Module 1 Interrupt Steering 2 - Signal Loss

R/W

0x0608

Module 1 Interrupt Steering 3 - Reference Loss

R/W

0x060C

Module 1 Interrupt Steering 4 - Phase Lock

R/W

0x0610

Module 1 Interrupt Steering 5 - DS Rotation

R/W

0x0614

Module 1 Interrupt Steering 6 - Overcurrent

R/W

0x0618 to 0x067C

Module 1 Interrupt Steering 7-32 - Reserved

R/W

0x0700

Module 2 Interrupt Vector 1 - BIT

R/W

0x0704

Module 2 Interrupt Vector 2 - Signal Loss

R/W

0x0708

Module 2 Interrupt Vector 3 - Reference Loss

R/W

0x070C

Module 2 Interrupt Vector 4 - Phase Lock

R/W

0x0710

Module 2 Interrupt Vector 5 - DS Rotation

R/W

0x0714

Module 2 Interrupt Vector 6 - Overcurrent

R/W

0x0718 to 0x077C

Module 2 Interrupt Vector 7-32 - Reserved

R/W

0x0800

Module 2 Interrupt Steering 1 - BIT

R/W

0x0804

Module 2 Interrupt Steering 2 - Signal Loss

R/W

0x0808

Module 2 Interrupt Steering 3 - Reference Loss

R/W

0x080C

Module 2 Interrupt Steering 4 - Phase Lock

R/W

0x0810

Module 2 Interrupt Steering 5 - DS Rotation

R/W

0x0814

Module 2 Interrupt Steering 6 - Overcurrent

R/W

0x0818 to 0x087C

Module 2 Interrupt Steering 7-32 - Reserved

R/W

0x0900

Module 3 Interrupt Vector 1 - BIT

R/W

0x0904

Module 3 Interrupt Vector 2 - Signal Loss

R/W

0x0908

Module 3 Interrupt Vector 3 - Reference Loss

R/W

0x090C

Module 3 Interrupt Vector 4 - Phase Lock

R/W

0x0910

Module 3 Interrupt Vector 5 - DS Rotation

R/W

0x0914

Module 3 Interrupt Vector 6 - Overcurrent

R/W

0x0918 to 0x097C

Module 3 Interrupt Vector 7-32 - Reserved

R/W

0x0A00

Module 3 Interrupt Steering 1 - BIT

R/W

0x0A04

Module 3 Interrupt Steering 2 - Signal Loss

R/W

0x0A08

Module 3 Interrupt Steering 3 - Reference Loss

R/W

0x0A0C

Module 3 Interrupt Steering 4 - Phase Lock

R/W

0x0A10

Module 3 Interrupt Steering 5 - DS Rotation

R/W

0x0A14

Module 3 Interrupt Steering 6 - Overcurrent

R/W

0x0A18 to 0x0A7C

Module 3 Interrupt Steering 7-32 - Reserved

R/W

0x0B00

Module 4 Interrupt Vector 1 - BIT

R/W

0x0B04

Module 4 Interrupt Vector 2 - Signal Loss

R/W

0x0B08

Module 4 Interrupt Vector 3 - Reference Loss

R/W

0x0B0C

Module 4 Interrupt Vector 4 - Phase Lock

R/W

0x0B10

Module 4 Interrupt Vector 5 - DS Rotation

R/W

0x0B14

Module 4 Interrupt Vector 6 - Overcurrent

R/W

0x0B18 to 0x0B7C

Module 4 Interrupt Vector 7-32 - Reserved

R/W

0x0C00

Module 4 Interrupt Steering 1 - BIT

R/W

0x0C04

Module 4 Interrupt Steering 2 - Signal Loss

R/W

0x0C08

Module 4 Interrupt Steering 3 - Reference Loss

R/W

0x0C0C

Module 4 Interrupt Steering 4 - Phase Lock

R/W

0x0C10

Module 4 Interrupt Steering 5 - DS Rotation

R/W

0x0C14

Module 4 Interrupt Steering 6 - Overcurrent

R/W

0x0C18 to 0x0C7C

Module 4 Interrupt Steering 7-32 - Reserved

R/W

0x0D00

Module 5 Interrupt Vector 1 - BIT

R/W

0x0D04

Module 5 Interrupt Vector 2 - Signal Loss

R/W

0x0D08

Module 5 Interrupt Vector 3 - Reference Loss

R/W

0x0D0C

Module 5 Interrupt Vector 4 - Phase Lock

R/W

0x0D10

Module 5 Interrupt Vector 5 - DS Rotation

R/W

0x0D14

Module 5 Interrupt Vector 6 - Overcurrent

R/W

0x0D18 to 0x0D7C

Module 5 Interrupt Vector 7-32 - Reserved

R/W

0x0E00

Module 5 Interrupt Steering 1 - BIT

R/W

0x0E04

Module 5 Interrupt Steering 2 - Signal Loss

R/W

0x0E08

Module 5 Interrupt Steering 3 - Reference Loss

R/W

0x0E0C

Module 5 Interrupt Steering 4 - Phase Lock

R/W

0x0E10

Module 5 Interrupt Steering 5 - DS Rotation

R/W

0x0E14

Module 5 Interrupt Steering 6 - Overcurrent

R/W

0x0E18 to 0x0E7C

Module 5 Interrupt Steering 7-32 - Reserved

R/W

0x0F00

Module 6 Interrupt Vector 1 - BIT

R/W

0x0F04

Module 6 Interrupt Steering 2 - Signal Loss

R/W

0x0F08

Module 6 Interrupt Steering 3 - Reference Loss

R/W

0x0F0C

Module 6 Interrupt Steering 4 - Phase Lock

R/W

0x0F10

Module 6 Interrupt Steering 5 - DS Rotation

R/W

0x0F14

Module 6 Interrupt Steering 6 - Overcurrent

R/W

0x0F18 to 0x0F7C

Module 6 Interrupt Vector 7-32 - Reserved

R/W

0x1000

Module 6 Interrupt Steering 1 - BIT

R/W

0x1004

Module 6 Interrupt Steering 2 - Signal Loss

R/W

0x1008

Module 6 Interrupt Steering 3 - Reference Loss

R/W

0x100C

Module 6 Interrupt Steering 4 - Phase Lock

R/W

0x1010

Module 6 Interrupt Steering 5 - DS Rotation

R/W

0x1014

Module 6 Interrupt Steering 6 - Overcurrent

R/W

0x1018 to 0x107C

Module 6 Interrupt Steering 7-32 - Reserved

R/W

APPENDIX: PIN-OUT DETAILS

Pin-out details (for reference) are shown below, with respect to DATOIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals.

Module Signal (Ref Only)

DS-1CH 8VA (DSX, DRX)

DS-2CH (DSX, DRX)

DS-3CH (DSX, DRX)

DATIO1

S1-SNS-CH1

S1-CH1

S3-CH1

DATIO2

S3-SNS-CH1

RHI-CH1

RHI-CH1

DATIO3

S1-SNS-CH1

S3-SNS-CH1

DATIO4

RLO-CH1

RLO-CH1

DATIO5

S1-CH1

S3-CH1

S1-CH1

DATIO6

S3-CH1

S2-CH1

S1-CH2

DATIO7

S3-SNS-CH1

S2-SNS-CH1

DATIO8

S2-SNS-CH1

RHI-CH2

DATIO9

N/C (SIN-PWM-CH)

S2-CH1

DATIO10

N/C (SIN-PWM)

S4-SNS-CH1

RLO-CH2

DATIO11

N/C (COS-PWM-CH1)

S4-CH1

DATIO12

S4-CH1

S3-CH2

DATIO13

S2-SNS-CH1

S4-CH2

S3-CH3

DATIO14

S4-SNS-CH1

S1-CH2

RHI-CH3

DATIO15

S4-SNS-CH2

S3-SNS-CH3

DATIO16

N/C (COS-PWM)

S1-SNS-CH2

RLO-CH3

DATIO17

S2-CH1

S2-CH2

S1-CH3

DATIO18

S4-CH1

S3-CH2

S2-CH2

DATIO19

S2-SNS-CH2

S4-CH3

DATIO20

S3-SNS-CH2

S4-CH2

DATIO21

N/C (COS-PWM-CH2)

S4-SNS-CH3

DATIO22

RHI-CH2

S4-SNS-CH2

DATIO23

RHI-CH1

N/C (SIN-PWM-CH2)

S2-CH3

DATIO24

RLO-CH1

RLO-CH2

DATIO25

S1-SNS-CH1

DATIO26

S1-SNS-CH2

DATIO27

S4-SNS-CH1

DATIO28

S3-SNS-CH2

DATIO29

S1-SNS-CH3

DATIO30

S2-SNS-CH2

DATIO31

S2-SNS-CH3

DATIO32

DATIO33

DATIO34

DATIO35

DATIO36

DATIO37

DATIO38

DATIO39

DATIO40

N/C

Not connected. Note that bold signals in parentheses (XXXXX) are for internal use only

STATUS AND INTERRUPTS

Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.

For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.

Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.

Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).

Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.

Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).

  • Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edgetriggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.

  • Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Interrupt Trigger Types

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

Dynamic and Latched Status Registers Examples

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Status and Interrupts Fig1

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

No Clearing of Latched Status

Clearing of Latched Status (Edge-Triggered)

Clearing of Latched Status (Level-Triggered)

Time

Dynamic Status

Latched Status

Action

Latched Status

Action

Latched

T0

0x0

0x0

Read Latched Register

0x0

Read Latched Register

0x0

T1

0x1

0x1

Read Latched Register

0x1

0x1

Write 0x1 to Latched Register

Write 0x1 to Latched Register

0x0

0x1

T2

0x0

0x1

Read Latched Register

0x0

Read Latched Register

0x1

Write 0x1 to Latched Register

0x0

T3

0x2

0x3

Read Latched Register

0x2

Read Latched Register

0x2

Write 0x2 to Latched Register

Write 0x2 to Latched Register

0x0

0x2

T4

0x2

0x3

Read Latched Register

0x1

Read Latched Register

0x3

Write 0x1 to Latched Register

Write 0x3 to Latched Register

0x0

0x2

T5

0xC

0xF

Read Latched Register

0xC

Read Latched Register

0xE

Write 0xC to Latched Register

Write 0xE to Latched Register

0x0

0xC

T6

0xC

0xF

Read Latched Register

0x0

Read Latched

0xC

Write 0xC to Latched Register

0xC

T7

0x4

0xF

Read Latched Register

0x0

Read Latched Register

0xC

Write 0xC to Latched Register

0x4

T8

0x4

0xF

Read Latched Register

0x0

Read Latched Register

0x4

Interrupt Examples

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Status and Interrupts Fig2

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

Time

Latched Status (Edge-Triggered – Clear Multi-Channel)

Latched Status (Edge-Triggered – Clear Single Channel)

Latched Status (Level-Triggered – Clear Multi-Channel)

Action

Latched

Action

Latched

Action

Latched

T1 (Int 1)

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Write 0x1 to Latched Register

Write 0x1 to Latched Register

Write 0x1 to Latched Register

0x0

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T2.

0x1

T3 (Int 2)

Interrupt Generated Read Latched Registers

0x2

Interrupt Generated Read Latched Registers

0x2

Interrupt Generated Read Latched Registers

0x2

Write 0x2 to Latched Register

Write 0x2 to Latched Register

Write 0x2 to Latched Register

0x0

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.

0x2

T4 (Int 3)

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x3

Write 0x1 to Latched Register

Write 0x1 to Latched Register

Write 0x3 to Latched Register

0x0

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.

0x3

Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.

0x2

T6 (Int 4)

Interrupt Generated Read Latched Registers

0xC

Interrupt Generated Read Latched Registers

0xC

Interrupt Generated Read Latched Registers

0xE

Write 0xC to Latched Register

Write 0x4 to Latched Register

Write 0xE to Latched Register

0x0

Interrupt re-triggers Write 0x8 to Latched Register

0x8

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.

0xE

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.

0xC

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.

0x4

Revision History

Module Manual - DS1-DSN Revision History

Revision

Revision Date

Description

C

2022-07-08

ECO C09252, transition to docbuilder format. Replaced 'Specifications' section with 'Data Sheet' section. Pg.6, defined Number of Channels. Pg.6, added additional Accuracy details for DSL/DRL/DSM/DRM. Pg.6, defined Output Voltage specs. Pg.6, defined Output Load specs and added derating note. Pg. 6, removed '3-channel HV model only' references from rotation specs. Pg. 7, added Current specs for 2 CH LV/3 CH LV modules. Pg.9, added description of Transformation Ratio to Principle of Operation. Pg.9, added power-on self-test/CBIT/IBIT details to 'Diagnostic Capability'. Pg.10, added Power On/Off register description. Pg.16, added Test Registers. Pg.17, added Channel Status Enabled register description. Pg.21, added Power On/Off register offset. Pg.23, added Channel Status and Test register offsets. Pg.26, added Appendix: Pin-Out Details.

Module Manual - Status and Interrupts Revision History

Revision

Revision Date

Description

C

2021-11-30

C08896; Transition manual to docbuilder format - no technical info change.

NAI Cares

North Atlantic Industries (NAI) is a leading independent supplier of Embedded I/O Boards, Single Board Computers, Rugged Power Supplies, Embedded Systems and Motion Simulation and Measurement Instruments for the Military, Aerospace and Industrial Industries. We accelerate our clients’ time-to-mission with a unique approach based on a Configurable Open Systems Architecture™ (COSA®) that delivers the best of both worlds: custom solutions from standard COTS components.

We have built a reputation by listening to our customers, understanding their needs, and designing, testing and delivering board and system-level products for their most demanding air, land and sea requirements. If you have any applications or questions regarding the use of our products, please contact us for an expedient solution.

Please visit us at: www.naii.com or select one of the following for immediate assistance:

Application Notes

Calibration and Repairs

Call Us

(631) 567-1100

Help Bot

X