Function: The value represents voltage or engineering units depending on mode.

Type: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: Values are dependent on Polarity and Range settings for the channel

Read/Write: R

Initialized Value: NA

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: Sets input format for polarity and range for each channel. Note, if the Enable Floating Point Mode register is set to 1, the Floating Point Scale register must be set to the Range for direct voltage readout.

Type: unsigned binary word (32-bit) Data Range: See table below.

Read/Write: R/W

Initialized Value: 0x0000 0010 (ADE: ± 10 V, ADF: ± 100 V)

Operational Settings: For bipolar/unipolar selection, program D4 bit as 0 for unipolar and 1 for bipolar as shown in table below.

Polarity and Range

Range

Function: Sets the desired sample rate for all channels.

Type: unsigned binary word (32-bit)

Data Range: 1000 – 200000 (0x0000 03E8 to 0x0003 0D40)

Read/Write: R/W

Initialized Value: 200000 (0x0003 0D40)

Operational Settings: LSB is 1Hz. Sample rate applies to all channels.

Function: The break frequency is the 3 dB point of a digital, second-order, IIR low-pass filter.

Type: unsigned binary word (32-bit)

Data Range: 0 Hz to 90 kHz (0x0000 0000 to 0x0001 5F90)

Read/Write: R/W

Initialized Value: 20 kHz (0x0000 4E20)

Operational Settings: LSB is 1 Hz. The break frequency must not be less than 1% of the clock rate frequency. (Example: For a clock rate frequency of 2 kHz, the Filter Break Frequency should be no less than 20 Hz). Set to 0 to disables filter.

Acquisition & Conversion Time: Total time required to obtain digital result. It consists of acquisition, decimator group delay when engaged, and IIR filter.

Acquisition & Conversion time will vary depending on the programmed sample rates. Expect a total delay of 5.5µs when sampling at 200kHz (max). Refer to the following chart for lower sample rates:

Function: Latches all A/D channels.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Set to 1 to latch and to 0 to unlatch. Bit-mapped per channel.

Note: The channel’s A/D Reading register will maintain the same reading while the Latch A/D bit is set to 1. Sampling for the channel will resume for that channel only when the bit is set to 0.

Latch A/D Channel

Function: Sets bit to enable the associated Built-In Self-Test (BIST): IBIT, CBIT and UBIT.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R/W

Initialized Value: 0x4 (CBIT Test Enabled)

Operational Settings: BIT tests include an on-line (CBIT) test and two off-line (UBIT, IBIT) tests. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggers when the BIT testing detects failures.

Test Enabled

Function: Specifies voltage to be applied for the A/D UBIT off-line test.

Type: signed binary word (32-bit)

Data Range: Voltage and Current values are dependent on Polarity and Range settings for the channel. Unipolar: 0x0000 to 0x0000 FFFF Bipolar (2’s compliment. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: LSB is dependent on the Range setting. Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: This is a counter that reports the number of 16-bit words stored in the FIFO buffer.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R

Initialized Value: 0

Operational Settings: Every time a read operation is made from the A/D Data memory address, its corresponding Words in FIFO counter will be decremented by one. The maximum number of words that can be stored in the FIFO is 1 mega words.

The FIFO Almost Empty, FIFO Low Watermark, FIFO High Watermark, FIFO Almost Full and FIFO Buffer Size sets the threshold limits that are used to set the bits in the FIFO Status register.

FIFO Almost Empty

Function: The FIFO Almost Empty is used to set the limits for the “almost empty” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When the Words in FIFO counter is greater than or equal to the value stored in the FIFO Almost Empty register, the “almost empty” bit (D1) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the register, the “almost empty” bit (D1) of the FIFO Status register will be reset.

FIFO Low Watermark

Function: The FIFO Low Watermark (low-threshold level) is used to set the limits for the “low watermark” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When the Words in FIFO counter is less than or equal to the value stored in the FIFO Low Watermark register, the “low watermark” bit (D2) of the FIFO Status register will be set. When the Words in FIFO counter is greater than the value stored in the register, the “low watermark” bit (D2) of the FIFO Status register will be reset.

FIFO High Watermark

Function: The FIFO High Watermark (high-threshold level) is used to set the limits for the “high watermark” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When the Words in FIFO counter is greater than or equal to the value stored in the FIFO High Watermark register, the “high watermark” bit (D3) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the highthreshold, the “high watermark” bit (D3) of the FIFO Status register will be reset.

FIFO Almost Full

Function: The FIFO Almost Full is used to set the limits for the “almost full” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When the Words in FIFO counter is greater than or equal to the value stored in the FIFO Almost Full register, the “almost full” bit (D4) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the register, the “almost full” bit (D4) of the FIFO Status register will be reset.

FIFO Buffer Size

Function: Sets the number of samples to be taken and placed into the FIFO when a trigger occurs.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R/W

Initialized Value: 0x000F FFFF

Operational Settings: The size of each sample (number of words written to the FIFO per sample) is determined by the sample format described by the FIFO Buffer Control register. When the Words in FIFO counter reaches the FIFO Buffer Size, the “sample done” bit (D6) is set and no additional samples will be placed in the FIFO. When Words in FIFO counter is less than FIFO Buffer Size, the “sample done” bit (D6) will be reset.

Function: Sets the format of the samples to be stored in the FIFO buffer which is determined by the bitmapped table.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0014

Read/Write: R/W

Initialized Value: 0

Operational Settings: The Time Stamp data format (D4) requires one word of storage space from the FIFO buffer. For example, if (D4) is set to 0 and the FIFO Buffer Size register is set to 1, a FIFO write will put one word of data in the FIFO memory space per sample and discard the timestamp. Since the maximum physical size of FIFO is 1M words for each channel, the value in the FIFO Buffer Size and Data Control registers could cause an overflow to the FIFO buffer. When an overflow condition occurs, any data that is not place in the FIFO will be lost.

Function: Sets the number of delay samples before the actual FIFO data collection begins.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: The data collected during the delay period will be discarded.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0 (No Skip Count (FIFO stores every sample))

Operational Settings: If the sample rate for a channel is 10 kHz, there would be a new sample every 100µs. By setting the FIFO skip count to 1, the FIFO will store a new sample every 200 µs, or at a 5 kHz rate.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: W

Initialized Value: N/A

Operational Settings: This resets the Words in FIFO to zero; Clear FIFO register does not clear data in the buffer. A read to the buffer data will give “aged” data. Write a 1 to reset the Words in FIFO for the channel.

Clear FIFO

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0x1FF

Read/Write: R/W

Initialized Value: 0 (Disable Trigger)

Operational Settings: For the current implementation, triggering of FIFO is by Software Trigger only. Hardware triggering will be implemented in a future release. Hardware triggering will be platform dependent based on pin-outs and I/O availability. See the tables that follow for the current and pending settings.

FIFO Trigger Control

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: W

Initialized Value: 0 (Not Triggered)

Operational Settings: To use this operation, the FIFO Trigger Control register must be set up as described in the FIFO Trigger Control register. Write a 1 to trigger FIFO collection for all channels.

FIFO Software Trigger

Function: Sets all channels for floating point mode or integer module.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: R/W

Initialized Value: 0 (Integer mode)

Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode. Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Enable Floating Point Mode

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

Read/Write: R/W

Initialized Value: 0.0

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: This register sets the floating point scale to multiply to the AD data.

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

Read/Write: R/W

Initialized Value: 0.0

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: Indicates whether the module’s internal processing is converting the register values and internal values to the binary representation of the mode selected (Integer or Floating Point).

Type: unsigned binary word (32-bit)

Data Range: 0 to 1 Read/Write: R

Initialized Value: 0

Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

Floating Point State

Function: Sets BIT Threshold value (in milliseconds) to use for all channels for BIT failure indication.

Type: unsigned binary word (32-bit)

Data Range: 1 ms to 65 seconds

Read/Write: R/W

Initialized Value: 5 ms

Operational Settings: The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module.

Function: Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: W

Initialized Value: 0

Operational Settings: Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.

NOTE: BIT Count Clear is a shared register between the ADE/ADF and DA2 functions. Bits D7:D0 are dedicated to the ADE/ADF functions, and bits D15:D8 are dedicated to the DA2 function.

BIT Clear Count

Function: Determines whether to update the status for the channels. This feature can be used to “mask” status bits of unused channels in status registers that are bitmapped by channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF (Channel Status)

Read/Write: R/W

Initialized Value: 0x0000 FFFF

Operational Settings: When the bit corresponding to a given channel in the Channel Status Enable register is not enabled (0) the status will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status, Open/Over-Voltage Status, and Front-end Amplifier Failure Status).

NOTE: Channel Status Enable is a shared register between the ADE/ADF and DA2 functions. Bits D7:D0 are dedicated to the ADE/ADF functions, and bits D15:D8 are dedicated to the DA2 function.

NOTE: Background BIT will continue to run even if the Channel Status Enable is set to ‘0'.

Channel Status Enable

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The BIT Status register will indicate an error when the voltage read is not within the error of the set value.

NOTE: BIT Status is a shared register between the ADE/ADF and DA2 functions. Bits D7:D0 are dedicated to the ADE/ADF functions, and bits D15:D8 are dedicated to the DA2 function.

BIT Dynamic Status BIT Latched Status BIT Interrupt Enable BIT Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Upon detection of a BIT error, the following registers provide additional information about the error:

Power-on BIT Error (Indicates a PBIT error that occurred on power-on. Bit will remain set until the BIT Count Clear register is written to. This register is OR’d into BIT status.)

Anti-Aliasing Filter Error (Indicates a common-mode range input error on the front-end voltage input circuitry. This register is OR’d into BIT status.)

Voltage Reading Accuracy Error (Indicates voltage reading accuracy outside of spec compared with redundant reading. This is the same as CBIT. This register is OR’d into BIT status.)

There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0-D6 is used to show the different conditions of the buffer.

FIFO Dynamic Status FIFO Latched Status FIFO Interrupt Enable FIFO Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the FIFO status type; there is a separate register for each channel.

Type: binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 007F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Note:

There are four registers associated with the Open/Over-Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. These registers are only applicable to ADE function.

Note: Channel 8’s negative pin (IN_CH08-) on the I/O connector MUST be tied to ground for the open detection circuitry to function properly. Failure to make this connection to ground will cause intermittent open-detect behavior on all channels.

Note: both ends of any unused channels (Pos/Neg) should be tied to the channel 8 negative pin, referred to as the Common Mode Reference Point (CMRP; isolated from system power/ground). Tying only one end of a channel, while leaving the opposing end open, may cause Open Circuit Detection to deliver unwanted voltages to your channels in use.

Open/Over-Voltage Dynamic Status Open/Over-Voltage Latched Status Open/Over-Voltage Interrupt Enable Open/Over-Voltage Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Open/Over-Voltage error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the External Power Loss Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

D0 = +12V External Power Loss

D1 = -12V External Power Loss

External Power Loss Dynamic Status External Power Loss Latched Status External Power Loss Interrupt Enable External Power Loss Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s External Power Loss error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0003

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0

The Analog-to-Digital function provide registers that support threshold detection. Refer to “Analog-to-Digital Threshold and Saturation Programming Module Manual” for the register descriptions.

The Analog-to-Digital function provide registers that support saturation detection. Refer to “Analog-to-Digital Threshold and Saturation Programming Module Manual” for the register descriptions.

There are four registers associated with the Front-end Amplifier Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. These registers are only applicable to the ADF function.

Front-end Amplifier Failure Dynamic Status Front-end Amplifier Failure Latched Status Front-end Amplifier Failure Interrupt Enable Front-end Amplifier Failure Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Front-end Amplifier Failure error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0

Data is periodically transferred between the Lattice FPGA and the Xilinx FPGA. A CRC value is calculated and verified with each data transfer. A CRC error flag is sent from the Lattice FPGA to the Xilinx FPGA if a CRC error is detected. The Xilinx FPGA contains a counter that will increase by two when a CRC error is flagged and decremented by one when there is no CRC error. If the counter reaches ten, the Xilinx FPGA will set the Inter-FPGA Failure status bit and shut down the isolated power supply. To recover from an Inter-FPGA Failure, the module needs to be reset and re-initialized.

There are four registers associated with the Inter-FPGA Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. 0 = Normal; 0xFFFF = Inter-FPGA Communication Failure. The status represents the status for all channels on the module.

NOTE: Inter-FPGA Failure Status is a shared register between the ADE/ADF and DA2 functions. Bits D7:D0 are dedicated to the ADE/ADF functions, and bits D15:D8 are dedicated to the DA2 function.

Inter-FPGA Failure Dynamic Status Inter-FPGA Failure Latched Status Inter-FPGA Failure Interrupt Enable Inter-FPGA Failure Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Inter-FPGA Failure error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Function: Sets the output voltage for the channel.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: DAC values are dependent on Voltage Range setting for the channel

Read/Write: R/W

Initialized Value: 0

Operational Settings: Refer to section Appendix B: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: Sets voltage polarity and range for each channel. The value written to the DAC Value registers will correlate to the voltage range set in this register. Note: if the Enable Floating Point Mode register is set to 1, the Floating Point Scale register must be set to the reciprocal of Voltage Range for direct voltage output.

Type: unsigned binary word (32-bit)

Data Range: See table below

Read/Write: R/W

Initialized Value: 0 (Unipolar: 0-5 V)

Operational Settings: Write to the register with a value from the table to select the range. For example, for a ±10V bipolar range write a 0x4 to the register.

Voltage Range

Function: Enables the voltage to appear on the output.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write*: R/W

Initialized Value: 0 (Channel outputs are disabled)

Operational Settings: Set bit to 1 to activate the output. Set bit to 0 to disable the output.

Output Enable

Function: Sets the output rate for the DAC output and FIFO Data Output

Type: unsigned binary word (32bit)

Data Range: 0x0000 09C4 to 0x0000 61A8; 400µs (2.5kHz) to 40µs (25kHz).

Read/Write: R/W

Initialized Value: 0x0000 61A8 (40µs) (25kHz)

Operational Settings: This setting is the output rate for each DAC. One update rate applies to all channels.

Function: Resets over loaded channels based on the current value read in the Wrap Current register.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: W

Initialized Value: 0

Operational Settings: Set to 1 to reset over loaded channels. Writing a 1 to this register will re-enable over loaded channels.

Overcurrent Reset