AR1 Communication Modules ARINC Communications Function Modules 12 Channels, ARINC 429/575 Communications

The AR1 provides an ARINC 429/575 communications interface with 12 channels. This module only provides an interface and data management. Any specific protocol handling must be programmed by the user in the application layer. Each channel is programmable as either Tx or Rx.

ARINC 429 is a data transfer standard for aircraft avionics. It uses a self-clocking, self-synchronizing data bus protocol (Tx and Rx are on separate ports). The physical connection wires are twisted pairs carrying balanced differential signaling. Data words are 32-bits in length and most messages consist of a single data word. Messages are transmitted at either 12.5 or 100 kbit/s to other system elements that are monitoring the bus messages. The transmitter constantly transmits either 32-bit data words or the Null state. A single wire-pair is limited to one transmitter and no more than 20 receivers. The protocol allows for self-clocking at the receiver end, thus eliminating the need to transmit clocking data. ARINC 429 is an alternative to MIL-STD-1553.

ARINC 575 is an equipment characteristic for a Digital Air Data System (DADS) that provides essential air-data information for displays, autopilots, and other flight controls and instrumentation on commercial and transport-type aircraft. ARINC 575 defined a digital databus for distribution of information to displays and other systems. This databus was later described in ARINC 419 and became what is now known as ARINC 429. There are only minor differences between the digital databus of ARINC 575 and that of ARINC 429. The most significant difference is that ARINC 429 reserves bit 32 for parity, while ARINC 575 could use bit 32 for either parity (when BNR) or data (when BCD).

For both the ARINC 429 and ARINC 575 standards, each channel is software-selectable for transmit or receive, and for Hi or Lo speed. When receiving a message, the receiver logic converts the serial BRZ data stream to a 32-bit wide parallel data word. If the Label, SDI, and parity bits pass validation, the ARINC data word is sent to the Receive FIFO (to be read by the user). When transmitting a message, message data can be sent immediately or buffered for synchronized transmission. In buffer mode, ARINC words are read from the Txmit buffer and sent out at the Txmit Interval Rate. In repeat mode, ARINC message data is sent continuously. The user interface supports FIFO buffering and interrupts. Txmit data can be sent immediately or scheduled. To schedule a Txmit sequence, the Txmit FIFO can be loaded with a sequence of up to 256 ARINC data words. The transmission interval is programmable. Enabling the channel begins transmission. Tx and Rx data are continuously monitored and verified.

Receive/Transmit mode programmable per channel 100 kHz or 12.5 kHz operation per channel Transmit: 255 message FIFO or scheduled transmits per channel Async transmits during scheduled transmits Receive: 255 message FIFO or mailbox buffering per channel Message Validation (SDI/Label Filtering) on received messages per channel Selectable hardware parity generation/checking Receive time stamping Continuous BIT Loop-back test

abc

NAI’s Custom-On-Standard Architecture™ (COSA®) offers a choice of over 40 Intelligent I/O, communications, or Ethernet switch functions, providing the highest packaging density and greatest flexibility of any 3U SBC in the industry. Preexisting, fully-tested functions can be combined in an unlimited number of ways quickly and easily.

The 75PPC1 includes BSP and SDK support for Wind River® VxWorks®. In addition, software support kits are supplied, with source code and board-specific library I/O APIs, to facilitate system integration. Each I/O function has dedicated processing, unburdening the SBC from unnecessary data management overhead.

BIT continuously monitors the status of all I/O during normal operations and is totally transparent to the user. SBC resources are not consumed while executing BIT routines. This simplifies maintenance, assures operational readiness, reduces life-cycle costs and— keeps your systems mission ready.

Eliminate man-months of integration with a configured, field-proven system from NAI. Specification to deployment is a seamless experience as all design, state-of-the-art manufacturing, assembly and test are performed— by one trusted source. All facilities are in the U.S. and optimized for high-mix/low volume production runs and extended lifecycle support.

From design-in to production, and beyond, NAI’s product lifecycle management strategy ensures the long-term availability of COTS products through configuration management, technology refresh, and obsolescence component purchase and storage.

As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurement and simulation, communications, Ethernet switch, and SBC functions. Our ARINC 429/575 Communications Module (AR1) is designed to meet data transfer standards and protocols used in aircraft avionics systems. With its adherence to industry-standard protocols and the ability to support both ARINC 429 and 575 communications, the AR1 offers exceptional performance and reliability. This user manual is designed to help you get the most out of your AR1 function module.

AR1 Overview

The AR1 ARINC 429/575 Communications Module offers a variety of features that highlight its role as in data management and as an interface. Some of the key features include:

ARINC communications:

The module supports the following ARINC communications:

ARINC 429 is a widely adopted data transfer standard, serving as an alternative to MIL-STD-1553. It utilizes a self-clocking, selfsynchronizing data bus protocol with separate transmit and receive ports. The physical connection consists of twisted pairs carrying balanced differential signaling. Each data word is 32 bits in length, with most messages containing a single data word. Messages are transmitted at either 12.5 or 100 kbps, allowing other system elements to monitor the bus messages. The transmitter continuously transmits 32-bit data words or the NULL state. A single-wire pair can accommodate one transmitter and up to 20 receivers. Notably, the receiver end of the protocol enables self-clocking, eliminating the need for transmitting clocking data.

In addition to ARINC 429, the AR1 function module also supports ARINC 575, a data transfer protocol specifically used for the Digital Air Data System (DADS) on commercial and transport aircraft. ARINC 575 defines a digital data bus that distributes crucial air-data information to displays, autopilots, and flight control instrumentation.

While there are minor differences between the digital data bus of ARINC 575 and ARINC 429, the most significant distinction lies in the usage of bit 32. In ARINC 429, bit 32 is reserved for parity, whereas ARINC 575 can utilize bit 32 for either parity (when using BNR encoding) or data (when using BCD encoding).

Receive/Transmit Mode Programmability:

Each channel of the module can be programmed to operate in either receive or transmit mode according to your specific application needs.

Flexible Operation:

The module supports both 100 kHz and 12.5 kHz operation per channel, allowing you to choose the appropriate speed for your communication requirements.

Transmit Capabilities:

Enjoy the convenience of a 255 message FIFO or scheduled transmits per channel, allowing you to efficiently manage and control the transmission of messages. Additionally, asynchronous transmits can be performed alongside scheduled transmits.

Receive Capabilities:

Benefit from a 255 message FIFO or mailbox buffering per channel, providing ample storage for incoming messages. This ensures reliable reception and efficient handling of data.

Message Validation:

The module supports SDI/Label Filtering, enabling you to validate received messages based on specific criteria per channel. This feature enhances the overall data integrity and ensures only relevant information is processed.

Hardware parity:

You have the option to enable selectable hardware parity generation/checking, which adds an extra layer of data integrity verification during transmission and reception.

Receive Time Stamping:

Gain valuable insights into message reception with the module’s receive time stamping feature. This allows precise timing analysis and synchronization in your communication system.

Continuous Built-In Test (BIT):

The AR1 incorporates continuous BIT functionality, providing self-diagnostics and monitoring capabilities to ensure reliable operation and easy troubleshooting.

Loop-Back Test:

Verify the integrity of the module by performing loop-back tests. This feature allows you to validate the communication path and confirm proper functionality.

Tri-State Outputs:

The module’s outputs support tri-state functionality, allowing you to control the state of the outputs as needed. This enables seamless integration with other system components.

High and Low-Speed Slew Rate Outputs:

The module offers both high and low-speed slew rate outputs, providing flexibility in meeting the requirements of various communication interfaces.

Module Factory Defaults

Module AR1 provides up to 12 programmable ARINC-429 channels. Each channel is software selectable for transmit and/or receive, high or low speed, and odd or no parity. Therefore, AR1 can support multiple ARINC 429 and 575 channels simultaneously.

Serial BRZ data is decoded for logic states: one, zero or null. Once Word Gap is detected (4 null states) the receiver waits for either a zero or one state to start the serial-to-parallel shift function. If a waveform timing fault is detected before the serial/parallel function is complete, operation is terminated and the receiver returns to waiting for Word Gap detection. The serial-to-parallel output data is validated for odd parity, Label and Serial-to-Digital Interface (SDI).

If message validation (filtering) is enabled, the module compares the SDI/Label of incoming ARINC messages to a list of desired SDI/Labels in validation (match) memory and only stores messages with an SDI/Label in the list. The message is stored in the receive FIFO or mailbox, depending if the channel is in FIFO receive mode or mailbox receive mode. In FIFO Receive Mode, received ARINC messages / words are stored with an associated status word and an optional time-stamp value in the channel’s receive FIFO. Additionally, the Rx FIFO can be set for either bounded or circular mode, which determines FIFO behavior when it is full. In bounded mode, newly received ARINC messages are discarded if the FIFO is full whereas in circular mode, new ARINC messages overwrite the oldest messages in the FIFO. In mailbox mode, received ARINC words are stored in mailboxes or records in RAM that are indexed by the SDI/Label of the ARINC word. Each mailbox contains a status word associated with the message, the ARINC message / word, and an optional 32-bit timestamp value. The status word indicates parity error and new message status.

Transmit Operation

Transmitters are tri-stated when TX is not enabled. Transmit operates in one of three modes: Immediate FIFO, Triggered FIFO, and Scheduled. In immediate mode, ARINC data is sent as soon as data is written to the transmit FIFO. In Triggered FIFO mode, a write to the Transmit Trigger register is needed to start transmission of the transmit FIFO contents. Transmission continues until the FIFO is empty. To transmit more data after the FIFO empties out, issue a new trigger after filling the transmit FIFO with new data.

For either FIFO mode, a transmit FIFO Rate register is provided to control rate of transmission. The contents of this register specify the gap time between transmitted words from the FIFO. The default is the minimum ARINC gap time of 4-bit times.

Schedule mode transmits ARINC data words according to a prebuilt schedule table in Transmit Schedule RAM. In the Schedule table, various commands define what messages are sent and the duration of gaps between each message. Note that a Gap (Gap or Fixed Gap) command must be explicitly added in between each Message command otherwise a gap will not be inserted between messages. The ARINC data words and gap times are stored in the Transmit Message RAM and can be updated on the fly as the schedule executes. A write to the Transmit Trigger register initiates the schedule and commands are executed starting from the first command (address 0x0) in the Schedule RAM. While a schedule is running, an ARINC word can be transmitted asynchronously by writing the async data word to the Async Transmit Data register. After it has transmitted, the Async Data Available bit will be cleared from the Channel Status register and the Async Data Sent Interrupt will be set if enabled. The Async Data Available bit in Channel Status also gets cleared by a Stop Cmd in a schedule or if a Transmit Stop command is issued from the Transmit Stop register. Use the Fixed Gap command instead of the Gap command to disable async transmissions during the schedule gap time. Gap and Fixed Gap commands can both be used when building the transmit schedule.

ARINC 429/575 scheduling is controlled by commands that are written to the Transmit Schedule RAM. The available commands are:

Message

Gap

Fixed Gap

Pause

Schedule Interrupt

Jump Stop

This command takes a parameter that specifies the location in Transmit Message memory containing the ARINC data word to be sent. The word is transmitted when the Message command is executed. This ARINC word can be modified in Tx Message memory while the schedule is running.

This command takes a parameter that specifies the location in Transmit Message memory containing a 20-bit gap time value. Values less than 4 are invalid. If the previous command was a Message, then that message is transmitted and then the transmitter waits out the specified gap time transmitting nulls. An exception to this is if there is an async data word available. If the gap time is greater or equal to 40 bit times (4-bit gap time plus one ARINC word plus another 4-bit gap time) an async data word, if available, will be transmitted during this time. If a new async data word is made available and the remaining gap time is large enough to accommodate another async data word transmission, then the new async data word will be transmitted after a 4-bit gap time. Multiple async data word transmissions can thus occur as long as the remaining gap time is large enough to accommodate a message and the required minimum 4-bit gap time. Otherwise, the transmitter waits out the remaining gap time before executing the next command.

This command takes a parameter that specifies the location in Transmit Message memory containing a 20-bit gap time value. Values less than 4 are invalid. If the previous command was a Message, then that message is transmitted with the specified gap time appended. If the previous command was not a Message, then the transmitter waits for the specified gap time before executing the next command. The difference between the Fixed Gap and Gap command is that Fixed Gap will prevent the transmission of async data words during the gap time. Use Fixed Gap to only allow nulls to be transmitted during the gap time.

This command causes the transmitter to pause execution of the schedule after transmitting the current word. Either a Transmit Trigger command is issued to resume execution, or a Transmit Stop command is issued to halt execution.

This command causes the Schedule Interrupt to be set if Schedule Interrupt is enabled. An unlatched version of this flag is also visible in the channel status register.

Jumps to the 9-bit address in Schedule memory pointed to by this command and resumes execution there.

This command causes the transmitter to stop execution of the schedule after transmitting the current word.

The AR1 module supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are logically ORed together and stored in the BIT Dynamic Status and BIT Latched Status registers.

The power-on self-test is performed on each channel automatically when power is applied and reports the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.

The background Built-In-Test or Continuous BIT (CBIT) runs in the background for each enabled channel. In Transmit operations, internal transmit data is compared to loop-back data received by the ARINC receivers. When the channel is configured for Receive operation, receive data is continuously monitored via a secondary parallel path circuit and compared to the primary input receive data. If the data does not match, the technique used by the automatic background BIT test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. The “add- 2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state. Results of the Continuous BIT are stored in the BIT Dynamic Status and BIT Latched Status register.

The Initiated Built-In-Test (IBIT) is an internal loopback available for each channel of the AR1 module. The test is initiated by setting the bit for the associated channel in the Test Enabled register to a 1. Once enabled, they must wait at least 3 msec before checking to see if the bit for the associated channel in the Test Enabled register reads a 0. When the AR1 clears the bit, it means that the test has completed, and its results can be checked. The results of the IBIT is stored in the BIT Dynamic Status and BIT Latched Status registers, a 0 indicates that the channel has passed and a 1 indicates that it failed.

Transmit and receive operation of an AR1 channel can be verified internally by enabling both Tx and Rx on the same channel. Tx Scheduling is not supported when the channel is placed in this mode.

The module is normally configured for transient protection but can be specified without if protection is implemented externally.

The AR1 Module provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

The AR1 Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Receive Registers

The registers listed are associated with data that is received on the AR1 channels. Two modes of message storage are supported: Receive FIFO and Receive Mailbox.

Receive FIFO Mode Registers

The Receive FIFO Mode Registers contain information about ARINC messages that are received via the Receive FIFO buffer on the AR1 channel. The registers associated with this feature are:

Receive FIFO Message Buffer

Receive FIFO Message Count

Receive FIFO Almost Full Threshold

Receive FIFO Size

The registers listed are associated with data that is received on the AR1 channels. Two modes of message storage are supported: Receive FIFO and Receive Mailbox.

The Receive FIFO Mode Registers contain information about ARINC messages that are received via the Receive FIFO buffer on the AR1 channel. The registers associated with this feature are: * Receive FIFO Message Buffer * Receive FIFO Message Count * Receive FIFO Almost Full Threshold * Receive FIFO Size

The registers listed are associated with data that is received on the AR1 channels. Two modes of message storage are supported: Receive FIFO and Receive Mailbox.

The Receive Mailbox Mode Registers contain information about ARINC messages that are received via mailboxes on the AR1 channel. The registers associated with this feature are:

Receive FIFO SDI/Label Buffer

Receive FIFO SDI/Label Count

Receive FIFO Almost Full Threshold

Receive FIFO Size

Mailbox Status Data

Mailbox Message Data

Mailbox Timestamp Data

If message validation (filtering) is enabled, the module compares the SDI/Label of incoming ARINC messages to a list of desired SDI/Labels in validation (match) memory and only stores messages with an SDI/Label in the list.

The registers listed are associated with data that is to be transmitted from the AR1 channels. Two modes of message storage are supported: Transmit FIFO and Transmit Scheduling.

The Transmit FIFO Mode Registers contain information about ARINC messages that are to be transmitted via the Transmit FIFO buffer on the AR1 channel. The registers associated with this feature are:

Transmit FIFO Message Buffer

Transmit FIFO Message Count

Transmit FIFO Almost Empty Threshold

Transmit FIFO Rate

The registers listed are associated with data that is to be transmitted from the AR1 channels. Two modes of message storage are supported: Transmit FIFO and Transmit Scheduling.

The Transmit Scheduling Registers are utilized when the channel is set up to run a Transmit Schedule. The memories/registers associated with this feature are:

Transmit Schedule RAM

Transmit Message RAM

Async Transmit Data Register

Control of the transmission of ARINC messages includes the ability to start/resume, pause and stop the transmission of the message.

The AR1 control registers provide the ability to reset all the channels in the AR1 module and configuring and controlling individual AR1 channels.

The AR1 module provides the ability to run an initiated test (IBIT). Writing a 1 to the bit associated with the channel in the Test Enabled register.

The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The Reset BIT register provides the ability to reset the BIT counter used in CBIT.

Refer to “Module Common Registers Module Manual” for the register descriptions.

The AR1 Module provides status registers for BIT and Channel.

Key: Regular Italic = Incoming Data Regular Underline = Outgoing Data Bold Italic = Configuration/Control Bold Underline = Status

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).

All Channels

All Channels

Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.

BIT Status

++After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.

The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.