NAI’s DT2 Discrete/Switch module is a versatile electronic device designed for reliable and high-performance operation in harsh environments. This module features 16 independent, isolated, programmable channels that can be used for input voltage measurements (±80 V), or as a bidirectional current switch (up to 625 mA per channel). The module includes diode clamping on each channel, which provides protection against inductive loads.

The DT2 offers a wide range of features for accurate and reliable control and monitoring of switches and inductive loads. Key features of the module include:

Overall, NAI’s DT2 Discrete/Switch Module is a highly versatile device that offers a wide range of features for accurate and reliable control and monitoring of switches and inductive loads. Its programmable channels, automatic protection features, and clean switching make it an excellent choice for a wide range of industrial and military applications.

Each channel contains both an isolated differential amplifier and a dual N-Channel MOSFET, configured as isolated Solid-State Relay (SSR). The SSR is energized, so both AC and DC current can flow through the channels I/O pins. The MOSFET presents a low ~.5 Ω on impedance. The module contains circuitry to measure the current through the SSR and the voltage present on the I/O pins.

Four threshold levels: Max High Threshold, Upper Threshold, Lower Threshold, and Min Low Threshold offer maximum user flexibility. All four threshold levels must be programmed. For input or output, the threshold levels will define the logic states. For proper operation, the threshold values should be programmed such that:

Max High Threshold > Upper Threshold > Lower Threshold > Min Low Threshold

Program Upper and Lower Thresholds, keeping the 0.25 V min. differential in mind, and then add debounce time as required. When the input signal exceeds the Upper Threshold, a logic high 1 is maintained until the input signal falls below the Lower Threshold. Conversely, when the input signal falls below the Lower Threshold, a logic low 0 is maintained until the input signal rises above the Upper Threshold.

The Debounce register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Once a signal level is a logic voltage level period longer than the Debounce Time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed Debounce Time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state.

BIT is always enabled, and continually checks the health of each channel. This is accomplished by internal test circuitry that is incorporated into each 16-channel module. The test circuit is sequentially connected across each channel and checks that the commanded mode (input or switch closure) is correctly set, and depending upon the configuration, verifies that the channel data agrees with the test data or a possible fault is detected. Additionally, each output is continually checked for overcurrent, which is manually set for each channel. If the switch is open and current is any value other than 0 A, a BIT error will occur. If the switch is closed and voltage is any value other than 0 V, a BIT error will occur.

The Discrete I/O Function Module provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

The Discrete I/O Function Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

The Discrete I/O Function Module provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the Principle of Operation description.

Function: Opens and closes the switch for each channel.

Type: unsigned binary word (32-bit)

Read/Write: R/W

Initialized Value: 0x0000 0000

Operational Settings: Write integer 0 for input; Write 1, for closed switch.

Switch Control

Function: Enables a 3.3V pull-up on the channel that may be used for open circuit detection.

Type: unsigned binary word (32-bit)

Read/Write: R/W

Initialized Value: 0x0000 0000

Operational Settings: Write integer 1 for open circuit detection. Default is 0, which does not provide open circuit detection. When an open circuit occurs, the voltage read on the channel will be pulled up to ~2.7 V. Normal reading is 0.

Open Circuit Detection

Function: Reads whether the state of the switch is open or closed. Used as part of CBIT status determination.

Type: unsigned binary word (32-bit)

Read/Write: R

Initialized Value: N/A

Operational Settings: N/A

Switch State

Function: Reads High 1 or Low 0 as defined by internal channel threshold values.

Type: unsigned binary word (32-bit) |Data Range: |0x0000 0000 to 0x0000 FFFF

Read/Write: R

Initialized Value: N/A

Operational Settings: N/A

Read I/O

Function: Sets the maximum high threshold value. Programmable per channel from -80 to 80 VDC, with binary 10-bit word resolution (LSB=100 mv).

Type: signed binary dword (32-bit) |Data Range: |0xFFFF FCE0 to 0x0000 0320 (-80.0V to 80.0V) Read/Write: R/W Initialized Value: 0x64 (10V)

Operational Settings: Assumes that the programmed level is the maximum voltage used to indicate a Max High Threshold. If a signal is greater than the Max High Threshold value, a flag is set in the Max High Threshold Status register. The Max High Threshold register may be used to monitor any type of high signal voltage condition or threshold such as a “Short to +V” as it applies to input measurement as well as contact sensing applications.

Function: Sets the upper threshold value. Programmable per channel from -80 to 80 VDC, with binary 10-bit word resolution (LSB=100 mv).

Type: signed binary word (32-bit) |Data Range: |0xFFFF FCE0 to 0x0000 0320 (-80.0V to 80.0V) Read/Write: R/W Initialized Value: 0x32 (5V)

Operational Settings: A signal is considered logic High (1) when its value exceeds the Upper Threshold and does not consequently fall below the Upper Threshold in less than the programmed Debounce Time.

Function: Sets the lower threshold value. Programmable per channel from -80 to 80 VDC, with binary 10-bit word resolution (LSB=100 mv).

Type: signed binary dword (32-bit) |Data Range: |0xFFFF FCE0 to 0x0000 0320 (-80.0V to 80.0V) Read/Write: R/W Initialized Value: 0x1E (3V)

Operational Settings: A signal is considered logic Low (0) when its value falls below the Lower Threshold and does not consequently rise above the Lower Threshold in less than the programmed Debounce Time.

Function: Sets the minimum low threshold. Programmable per channel from -80 to 80 VDC, with binary 10-bit word resolution (LSB=100 mv).

Type: signed binary dword (32-bit) |Data Range: |0xFFFF FCE0 to 0x0000 0320 (-80.0V to 80.0V) Read/Write: R/W Initialized Value: 0x0 (0V)

Operational Settings: The programmed level is the voltage used to indicate a minimum low threshold. If a signal is less than the Min Low Threshold value, a flag is set in the Min Low Threshold Status register. The Min Low Threshold register may be used to monitor any type of low signal voltage condition or threshold such as a “Short to Ground” as it applies to input measurement as well as contact sensing applications.

Function: Reads actual voltage at I/O pin per individual channel.

Type: signed binary dword (32-bit) |Data Range: |0xFFFF FCE0 to 0x0000 0320 (-80.0V to 80.0V) Read/Write: R Initialized Value: N/A

Operational Settings: Value is a signed binary 32-bit word, where LSB = 100 mV. Data is read as 2’s complement number. For example, if output voltage word is 0x00F0 (240d), actual voltage is 24.0 V.

Voltage Reading (Sampled)

|Function: Reads averaged value of the output voltage at I/O pin per individual channel. |Type: signed binary dword (32-bit) |Data Range: 0xFFFF FCE0 to 0x0000 0320 (-80.0V to 80.0V) |Read/Write: R |Initialized Value: N/A |Operational Settings: Value is an unsigned binary 10-bit word, where LSB=100 mV. For example, if output voltage word is 0x00F0 (240d), actual voltage is 24.0 V.

Voltage Reading (Averaged)

Function: Reads current through the P/N pins per channel.

Type: signed binary dword (32-bit) |Data Range: |0xFFFF FEC8 to 0x0000 0138 (-624 mA to 624 mA) Read/Write: R Initialized Value: Updated by module as per conditions Operational Settings: Value is signed binary 32-bit word, where LSB=2 mA. Read as 2’s complement; Current source is positive, Current sink is negative. For example, if output current word is 0x0064 (100d), actual current is 200 mA.

Current Reading (Sampled)

Function: Reads averaged current through the P/N pins per channel.

Type: signed binary dword (32-bit) |Data Range: |0xFFFF FEC8 to 0x0000 0138 (-624 mA to 624 mA) Read/Write: R Initialized Value: N/A

Operational Settings: Value is signed binary 32-bit word, where LSB=2 mA. Read as 2’s complement; Current source is positive, Current sink is negative. For example, if output current word is 0x0064 (100d), actual current is 200 mA.

Current Reading (Averaged)

Function: Sets the Debounce time (LSB= 10 μs; 32-bit resolution) for each channel.

Type: unsigned binary dword (32-bit) |Data Range: |0x0000 0000 to 0xFFFF FFFF Read/Write: R/W Initialized Value: 0 (no debounce/disabled)

Operational Settings: The Debounce Time register, when programmed for a non-zero value, is used with channels to “filter” or “ignore” expected application spurious initial transitions. Enter required Debounce Time into appropriate channel registers. LSB weight is 10 µs/bit (register may be programmed from 0x0000 0000 (debounce filter inactive) through a maximum of 0xFFFF FFFF (2^32 * 10µs). (full scale w/ 10 µs resolution). Once a signal level is a logic voltage level period longer than the debounce time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed Debounce Time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state. Enter a value of 0 to disable debounce filtering.

Function: Sets the overcurrent value for each channel.

Type: signed binary dword (32-bit) |Data Range: |0xFFFF FEC8 to 0x0000 0138 (-624 mA to 624 mA) Read/Write: R/W Initialized Value: 0x138 (624 mA)

Operational Settings: LSB = 2 mA

Overcurrent Value

Function: Resets disabled channels in Overcurrent Latched Status register following an overcurrent condition as measured by the Current Reading register.

Type: unsigned binary dword (32-bit) |Data Range: |0x0000 0000 to 0x0000 0001

Read/Write: R/W

Initialized Value: 0x0

Operational Settings: 1 is written to reset disabled channels. Processor will write a 0 back to the Overcurrent Reset register when reset process is complete.

Overcurrent Reset

The Discrete Module provides status registers for BIT, Low-to-High Transition, High-to-Low Transition, Overcurrent, Above Max High Threshold, Below Min Low Threshold, and Mid-Range.

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

BIT Dynamic Status BIT Latched Status BIT Interrupt Enable BIT Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit) |Data Range: |0x0000 0000 to 0x0000 FFFF Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0

Note: Faults are detected (associated channel(s) bit set to 1) within 10 ms.

There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Overcurrent Dynamic Status Overcurrent Latched Status Overcurrent Interrupt Enable Overcurrent Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Overcurrent error.

Type: unsigned binary word (32-bit) |Data Range: |0x0000 0000 to 0x0000 FFFF Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0 |Note: |Status is indicated (associated channel(s) bit set to 1), within 80 ms. |Note: |Channel(s) shut down by overcurrent sensed can be reset by writing to the Overcurrent Reset register

There are four registers associated with the Above Max High Threshold Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.

Above Max High Threshold Dynamic Status Above Max High Threshold Latched Status Above Max High Threshold Interrupt Enable Above Max High Threshold Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Above Max High Threshold event.

Type: unsigned binary word (32-bit) |Data Range: |0x0000 0000 to 0x0000 FFFF Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0

There are four registers associated with the Above Max High Threshold Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.

Below Min Low Threshold Dynamic Status Below Min Low Threshold Latched Status Below Min Low Threshold Interrupt Enable Below Min Low Threshold Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Below Min Low Threshold event.

Type: unsigned binary word (32-bit) |Data Range: |0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the Mid-Range Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.

Mid-Range Dynamic Status Mid-Range Latched Status Mid-Range Interrupt Enable Mid-Range Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Mid-Range event.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0 |Note: |Voltage level needs to be between the upper and lower thresholds for the debounce time for this status to assert. |Note: |In the event this status is asserted, the Input/Output state will hold its previous state.

There are four registers associated with the High-to-Low Transition Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Low-to-High Dynamic Status

Low-to-High Latched Status

Low-to-High Interrupt Enable

Low-to-High Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Low-to-High Transition event.

Type: unsigned binary word (32-bit) |Data Range: |0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0 |Note: Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.

|Note: |Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs. |Note: |Transition status follows the value read by the Input/Output State register.

There are four registers associated with the High-to-Low Transition Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

|High-to-Low Dynamic Status High-to-Low Latched Status High-to-Low Interrupt Enable High-to-Low Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s High-to-Low Transition event.

Type: unsigned binary word (32-bit) |Data Range: |0x0000 0000 to 0x0000 FFFF |Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0 |Note: |Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.

|Note: |Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs. |Note: |Transition status follows the value read by the Input/Output State register.

The Discrete Module provides registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status register descriptions.

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

The User Watchdog Timer (UWDT) Capability is available on the following modules:

The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.

The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:

A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.

The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.

The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.

Figure 1. User Watchdog Timer Overview

Figure 2. User Watchdog Timer Example

Figure 3. User Watchdog Timer Failures

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

Key

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.