Function: This register is the transmit data FIFO. In immediate or triggered FIFO modes, transmit data is placed here prior to transmission. ARINC data words are 32-bits.

Type: unsigned character word

Data Range: 0 to 0xFFFFFFFF

Read/Write: W

Initialized Value: N/A

Operational Settings: ARINC data words are 32-bits.

Tx FIFO

Function: In FIFO receive mode, the received ARINC messages are read back from here.

Type: unsigned integer word

Data Range: 0 to 0xFFFFFFFF

Read/Write: R

Initialized Value: N/A

Operational Settings: In normal mode, reads from this register retrieve the ARINC data word. In FIFO extended write mode, perform two reads from this register to retrieve the Status/timestamp word and the ARINC data word, respectively.

Rx FIFO

PE = Parity Error ‘1' Calculated parity does not match the received parity bit BE = BIT Error ‘1' BIT word did not match received word T = Timestamp 28-bit Timestamp value

Function: Specifies the level of the transmit buffer, equal or below, at which the Tx FIFO Almost Empty Status bits in the Latched Status and Dynamic Status registers are set.

Type: unsigned integer

Data Range: 0 to 1023

Read/Write: R/W

Initialized Value: 0x20 (32)

Operational Settings: This register is not reset by a channel reset.

Tx FIFO Almost Empty Value

Function: Specifies the level of the transmit buffer, equal or above, at which the Tx FIFO Almost Full Status bits in the Latched Status and Dynamic Status registers are set.

Type: unsigned integer

Data Range: 0 to 1023

Read/Write: R/W Initialized Value*: 0x80 (128)

Operational Settings: This register is not reset by a channel reset.

Tx FIFO Almost Full Value

Function: Specifies the level of the receive buffer, equal or below, at which the Rx FIFO Almost Full Status bits in the Latched Status and Dynamic Status registers are set.

Type: unsigned integer

Data Range: 0 to 1023

Read/Write: R/W

Initialized Value: 0x20 (32)

Operational Settings: This register is not reset by a channel reset.

Rx FIFO Almost Empty Value

Function: Specifies the level of the receive buffer, equal or above, at which the Rx FIFO Almost Full Status bits in the Latched Status and Dynamic Status registers are set.

Type: unsigned integer

Data Range: 0 to 1023

Read/Write: R/W

Initialized Value: 0x80 (128)

Operational Settings: This register is not reset by a channel reset.

Rx FIFO Almost Full Value

Function: Contains the number of ARINC 32-bit words in the transmit FIFO.

Type: unsigned integer word

Data Range: 0 to 1024

Read/Write: R

Initialized Value: 0

Operational Settings: Used only in FIFO transmit modes.

Tx FIFO Count

Function: Contains the number of words in the receive FIFO.

Type: unsigned integer word

Data Range: 0 to 1024

Read/Write: R

Initialized Value: 0

Operational Settings: If timestamp is disabled, the number of words will equal the number of ARINC data words. If timestamp is enabled, the number of words will be three per ARINC data words. One for the status, one for the ARINC message and one for the timestamp

Rx FIFO Count

Function: Specifies gap time between transmitted messages.

Type: 32-bit unsigned integer

Data Range: 1-1023

Read/Write: R/W

Initialized Value: 4

Operational Settings: Each LSB is 1-bit time. Rates less than 4 are not valid for AR579.

Transmit Gap Time (AR579)

Function: Determines the resolution of the timestamp counter.

Type: binary word

Data Range: not applicable

Read/Write: R/W

Initialized Value: 0x0000 (1 µs)

Operational Settings: The LSB can have one of four time values. Set bit D2 to 1 to zero out the timestamp counter. The default LSB value is 1 µs

Timestamp Control Register (AR579)

Function: Read current 28-bit timestamp value.

Type: unsigned integer

Data Range: 0 to 0xFFFFFFF

Read/Write: R

Initialized Value: not applicable

Operational Settings: The time value of each LSB is determined by the resolution set in the Timestamp Control Register.

Timestamp Register (AR579)

Function: Specifies the transmit and receive configuration for the channel

Type: binary word

Data Range: not applicable

Read/Write: R/W

Initialized Value: not applicable

Operational Settings: When BOUNDED RX FIFO is set to 0, after the FIFO is full, the new data will overwrite the oldest value in the FIFO. When BOUNDED RX FIFO is set to 1, after the FIFO is full, the circuitry will block additional writes to the FIFO.

When the Rx Parity Disable bit is set to 0, ARINC data bit 32 is treated as an odd parity bit. The receiver checks the received ARINC word for odd parity and will flag an error if it is not correct. Parity generation is not available. The user is responsible for generating the odd parity bit for transmitted data. When Rx Parity Disable Is set to 1, parity checking will be disabled.

When the Rx Store on Error bit is set to 0, received words are stored in the receive FIFO, regardless of their parity condition. When the Rx Store on Error bit is set to 1 and parity is enabled, received words that contain a parity error will not be stored in the receive FIFO.

When Rx Time Stamp Enable bit is set to 1, the receiver stores a 32-bit time stamp value along with the received ARINC word and status. The timestamp has 4 selectable resolutions and can be reset via the Time Stamp Control register. It is recommended to clear the Receive FIFOs whenever the Receive mode or Time Stamp Enable mode is changed to ensure that extraneous data is not leftover from a previous receive operation.

When BOUNDED TX FIFO is set to 0, after the FIFO is full, the new data will overwrite the oldest value in the FIFO. When BOUNDED TX FIFO is set to 1, after the FIFO is full, the circuitry will block additional writes to the FIFO.

When Tx FIFO Immediate is set to 0, writes to the FIFO will not be transmitted until a Transmit Initiate bit is set in the Control register. When Tx FIFO Immediate is set to 1, writes to the FIFO will immediately be transmitted. When SLOPE CONTROL is set to 0, the Tx has a 10 µs rise/fall time. When SLOPE CONTROL is set to 1, the Tx has 1.5 µs output rise/fall time.

Channel Configuration (AR579)

Function: Specifies the transmit and receive configuration for the channel.

Type: binary word

Data Range: not applicable

Read/Write: R/W

Initialized Value: not applicable

Operational Settings: The BOUNDED RX FIFO bit is used to select the behavior of a full FIFO. When BOUNDED RX FIFO is set to 0, after the FIFO is full, the new data will overwrite the oldest value in the FIFO.

When BOUNDED RX FIFO is set to 1, after the FIFO is full, the circuitry will block additional writes to the FIFO.

When BOUNDED TX FIFO is set to 0, after the FIFO is full, the new data will overwrite the oldest value in the FIFO. When BOUNDED TX FIFO is set to 1, after the FIFO is full, the circuitry will block additional writes to the FIFO. When Tx FIFO Immediate is set to 0, writes to the FIFO will not be transmitted until a Transmit Initiate bit is set in the Control register. When Tx FIFO Immediate is set to 1, writes to the FIFO will immediately be transmitted. TX LOOPBACK connects the Rx Channel to the Tx Channel. This can be used to test the channel.

Channel Configuration (AR568)

Function: Sets the control for the Tx Channel.

Type: binary word

Data Range: not applicable

Read/Write: R/W

Initialized Value: not applicable

Operational Settings: The Transmit Enable bit should be set after all transmit parameters are set up. This is important in Tx Immediate FIFO mode since this mode transmits as soon as data is put into the Tx FIFO. For the other transmit modes, a Tx Initiate is required before transmission begins. Tx Initiate is self-cleared after the last word is sent from the Tx FIFO.

CLEAR Tx FIFO clears the Tx FIFO and is self-clearing. TX RESET ALL clears the Tx circuitry, resets the TX ENABLE and TX INITIATE bits, clears the Tx Fifo, and is self-clearing.

Tx Channel Control

Function: Sets the control for the Rx Channel.

Type: binary word

Data Range: not applicable

Read/Write: R/W

Initialized Value: not applicable

Operational Settings: The RX Enable bit should be set after all receive parameters are set up. After setting this bit, the module will look for a minimum 4-bit gap time before decoding any ARINC bits to prevent it from receiving a partial ARINC word.

CLEAR RX FIFO clears the Rx FIFO and is self-clearing. RX RESET ALL clears the Rx circuitry, resets the RX ENABLE bit, clears the Rx FIFO, and is self-clearing.

Rx Channel Control

Function: Contains the Built-In-Test (BIT) status of both channels on the module.

Type: binary word

Data Range: N/A

Read/Write: R

Initialized Value: 0x0

Operational Settings: When a BIT error is detected, the channel’s respective bit is set to 1 in this register.

BIT Dynamic Status

Function: Channels set for Inputs – Latched Fault Status (BIT Error) is set when a redundant measurement is inconsistent with the input measurement level detected. Channels set for Outputs – BIT Error is set when a dedicated measurement circuit compares the commanded level with the actual output level and the measurement is inconsistent with the commanded level.

Type: binary word (32-bit)

Data Range: 0x 0000 0000 to 0x 0000 0003

Read/Write: R/W

Initialized Value: 0

Operational Settings: 1 is written when a fault is detected. 0 indicates no fault detected.

BIT Latched Status

Function: When enabled, interrupts are generated for each channel when the BIT Latched Status register indicates a fault.

Type: binary word (32-bit)

Data Range: 0x 0000 0000 to 0x 0000 0003

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to enable interrupts. Write a 0 to disable interrupts.

BIT Interrupt Enable

Function: When the BIT Interrupt Enable register is enabled, this register determines whether the interrupt will be generated for either “sense on edge” or “sense on level” event detection. Sense on “edge” requires a change from “no-go” to “go” state to trigger the status detection, while sense on “level” is independent of the previous state.

Type: binary word (32-bit)

Data Range: 0x 0000 0000 to 0x 0000 0003 Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge. Default: Sense on edge (0)

BIT Set Edge/Level Interrupt

Function: Real-time status

Type: binary word

Data Range: not applicable

Read/Write: R/W

Initialized Value: not applicable

Operational Settings: The Rx Data Available bit is set when the receive FIFO is not empty.

The Rx FIFO Read Error bit will set whenever a read command is issued on an empty Rx FIFO. The Rx FIFO Overflow bit is dependent on the BOUNDED RX FIFO. If BOUNDED RX FIFO is set to 0, RX FIFO OVERFLOW is set whenever the receiver overwrites the oldest data because the receive FIFO was full. If BOUNDED RX FIFO is set to 1, RX FIFO OVERFLOW is set whenever the receiver discards data because the receive FIFO is full.

The Rx PARITY ERROR (AR579 mode only) is set when the parity valued received from the data word does not equal the generated odd parity.

The Rx FRAME ERROR is set if the receiver circuit does not acquire the 32-bit word correctly. The Tx BUSY bit is set if the Tx is actively transmitting data The Tx FIFO Overflow bit is set whenever the user attempts to write to a full TxFIFO.

Function: Indicates latched status of each channel.

Type: binary word

Data Range: N/A

Read/Write: R/W

Initialized Value: N/A

Operational Status: These events are latched when they occur. Clear a latched status bit by writing a ‘1' to the corresponding bit. Interrupts may be triggered if enabled by setting the corresponding status event Interrupt Enable bits in the Interrupt Enable register. See the specific bit function description and reference software programming (API) for details as applicable.

Latched Status

Function: Enables interrupts for various functions.

Type: binary word

Data Range: N/A

Read/Write: R/W

Initialized Value: N/A

Operational Settings: Set the corresponding bit for a function to 1 to enable interrupts. See specific registers for function description and programming.