The DA3 module supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are logically OR’d together and stored in the BIT Dynamic Status and BIT Latched Status registers.

The DA3 includes two voltage feedback sense lines for each output channel. They provide automatic output drive voltage compensation during higher current applications that may induce voltage drops in the wiring. It is always recommended that the sense lines be utilized and connected at the external load to provide maximum measurement accuracy (which ensures that the commanded voltage is applied at the load). Sense (Hi) should be connected to Output (Hi), and Sense (Lo) should be connected to Output (Lo).

Channels that are programmed for voltage command mode are required to utilize the sense lines for maximum accuracy. If additional wiring is prohibitive in the application, the sense lines may alternately be terminated at the connector.

Channels that are programmed for current command mode may utilize the sense lines, but it is not required. Current mode is controlled via internal feedback, making the compensated voltage at the load irrelevant.

The DA3 module provides the ability to use memory buffers either as a Pattern buffer, (addressable RAM used for creating an output pattern (or cycling)) or as a FIFO buffer. These buffers provide greater control of the output voltage and signal data. The D/A buffers will accept, store and output the voltage (and/or current) commands, once enabled and triggered, for applications requiring simulation of waveform generation; single or periodic. The output data command word is formatted as a percentage of the full scale (FS) range selection, which allows maximum resolution and accuracy at lower voltage ranges.

The D/A Module provides registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

The D/A Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

The D/A Module Data, Voltage and Current Measurement registers can be programmed to be utilized as single precision floating point values (IEEE754) or as a 32-bit integer value.

When the Enable Floating Point Mode register is set to 1 (Floating Point Mode) the following registers are formatted as Single Precision Floating Point Value (IEEE-754):

Wrap Voltage (Volts)

Wrap Current (mA)

DAC Value (Voltage (Volts) or Current (mA))*

When the Enable Floating Point Mode register is set to 1, it is important that these registers are updated with the Single Precision Floating Point (IEEE-754) representation of the value for proper operation of the channel. Conversely, when the Enable Floating Point Mode register is set to 0, these registers must be updated with the Integer 32-bit representation of the value. Note, when changing the Enable Floating Point Mode from Integer Mode to Floating Point Mode or vice versa, the following step should be followed to avoid faults from falsely being generated because interior registers have an incorrect binary representation of the values:

It is very often necessary to relate D/A voltage and current to other engineering units such as PSI (Pounds per Square Inch). When the Enable Floating Point Mode register is set to 1, the values entered for the Floating Point Offset register and the Floating-Point Scale register will be used to convert the D/A data from engineering units to voltage or current values. The purpose of this is to offload the processing that is normally performed by the mission processor to convert the physical quantity to voltage or current values for the DAC Value register and the FIFO Buffer Data register. When enabled, the module will compute the D/A data as follows:

D/A Value as Volts/Current (Floating Point) = (D/A Value in Engineering Units (Floating Point) + *Floating Point Offset) * Floating Point Scale8

Note:

When Enable Floating Point Mode is set to 1 (Floating Point Mode) the listed registers below are formatted as Single Precision Floating Point Value (IEEE-754) and the values specified in the Floating Point Offset register and the Float Point Scale register are applied:

The Digital-to-Analog Modules provide support for Watchdog Timer capability. Refer to “Watchdog Timer Module Manual” for the Principle of Operation description.

Function: Sets the output voltage or current for the channel.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: DAC values are dependent on Voltage Range/Current Range setting for the channel

Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x0000 FFFF;

Bipolar (2’s compliment. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples

Function: Sets each channel for voltage-control or current-control mode.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R/W

Initialized Value: 0 (Voltage Mode for all channels)

Operational Settings: Write a 1 to set the channel for current-control mode.

Write a 0 to set the channel for voltage-control mode. Bit-mapped per channel.

Note: Both the Voltage and Current command mode rely on the Voltage Range setting to establish the internal power supply (±VCC) output driver power supply rail voltages. The ±VCC internal power supply rails must be adequately set for the output voltage required by the load, even when operating in current command mode.

Voltage/Current Mode

Function: Sets voltage polarity and range for each channel. If the channel is set for voltage-control mode, the value written to the DAC Value register (or values coming from the memory buffer) will correlate to the voltage range set in this register.

Note, if the Enable Floating Point Mode register is set to 1, the Floating Point Scale register must be set to the reciprocal of Voltage Range.

Type: unsigned binary word (32-Bit)

Data Range: See table below.

Read/Write: R/W

Initialized Value: 0 (Unipolar: 0-20 V)

Operational Settings: Write to the register with a value from the table to select the range. Ex: for the 0-20V unipolar range write a 0x0.

Note: The voltage range setting also sets the module/channels internal power supply ±VCC rails for the output driver when either voltage or current mode is selected. The multiple internal power VCC settings optimize the power efficiency for the expected operating range.

Voltage Range

Function: Sets current polarity and range for each channel. If the channel is set for current-control mode, the value written to the DAC Value register (or values coming from the memory buffer) will correlate to the current range set in this register. Note, if the Enable Floating Point Mode register is set to 1, the Floating Point Scale register must be set to the reciprocal of Current Range.

Type: unsigned binary word (32-Bit)

Data Range: See table below.

Read/Write: R/W

Initialized Value: 0 (Unipolar: 0-50 mA)

Operational Settings: Write to the register with a value from the table to select the range.

For example, for the ±50 mA bipolar range write 0x3 to the register. If this current range is exceeded and the Current Range Exceeded Interrupt Enable register is enabled, then a Current Range Exceeded Status interrupt will occur.

If the Voltage Range register is set to 40V but the Current Range register is set to 50 mA maximum if 50 mA is exceeded then an interrupt will occur. Overcurrent conditions are always checked for at the maximum range (±100 mA).

Note: The Voltage Range setting determines the internal power supply rails (±VCC) for the output driver when commanding voltage or current. In current command mode, ensure that the selected range aligns with the required rail voltages (±10 V, ±20 V, or ±40 V) for the commanded current range and external load impedance. The internal VCC power supply rails must be set to exceed the voltage required for the commanded current.

Example: For a ±30 mA current into a 200-ohm load, Vmax(load) = (30 mA x 200) = 6 V, one could leave the Voltage Range as the defualt 'Initialized Value: 0 (Unipolar: 0-20 V)" or it can be set to "Bipolar: ±10 V" for better/optimal power dissipation efficiency. For a 1000-ohm load, Vmax(load) = 30 V, set Voltage Range to either "Unipolar: 0 - 40 V" or "Bipolar: ±40 V" to set the required internal power supply VCC rails to ±40 V.

If the Voltage Range register is set with the internal power supply rails (±VCC) lower than demanded by the current command and load, the output drive will be current 'clipped', triggering a BIT fault. Overcurrent is checked at the maximum range (±100 mA). either voltage or current mode is selected. The multiple internal power VCC settings optimize the power efficiency for the expected operating range.

Current Range

Function: Enables the DAC’s channel power.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R/W

Initialized Value: 0x0000 000F (Channel power is enabled)

Operational Settings: Set bit to 1 to enable the power. Set bit to 0 to disable the power.

Power Enable

Function: Sets the output rate for the DAC output, FIFO Data Output and RAM Output.

Type: unsigned binary word (32bit)

Data Range: 0x001E 8480 to 0x0003 0D40; 500ns (2MHz) to 5µs (200kHz).

Read/Write: R/W

Initialized Value: 0x001E 8480 (500ns) (2MHz)

Operational Settings: This setting is the output rate for each DAC. One update rate applies to all channels.

Function: Resets over loaded channels based on the Overcurrent Status register.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1 Read/Write: W Initialized Value: 0

Operational Settings: Set to 1 to reset over loaded channels. Writing a 1 to this register will re-enable over loaded channels.

Overcurrent Reset

Function: Sets the overcurrent value to be used to determine the overcurrent condition.

Type: unsigned binary word (32-bit)

Data Range: 0x0001 to 0x0078; 1 mA to 120 mA.

Read/Write: R/W

Initialized Value: 0x0078 (120 mA); Note - steady state current rating for each channel is still 100mA

Operational Settings: LSB = 1 mA. This setting is the value that is used to determine the overcurrent condition for each channel. This value is applied to both positive and negative currents. Note, the maximum value for the overcurrent value is 120 mA; values greater than this will be forced to the maximum value.

Function: Wrap voltage reading from the channel’s output. Also used in conjunction with BIT to verify that the output voltage is within range of the user set DAC value (voltage-control mode).

Accuracy is 0.2% FS.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)

Unipolar: 0x0000 0000 to 0x0003 FFFF

Bipolar (2’s compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0001 7FFF

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: 0

Operational Settings: To calculate the LSB subtract the minimum voltage range from the maximum voltage range then divide by 2^16. For example, if the value in the Voltage Range Register is range 0-10V then the LSB would have value (10-0)/2^16 = .153 mV. Sign bit = D17 for bipolar ranges.

Wrap Voltage (Enable Floating Point Mode: Integer Mode)

Wrap Voltage (Enable Floating Point Mode: Floating Point Mode)

Function: Wrap current reading from the channel’s output. Reads current values of D/A outputs being delivered per channel. Also, used in conjunction with BIT to verify that the output current is within range of the user set DAC value (current-control mode). Accuracy is 0.2% FS.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)

Unipolar: 0x0000 0000 to 0x0003 FFFF

Bipolar (2’s compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0001 7FFF

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: 0

Operational Settings: To calculate the LSB subtract the minimum range from the maximum range then divide by 2^16. Sign bit = D17 for bipolar ranges. In Voltage mode, the range is fixed to 100mA.

Wrap Current (Enable Floating Point Mode: Integer Mode)

Wrap Current (Enable Floating Point Mode: Floating Point Mode)

Function: Sets bit to enable the associated CBIT (“D2”) or IBIT (“D3”). Note – CBIT cannot be disabled

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000C

Read/Write: R/W

Initialized Value: 0x4 (CBIT Test Enabled)

Operational Settings: BIT tests include an on-line CBIT and an off-line IBIT tests. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects failures.

Test Enabled

Function: Sets the data mode of the channel. The output can be based on either the DAC Value register or the RAM Buffer.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R/W

Initialized Value: 0 (The output will reflect the DAC Value register value)

Operational Settings: Write a 1 to use the memory buffer. Bit-mapped per channel.

Data Mode

Function: Selects how the memory buffer will be used; either as a Pattern buffer (addressable RAM used for creating an output pattern (or cycling)) or FIFO buffer.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R/W

Initialized Value: 0 (RAM Mode)

Operational Settings: Write a 1 to use the buffer for the channel as a FIFO. Write a 0 to use the buffer as Pattern RAM. To use the memory buffer, ensure that the Data Mode register is set properly.

Bit-mapped per channel.

Buffer Mode

Function: Data in the form of DAC values are written to this register one word at a time (16-bits), and will be outputted to the channel’s output once triggered. Buffer will be emptied one value at a time when triggered.

Type: signed binary word (32-bits) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)

Unipolar: 0x0000 0000 to 0x0000 FFFF

Bipolar (2’s compliment. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: W

Initialized Value: N/A

Operational Settings: Data is held in FIFO until triggered.

FIFO size is 32767 words per channel (each channel has its own buffer).

Function: Reports the number of words stored in the FIFO buffer.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 7FFF (empty to 32767)

Read/Write: R

Initialized Value: 0 (FIFO is empty)

Operational Settings: Each time a value is written to the FIFO buffer this count is incremented by 1. Once the FIFO is triggered, after each value is outputted to the DAC, this count will be decremented by 1. Watermarks and threshold values can be setup to trigger interrupts when this count crosses user defined values. The maximum number of words that can be stored in the FIFO is 32767 words.

Function: This register enables the user to set the limit for the “almost empty” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 7FFF

Read/Write: R/W

Initialized Value: 0x400 (1024)

Operational Settings: When the FIFO Word Count is less than or equal to the value stored in the FIFO

Almost Empty Value register, the “almost empty” bit (D1) of the FIFO Status register will be set. When the FIFO Count is greater than the value stored in the register, the “almost empty” bit (D1) of the FIFO Status register will be cleared.

Function: The FIFO low watermark threshold enables the user to set the limit for the “low watermark” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 7FFF

Read/Write: R/W

Initialized Value: 0x2000 (8192)

Operational Settings: When the FIFO Count is less than or equal than the value stored in the FIFO Low Watermark Value register, the “low watermark” bit (D2) of the FIFO Status register will be set. When the FIFO Count is greater than the value stored in the register, the “low watermark” bit (D2) of the FIFO Status register will be cleared.

Function: The FIFO high watermark threshold enables the user to set the limit for the “high watermark” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 7FFF

Read/Write: R/W

Initialized Value: 0x6000 (24576)

Operational Settings: When the FIFO Count is greater than or equal to the value stored in the FIFO High Watermark Value register, the “high watermark” bit (D3) of the FIFO Status register will be set. When the FIFO Count counter is less than the value stored in the register, the “high watermark” bit (D3) of the FIFO Status register will be cleared.

Function: This register enables the user to set the limits for the “almost full” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 7FFF

Read/Write: R/W

Initialized Value: 0x7C00 (31744)

Operational Settings: When the FIFO Count register is greater than or equal to the value stored in the FIFO Almost Full Value register, the “almost full” bit (D4) of the FIFO Status register will be set. When the FIFO Count is less than the value stored in the FIFO Almost Full Value register, the “almost full” bit (D4) of the FIFO Status register will be cleared

Function: Clears the FIFO buffer.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: W

Initialized Value: 0

Operational Settings: Writing a 1 will clear the FIFO buffer and reset the count in the FIFO Word Count register.

Clear FIFO

Function: If the memory buffer is enabled writing the trigger value to this register will start the output. Values stored in the FIFO will be output at the set update rate until the FIFO is empty.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: R/W

Initialized Value: 0

Operational Settings: To initiate output from the FIFO Data register the Use FIFO register must be enabled. Then write a 1 to the FIFO Control register to begin outputting data. The 1 will clear once the FIFO empties.

FIFO Software Trigger

Function: Control the RAM data output.

Type: unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R/W

Initialized Value: 0

Operational Settings: The Pattern Start Address register determines where the Pattern output will begin when enabled. The Pattern End Address register determines where the Pattern output will end when enabled. After the pattern at the Pattern End Address is outputted, it will loop back to the start address.

Description

Pattern RAM Control

Function: Programs the starting address for the Pattern output buffer. There are 32767 address locations.

Type: unsigned binary word (32-bit)

Data Range: Ch 1: 0x0002 0000 to 0x0003 FFFC; Ch 2: 0x0004 0000 to 0x0005 FFFC; Ch 3: 0x0006 0000 to 0x0007 FFFC; Ch 4: 0x0008 0000 to 0x0009 FFFC

Read/Write: R/W

Initialized Value: Ch 1: 0x0002 0000; Ch 2: 0x0004 0000; Ch 3: 0x0006 0000; Ch 4: 0x0008 0000;

Operational Settings: Address where the Pattern buffer will start when it is enabled.

Function: Programs the ending address for the Pattern output buffer. There are 32767 address locations.

Type: unsigned binary word (32-bit)

Data Range: Ch 1: 0x0002 0000 to 0x0003 FFFC; Ch 2: 0x0004 0000 to 0x0005 FFFC; Ch 3: 0x0006 0000 to 0x0007 FFFC; Ch 4: 0x0008 0000 to 0x0009 FFFC

Read/Write: R/W

Initialized Value: Ch 1: 0x0002 0000; Ch 2: 0x0004 0000; Ch 3: 0x0006 0000; Ch 4: 0x0008 0000;

Operational Settings: Address where the Pattern buffer will end when it is enabled. After the DAC value that is stored at this address is outputted, the buffer will jump back to the Pattern Start Address.

Function: Set the number of Pattern cycles for a channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0001 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When the Pattern buffer is enabled in burst mode, it will loop from the Pattern Start Address to the Pattern End Address the number of times that is set in this register.

Function: Sets all channels for floating point mode or integer module.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: R/W

Initialized Value: 0 (Integer mode)

Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode.

Function: This register sets the floating-point offset to add to DA output.

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

Read/Write: R/W

Initialized Value: 0.0

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point examples.

Function: This register sets the floating-point scale to multiple to the DA output.

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: N/A Read/Write: R/W Initialized Value: 0.0

Operational Settings: When changing the Voltage Range or Current Range, the Floating Point Scale needs to be adjusted in order for the Wrap Voltage and Wrap Current floating point representation to be scaled correctly.

Function: Indicates whether the module’s internal processing is converting the register values and internal values to the binary representation of the mode selected (Integer or Floating Point).

Type: unsigned binary word (32-bit)

Data Range: 0 to 1

Read/Write: R

Initialized Value: 0

Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

Floating Point State

Function: Sets BIT Threshold value (in milliseconds) to use for all channels for BIT failure indication.

Type: unsigned binary word (32-bit) Data Range: 1 ms to 2^32 ms

Read/Write: R/W

Initialized Value: 0x5 (5ms)

Operational Settings: The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module.

Function: Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: W

Initialized Value: 0

Operational Settings: Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.

Reset BIT

Function: Determines whether to update the status for the channels. This feature can be used to “mask” status bits of unused channels in status registers that are bitmapped by channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F (Channel Status)

Read/Write: R/W

Initialized Value: 0x0000 000F

Operational Settings: When the bit corresponding to a given channel in the Channel Status Enabled register is not enabled (0) the status will be masked and report “0” or “no failure”.

This applies to all statuses that are bitmapped by channel (BIT Status, Overcurrent Status and Summary Status).

Note, Background BIT will continue to run even if the Channel Status Enabled is set to ‘0'.

Channel Status Enabled

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The BIT Status register will indicate an error when the D/A conversion is outside 0.2% FS accuracy spec.

BIT Dynamic Status

BIT Latched Status

BIT Interrupt Enable

BIT Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Notes: BIT Status is part of background testing and the status register may be checked or polled at any given time

There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Overcurrent Dynamic Status

Overcurrent Latched Status

Overcurrent Interrupt Enable

Overcurrent Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Current Range Exceeded Dynamic Status

Current Range Exceeded Latched Status

Current Range Exceeded Interrupt Enable

Current Range Exceeded Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Current Range Exceeded error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the External Power Under Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

D0 = +12V External Power Under Voltage

D1 = -12V External Power Under Voltage

External Power Under Voltage Dynamic Status

External Power Under Voltage Latched Status

External Power Under Voltage Interrupt Enable

External Power Under Voltage Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s External Power Under Voltage error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Data is periodically transferred between the processing module and functional module within the FPGA.

A CRC value is calculated and verified with each data transfer. In order to recover from an Inter-FPGA Failure, the module needs to be reset and re-initialized.

There are four registers associated with the Inter-FPGA Status/Watchdog Timer Fault: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

The lower 16-bits represent the Inter-FPGA Failure Status: 0 = Normal; 0x000F = Inter-FPGA Communication Failure. The status represents the status for all channels on the module. Bit 31 represents the Watchdog Timer Fault: 0 = Normal; 1 = Watchdog Timer Fault.

Inter-FPGA Failure/Watchdog Timer Fault Dynamic Status

Inter-FPGA Failure/Watchdog Timer Fault Latched Status

Inter-FPGA Failure/Watchdog Timer Fault Interrupt Enable

Inter-FPGA Failure/Watchdog Timer Fault Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Inter-FPGA Failure and Watchdog Timer Fault error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Summary Status Dynamic Status

Summary Status Latched Status

Summary Status Interrupt Enable

Summary Status Set Edge/Level Interrupt

Function: Sets the corresponding bit when a fault is detected for BIT, Overcurrent, Current Range Exceeded, External Power Under Voltage or Inter-FPGA Failure on that channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0-D5 is used to show the different conditions of the buffer.

Function: Sets the corresponding bit associated with the FIFO status type; there are separate registers for each channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 003F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 1 (Empty)

Notes:

Shown below is an example of interrupts generated for the High Watermark. As shown, the interrupt is generated as the FIFO Word Count crosses the High Watermark. The interrupt will not be generated a second time until the count goes below the watermark and then above it again.

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.