Function: Data intended to be transmitted is placed in this buffer prior to transmission.

Type: unsigned character word

Data Range: 0x0000 0000 to 0x FFFF FFFF

Read/Write: W

Initialized Value: Not Applicable (NA)

Operational Settings: Data words are 8-bit and occupy the register’s lowest significant bits (LSBs), or low byte.

Transmit Buffer

Data only in Asynchronous 9-bit mode

Function: Received data is placed in this buffer.

Type: unsigned integer word.

Data Range: 0x0000 0000 to 0x FFFF FFFF

Read/Write: R

Initialized Value: NA

Operational Settings: Data is received in the low byte as unsigned integer. The high byte is used for status.

Receive Buffer

PE = Parity Error ‘1' Calculated parity does not match the received parity bit FE = Framing Error ‘1' A character framing error was detected. OE = Overrun Error ‘1' A character was received while the FIFO was full BOF = Beginning Of Frame '1' Indicates first character of frame. Useful to identify multiple frames in large buffer. EOF = End Of Frame ‘1' Indicates End of Frame. Useful to identify multiple frames in large buffer. P = Parity Bit This bit carries the Parity bit of the last received character ER2..0: HDLC Error Code: 000 = Good Frame 111 = CRC Error 001 = Frame Aborted

Function: Contains the number of words to be transmitted.

Type: unsigned integer

Data Range: 0x0000 0000 to 0x 0x2000000

Read/Write: R

Initialized Value: 0

Operational Settings: Reads Integers

Number of Words Tx Buffer

Function: Contains the number of words received.

Type: unsigned integer

Data Range: 0x0000 0000 to 0x2000000

Read/Write: R

Initialized Value: 0

Operational Settings: Reads Integers

Number of Words Rx Buffer

Function: Configures the associated channel for either asynchronous, mono-synchronous, bi-synchronous, or HDLC mode.

Type: unsigned integer

Data Range: NA

Read/Write: W

Initialized Value: 0, Asynchronous

Operational Settings: See table below.

Protocol

Function: Configures clock for internal (driven) or external (received) transmit/receive clocks

Type: unsigned integer

Data Range: NA

Read/Write: W

Initialized Value: 0

Operational Settings: Applicable only for Sync or HDLC as set by Protocol register.

Clock Mode

Function: Configures the interface level (RS-232, RS-422, RS-423 (Pending), RS-485, Loop Back, or Tri-State) for the associated channel.

Type: unsigned integer

Data Range: NA

Read/Write: W

Initialized Value: 5

Operational Settings: Loop Back selection connects the channel’s transmit and receive line internally. To implement, user must send data and look at Receive FIFO to verify that the sent data. Loop Back is usually used for test.

Note: Synchronous modes (mono-synchronous, bi-synchronous, or HDLC mode) should not be put in manual loopback or FPGA loopback mode. Synchronous modes are designed to have one channel drive the clock and one channel receive the clock. In loopback modes, the internal clock will be used for both Tx and Rx. While this may work, it is not recommended or reliable. If two channels are wired to each other for external loopback, then the clock must be inverted.

Interface Levels

Function: Sets the transmit/receive configuration for the associated channel.

Type: binary word

Data Range: NA

Read/Write: R/W

Initialized Value: 0

Operational Settings: Functions depend upon programmed protocol (see Protocol Register).

Lower Bits - Bits D0 through D15 of this register are used to configure CRC function and OPEN and IDLE flags. In HDLC mode, error protection is done by CRC generation and checking. The frame sequence at the end of each frame consists of two or four bytes of CRC checksum. 32-bit or CCITT algorithms may be selected. Upper Bits - Bits D16 through D31 of this register are used to set the transmit/receive configuration for the associated channel. Functions depend upon programmed protocol (see Protocol Register).

BIT - Set ENABLE CHANNEL bit, D24 low (0) to clear the selected channel. Set INITIATE BIT D27 high (1) to initiate BIT. After 5 ms, a 0 should be read, which indicates that the BIT test is complete. The BIT Status register reports the channel status.

Tx-Rx Configuration Upper Bits (Hi)

Tx-Rx Configuration Lower Bits (Lo)

Notes: To use RTC/CTS functions as GPIO set the RTS/CTS FLOW CONTROL D0 to 0. To change the state of RTS output write a 1 or 0 to bit D0 in the Channel Control register for RTS/GPIO. For monitoring the RTS/CTS functions as GPIO it is recommended to use the Latched Status register.

Function: Channel control configuration.

Type: binary word

Data Range: NA

Read/Write: R/W

Initialized Value: 0

Operational Settings: Real time control of the Serial channel.

Channel Control

Notes: 1. RTS/CTS as GPIO when RTS/CTS Flow Control disabled. 2. BIT is self-clearing. 3. BIT is cleared when all data from the Tx Buffer is transmitted. 4. To program for Multi-Drop Mode, the interface level must be set to RS485 and the Tristate Transmit line D0 must be set.

Function: Channel data configuration.

Type: binary word

Data Range: NA

Read/Write: R/W

Initialized Value: 0

Operational Settings: Sets up the Serial channel configuration.

Data Configuration

Function: Sets the baud rate for communications. Type: 24-bit unsigned integer

Data Range: 300 to 10 Mbps Sync (1Mbps Async), Baud Rate High & Low Registers combined

Read/Write: R/W

Initialized Value: 9600 Baud

Operational Settings: Both the Baud Rate High Register and Baud Rate Low Register are combined to determine the communications baud rate. Enter the desired baud rate directly as 24-bit unsigned integer.

Baud Rate High Register

Baud Rate Low Register

Function: Determines both the number of preambles and the preamble pattern sent out during preamble transmission.

Type: binary word

Data Range: Up to “n” preambles (value 0xDD)

Read/Write: R/W

Initialized Value: 0

Operational Settings: The high byte indicates the number of preambles. The low byte describes the preamble pattern. Preamble transmission applies to both the HDLC and Sync modes. In HDLC-mode, zero-bit insertion is disabled during preamble transmission. Affected Modes: HDLC, Bi-Sync.

Preamble

Function: Specifies the minimum size, in bytes, of the transmit buffer before the TxFIFO Almost Empty Status bit D1 in the FIFO Status register is flagged (High True).

Type: unsigned integer

Data Range: 0 to Buffer Size

Read/Write: R/W

Initialized Value: 100 decimal (64h)

Operational Settings: If the interrupt is enabled (see Interrupt Enable register), a System interrupt will be generated.

Tx Buffer Almost Empty

Function: Specifies the maximum size, in bytes, of the receive buffer before the RxFIFO Almost Full Status bit D0 in the FIFO Status register is flagged (High True).

Type: unsigned integer

Data Range: 0 to Buffer Size

Read/Write: R/W

Initialized Value: 2097051 (0x1FFF9B)

Operational Settings: If the interrupt is enabled (see Interrupt Enable register), a System interrupt will be generated.

Rx Buffer Almost Full

Function: Defines the Receive Buffer High Watermark value.

Type: binary word

Data Range: Low Watermark < High Watermark < 0x1FFF9B

Read/Write: R/W

Initialized Value: 2097051 (0x1FFF9B)

Operational Settings: When Rx Buffer size equals the High Watermark value, FIFO Status bit D3 is flagged and:

The Watermark registers are used for XON/XOFF and/or RTS/CTS flow control. The Receive Buffer High Watermark register value controls when the XOFF character is sent when using software flow control and controls when the RTS signal would be negated when using hardware flow control. For software flow control operation, the XOFF character would be sent once when the number of bytes in the Rx FIFO equals the value in the Receive Buffer High Watermark register. Once the XOFF has been sent, it cannot be sent again until the XON character has been sent. The valid state transitions to sending the XOFF character can be either no previous XON/XOFF character sent or a previous XON character sent. There is also a High Watermark Reached interrupt enable/ disable bit in the Interrupt Enable register and a High Watermark Reached bit in the ISR, (Interrupt Status Register). When the High Watermark is reached, an interrupt request will be generated, when the interrupt enable/disable bit is enabled

Rx Buffer High Watermark

Function: Defines the Receive Buffer Low Watermark value.

Type: binary word

Data Range: 0 < Low Watermark < High Watermark < 0x1FFF9B

Read/Write: R/W

Initialized Value: 2048 decimal (800h) When the Rx Buffer size is less than the Low Watermark value, FIFO Status bit D3 is flagged.

The Watermark registers are used for XON/XOFF and/or RTS/CTS flow control. The Receive Buffer Low Watermark register value controls when the XON character is sent when using software flow control and controls when the RTS signal would be asserted when using hardware flow control. For software flow control operation, the XON character would be sent once when the number of bytes in the Rx FIFO equals the value in the Receive Buffer Low Watermark register AND an XOFF character has been sent prior to this XON character. The valid state transition to sending the XON character can only be from the state of a previous XOFF character that has been sent. There is a Low Watermark Reached interrupt enable/disable bit in the Interrupt Enable register and a Low Watermark Reached bit in the ISR, (Interrupt Status register). When the Low Watermark is reached, an interrupt request will be generated, when the interrupt enable/disable bit is enabled.

Rx Buffer Low Watermark

Function: Mode dependent for HDLC and Synchronous modes. See Operational Settings.

Type: unsigned character word

Data Range: NA

Read/Write: R/W

Initialized Value: A5h

Operational Settings: If using HDLC mode, this value is compared to the address of the received message and if it’s equal, the message is stored in the receive buffer. If using Mono/Bi-Synchronous mode, this value is considered the “Sync Character” and is used for communication synchronization. The receiver searches incoming data for the Sync Character. Once found, communication is synchronized and additional data is valid. When in 16-bit, high byte is sent before low byte. Modes Affected: HDLC and Synchronous.

HDLC Rx Address/Sync Character

Function: Mode dependent for HDLC and Synchronous modes. See Operational Settings.

Type: unsigned character

Data Range: NA

Read/Write: R/W

Initialized Value: A5h

Operational Settings: If using HDLC mode, this value is compared to the address of the received message and if it’s equal, the message is stored in the receive buffer. If using Mono/Bi-Synchronous mode, this value is considered the “Sync Character” and is used for communication synchronization. The receiver searches incoming data for the Sync Character. Once found, communication is synchronized and additional data is valid. When in 16-bit, high byte is sent before low byte. Modes Affected: HDLC and Synchronous.

HDLC Tx Address/Sync Character

Function: Specifies the XON character for in-band flow control in Async mode.

Type: unsigned character (usually a member of the ASCII data set)

Data Range: NA

Read/Write: R/W

Initialized Value: 11h

Modes Affected: Async

Operational Settings: When software flow control is enabled, this value is sent as the XON character.

XON Character

Function: Specifies the XOFF character for in-band flow control in Async mode.

Type: unsigned character (usually a member of the ASCII data set)

Data Range: NA

Read/Write: R/W

Initialized Value: 13h

Modes Affected: Async

Operational Settings: When software flow control is enabled, this value is sent as the XOFF character.

XOFF Character

Function: Contains the termination character used for termination detection.

Type: unsigned character (usually a member of the ASCII data set)

Data Range: NA

Read/Write: R/W

Initialized Value: 3h

Operational Settings: When using the Asynchronous or Bi-Synchronous modes, the receive data stream is monitored for the occurrence of the termination character. When this character is detected, an interrupt is generated, if enabled and not masked. Modes Affected: Async and Sync.

Termination Character

Function: Determines the timeout period.

Type: unsigned integer

Data Range: 0 to 65535

Read/Write: R/W

Initialized Value: 9C40h (1 second)

Operational Settings: If there is no receive line activity for the configured period of time, a timeout is indicated in the Interrupt Status register, bit D10. LSB is 25µs. Modes Affected: Async.

Time Out Value

Function: Checks the corresponding bit for a channel’s BIT Status in real time.

Type: 32-bit unsigned integer

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R

Initialized Value: 0

Operational Settings: 0 = Normal; 1 = Non-functional Serial Loopback. BIT is initiated by the user for serial communications modules

BIT Dynamic Status

Function: Checks the corresponding bit for a channel’s BIT Status. Latches status until reset.

Type: 32-bit unsigned integer

Data Range: 0x 0000 0000 to 0x 0000 00FF

Read/Write: R/W

Initialized Value: 0

Operational Settings: 0 = Normal; 1 = Non-functional Serial Loopback. Write 1 to reset the register. BIT is initiated by the user for serial communications modules

BIT Latched Status

Function: Generates an interrupt when BIT Dynamic Status or BIT Latched Status registers indicate a fault condition. Interrupt #1. Type: 32-bit unsigned integer

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R/W

Initialized Value: 0

Operational Settings: 0 = Disabled; 1 = Enabled.

BIT Interrupt Enable

Function: Selects whether BIT Interrupt Enable will initiate on a rising edge or level.

Type: 32-bit unsigned integer

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R/W

Initialized Value: 0

Operational Settings: 0 = Rising Edge; 1 = Level.

BIT Set Edge/Level Interrupt

Function: Describes current FIFO Status.

Type: binary word

Data Range: NA

Read/Write: R

Initialized Value: NA

Operational Settings: See Rx Almost Full, Tx Almost Empty, Rx High Watermark and Rx Low Watermark specific registers for function description and programming.

FIFO Status

Function: Describes the status of 15 different events.

Type: binary word

Data Range: NA

Read/Write: R/W

Initialized Value: NA

Operational Settings: These events are NOT latched. They are dynamic. Use this register to read current or real-time status. It is recommended to read these events using the Latched Status register as the Dynamic Status register may capture a fleeting event. A purpose for this register is a sanity check to determine if a latched state still exists. See specific registers for function description and programming

Dynamic Status