Function: Sets each channel for either unipolar or bipolar mode.

Type: binary word (16-bit)

Data Range: Unipolar: 0 to 0x0000 FFFF; Bipolar: 0xFFFF 8000 to 0x0000 7FFF

Read/Write: R/W

Initialized Value: 0x0000 0000

Operational Settings: Two’s complement format for bipolar mode. See Data Range values above for unipolar and bipolar modes.

Default: 0x0000 0000

Set D/A Data

Function: Sets input format for polarity and range for each channel.

Type: binary word

Data Range: NA

Read/Write: R/W

Initialized Value: 0x0000000

Operational Settings: Set the range using bits D0, D1, D2 and D3. See table below.

Default: Bipolar

Notes: For bipolar/unipolar selection, program D4 to 0 for unipolar or 1 for bipolar.

Polarity & Range

Function: Filters output to provide a smooth analog waveform for each channel.

Type: binary word

Data Range: NA

Read/Write: R/W

Initialized Value: 0x0000 0000

Operational Settings: 0x00=off (3.3us), 0x10=1500 pF (122us), 0x11=0.015 uF (1.32ms), 0x12=0.15 uF (11.2ms), 0x13=0.47 uF (21ms).

See table below.

Default: 0x0000 0000

Notes: Set D4 to 0 to Disable or 1 to Enable register. Set D1 and D0 (Bandwidth Select) as indicated above.

Capacitor/Bandwidth Select

Function: Used to read the measured output voltage.

Type: binary word (32-bit)

Data Range: 0xFFFF 8000 to 0x0000 7FFF

Read/Write: R

Initialized Value: 0x0000 0000

Operational Settings: Fixed in bipolar mode with no ranges - 0x7FFF= 13 V.

Default: 0x0000 0000

Wrap Voltage

Function: Reads current values of D/A outputs being delivered per channel. (Bipolar mode only.)

Type: binary word (32-bit)

Data Range: For bipolar mode: 0xFFFF 8000 to 0x0000 7FFF

Read/Write: R

Initialized Value: 0

Operational Settings: Fixed in bipolar mode with no ranges - 0x7FFF = 25 mA.

Default: 0x0000 0000

Current Reading

Function: Starts/triggers FIFO when FIFO registers are enabled or writes D/A data that was previously written when the Output Data Trigger register is enabled. FIFO can be started/triggered by different sources.

Data Range: 0x0 to 0xFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: See the tables that follow for settings.

Default: Disabled Trigger

X= Don’t care

Function: Sets up trigger control for D/A outputs for each channel.

Type: binary word (32-bit)

Data Range: 0 to 0x0000 0001

Read/Write: R

Initialized Value: 0

Operational Settings: D/A output voltages can be programmed to change only with a synchronizing trigger, or to constantly update, based on the settings of the register. 0 = Constant Update; 1 = Trigger. When in trigger mode, the trigger control register is used to set up what kind of trigger condition (hardware, software, which edge, etc.). Once that trigger condition is met, the data in the D/A data is updated. If in constant update mode, the D/A data is update immediately upon writing the data.

Default: 0

Output Data Trigger

Function: Software trigger is used to kick start the FIFO buffer and the output of data or the output of the Set D/A Data depending if the FIFO buffer control is enabled or not.

Data Range: 0 to 0x0000 0001

Read/Write: R/W

Initialized Value: 0

Operational Settings: In order to use this operation, the Trigger Control register must be set up as described in the Trigger Control register and the Output Data Trigger register must be enabled. Write a 1 to trigger FIFO output for each channel (bitmapped for each channel).

Default: Not Triggered

Function: Single 32-bit register that sets the desired sample rate for all channels.

Data Range: 0x186A0 to 0x61A80

Read/Write: R/W

Initialized Value: 400 kHz

Operational Settings: Sets sampling rate for all channels. Range is 100 kHz to 400 kHz.

Default: Initialized to 400 kHz sampling rate per channel

DA Sample Rate

Function: Sets each channel for voltage mode or current mode.

Register Offset(s): 0x1280

Data Range: 0 to 0xFFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Set bit to 1 for Current mode and 0 for Voltage mode.

Default: Voltage mode

Function: Enables D0, D2 and D3 BIT testing

Register Offset(s) Ch1-Ch12: 0x0248

Data Range: NA

Read/Write: R/W

Initialized Value: 0

Operational Settings: 0 = Disabled; 1 = Enabled

Default: 0

Function: Data is written to this register and can be retrieved, one word at a time (16-bits), in the Register Offset(s) Ch1-Ch12 addresses listed below. Buffer can be completely emptied when triggered. Data Range: For bipolar mode: 7FFFh = +FS, 8000h = -FS. For unipolar mode, range is from 0h to FFFFh = FS.

Read/Write: R/W

Initialized Value: 0

Operational Settings: The data is presented depending upon how the Set D/A Data register is set, (either unipolar or bipolar). Data is held in FIFO until triggered.

Default: Nothing in FIFO

Function: This is a counter that reports the number of 16-bit words stored in the FIFO buffer.

Type: binary word (32-bit)

Data Range: 0 to 0x001F FFFF

Read/Write: R

Initialized Value: 0

Operational Settings: Every time a FIFO Buffer Data register word is sent out after triggering, its corresponding FIFO Word Count register will be decremented by one. The maximum number of words that can be stored in the FIFO is 1 mega words (2 M pending).

Default: Nothing in FIFO (empty)

Function: Clears FIFO whenever clear memory is set or reset for the individual channel in the Register Offset Ch1-Ch12 addresses listed below.

Data Range: 0x0000 0000 to 0x0000 0001

Read/Write: R/W

Initialized Value: 0

Operational Settings: Any write operation will clear FIFO Buffer Data register.

Default: Not clearing

Function: This register enables the user to set the limits for the “almost empty” status.

Type: binary word (32-bit)

Data Range: 0 to 0x001F FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When the FIFO Word Count register is less than or equal to the value stored in the FIFO Empty Mark register, the “almost empty” bit (B0) of the FIFO Status register will be set. When the Words in FIFO counter is greater than the value stored in the register, the almost empty bit (B1) of the FIFO Status register will be reset. Set = logical 1 Reset = logical 0

Default: Not set

Function: The FIFO Low Mark (low-threshold level) is used to set or reset the low limit bit (B2) of the individual FIFO Status register in the Register Offset Ch1-Ch12 addresses listed below.

Data Range: 0 to 0x001F FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When the FIFO Word Count register is less than or equal than the value stored in the FIFO Low Mark register, the low limit bit (B2) of the FIFO Status register will be set. When the FIFO Word Count counter is greater than or equal to the value stored in the register, the low limit bit (B2) of the FIFO Status register will be reset. Set = logical 1 Reset = logical 0

Default: Not set

Function: The FIFO High Mark (hi-threshold level) is used to set the high limit bit (B3) of the individual channel FIFO Status register in the Register Offset Ch1-Ch12 addresses listed below.

Data Range: 0 to 0x001F FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When the FIFO Word Count register is greater than or equal to the value stored in the FIFO High Mark register, the high limit bit(B3) of the FIFO Status register will be set. When the FIFO Word Count register is less than the value stored in the hi-threshold, the high limit bit (B3) of the FIFO Status register will be reset.

Set = logical 1

Reset = logical 0

Default: Not set

Function: This register enables the user to set the limits for the “almost full” status.

Data Range: 0 to 0x001F FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When the FIFO Word Count register is greater than or equal to the value stored in the FIFO Full register, the almost full bit (B4) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the register, the almost full bit (B4) of the FIFO Status register will be reset. Set = logical 1 Reset = logical 0

Default: Not set

Function: Enables the usage of the FIFO buffer and the FIFO mode.

Data Range: 0 to 0x000 000FF

Read/Write: R/W

Initialized Value: 0

Operational Settings: FIFO Enable (B0) enables using the FIFO registers as the source for output of data to the D/A converters. Enable Repeat Mode (B1) functionality is pending and will be implemented at a later date.

FIFO Buffer Control

Function: Continuously reports the status of the Built In Self Tests.

Read/Write: R

Initialized Value: 0

Operational Settings: 0 = Normal; 1 = Non-compliant D/A conversion (outside 0.2% FS range accuracy spec).

Notes: BIT Status is part of background testing and the status register may be checked or polled at any given time.

BIT Dynamic Status

Function: Latches high when there’s a non-compliant status until cleared.

Read/Write: R/W

Initialized Value: 0

Operational Settings: 0 = Normal; 1 = Non-compliant D/A conversion (outside 0.2% FS range accuracy spec). Write a 1 to this register to clear status.

Notes: BIT Status is part of background testing and the status register may be checked or polled at any given time.

BIT Latched Status

Function: Sets the bit to enable interrupts for the corresponding channel.

Read/Write: R/W

Initialized Value: 0

Operational Settings: When enabled, a non-compliant channel will trigger an interrupt.

Default: 00h to disable all channels

BIT Interrupt Enable

Function: When the BIT Interrupt Enable register is enabled, this register determines whether the interrupt will be generated for either “sense on edge” or “sense on level” event detection.

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge.

Default: Sense on edge (0)

BIT Set Edge/Level Interrupt

Function: Checks the corresponding bit for a channel’s FIFO Status. The FIFO Dynamic Interrupt Status register indicates the current condition of the FIFO buffer. Type: binary word (32-bit)

Data Range: 0 to 0x0000 007F

Read/Write: R

Initialized Value: 0

Operational Settings: D0-D6 is used to show the different conditions of the buffer.

FIFO Dynamic Status

Function: Checks the corresponding bit for a channel’s FIFO Status. The FIFO Latched Interrupt Status register maintains the last condition of the FIFO buffer, until cleared. Type: binary word (32-bit)

Data Range: 0 to 0x0000 007F

Read/Write: R/W

Initialized Value: 0

Operational Settings: D0-D6 is used to show the different conditions of the buffer. Write a 1 to this register to clear status.

FIFO Latched Status

Function: Sets the corresponding channel bit to enable an interrupt for each of the conditions indicated in the FIFO Status register (D0..D6).

Data Range: 0 to 0x7FFF

Read/Write: R/W

Initialized Value: 0 Operational Settings: When enabled, an interrupt will be generated for each of the following conditions. Each channel may be set for a different condition.

FIFO Status Interrupt Enable

Function: When the FIFO Mask Status Interrupt Enable register is enabled, this register determines whether the interrupt will be generated for either “sense on edge” or “sense on level” event detection.

Data Range: 0 to 0x7FFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge.

Default: Sense on edge (0)

FIFO Set Edge/Level Interrupt

Function: Continuously reports the overcurrent status of each channel.

Read/Write: R

Initialized Value: 0

Operational Settings: 0 = Normal; 1 = Overcurrent

Overcurrent Dynamic Status

Function: Latches high when an overcurrent condition occurs until cleared.

Read/Write: R/W

Initialized Value: 0

Operational Settings: 0 = Normal; 1 = Overcurrent. Write a 1 to this register to clear status.

Overcurrent Latched Status

Function: Sets the corresponding channel bit to enable an interrupt for an overcurrent condition as specified in the Current Reading register.

Read/Write: R/W

Initialized Value: 0

Operational Settings: When enabled, a non-compliant channel will trigger an interrupt.

Default: 00h to disable all channels

Overcurrent Interrupt Enable

Function: When the Overcurrent Mask Status Interrupt Enable register is enabled, this register determines whether the interrupt will be generated for either “sense on edge” or “sense on level” event detection.

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge.

Default: Sense on edge (0)

Overcurrent Set Edge/Level Interrupt

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

The User Watchdog Timer (UWDT) Capability is available on the following modules:

The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.

The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:

A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.

The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.

The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.

Figure 1. User Watchdog Timer Overview

Figure 2. User Watchdog Timer Example

Figure 3. User Watchdog Timer Failures

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

Key