16-Channel D/A Output Module
Edit this on GitLab
INTRODUCTION
As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurement and simulation, communications, Ethernet switch, and SBC functions. Our DA2 module provides sixteen independent Digital-to-Analog (D/A) output channels with a full-scale range of ±10 VDC at a maximum of ±10 mA. Linearity/accuracy is ±0.10% FS range over temperature. The DA2 provides a FIFO output buffer, which is programmable for the application. This user manual is designed to help you get the most out of our DA2 smart function module.
DA2 Overview
NAI’s DA2 modules offers several features designed to suit a variety of system requirements, including:
Sixteen (16) Channels of Digital-to-Analog I/O Interface:
The DA2 provides sixteen channels of high-quality 16-bit D/A output offering a full-scale range of ±10 VDC at a maximum of ±10 mA.
Designed to meet IEC 801-2 Level 2 testing requirements:
The DA2 ensures reliable performance and compliance with industry standards by meeting the testing requirements of IEC 801-2 Level 2. This capability guarantees that the module can effectively handle electromagnetic compatibility challenges, highlighting the product’s resilience in various operating environments..
Continuous Built-In Test (BIT):
The module incorporates continuous BIT functionality, providing self-diagnostics and monitoring capabilities to ensure reliable operation and easy troubleshooting.
Automatic Shutdown Protection:
The DA2 module utilizes an automatic shutdown protection feature to enhance operational safety by swiftly responding to potentially harmful conditions. This functionality not only safeguards the module from damage but also provides users with clear and immediate feedback by displaying the results in a status word, ensuring efficient troubleshooting and maintenance processes.
Extended D/A FIFO Buffering Capabilities:
The extended D/A output FIFO buffering capabilities of the DA2 module facilitate efficient signal processing and management, ensuring smooth operation and accurate output generation. By offering a buffering mechanism, the module can handle fluctuations in data flow, reducing the risk of data loss or distortion. This feature is particularly advantageous in applications requiring precise timing or synchronization, enhancing overall system performance and reliability.
PRINCIPLE OF OPERATION
In addition to the functions and features already described, each module includes extensive background BIT/diagnostics that run in the background in normal operation without user intervention. In addition to output signal read-back (wrap) capabilities, overloaded outputs will be detected with automatic channel shutdown protection, with the results displayed in a status word. The modules also include D/A FIFO Buffering for greater control of the output voltage and signal data. The FIFO D/A buffer will accept, store and output the voltage commands, once enabled and triggered, for applications requiring simulation of waveform generation; single or periodic. The output data command word is formatted as a percentage of the full scale (FS) range selection, which allows maximum resolution and accuracy at lower voltage ranges.
Built-In Test (BIT)/Diagnostic Capability
The DA2 module supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are logically OR’d together and stored in the BIT Dynamic Status and BIT Latched Status registers.
Power-On Self-Test (POST)/Power-On BIT (PBIT)/Start-Up BIT (SBIT)
The power-on self-test is performed on each channel automatically when power is applied and report the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.
Continuous Background Built-In Test (CBIT)
The background Built-In-Test or Continuous BIT (CBIT) (“D2”) runs in the background where each channel is checked to a test accuracy of 0.2% FS. The testing is totally transparent to the user, requires no external programming, and has no effect on the operation of the module or card.
The technique used by the continuous background BIT (CBIT) test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. Note, the interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained; i.e. at a ten second interval, not a 10-millisecond interval). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state.
Initiated Built-In Test (IBIT)
The DA2 module support an off-line Initiated Built-in Test (IBIT) (“D3”).
The IBIT test uses an internal A/D that measures all D/A channels while they remain connected to the I/O and cycle through 16 signal levels from -FS to +FS. Each channel will be checked to a test accuracy of 0.2% FS. Test cycle is completed within 45 seconds (depending on update rate) and results can be read from the Status registers when IBIT bit changes from 1 to 0. This test requires no user programming and can be enabled via the bus.
D/A FIFO Buffering
The Digital-to-Analog modules include D/A FIFO Buffering for greater control of the output voltage and signal data. The D/A FIFO buffers will accept, store and output the voltage (and/or current) commands, once enabled and triggered, for applications requiring simulation of waveform generation; single or periodic. The output data command word is formatted as a percentage of the full scale (FS) range selection, which allows maximum resolution and accuracy at lower voltage ranges.
Status and Interrupts
The D/A Module provides registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.
Module Common Registers
The D/A Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.
Engineering Scaling Conversion
The D/A Module Data, Voltage and Current Measurement registers can be programmed to be utilized as single precision floating point values (IEEE-754) or as a 32-bit integer value.
When the Enable Floating Point Mode register is set to 1 (Floating Point Mode) the following registers are formatted as Single Precision Floating Point Value (IEEE-754):
-
Wrap Voltage (Volts)
-
Wrap Current (mA)
-
Internal Voltage (Volts)
-
DAC Value (Voltage (Volts))
-
FIFO Buffer Data
When the Enable Floating Point Mode register is set to 1, it is important that these registers are updated with the Single Precision Floating Point (IEEE-754) representation of the value for proper operation of the channel. Conversely, when the Enable Floating Point Mode register is set to 0, these registers must be updated with the Integer 32-bit representation of the value. Note: When changing the Enable Floating Point Mode from Integer Mode to Floating Point Mode or vice versa, the following step should be followed to avoid faults from falsely being generated because internal registers have an incorrect binary representation of the values:
-
Set the Enable Floating Point Mode register to the desired mode (Integer or Floating Point).
-
Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete. Data registers will be converted to the units specified and can be read in that specified format.
-
Initialize configuration and control registers with the values in the units specified (Integer or Floating Point).
It is very often necessary to relate D/A voltage and current to other engineering units such as PSI (Pounds per Square Inch). When the Enable Floating Point Mode register is set to 1, the values entered for the Floating Point Offset register and the Floating-Point Scale register will be used to convert the D/A data from engineering units to voltage or current values. The purpose of this is to offload the processing that is normally performed by the mission processor to convert the physical quantity to voltage or current values for the DAC Value register and the FIFO Buffer Data register. When enabled, the module will compute the D/A data as follows:
D/A Value as Volts/Current (Floating Point) = (D/A Value in Engineering Units (Floating Point) + Floating Point Offset) * Floating Point Scale
Note:
When Enable Floating Point Mode is set to 1 (Floating Point Mode) the listed registers below are formatted as Single Precision Floating Point Value (IEEE-754) and the values specified in the Floating Point Offset register and the Float Point Scale register are applied:
DAC Value
FIFO Buffer Data – any data left in the FIFO prior to changing the Floating Point Mode will be invalid.
Watchdog Timer Capability
The Digital-to-Analog Modules provide support for Watchdog Timer capability. Refer to “Watchdog Timer Module Manual” for the Principle of Operation description.
REGISTER DESCRIPTIONS
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.
D/A Output Registers
The D/A output is normally in terms of voltage. When the Enable Floating Point Mode is enabled, the register value is formatted as a Single Precision Floating Point Value (IEEE-754). In addition, the D/A output value can be specified in engineering units rather than voltage by setting the Floating Point Scale and Floating Point Offset register values to reflect the conversion algorithm.
DAC Value
Function: Sets the output voltage for the channel.
Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: DAC values are dependent on Voltage Range setting for the channel
Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x0000 FFFF
Bipolar (2’s compliment. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF
Enable Floating Point Mode: 1 (Floating Point Mode)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 0
Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.
D/A Control Registers
The D/A control registers provide the ability to specify the polarity and voltage range, update rate, and the enabling or disabling of the D/A outputs. The D/A channels are monitored to detect overcurrent conditions and will automatically disable the D/A output. In the event of an overcurrent condition, the D/A channel needs to be “reset” by writing to the Overcurrent Reset register.
Voltage Range
Function: Sets voltage polarity and range for each channel. The value written to the DAC Value registers will correlate to the voltage range set in this register. Note, if the Enable Floating Point Mode register is set to 1, the Floating Point Scale register must be set to the reciprocal of Voltage Range for direct voltage output.
Type: unsigned binary word (32-bit)
Data Range: See table below
Read/Write: R/W
Initialized Value: 0 (Unipolar: 0-5 V)
Operational Settings: Write to the register with a value from the table to select the range.
For example, for a ±10V bipolar range write a 0x4 to the register.
Reg Value |
Voltage Range |
0x0 |
Unipolar: 0 – 5 V |
0x1 |
Unipolar: 0 – 10 V |
0x2 |
Bipolar: ± 2.5 V |
0x3 |
Bipolar: ± 5 V |
0x4 |
Bipolar: ± 10 V |
Voltage Range
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D |
D |
Output Enable
Function: Enables the voltage to appear on the output.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R/W
Initialized Value: 0 (Channel outputs are disabled)
Operational Settings: Set bit to 1 to activate the output. Set bit to 0 to disable the output.
Output Enable
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Update Rate
Function: Sets the output rate for the DAC output and FIFO Data Output
Type: unsigned binary word (32bit)
Data Range: 0x0000 09C4 to 0x0000 61A8; 400µs (2.5kHz) to 40µs (25kHz).
Read/Write: R/W
Initialized Value: 0x0000 61A8 (40µs) (25kHz)
Operational Settings: This setting is the output rate for each DAC. One update rate applies to all channels.
Overcurrent Reset
Function: Resets over loaded channels based on the current value read in the Wrap Current register.
Type: unsigned binary word (32-bit)
Data Range: 0 or 1 Read/Write: W Initialized Value: 0
Operational Settings: Set to 1 to reset over loaded channels. Writing a 1 to this register will re-enable over loaded channels.
Overcurrent Reset
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D/A Measurement Registers
The measured voltage and current for the D/A output can be read from the Wrap Voltage, Wrap Current and Internal Voltage registers.
Wrap Voltage
Function: Wrap voltage reading from the channel’s output. Used in conjunction with BIT to verify that the output voltage is within range.
Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode)
Unipolar: 0x0000 0000 to 0x0003 FFFF; Bipolar: 0x0002 0000 – 0x0001 FFFF
Bipolar (2’s compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0001 7FFF
Enable Floating Point Mode: 1 (Floating Point Mode)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: 0
Operational Settings:
Integer Mode: To calculate the LSB subtract the minimum voltage range from the maximum voltage range then divide by 2^16. For example, if the value in the Voltage Range register is range 0-10V then the LSB would have value (10-0)/2^16 = .153 mV. Sign bit = D17 for bipolar ranges.
Floating Point Mode: Convert the IEEE-754 Single Precision 32-bit value to a floating point value. For example, if the register value is 0x4020 0000, this is equivalent to 2.5, which represents 2.5V.
Wrap Voltage (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Wrap Voltage (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Wrap Currrent
Function: Wrap current reading from the channel’s output. Reads current values of D/A outputs being delivered per channel.
Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode)
Bipolar (2’s compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0000 7FFF
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: 0
Operational Settings:
Integer Mode: LSB = 305 nA. Sign bit = D17.
Floating Point Mode: Convert the IEEE-754 Single Precision 32-bit value to a floating point value.
Wrap Current (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Wrap Current (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Internal Voltage
Function: Read the internal voltage value. The interval voltage reading is the voltage before the output switch. If the Output Enable register is configured to be disabled, the Internal Voltage register will contain the voltage reading that would be outputted.
Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 – 0x0003 FFFF
Bipolar (2’s compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0001 7FFF
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: 0
Operational Settings:
Integer Mode: To calculate the LSB subtract the minimum voltage range from the maximum voltage range then divide by 2^16. Sign bit = D17 for bipolar ranges.
Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754) value.
Internal Voltage (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Internal Voltage (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D/A Test Registers
Two different tests, one on-line (CBIT) and one off-line (IBIT), can be selected.
Test Enabled
Function: Sets bit to enable the associated CBIT (“D2”) or IBIT (“D3”). Note, CBIT cannot be disabled.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000C
Read/Write: R/W
Initialized Value: 0x4 (CBIT Test Enabled)
Operational Settings: BIT tests include an on-line CBIT and an off-line IBIT tests. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects failures.
Test Enabled
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
IBIT Test D |
CBIT Test 1 |
0 |
0 |
FIFO Registers
The FIFO registers are configurable for each channel.
Data Mode
Function: Sets the data mode of the channel. The output can be based on either the DAC Value register or the RAM Buffer.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: Write a 0 to set the data source to the DAC Value Register. Write a 1 to set the data source to the FIFO Buffer.
Data Mode
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
FIFO Buffer Data
Function: Data in the form of DAC values are written to this register one word at a time (16 bits) and will be outputted to the channel’s output once triggered. Buffer will be emptied one value at a time when triggered.
Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x0000 FFFF
Bipolar (2’s compliment. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: W
Initialized Value: 0
Operational Settings: Data is held in FIFO until triggered. FIFO size is 1 mega words per channel (each channel has its own buffer).
Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.
FIFO Buffer Data (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
FIFO Buffer Data (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
FIFO Word Count
Function: Reports the number of words stored in the FIFO buffer.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x000F FFFF
Read/Write: R
Initialized Value: 0 (FIFO is empty)
Operational Settings: Each time a value is written to the FIFO buffer this count is incremented by 1. Once the FIFO is triggered, after each value is outputted to the DAC, this count will be decremented by 1. Watermarks and threshold values can be setup to trigger interrupts when this count crosses user defined values. The maximum number of words that can be stored in the FIFO is 1 mega words.
FIFO Thresholds
The FIFO Almost Empty, FIFO Low Watermark, FIFO High Watermark, and FIFO Almost Full sets the threshold limits that are used to set the bits in the FIFO Status register.
FIFO Almost Empty
Function: The FIFO Almost Empty is used to set the limits for the “almost empty” status.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x000F FFFF
Read/Write: R/W
Initialized Value: 0x400 (1024)
Operational Settings: When the FIFO Word Count register is less than or equal to the value stored in the FIFO Almost Empty Value register, the “almost empty” bit (D1) of the FIFO Status register will be set. When the Words in FIFO counter is greater than the value stored in the register, the “almost empty” bit (D1) of the FIFO Status register will be reset.
FIFO Low Watermark
Function: The FIFO Low Watermark (low-threshold level) is used to set the limits for the “low watermark” status.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x000F FFFF
Read/Write: R/W
Initialized Value: 0x2000 (8192)
Operational Settings: When the FIFO Word Count register is less than or equal to the value stored in the FIFO Low Watermark Value register, the “low watermark” bit (D2) of the FIFO Status register will be set. When the FIFO Word Count counter is greater than or equal to the value stored in the register, the “low watermark” bit (D2) of the FIFO Status register will be reset.
FIFO High Watermark
Function: The FIFO High Watermark (high-threshold level) is used to set the limits for the “high watermark” status.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x000F FFFF
Read/Write: R/W
Initialized Value: 0x6000 (24576)
Operational Settings: When the FIFO Word Count register is greater than or equal to the value stored in the FIFO High Watermark Value register, the “high watermark” bit (D3) of the FIFO Status register will be set. When the FIFO Word Count register is less than the value stored in the FIFO High Watermark Value, the “high watermark” bit (D3) of the FIFO Status register will be reset.
FIFO Almost Full
Function: The FIFO Almost Full is used to set the limits for the “almost full” status.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x000F FFFF
Read/Write: R/W
Initialized Value: 0x7C00 (31744)
Operational Settings: When the FIFO Word Count register is greater than or equal to the value stored in the FIFO Almost Full Value register, the “almost full” bit (D4) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the register, the “almost full” bit (D4) of the FIFO Status register will be reset
Clear FIFO
Function: Clears the FIFO buffer. Type: unsigned binary word (32-bit) Data Range: 0 or 1
Read/Write: W
Data Range: 0 or 1
Initialized Value: 0
Operational Settings: Writing a 1 will clear the FIFO buffer and reset the count in the FIFO Word Count register.
Clear FIFO
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Pattern Control
Function: Enable to output all the values written to the FIFO Buffer and then repeat.
Note: Pattern Control for the DA2 supports Loop Mode only.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: To activate FIFO Loop Mode in the Pattern Control Register, set the Data Mode register to 1. Then set the bit for the specific channel in the Pattern Control register to 1. Finally, write a 1 to the Software Trigger register. The FIFO will output all values written to the FIFO Data register and then repeat. To stop looping write a 0 to the Software Trigger register.
Pattern Control (FIFO Loop Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Software Trigger
Function: If the memory buffer is enabled writing the trigger value to this register will start the output. Values stored in the FIFO will be output at the set update rate until the FIFO is empty.
Type: unsigned binary word (32-bit)
Data Range: 0 or 1
Read/Write: R/W
Initialized Value: 0
Operational Settings: To initiate output from the FIFO Buffer, the Data Mode register must be set to FIFO Mode. Then write a 1 to the Software Trigger register to begin outputting data. The 1 will clear once the FIFO empties.
Software Trigger
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Engineering Scaling Conversion Registers
The D/A Module Data, Voltage and Current Measurement registers can be programmed to be utilized as an IEEE 754 single-precision floating- point value or as a 32-bit integer value.
Enable Floating Point Mode
Function: Sets all channels for floating point mode or integer module.
Type: unsigned binary word (32-bit)
Data Range: 0 or 1
Read/Write: R/W
Initialized Value: 0 (Integer mode)
Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode.
Floating Point Offset
Function: Single 32-bit register that sets the floating-point offset to add to D/A output.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: N/A
Read/Write: R/W
Initialized Value: 0.0
Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point examples.
Floating Point Scale
Function: Single 32-bit register that sets the floating-point scale to multiple to the D/A output.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: N/A
Read/Write: R/W
Initialized Value: 0.0
Operational Settings: When changing the Voltage Range, the Floating Point Scale needs to be adjusted in order for the Wrap Voltage and Wrap Current floating point representation to be scaled correctly.
Floating Point State
Function: Indicates whether the module’s internal processing is converting the register values and internal values to the binary representation of the mode selected (Integer or Floating Point).
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: R
Initialized Value: 0
Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).
Floating Point State
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Background BIT Threshold Programming Registers
The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The Reset BIT register provides the ability to reset the BIT counter used in CBIT.
Background BIT Threshold
Type: unsigned binary word (32-bit) Data Range: 1 ms to 2^32 ms Read/Write: R/W
Initialized Value: 5 (5 ms)
Operational Settings: The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module.
Reset BIT
Function: Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: W
Initialized Value: 0
Operational Settings: Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.
Reset BIT
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Watchdog Timer Registers
Refer to “Watchdog Timer Module Manual” for the Watchdog Timer Register Descriptions.
Module Common Registers
Refer to “Module Common Registers Module Manual” for the register descriptions.
Status and Interrupt Registers
The DA2 Module provides status registers for BIT, Overcurrent, External Power Under Voltage, Inter-FPGA Failure, and FIFO.
Channel Status Enabled
Function: Determines whether to update the status for the channels. This feature can be used to “mask” status bits of unused channels in status registers that are bitmapped by channel.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF (Channel Status)
Read/Write: R/W
Initialized Value: 0x0000 FFFF
Operational Settings: When the bit corresponding to a given channel in the Channel Status Enabled register is not enabled (0) the status will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status, Overcurrent Status and Summary Status). Note, Background BIT will continue to run even if the Channel Status Enabled is set to ‘0'.
Channel Status Enabled
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
BIT Status
There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The BIT Status register will indicate an error when the D/A conversion is outside 0.2% FS accuracy spec.
BIT Dynamic Status
BIT Latched Status
BIT Interrupt Enable
BIT Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Function: Reports the corresponding bit associated with the channel’s BIT error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Notes: BIT Status is part of background testing and the status register may be checked or polled at any given time.
Overcurrent Status
There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Overcurrent Dynamic Status
Overcurrent Latched Status
Overcurrent Interrupt Enable
Overcurrent Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Function: Reports the corresponding bit associated with the channel’s Overcurrent error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
External Power Under Voltage Status
There are four registers associated with the External Power Under Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
D0 = +12V External Power Under Voltage
D1 = -12V External Power Under Voltage
External Power Under Voltage Dynamic Status
External Power Under Voltage Latched Status
External Power Under Voltage Interrupt Enable
External Power Under Voltage Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
-12V |
+12V |
Function: Reports the corresponding bit associated with the channel’s External Power Under Voltage error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 0003
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Inter-FPGA Failure Status/Watchdog Timer Fault
Data is periodically transferred between the processing module and functional module within the FPGA. A CRC value is calculated and verified with each data transfer. In order to recover from an Inter-FPGA Failure, the module needs to be reset and re-initialized.
There are four registers associated with the Inter-FPGA Status/Watchdog Timer Fault: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
The lower 16-bits represent the Inter-FPGA Failure Status: 0 = Normal; 0xFFFF = Inter-FPGA Communication Failure. The status represents the status for all channels on the module. Bit 31 represents the Watchdog Timer Fault: 0 = Normal; 1 = Watchdog Timer Fault.
Inter-FPGA Failure/Watchdog Timer Fault Dynamic Status
Inter-FPGA Failure/Watchdog Timer Fault Latched Status
Inter-FPGA Failure/Watchdog Timer Fault Interrupt Enable
Inter-FPGA Failure/Watchdog Timer Fault Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Function: Sets the corresponding bit associated with the channel’s Inter-FPGA Failure and Watchdog Timer Fault error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x8000 FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Summary Status
There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Summary Status Dynamic Status
Summary Status Latched Status
Summary Status Interrupt Enable
Summary Status Set Edge/Level Interrupt
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit when a fault is detected for BIT, Overcurrent, External Power Under Voltage or Inter-FPGA Failure on that channel.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
FIFO Status
There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0-D5 is used to show the different conditions of the buffer.
Bit |
Description |
Configurable? |
D0 |
Empty; 1 when FIFO Word Count = 0 |
No |
D1 |
Almost Empty; 1 when FIFO Word Count ⇐ “FIFO Almost Empty” register |
Yes |
D2 |
Low Watermark; 1 when FIFO Word Count ⇐ “FIFO Low Watermark” register |
Yes |
D3 |
High Watermark; 1 when FIFO Word Count >= “FIFO High Watermark” register |
Yes |
D4 |
Almost Full; 1 when FIFO Word Count >= “FIFO Almost Full” register |
Yes |
D5 |
Full; 1 when FIFO Word Count = 1 Mega Words (0x000F FFFF) |
No |
FIFO Dynamic Status
FIFO Latched Status
FIFO Interrupt Enable
FIFO Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D |
D |
D |
D |
D |
Function: Sets the corresponding bit associated with the FIFO status type; there are separate registers for each channel.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 003F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 1 (Empty)
Notes: Shown below is an example of interrupts generated for the High Watermark. As shown, the interrupt is generated as the FIFO Word Count crosses the High Watermark. The interrupt will not be generated a second time until the count goes below the watermark and then above it again.
Interrupt Steering and Vector
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note: the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
Interrupt Vector
Function: Set an identifier for the interrupt.
Type: unsigned binary word (32-bit) Data Range: 0 to 0xFFFF FFFF Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function: Sets where to direct the interrupt.
Type: unsigned binary word (32-bit) Data Range: See table Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME |
1 |
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) |
2 |
Direct Interrupt to PCIe Bus |
5 |
Direct Interrupt to cPCI Bus |
6 |
0x07F8 |
Module Sensor Summary Status |
FUNCTION REGISTER MAP
Key: Bold Italic = Configuration/Control
Bold Underline = Measurement/Status
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a ‘1' to a bit set to ‘1' will set the bit to ‘0').
-
Data is available in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode. ~ Data is always in Floating Point.
D/A Output Registers
The D/A output is normally in terms of voltage. When the Enable Floating Point Mode is enabled, the register value is formatted as a Single Precision Floating Point Value (IEEE-754). In addition, the D/A output value can be specified in engineering units rather than voltage by setting the Floating Point Scale and Floating Point Offset register values to reflect the conversion algorithm.
DAC Value
Function: Sets the output voltage for the channel.
Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: DAC values are dependent on Voltage Range setting for the channel
Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x0000 FFFF
Bipolar (2’s compliment. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF
Enable Floating Point Mode: 1 (Floating Point Mode)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 0
Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.
D/A Control Registers
The D/A control registers provide the ability to specify the polarity and voltage range, update rate, and the enabling or disabling of the D/A outputs. The D/A channels are monitored to detect overcurrent conditions and will automatically disable the D/A output. In the event of an overcurrent condition, the D/A channel needs to be “reset” by writing to the Overcurrent Reset register.
Voltage Range
Function: Sets voltage polarity and range for each channel. The value written to the DAC Value registers will correlate to the voltage range set in this register. Note, if the Enable Floating Point Mode register is set to 1, the Floating Point Scale register must be set to the reciprocal of Voltage Range for direct voltage output.
Type: unsigned binary word (32-bit)
Data Range: See table below
Read/Write: R/W
Initialized Value: 0 (Unipolar: 0-5 V)
Operational Settings: Write to the register with a value from the table to select the range.
For example, for a ±10V bipolar range write a 0x4 to the register.
Reg Value |
Voltage Range |
0x0 |
Unipolar: 0 – 5 V |
0x1 |
Unipolar: 0 – 10 V |
0x2 |
Bipolar: ± 2.5 V |
0x3 |
Bipolar: ± 5 V |
0x4 |
Bipolar: ± 10 V |
Voltage Range
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D |
D |
Output Enable
Function: Enables the voltage to appear on the output.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R/W
Initialized Value: 0 (Channel outputs are disabled)
Operational Settings: Set bit to 1 to activate the output. Set bit to 0 to disable the output.
Output Enable
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Update Rate
Function: Sets the output rate for the DAC output and FIFO Data Output
Type: unsigned binary word (32bit)
Data Range: 0x0000 09C4 to 0x0000 61A8; 400µs (2.5kHz) to 40µs (25kHz).
Read/Write: R/W
Initialized Value: 0x0000 61A8 (40µs) (25kHz)
Operational Settings: This setting is the output rate for each DAC. One update rate applies to all channels.
Overcurrent Reset
Function: Resets over loaded channels based on the current value read in the Wrap Current register.
Type: unsigned binary word (32-bit)
Data Range: 0 or 1 Read/Write: W Initialized Value: 0
Operational Settings: Set to 1 to reset over loaded channels. Writing a 1 to this register will re-enable over loaded channels.
Overcurrent Reset
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D/A Measurement Registers
The measured voltage and current for the D/A output can be read from the Wrap Voltage, Wrap Current and Internal Voltage registers.
Wrap Voltage
Function: Wrap voltage reading from the channel’s output. Used in conjunction with BIT to verify that the output voltage is within range.
Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode)
Unipolar: 0x0000 0000 to 0x0003 FFFF; Bipolar: 0x0002 0000 – 0x0001 FFFF
Bipolar (2’s compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0001 7FFF
Enable Floating Point Mode: 1 (Floating Point Mode)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: 0
Operational Settings:
Integer Mode: To calculate the LSB subtract the minimum voltage range from the maximum voltage range then divide by 2^16. For example, if the value in the Voltage Range register is range 0-10V then the LSB would have value (10-0)/2^16 = .153 mV. Sign bit = D17 for bipolar ranges.
Floating Point Mode: Convert the IEEE-754 Single Precision 32-bit value to a floating point value. For example, if the register value is 0x4020 0000, this is equivalent to 2.5, which represents 2.5V.
Wrap Voltage (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Wrap Voltage (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Wrap Currrent
Function: Wrap current reading from the channel’s output. Reads current values of D/A outputs being delivered per channel.
Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode)
Bipolar (2’s compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0000 7FFF
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: 0
Operational Settings:
Integer Mode: LSB = 305 nA. Sign bit = D17.
Floating Point Mode: Convert the IEEE-754 Single Precision 32-bit value to a floating point value.
Wrap Current (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Wrap Current (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Internal Voltage
Function: Read the internal voltage value. The interval voltage reading is the voltage before the output switch. If the Output Enable register is configured to be disabled, the Internal Voltage register will contain the voltage reading that would be outputted.
Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 – 0x0003 FFFF
Bipolar (2’s compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0001 7FFF
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: 0
Operational Settings:
Integer Mode: To calculate the LSB subtract the minimum voltage range from the maximum voltage range then divide by 2^16. Sign bit = D17 for bipolar ranges.
Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754) value.
Internal Voltage (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Internal Voltage (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D/A Test Registers
Two different tests, one on-line (CBIT) and one off-line (IBIT), can be selected.
Test Enabled
Function: Sets bit to enable the associated CBIT (“D2”) or IBIT (“D3”). Note, CBIT cannot be disabled.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000C
Read/Write: R/W
Initialized Value: 0x4 (CBIT Test Enabled)
Operational Settings: BIT tests include an on-line CBIT and an off-line IBIT tests. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects failures.
Test Enabled
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
IBIT Test D |
CBIT Test 1 |
0 |
0 |
FIFO Registers
The FIFO registers are configurable for each channel.
Data Mode
Function: Sets the data mode of the channel. The output can be based on either the DAC Value register or the RAM Buffer.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: Write a 0 to set the data source to the DAC Value Register. Write a 1 to set the data source to the FIFO Buffer.
Data Mode
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
FIFO Buffer Data
Function: Data in the form of DAC values are written to this register one word at a time (16 bits) and will be outputted to the channel’s output once triggered. Buffer will be emptied one value at a time when triggered.
Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x0000 FFFF
Bipolar (2’s compliment. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: W
Initialized Value: 0
Operational Settings: Data is held in FIFO until triggered. FIFO size is 1 mega words per channel (each channel has its own buffer).
Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.
FIFO Buffer Data (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
FIFO Buffer Data (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
FIFO Word Count
Function: Reports the number of words stored in the FIFO buffer.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x000F FFFF
Read/Write: R
Initialized Value: 0 (FIFO is empty)
Operational Settings: Each time a value is written to the FIFO buffer this count is incremented by 1. Once the FIFO is triggered, after each value is outputted to the DAC, this count will be decremented by 1. Watermarks and threshold values can be setup to trigger interrupts when this count crosses user defined values. The maximum number of words that can be stored in the FIFO is 1 mega words.
FIFO Thresholds
The FIFO Almost Empty, FIFO Low Watermark, FIFO High Watermark, and FIFO Almost Full sets the threshold limits that are used to set the bits in the FIFO Status register.
FIFO Almost Empty
Function: The FIFO Almost Empty is used to set the limits for the “almost empty” status.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x000F FFFF
Read/Write: R/W
Initialized Value: 0x400 (1024)
Operational Settings: When the FIFO Word Count register is less than or equal to the value stored in the FIFO Almost Empty Value register, the “almost empty” bit (D1) of the FIFO Status register will be set. When the Words in FIFO counter is greater than the value stored in the register, the “almost empty” bit (D1) of the FIFO Status register will be reset.
FIFO Low Watermark
Function: The FIFO Low Watermark (low-threshold level) is used to set the limits for the “low watermark” status.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x000F FFFF
Read/Write: R/W
Initialized Value: 0x2000 (8192)
Operational Settings: When the FIFO Word Count register is less than or equal to the value stored in the FIFO Low Watermark Value register, the “low watermark” bit (D2) of the FIFO Status register will be set. When the FIFO Word Count counter is greater than or equal to the value stored in the register, the “low watermark” bit (D2) of the FIFO Status register will be reset.
FIFO High Watermark
Function: The FIFO High Watermark (high-threshold level) is used to set the limits for the “high watermark” status.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x000F FFFF
Read/Write: R/W
Initialized Value: 0x6000 (24576)
Operational Settings: When the FIFO Word Count register is greater than or equal to the value stored in the FIFO High Watermark Value register, the “high watermark” bit (D3) of the FIFO Status register will be set. When the FIFO Word Count register is less than the value stored in the FIFO High Watermark Value, the “high watermark” bit (D3) of the FIFO Status register will be reset.
FIFO Almost Full
Function: The FIFO Almost Full is used to set the limits for the “almost full” status.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x000F FFFF
Read/Write: R/W
Initialized Value: 0x7C00 (31744)
Operational Settings: When the FIFO Word Count register is greater than or equal to the value stored in the FIFO Almost Full Value register, the “almost full” bit (D4) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the register, the “almost full” bit (D4) of the FIFO Status register will be reset
Clear FIFO
Function: Clears the FIFO buffer. Type: unsigned binary word (32-bit) Data Range: 0 or 1
Read/Write: W
Data Range: 0 or 1
Initialized Value: 0
Operational Settings: Writing a 1 will clear the FIFO buffer and reset the count in the FIFO Word Count register.
Clear FIFO
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Pattern Control
Function: Enable to output all the values written to the FIFO Buffer and then repeat.
Note: Pattern Control for the DA2 supports Loop Mode only.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: To activate FIFO Loop Mode in the Pattern Control Register, set the Data Mode register to 1. Then set the bit for the specific channel in the Pattern Control register to 1. Finally, write a 1 to the Software Trigger register. The FIFO will output all values written to the FIFO Data register and then repeat. To stop looping write a 0 to the Software Trigger register.
Pattern Control (FIFO Loop Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Software Trigger
Function: If the memory buffer is enabled writing the trigger value to this register will start the output. Values stored in the FIFO will be output at the set update rate until the FIFO is empty.
Type: unsigned binary word (32-bit)
Data Range: 0 or 1
Read/Write: R/W
Initialized Value: 0
Operational Settings: To initiate output from the FIFO Buffer, the Data Mode register must be set to FIFO Mode. Then write a 1 to the Software Trigger register to begin outputting data. The 1 will clear once the FIFO empties.
Software Trigger
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Engineering Scaling Conversion Registers
The D/A Module Data, Voltage and Current Measurement registers can be programmed to be utilized as an IEEE 754 single-precision floating- point value or as a 32-bit integer value.
Enable Floating Point Mode
Function: Sets all channels for floating point mode or integer module.
Type: unsigned binary word (32-bit)
Data Range: 0 or 1
Read/Write: R/W
Initialized Value: 0 (Integer mode)
Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode.
Floating Point Offset
Function: Single 32-bit register that sets the floating-point offset to add to D/A output.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: N/A
Read/Write: R/W
Initialized Value: 0.0
Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point examples.
Floating Point Scale
Function: Single 32-bit register that sets the floating-point scale to multiple to the D/A output.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: N/A
Read/Write: R/W
Initialized Value: 0.0
Operational Settings: When changing the Voltage Range, the Floating Point Scale needs to be adjusted in order for the Wrap Voltage and Wrap Current floating point representation to be scaled correctly.
Floating Point State
Function: Indicates whether the module’s internal processing is converting the register values and internal values to the binary representation of the mode selected (Integer or Floating Point).
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: R
Initialized Value: 0
Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).
Floating Point State
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Background BIT Threshold Programming Registers
The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The Reset BIT register provides the ability to reset the BIT counter used in CBIT.
Background BIT Threshold
Type: unsigned binary word (32-bit) Data Range: 1 ms to 2^32 ms Read/Write: R/W
Initialized Value: 5 (5 ms)
Operational Settings: The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module.
Reset BIT
Function: Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: W
Initialized Value: 0
Operational Settings: Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.
Reset BIT
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Watchdog Timer Registers
Refer to “Watchdog Timer Module Manual” for the Watchdog Timer Register Descriptions.
Module Common Registers
Refer to “Module Common Registers Module Manual” for the register descriptions.
Status and Interrupt Registers
The DA2 Module provides status registers for BIT, Overcurrent, External Power Under Voltage, Inter-FPGA Failure, and FIFO.
Channel Status Enabled
Function: Determines whether to update the status for the channels. This feature can be used to “mask” status bits of unused channels in status registers that are bitmapped by channel.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF (Channel Status)
Read/Write: R/W
Initialized Value: 0x0000 FFFF
Operational Settings: When the bit corresponding to a given channel in the Channel Status Enabled register is not enabled (0) the status will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status, Overcurrent Status and Summary Status). Note, Background BIT will continue to run even if the Channel Status Enabled is set to ‘0'.
Channel Status Enabled
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
BIT Status
There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The BIT Status register will indicate an error when the D/A conversion is outside 0.2% FS accuracy spec.
BIT Dynamic Status
BIT Latched Status
BIT Interrupt Enable
BIT Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Function: Reports the corresponding bit associated with the channel’s BIT error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Notes: BIT Status is part of background testing and the status register may be checked or polled at any given time.
Overcurrent Status
There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Overcurrent Dynamic Status
Overcurrent Latched Status
Overcurrent Interrupt Enable
Overcurrent Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Function: Reports the corresponding bit associated with the channel’s Overcurrent error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
External Power Under Voltage Status
There are four registers associated with the External Power Under Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
D0 = +12V External Power Under Voltage
D1 = -12V External Power Under Voltage
External Power Under Voltage Dynamic Status
External Power Under Voltage Latched Status
External Power Under Voltage Interrupt Enable
External Power Under Voltage Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
-12V |
+12V |
Function: Reports the corresponding bit associated with the channel’s External Power Under Voltage error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 0003
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Inter-FPGA Failure Status/Watchdog Timer Fault
Data is periodically transferred between the processing module and functional module within the FPGA. A CRC value is calculated and verified with each data transfer. In order to recover from an Inter-FPGA Failure, the module needs to be reset and re-initialized.
There are four registers associated with the Inter-FPGA Status/Watchdog Timer Fault: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
The lower 16-bits represent the Inter-FPGA Failure Status: 0 = Normal; 0xFFFF = Inter-FPGA Communication Failure. The status represents the status for all channels on the module. Bit 31 represents the Watchdog Timer Fault: 0 = Normal; 1 = Watchdog Timer Fault.
Inter-FPGA Failure/Watchdog Timer Fault Dynamic Status
Inter-FPGA Failure/Watchdog Timer Fault Latched Status
Inter-FPGA Failure/Watchdog Timer Fault Interrupt Enable
Inter-FPGA Failure/Watchdog Timer Fault Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Function: Sets the corresponding bit associated with the channel’s Inter-FPGA Failure and Watchdog Timer Fault error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x8000 FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Summary Status
There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Summary Status Dynamic Status
Summary Status Latched Status
Summary Status Interrupt Enable
Summary Status Set Edge/Level Interrupt
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
CH4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit when a fault is detected for BIT, Overcurrent, External Power Under Voltage or Inter-FPGA Failure on that channel.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
FIFO Status
There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0-D5 is used to show the different conditions of the buffer.
Bit |
Description |
Configurable? |
D0 |
Empty; 1 when FIFO Word Count = 0 |
No |
D1 |
Almost Empty; 1 when FIFO Word Count ⇐ “FIFO Almost Empty” register |
Yes |
D2 |
Low Watermark; 1 when FIFO Word Count ⇐ “FIFO Low Watermark” register |
Yes |
D3 |
High Watermark; 1 when FIFO Word Count >= “FIFO High Watermark” register |
Yes |
D4 |
Almost Full; 1 when FIFO Word Count >= “FIFO Almost Full” register |
Yes |
D5 |
Full; 1 when FIFO Word Count = 1 Mega Words (0x000F FFFF) |
No |
FIFO Dynamic Status
FIFO Latched Status
FIFO Interrupt Enable
FIFO Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D |
D |
D |
D |
D |
Function: Sets the corresponding bit associated with the FIFO status type; there are separate registers for each channel.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 003F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 1 (Empty)
Notes: Shown below is an example of interrupts generated for the High Watermark. As shown, the interrupt is generated as the FIFO Word Count crosses the High Watermark. The interrupt will not be generated a second time until the count goes below the watermark and then above it again.
Interrupt Steering and Vector
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note: the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
Interrupt Vector
Function: Set an identifier for the interrupt.
Type: unsigned binary word (32-bit) Data Range: 0 to 0xFFFF FFFF Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function: Sets where to direct the interrupt.
Type: unsigned binary word (32-bit) Data Range: See table Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME |
1 |
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) |
2 |
Direct Interrupt to PCIe Bus |
5 |
Direct Interrupt to cPCI Bus |
6 |
0x07F8 |
Module Sensor Summary Status |
APPENDIX A: INTEGER/FLOATING POING MODE PROGRAMMING
Integer Mode Programming
The following registers should be configured as follows:
Register |
Value |
Description |
Voltage Range |
0x4 |
±10 volts |
Enable Floating Point |
0 |
Disable for Floating Point Mode |
Note: LSB for Bipolar ±10-volt range:
LSB = 10/0x00007FFF
10/32767=305uV
DAC Value (Integer) |
DAC Voltage Output |
1.000 of FS = 0x0000 7FFF |
32767 * LSB = 10.0 volts |
0.5 of FS = 0x0000 4000 |
16384 * LSB = 5.0 volts |
0.0 of FS = 0x0000 0000 |
0 * LSB = 0.0 volts |
-0.5 of FS = 0xFFFF C000 |
-16384 * LSB = -5.0 volts |
-1.0 of FS = 0xFFFF 8000 |
-32768 * LSB = -10. volts |
Floating Point Mode Voltage Programming
The following registers should be configured as follows:
Register |
Value |
Description |
Voltage Range |
0x4 |
±10 volts |
Enable Floating Point |
1 |
Enable for Floating Point Mode |
Floating Point Scale |
0.1 |
Scale = 1 / (Full Range) = 1 / 10.0 = 0.1 |
Floating Point Offset |
0.0 |
No Offset |
Note: LSB for Bipolar ±10-volt range:
LSB = 10/0x00007FFF
10/32767=305uV
DAC Value (volts) (Floating Point) |
DAC Value (Calculated by Module) |
DAC Value (Integer) |
DAC Voltage Output |
10.0 |
(10.0 + 0.0) *0.1 = 1 (FS) |
FS = 0x0000 7FFF |
32767 * LSB = 10.0 volts |
5.0 |
(5.0 + 0.0) *0.1 = 0.5 of FS |
0.5 of FS = 0x0000 4000 |
16384 * LSB = 5.0 volts |
0.0 |
(0.0 + 0.0) *0.1 = 0.0 of FS |
0.0 of FS = 0x0000 0000 |
0 * LSB = 0.0 volts |
-5.0 |
(-5.0 + 0.0) *0.1 = -0.5 of FS |
-0.5 of FS = 0xFFFF C000 |
-16384 * LSB = -5.0 volts |
-10.0 |
(-10.0 + 0.0) *0.1 = -1 (-FS) |
-FS = 0xFFFF 8000 |
-32768 * LSB = -10. volts |
Floating Point Mode Engineering Units Programming
Example #1:
An application wants to associate -10 to 10 volts to -5 to 5 inches.
The following registers should be configured as follows
Register |
Value |
Description |
Voltage Range |
0x4 |
±10 volts |
Enable Floating Point |
1 |
Enable for Floating Point Mode |
Floating Point Scale |
0.2 |
Scale = 1 / inches range = 1 / 5 = 0.2 |
Floating Point Offset |
0.0 |
No Offset |
Note: LSB for Bipolar ±10-volt range:
LSB = 10/0x00007FFF
10/32767=305uV
DAC Value (in) (Floating Point) |
DAC Value (Calculated by Module) |
DAC Value (Integer) |
DAC Voltage Output |
5.0 |
(5.0 + 0.0) * 0.2 = 1 (FS) |
FS = 0x0000 7FFF |
32767 * LSB = 10.0 volts |
2.5 |
(2.5 + 0.0) * 0.2 = .5 of FS |
0.5 of FS = 0x0000 4000 |
16384 * LSB = 5.0 volts |
0.0 |
(0.0 + 0.0) * 0.2 = 0 |
0.0 of FS = 0x0000 0000 |
0 * LSB = 0.0 volts |
-2.5 |
(-2.5 + 0.0) * 0.2 = -.5 of FS |
-0.5 of FS = 0xFFFF C000 |
-16384 * LSB = -5.0 volts |
-5.0 |
(-5.0 + 0.0) * 0.2 = -1 (-FS) |
-FS = 0xFFFF 8000 |
-32768 * LSB = -10. volts |
Example #2:
An application wants to associate 0 to 10 volts to 0 to 50 feet with a bias of 0.5 feet (in other words 0.5 feet is equivalent to 0 volts).
The following registers should be configured as follows:
Register |
Value |
Description |
Voltage Range |
0x1 |
Unipolar 0-10 volts |
Enable Floating Point |
1 |
Enable for Floating Point Mode |
Floating Point Scale |
0.02 |
Scale = 1 / feet range = 1 / 50 = 0.02 |
Floating Point Offset |
-0.50 |
Bias (0.5 feet) that is equivalent to 0 volts |
The following are sample outputs:
Note: LSB for Unipolar 10-volt range:
LSB = 10/0x0000FFFF
10/65535
DAC Value (ft) (Floating Point) |
DAC Value (Calculated by Module) |
DAC Value (Integer) |
DAC Voltage Output |
50.00 |
(50.0 - 0.50) * 0.02 = 0.99 of FS |
0.99 of FS = 0x0000 FD70 |
64880 * LSB = 9.90 volts |
25.00 |
(25.00 - 0.50) * 0.02 = 0.49 of FS |
0.49 of FS = 0x0000 7D70 |
32112 * LSB = 4.90 volts |
5.50 |
(5.50 - 0.50) * 0.02 = 0.10 of FS |
0.10 of FS = 0x0000 199A |
6554 * LSB = 1.00 volts |
0.50 |
(0.50 - 0.50) * 0.02 = 0.00 of FS |
0.00 of FS = 0x0000 0000 |
0 * LSB = 0.0 volts |
APPENDIX B: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
This section provides a mapping of the register names used in this document against register names used in previous releases.
Rev B - Register Names |
Rev A - Register Names |
D/A Output Registers |
|
DAC Value |
DAC Value |
D/A Control Registers |
|
Voltage Range |
Voltage Range |
Output Enable |
Enable Output |
Update Rate |
Update Rate |
Overcurrent Reset |
Overcurrent Reset |
D/A Measurement Registers |
|
Wrap Voltage |
Wrap Voltage |
Wrap Current |
Wrap Current |
Internal Voltage |
Internal Voltage |
D/A Test Registers |
|
Test Enabled |
Test Enable |
FIFO Registers |
|
Data Mode |
Use FIFO |
FIFO Buffer Data |
FIFO Buffer Data |
FIFO Word Count |
FIFO Word Count |
FIFO Almost Empty |
FIFO Empty Mark |
FIFO Low Watermark |
FIFO Low Mark |
FIFO High Watermark |
FIFO High Mark |
FIFO Almost Full |
FIFO Full Mark |
Clear FIFO |
FIFO Reset |
Pattern Control |
FIFO Loop Mode |
Software Trigger |
Software Trigger |
Engineering Scaling Conversion Registers |
|
Enable Floating Point Mode |
Floating Point Offset |
Floating Point Scale |
Floating Point State |
Background BIT Threshold Programming Registers |
|
Background BIT Threshold |
Reset BIT |
Status and Interrupt Registers |
|
Channel Status Enabled |
BIT Dynamic Status |
BIT Dynamic Status |
BIT Latched Status |
BIT Latched Status |
BIT Interrupt Enable |
Rev B - Register Names |
Rev A - Register Names |
Status and Interrupt Registers (continued) |
|
BIT Set Edge/Level Interrupt |
BIT Set Edge/Level Interrupt |
Overcurrent Dynamic Status |
Overcurrent Dynamic Status |
Overcurrent Latched Status |
Overcurrent Latched Status |
Overcurrent Interrupt Enable |
Overcurrent Interrupt Enable |
Overcurrent Set Edge/Level Interrupt |
Overcurrent Set Edge/Level Interrupt |
External Power Under Voltage Dynamic Status |
External Power Loss Dynamic Status |
External Power Under Voltage Latched Status |
External Power Loss Latched Status |
External Power Under Voltage Interrupt Enable |
External Power Loss Interrupt Enable |
External Power Under Voltage Set Edge/Level Interrupt |
External Power Loss Set Edge/Level Interrupt |
Inter-FPGA Failure Dynamic Status |
Inter-FPGA Failure Latched Status |
Inter-FPGA Failure Interrupt Enable |
Inter-FPGA Failure Set Edge/Level Interrupt |
Summary Dynamic Status |
Summary Latched Status |
Summary Interrupt Enable |
Summary Set Edge/Level Interrupt |
FIFO Dynamic Status |
FIFO Dynamic Status |
FIFO Latched Status |
FIFO Latched Status |
FIFO Interrupt Enable |
FIFO Interrupt Enable |
FIFO Set Edge/Level Interrupt |
FIFO Set Edge/Level Interrupt |
Interrupt Vector |
Interrupt Steering |
APPENDIX C: PIN-OUT DETAILS
Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals.
Module Signal (Ref Only) |
D/A (16 CH) (DA2) |
DATIO1 |
OUT_CH01 |
DATIO2 |
OUT_CH02 |
DATIO3 |
OUT_CH03 |
DATIO4 |
OUT_CH04 |
DATIO5 |
GND-DA |
DATIO6 |
GND-DA |
DATIO7 |
OUT_CH05 |
DATIO8 |
OUT_CH06 |
DATIO9 |
OUT_CH07 |
DATIO10 |
OUT_CH08 |
DATIO11 |
GND-DA |
DATIO12 |
GND-DA |
DATIO13 |
OUT_CH09 |
DATIO14 |
OUT_CH10 |
DATIO15 |
OUT_CH11 |
DATIO16 |
OUT_CH12 |
DATIO17 |
GND-DA |
DATIO18 |
GND-DA |
DATIO19 |
OUT_CH13 |
DATIO20 |
OUT_CH14 |
DATIO21 |
OUT_CH15 |
DATIO22 |
OUT_CH16 |
DATIO23 |
GND-DA |
DATIO24 |
GND-DA |
DATIO25 |
|
DATIO26 |
|
DATIO27 |
|
DATIO28 |
|
DATIO29 |
EXT-SYNC+ |
DATIO30 |
EXT-SYNC- |
DATIO31 |
|
DATIO32 |
|
DATIO33 |
|
DATIO34 |
|
DATIO35 |
|
DATIO36 |
|
DATIO37 |
|
DATIO38 |
|
DATIO39 |
|
DATIO40 |
|
N/A |
FIRMWARE REVISION NOTES
This section identifies the firmware revision in which specific features were released. Prior revisions of the firmware would not support the features listed.
Feature |
FPGA |
Bare Metal (BM) |
||
Firmware Revision |
Release Date |
Firmware Revision |
Release Date |
|
Power-On Self-Test (POST) / Power-on BIT (PBIT) / Start-up BIT(SBIT) |
2.6 and later |
10/08/2019 |
3.4 and later |
01/07/2020 |
Engineering Scaling Conversions |
2.6 and later |
10/08/2019 |
3.4 and later |
01/07/2020 |
Background BIT Threshold Programming |
2.6 and later |
10/08/2019 |
3.4 and later |
01/07/2020 |
Watchdog Timer Capability |
2.6 and later |
10/08/2019 |
3.4 and later |
01/07/2020 |
Channel Status Enabled and Summary Status |
2.6 and later |
10/08/2019 |
3.4 and later |
01/07/2020 |
STATUS AND INTERRUPTS
Edit this on GitLab
Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.
For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.
Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.
Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).
Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.
Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).
-
Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edgetriggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
-
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Interrupt Trigger Types
In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.
Example 1: Fault detection
This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.
Example 2: Threshold detection
This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.
Dynamic and Latched Status Registers Examples
The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.
Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States
No Clearing of Latched Status |
Clearing of Latched Status (Edge-Triggered) |
Clearing of Latched Status (Level-Triggered) |
||||
Time |
Dynamic Status |
Latched Status |
Action |
Latched Status |
Action |
Latched |
T0 |
0x0 |
0x0 |
Read Latched Register |
0x0 |
Read Latched Register |
0x0 |
T1 |
0x1 |
0x1 |
Read Latched Register |
0x1 |
0x1 |
|
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
|||||
0x0 |
0x1 |
|||||
T2 |
0x0 |
0x1 |
Read Latched Register |
0x0 |
Read Latched Register |
0x1 |
Write 0x1 to Latched Register |
||||||
0x0 |
||||||
T3 |
0x2 |
0x3 |
Read Latched Register |
0x2 |
Read Latched Register |
0x2 |
Write 0x2 to Latched Register |
Write 0x2 to Latched Register |
|||||
0x0 |
0x2 |
|||||
T4 |
0x2 |
0x3 |
Read Latched Register |
0x1 |
Read Latched Register |
0x3 |
Write 0x1 to Latched Register |
Write 0x3 to Latched Register |
|||||
0x0 |
0x2 |
|||||
T5 |
0xC |
0xF |
Read Latched Register |
0xC |
Read Latched Register |
0xE |
Write 0xC to Latched Register |
Write 0xE to Latched Register |
|||||
0x0 |
0xC |
|||||
T6 |
0xC |
0xF |
Read Latched Register |
0x0 |
Read Latched |
0xC |
Write 0xC to Latched Register |
||||||
0xC |
||||||
T7 |
0x4 |
0xF |
Read Latched Register |
0x0 |
Read Latched Register |
0xC |
Write 0xC to Latched Register |
||||||
0x4 |
||||||
T8 |
0x4 |
0xF |
Read Latched Register |
0x0 |
Read Latched Register |
0x4 |
Interrupt Examples
The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.
Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled
Time |
Latched Status (Edge-Triggered – Clear Multi-Channel) |
Latched Status (Edge-Triggered – Clear Single Channel) |
Latched Status (Level-Triggered – Clear Multi-Channel) |
|||
Action |
Latched |
Action |
Latched |
Action |
Latched |
|
T1 (Int 1) |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x1 |
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
||||
0x0 |
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear until T2. |
0x1 |
|||
T3 (Int 2) |
Interrupt Generated Read Latched Registers |
0x2 |
Interrupt Generated Read Latched Registers |
0x2 |
Interrupt Generated Read Latched Registers |
0x2 |
Write 0x2 to Latched Register |
Write 0x2 to Latched Register |
Write 0x2 to Latched Register |
||||
0x0 |
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear until T7. |
0x2 |
|||
T4 (Int 3) |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x3 |
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
Write 0x3 to Latched Register |
||||
0x0 |
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5. |
0x3 |
|||
Interrupt re-triggers Note, interrupt re-triggers after each clear until T7. |
0x2 |
|||||
T6 (Int 4) |
Interrupt Generated Read Latched Registers |
0xC |
Interrupt Generated Read Latched Registers |
0xC |
Interrupt Generated Read Latched Registers |
0xE |
Write 0xC to Latched Register |
Write 0x4 to Latched Register |
Write 0xE to Latched Register |
||||
0x0 |
Interrupt re-triggers Write 0x8 to Latched Register |
0x8 |
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7. |
0xE |
||
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8. |
0xC |
||||
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always. |
0x4 |
|||||
USER WATCHDOG TIMER MODULE MANUAL
Edit this on GitLab
User Watchdog Timer Capability
The User Watchdog Timer (UWDT) Capability is available on the following modules:
-
AC Reference Source Modules
-
AC1 - 1 Channel, 2-115 Vrms, 47 Hz - 20kHz
-
AC2 - 2 Channels, 2-28 Vrms, 47 Hz - 20kHz
-
AC3 - 1 Channel, 28-115 Vrms, 47 Hz - 2.5 kHz
-
-
Differential Transceiver Modules
-
DF1/DF2 - 16 Channels Differential I/O
-
-
Digital-to-Analog (D/A) Modules
-
DA1 - 12 Channels, ±10 VDC @ 25 mA, Voltage or Current Control Modes
-
DA2 - 16 Channels, ±10 VDC @ 10 mA
-
DA3 - 4 Channels, ±40 VDC @ ±100 mA, Voltage or Current Control Modes
-
DA4 - 4 Channels, ±80 VDC @ 10 mA
-
DA5 - 4 Channels, ±65 VDC or ±2 A, Voltage or Current Control Modes
-
-
Digital-to-Synchro/Resolver (D/S) or Digital-to-L( R )VDT (D/LV) Modules
-
(Not supported)
-
-
Discrete I/O Modules
-
DT1/DT4 - 24 Channels, Programmable for either input or output, output up to 500 mA per channel from an applied external 3 - 60 VCC source.
-
DT2/DT5 - 16 Channels, Programmable for either input voltage measurements (±80 V) or as a bi-directional current switch (up to 500 mA per channel).
-
DT3/DT6 - 4 Channels, Programmable for either input voltage measurements (±100 V) or as a bi-directional current switch (up to 3 A per channel).
-
-
TTL/CMOS Modules
-
TL1-TL8 - 24 Channels, Programmable for either input or output.
-
Principle of Operation
The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.
The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:
-
The application must not strobe during the Quiet time.
-
The application must strobe within the Window time.
-
The application must not strobe more than once in a single window time.
A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.
The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.
The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.
Figure 1. User Watchdog Timer Overview
Figure 2. User Watchdog Timer Example
Figure 3. User Watchdog Timer Failures
Register Descriptions
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.
User Watchdog Timer Registers
The registers associated with the User Watchdog Timer provide the ability to specify the UWDT Quiet Time and the UWDT Window that will be monitored to ensure that EXACTLY ONE User Watchdog Timer (UWDT) Strobe is written within the window.
UWDT Quiet Time
Function: Sets Quiet Time value (in microseconds) to use for the User Watchdog Timer Frame.
Type: unsigned binary word (32-bit)
Data Range: 0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write: R/W
Initialized Value: 0x0
Operational Settings: LSB = 1 µsec. The application must NOT write a strobe in the time between the previous strobe and the end of the Quiet time interval. In addition, the application must write in the UWDT Window EXACTLY ONCE.
UWDT Window
Function: Sets Window value (in microseconds) to use for the User Watchdog Timer Frame.
Type: unsigned binary word (32-bit)
Data Range: 0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write: R/W
Initialized Value: 0x0
Operational Settings: LSB = 1 µsec. The application must write the strobe once within the Window time after the end of the Quiet time interval. The application must write in the UWDT Window EXACTLY ONCE. This setting must be initialized to a non-zero value for operation and should allow sufficient tolerance for strobe timing by the application.
UWDT Strobe
Function: Writes the strobe value to be use for the User Watchdog Timer Frame.
Type: unsigned binary word (32-bit)
Data Range: 0x55AA
Read/Write: W
Initialized Value: 0x0
Operational Settings: At startup, the user watchdog is disabled. Write the value of 0x55AA to this register to start the user watchdog timer monitoring after initial power on or a reset. To prevent a disablement, the application must periodically write the strobe based on the user watchdog timer rules.
Status and Interrupt
The modules that are capable of User Watchdog Timer support provide status registers for the User Watchdog Timer.
User Watchdog Timer Status
The status register that contains the User Watchdog Timer Fault information is also used to indicate channel Inter-FPGA failures on modules that have communication between FPGA components. There are four registers associated with the User Watchdog Timer Fault/Inter-FPGA Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
User Watchdog Timer Fault/Inter-FPGA Failure Dynamic Status |
||
User Watchdog Timer Fault/Inter-FPGA Failure Latched Status |
||
User Watchdog Timer Fault/Inter-FPGA Failure Interrupt Enable |
||
User Watchdog Timer Fault/Inter-FPGA Failure Set Edge/Level Interrupt |
||
Bit(s) |
Status |
Description |
D31 |
User Watchdog Timer Fault Status |
0 = No Fault 1 = User Watchdog Timer Fault |
D30:D0 |
Reserved for Inter-FPGA Failure Status |
Channel bit-mapped indicating channel inter |
Function: Sets the corresponding bit (D31) associated with the channel’s User Watchdog Timer Fault error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value: 0
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.
In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
|
Note
|
the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map). |
Interrupt Vector
Function: Set an identifier for the interrupt.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function: Sets where to direct the interrupt.
Type: unsigned binary word (32-bit)
Data Range: See table
Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME |
1 |
|
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) |
2 |
Direct Interrupt to PCIe Bus |
5 |
Direct Interrupt to cPCI Bus |
6 |
Function Register Map
Key
Bold Underline |
= Measurement/Status/Board Information |
Bold Italic |
= Configuration/Control |
User Watchdog Timer Registers
0x01C0 |
UWDT Quiet Time |
R/W |
0x01C4 |
UWDT Window |
R/W |
0x01C8 |
UWDT Strobe |
W |
Status Registers
User Watchdog Timer Fault/Inter-FPGA Failure
0x09B0 |
Dynamic Status |
R |
0x09B4 |
Latched Status* |
R/W |
0x09B8 |
Interrupt Enable |
R/W |
0x09BC |
Set Edge/Level Interrupt |
R/W |
Interrupt Registers
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.
0x056C |
Module 1 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x066C |
Module 1 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x076C |
Module 2 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x086C |
Module 2 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x096C |
Module 3 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0A6C |
Module 3 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0B6C |
Module 4 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0C6C |
Module 4 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0D6C |
Module 5 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0E6C |
Module 5 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0F6C |
Module 6 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x106C |
Module 6 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
MODULE COMMON REGISTERS
Edit this on GitLab
The registers described in this document are common to all NAI Generation 5 modules.
Module Information Registers
The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.
FPGA Version Registers
The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.
FPGA Revision
Function: FPGA firmware revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the revision of the board’s FPGA
Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
FPGA Compile Timestamp
Function: Compile Timestamp for the FPGA firmware.
Type: unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Value corresponding to the compile timestamp of the board’s FPGA
Operational Settings: The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
day (5-bits) |
month (4-bits) |
year (6-bits) |
hr |
||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
hour (5-bits) |
minutes (6-bits) |
seconds (6-bits) |
|||||||||||||
FPGA SerDes Revision
Function: FPGA SerDes revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the SerDes revision of the board’s FPGA
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
FPGA Template Revision
Function: FPGA Template revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the template revision of the board’s FPGA
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
FPGA Zynq Block Revision
Function: FPGA Zynq Block revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Zynq block revision of the board’s FPGA
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
Bare Metal Version Registers
The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.
Bare Metal Revision
Function: Bare Metal firmware revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the revision of the board’s Bare Metal
Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
Bare Metal Compile Time
Function: Provides an ASCII representation of the Date/Time for the Bare Metal compile time.
Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Value corresponding to the ASCII representation of the compile time of the board’s Bare Metal
Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32
Word 1 (Ex. 0x2079614D) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Space (0x20) |
Month ('y' - 0x79) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Month ('a' - 0x61) |
Month ('M' - 0x4D) |
||||||||||||||
Word 2 (Ex. 0x32203731) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Year ('2' - 0x32) |
Space (0x20) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Day ('7' - 0x37) |
Day ('1' - 0x31) |
||||||||||||||
Word 3 (Ex. 0x20393130) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Space (0x20) |
Year ('9' - 0x39) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Year ('1' - 0x31) |
Year ('0' - 0x30) |
||||||||||||||
Word 4 (Ex. 0x31207461) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Hour ('1' - 0x31) |
Space (0x20) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
'a' (0x74) |
't' (0x61) |
||||||||||||||
Word 5 (Ex. 0x38333A35) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Minute ('8' - 0x38) |
Minute ('3' - 0x33) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
':' (0x3A) |
Hour ('5' - 0x35) |
||||||||||||||
Word 6 (Ex. 0x0032333A) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
NULL (0x00) |
Seconds ('2' - 0x32) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Seconds ('3' - 0x33) |
':' (0x3A) |
||||||||||||||
FSBL Version Registers
The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).
FSBL Revision
Function: FSBL firmware revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the revision of the board’s FSBL
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
FSBL Compile Time
Function: Provides an ASCII representation of the Date/Time for the FSBL compile time.
Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Value corresponding to the ASCII representation of the Compile Time of the board’s FSBL
Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time.
The hexadecimal values in the field below represent: May 17 2019 at 15:38:32
Word 1 (Ex. 0x2079614D) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Space (0x20) |
Month ('y' - 0x79) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Month ('a' - 0x61) |
Month ('M' - 0x4D) |
||||||||||||||
Word 2 (Ex. 0x32203731) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Year ('2' - 0x32) |
Space (0x20) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Day ('7' - 0x37) |
Day ('1' - 0x31) |
||||||||||||||
Word 3 (Ex. 0x20393130) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Space (0x20) |
Year ('9' - 0x39) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Year ('1' - 0x31) |
Year ('0' - 0x30) |
||||||||||||||
Word 4 (Ex. 0x31207461) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Hour ('1' - 0x31) |
Space (0x20) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
'a' (0x74) |
't' (0x61) |
||||||||||||||
Word 5 (Ex. 0x38333A35) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Minute ('8' - 0x38) |
Minute ('3' - 0x33) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
':' (0x3A) |
Hour ('5' - 0x35) |
||||||||||||||
Word 6 (Ex. 0x0032333A) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
NULL (0x00) |
Seconds ('2' - 0x32) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Seconds ('3' - 0x33) |
':' (0x3A) |
||||||||||||||
Module Serial Number Registers
The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.
Interface Board Serial Number
Function: Unique 128-bit identifier used to identify the interface board.
Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Serial number of the interface board
Operational Settings: This register is for information purposes only.
Functional Board Serial Number
Function: Unique 128-bit identifier used to identify the functional board.
Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Serial number of the functional board
Operational Settings: This register is for information purposes only.
Module Capability
Function: Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 0107
Read/Write: R
Initialized Value: 0x0000 0103
Operational Settings: A “1” in the bit associated with the capability indicates that it is supported.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Flt-Pt |
0 |
0 |
0 |
0 |
0 |
Pack |
FIFO Blk |
Blk |
Module Memory Map Revision
Function: Module Memory Map revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Module Memory Map Revision
Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
Module Measurement Registers
The registers in this section provide module temperature measurement information.
Temperature Readings Registers
The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.
Interface Board Current Temperature
Function: Measured PCB and Zynq Core temperatures on Interface Board.
Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB and Zynq core temperatures based on the table below
Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
PCB Temperature |
Zynq Core Temperature |
||||||||||||||
Functional Board Current Temperature
Function: Measured PCB temperature on Functional Board.
Type: signed byte (8-bits) for PCB
Data Range: 0x0000 0000 to 0x0000 00FF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB on the table below
Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PCB Temperature |
|||||||
Interface Board Maximum Temperature
Function: Maximum PCB and Zynq Core temperatures on Interface Board since power-on.
Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
PCB Temperature |
Zynq Core Temperature |
||||||||||||||
Interface Board Minimum Temperature
Function: Minimum PCB and Zynq Core temperatures on Interface Board since power-on.
Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
PCB Temperature |
Zynq Core Temperature |
||||||||||||||
Functional Board Maximum Temperature
Function: Maximum PCB temperature on Functional Board since power-on.
Type: signed byte (8-bits) for PCB
Data Range: 0x0000 0000 to 0x0000 00FF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB on the table below
Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PCB Temperature |
|||||||
Functional Board Minimum Temperature
Function: Minimum PCB temperature on Functional Board since power-on.
Type: signed byte (8-bits) for PCB
Data Range: 0x0000 0000 to 0x0000 00FF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB on the table below
Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PCB Temperature |
|||||||
Higher Precision Temperature Readings Registers
These registers provide higher precision readings of the current Zynq and PCB temperatures.
Higher Precision Zynq Core Temperature
Function: Higher precision measured Zynq Core temperature on Interface Board.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Zynq Core temperature on Interface Board
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Signed Integer Part of Temperature |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional Part of Temperature |
|||||||||||||||
Higher Precision Interface PCB Temperature
Function: Higher precision measured Interface PCB temperature.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Interface PCB temperature
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Signed Integer Part of Temperature |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional Part of Temperature |
|||||||||||||||
Higher Precision Functional PCB Temperature
Function: Higher precision measured Functional PCB temperature.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Functional PCB temperature
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Signed Integer Part of Temperature |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional Part of Temperature |
|||||||||||||||
Module Health Monitoring Registers
The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.
Module Sensor Summary Status
Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds.
Type: unsigned binary word (32-bits)
Data Range: See table below
Read/Write: R
Initialized Value: 0
Operational Settings: This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.
Bit(s) |
Sensor |
D31:D6 |
Reserved |
D5 |
Functional Board PCB Temperature |
D4 |
Interface Board PCB Temperature |
D3:D0 |
Reserved |
Module Sensor Registers
The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.
Sensor Threshold Status
Function: Reflects which threshold has been crossed
Type: unsigned binary word (32-bits)
Data Range: See table below
Read/Write: R
Initialized Value: 0
Operational Settings: The associated bit is set when the sensor reading exceed the corresponding threshold settings.
Bit(s) |
Description |
D31:D4 |
Reserved |
D3 |
Exceeded Upper Critical Threshold |
D2 |
Exceeded Upper Warning Threshold |
D1 |
Exceeded Lower Critical Threshold |
D0 |
Exceeded Lower Warning Threshold |
Sensor Current Reading
Function: Reflects current reading of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Minimum Reading
Function: Reflects minimum value of temperature sensor since power up
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Maximum Reading
Function: Reflects maximum value of temperature sensor since power up
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Lower Warning Threshold
Function: Reflects lower warning threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default lower warning threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.
Sensor Lower Critical Threshold
Function: Reflects lower critical threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default lower critical threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.
Sensor Upper Warning Threshold
Function: Reflects upper warning threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default upper warning threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.
Sensor Upper Critical Threshold
Function: Reflects upper critical threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default upper critical threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.
FUNCTION REGISTER MAP
Key
Bold Underline |
= Measurement/Status/Board Information |
Bold Italic |
= Configuration/Control |
Module Information Registers
0x003C |
FPGA Revision |
R |
0x0030 |
FPGA Compile Timestamp |
R |
0x0034 |
FPGA SerDes Revision |
R |
0x0038 |
FPGA Template Revision |
R |
0x0040 |
FPGA Zynq Block Revision |
R |
0x0074 |
Bare Metal Revision |
R |
0x0080 |
Bare Metal Compile Time (Bit 0-31) |
R |
0x0084 |
Bare Metal Compile Time (Bit 32-63) |
R |
0x0088 |
Bare Metal Compile Time (Bit 64-95) |
R |
0x008C |
Bare Metal Compile Time (Bit 96-127) |
R |
0x0090 |
Bare Metal Compile Time (Bit 128-159) |
R |
0x0094 |
Bare Metal Compile Time (Bit 160-191) |
R |
0x007C |
FSBL Revision |
R |
0x00B0 |
FSBL Compile Time (Bit 0-31) |
R |
0x00B4 |
FSBL Compile Time (Bit 32-63) |
R |
0x00B8 |
FSBL Compile Time (Bit 64-95) |
R |
0x00BC |
FSBL Compile Time (Bit 96-127) |
R |
0x00C0 |
FSBL Compile Time (Bit 128-159) |
R |
0x00C4 |
FSBL Compile Time (Bit 160-191) |
R |
0x0000 |
Interface Board Serial Number (Bit 0-31) |
R |
0x0004 |
Interface Board Serial Number (Bit 32-63) |
R |
0x0008 |
Interface Board Serial Number (Bit 64-95) |
R |
0x000C |
Interface Board Serial Number (Bit 96-127) |
R |
0x0010 |
Functional Board Serial Number (Bit 0-31) |
R |
0x0014 |
Functional Board Serial Number (Bit 32-63) |
R |
0x0018 |
Functional Board Serial Number (Bit 64-95) |
R |
0x001C |
Functional Board Serial Number (Bit 96-127) |
R |
0x0070 |
Module Capability |
R |
0x01FC |
Module Memory Map Revision |
R |
Module Measurement Registers
0x0200 |
Interface Board PCB/Zynq Current Temperature |
R |
0x0208 |
Functional Board PCB Current Temperature |
R |
0x0218 |
Interface Board PCB/Zynq Max Temperature |
R |
0x0228 |
Interface Board PCB/Zynq Min Temperature |
R |
0x0218 |
Functional Board PCB Max Temperature |
R |
0x0228 |
Functional Board PCB Min Temperature |
R |
0x02C0 |
Higher Precision Zynq Core Temperature |
R |
0x02C4 |
Higher Precision Interface PCB Temperature |
R |
0x02E0 |
Higher Precision Functional PCB Temperature |
R |
Revision History
Revision |
Revision Date |
Description |
C |
2023-06-13 |
ECO C11340, Transitioned manual to docbuilder format. Pg.6, replaced Specifications sectionwith Data Sheet. Pg.8, updated Introduction/replaced Features with Overview. Pg.9/20/30, addedmodule common registers. Pg.23, removed Summary Events Table. Pg.44, added Pin-OutDetails. |
Revision |
Revision Date |
Description |
C |
2021-11-30 |
C08896; Transition manual to docbuilder format - no technical info change. |
Revision |
Revision Date |
Description |
C |
2023-08-11 |
ECO C10649, initial release of module common registers manual. |
NAI Cares
Edit this on GitLab
North Atlantic Industries (NAI) is a leading independent supplier of Embedded I/O Boards, Single Board Computers, Rugged Power Supplies, Embedded Systems and Motion Simulation and Measurement Instruments for the Military, Aerospace and Industrial Industries. We accelerate our clients’ time-to-mission with a unique approach based on a Configurable Open Systems Architecture™ (COSA®) that delivers the best of both worlds: custom solutions from standard COTS components.
We have built a reputation by listening to our customers, understanding their needs, and designing, testing and delivering board and system-level products for their most demanding air, land and sea requirements. If you have any applications or questions regarding the use of our products, please contact us for an expedient solution.
Please visit us at: www.naii.com or select one of the following for immediate assistance: