Synchro Resolver Measurement Modules
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INTRODUCTION
As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurements and simulation, communications, Ethernet switch, and SBC functions. Our SD1-SD5 smart function modules provide Synchro-to-Digital (S/D) or Resolver-to-Digital (R/D) measurement. Synchros and Resolvers are transformer-type voltage/current transducers that convert a shaft or other rotating device’s angular position and/or velocity to a multi-wire AC electrical signal. Both deliver signals proportional to the Sine and/or Cosine of the shaft angle. The SD1-SD5 smart function modules convert these signals to a digital output corresponding to the shaft angle and/or velocity. See the following table for each model’s operating parameters.
Module ID |
No. of Channels |
Input Voltage (RMS VL-L) |
Frequency Range (Hz) |
SD1 |
4 |
2-28 |
47-1k |
SD2 |
4 |
2-28 |
1k-5k |
SD3 |
4 |
2-28 |
5k-10k |
SD4 |
4 |
2-28 |
10k-20k |
SD5 |
4 |
28-90 |
47-1k |
This user manual is designed to help you get the most out of our Synchro or Resolver-to-Digital smart function modules.
SD1-SD5 Overview
NAI’s SD1-SD5 modules offers a range of features designed to suit a variety of system requirements, including:
Isolated Excitation and Signal Input:
With isolated excitation and signal input, the Synchro/Resolver modules are able to interface to virtually any type of transformer-type voltage/current transducers that convert a shaft or other rotating device’s angular position and/or velocity to a multi-wire AC electrical signal.
Type II Servo Loop Processing:
The use of Type II servo loop processing techniques enables tracking up to the specified rate, at full accuracy. A step input will not cause any hang-up condition. Intermediate transparent latches, on all angle and velocity outputs, assure that valid data is always available. Our synthetic reference compensates for ±60° phase shifts, thus eliminating the need for individual compensation networks.
24-Bit Resolution:
The modules feature 24-bit resolution and a single speed accuracy of 1 arc-min. For two speed applications, the overall accuracy is calculated by dividing the accuracy of the fine channel (1 arc-min) by the gear ratio.
Measurement and Detection Capabilities:
The channels include many other useful application features such as signal, reference, and frequency measurements as well as signal under- and over-voltage detection, and reference under- and over-voltage detections.
Continuous Background Built-In-Test (BIT):
All channels have continuous background Built-In-Test (BIT), which provides real-time channel health to ensure reliable operation in mission-critical systems. This feature runs in the background and is transparent in normal operations.
Extended FIFO Buffering Capability:
The modules also include extended SD FIFO buffering capabilities for greater storage/management of the incoming signal samples (data) for post processing applications. Programmable FIFO buffer thresholds maximize data flow control (in and out of the FIFO).
PRINCIPLE OF OPERATION
Angle Measurement
The Synchro/Resolver channels feature 24-bit resolution with a single speed accuracy of as defined per the Synchro/Resolver to Digital Converter Specifications. For two-speed applications, the overall accuracy is calculated by dividing the accuracy of the fine channel by the gear ratio.
Multi-Speed Operation
For multi-speed operation, the pairs are defined as Ch.1 & 2 and Ch. 3 & 4. The coarse and fine channels will always read their respective angle, while the combined angle will be available in the Combined Angle register.
Signal/Reference
The Signal and Excitation RMS values (10 mV resolution) are available as well as the Excitation Frequency (1 Hz resolution).
Track/Hold
A LATCH feature is provided to permit the user to take a “snapshot” of the Synchro/Resolver angular position of all channels simultaneously to ensure no delay error when reading each channel angle register. Reading the channel angle register allow the register to be updated continually.
|
Note
|
While the register reading is being latched, the channel is still internally tracking the input angle. |
Angle Alert
After the angle alert function is enabled, and then a channel’s angle value exceeds a pre-programmed delta angle the associated status register will get set. An interrupt, if enabled, will be generated as soon as that threshold is reached. Thus, no polling of the angle registers is required until an angle has reached the specified difference.
Built-In Test (BIT)/Diagnostic Capability
The board supports four types of built-in tests: Power-On, Continuous Background (CBIT), User (UBIT) and Initiated. The results of these tests are stored in the BIT Dynamic Status and BIT Latched Status registers.
Power-On Self-Test (POST)
This board features a power-on self-test that will do an accuracy check of each channel and report the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST test is complete before reading the BIT Latched Status.
Continuous Background Built-In Test
All SD/RD measurement modules feature a background self-test capability or Continuous BIT (CBIT)(“D2”) test. The CBIT test enables reporting of automatic background BIT (accuracy) testing. Seamlessly and transparently, each channel is checked every 5° (from 0° to 355°) to a default accuracy of 0.05°. Any channel exceeding the tolerance will trigger an Interrupt (if enabled) and results are available in BIT Latched Status registers. The testing is totally transparent to the user, requires no external programming, has no effect on the standard operation of the card, and status reporting can be ignored without changing normal operation. The user can verify that the background BIT testing is executing by writing a value other than 0x0055 to the Test CBIT Verify register and then reading theTest CBIT Verify register after 200 µs. The value reported back will be 0x0055 while the background bit testing is active.
In addition to the above accuracy tests, Signal Fault Low Status, Reference Fault Low Status, Signal Fault High Status, Reference Fault High Status, Loss Lock (when in Multi-speed) and Delta Angle are always monitored during CBIT.
Initiate Built-In Test
The SD/RD module support two off-line Initiated Built-in Test, User Initiated BIT (UBIT) (“D0”) and Initiated BIT (IBIT) (“D3”).
UBIT is used to check the channel functionality without the need for external sources All channels use an internal stimulus to simulate angular positions that the user can set and then to read the data from the interface. All channels acquire data from this internal source.
IBIT test starts an initiated BIT test that utilizes an internal stimulus to generate and test 19 different angles to a test accuracy of 0.05. IBIT test cycle is completed within 5 seconds and the result can be read from the BIT status registers when IBIT (D3 of Test Enable Register) bit changes from 1 to 0. Any failure triggers an Interrupt (if enabled). The testing can be initiated or stopped.
|
Note
|
UBIT and IBIT are individual tests and will not operate concurrently. For example, if the UBIT mode is set, and the user would like to perform the IBIT test, the UBIT mode must be released before the IBIT test will run. The same holds true when the IBIT test is active. In order for the UBIT test to be activated, the user must disable the IBIT test. The CBIT test, however, can be set and the board can still perform with either the UBIT or IBIT tests. The CBIT test will momentarily stop while either of these tests are active and will return when the tests have completed. |
|
Note
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The default error limit that the BIT tests check to is 0.050 degrees. In some systems where the noise characteristics may result in larger errors, the user has the option to program their own limits, per channel, by writing to the BIT Error Limit registers. There is one BIT Error Limit register per channel and is written to as an IEEE-754 floating point number. |
SD/RD Threshold Programming
In addition to Built-in Tests, the SD/RD modules provide the ability to monitor Signal faults (under and over-voltage conditions), Reference faults (under and over-voltage conditions) and Open detects.
SD/RD FIFO Buffering
The SD/RD modules include SD/RD FIFO Buffering for greater control of the incoming signal (data) for analysis and display. When initialized and triggered, the SD/RD buffer will accept/store the data at the same rate specified in the FIFO Sample Rate register. Programmable buffer sample thresholds can be utilized for data flow control.
Status and Interrupts
The SD/RD Modules provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.
Engineering Scaling Conversions
There are separate floating point scale and offset registers for angle and velocity for each channel.
It is very often necessary to convert a Synchro/Resolver reading into another measurement unit. When the Enable Floating Point Mode register is set to 1, the values entered for the Floating Point Scale register and Floating Point Offset register will be used to convert the data (i.e., Angle and Velocity Data registers) to the associated engineering unit as follows:
SD Data in Engineering Units (Floating Point) =
(SD Value (Angle) * (Floating Point Scale/360°)) + Floating Point Offset
The purpose for providing this feature is to offload the processing that is normally performed by the mission processor to convert the integer values to engineering unit values.
When the Enable Floating Point Mode register is set to 1 (Floating Point Mode) the following registers are formatted as Single Precision Floating Point Values (IEEE-754):
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Angle Data
-
Combined Angle Data
-
Velocity Data
-
Measured Reference RMS Voltage
-
Measured Signal RMS Voltage
-
Measured Frequency
-
FIFO Buffer Data
-
Threshold Detect Levels* (Signal Faults, Reference Faults)
-
UBIT Test Angle*
-
Delta Angle*
*When the Enable Floating Point Mode register is set to 1, it is important that these registers are updated with the Single Precision Floating Point (IEEE-754) representation of the value for proper operation of the channel. Conversely, when the Enable Floating Point Mode register is set to 0, these registers must be updated with the Integer 32-bit representation of the value.
|
Note
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when changing the Enable Floating Point Mode from Integer Mode to Floating Point Mode or vice versa, the following step should be followed to avoid faults from falsely being generated because Thresholds and Test Angle registers have an incorrect binary representation of the values: |
-
Set the Enable Floating Point Mode register to the desired mode (Integer = 0 or Floating Point = 1).
-
Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete. Data registers will be converted to the units specified and can be read in that specified format.
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Initialize configuration and control registers with the values in the units specified (Integer or Floating Point).
The following registers are formatted as Single Precision Floating Point Values (IEEE-754) regardless of the value in the Enable Floating Point Mode register:
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Sine, Cosine, Sine+Cosine Voltages
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Sine, Cosine Detect Values
-
Open Detect Thresholds
-
BIT Error Limit
-
Angle and Velocity Floating Point Scales and Offsets
Module Common Registers
The SD/RD Function Modules provide module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.
REGISTER DESCRIPTIONS
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.
SD/RD Measurement Registers
When the Enable Floating Point Mode is enabled, the register values are formatted as Single Precision Floating Point Value (IEEE-754) values. In addition, the Floating Point Scale and register Floating Point Offset will be applied to convert the angle value to engineering units.
Angle Data
Function: Reads the individual channel angle in degrees when the channel is in single-speed or multi-speed mode.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0 to 359.9999 degrees Integer Mode (Enable Floating Point Mode register = 0) LSB is 360/2 or approximately 8.3819 x 10 degrees Floating Point Mode (Enable Floating Point Mode register = 1) Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: Note, for multispeed operation, the pairs are defined as Ch.1 & 2 and Ch. 3 & 4. The coarse and fine channels will always read their respective angle, while the combined angle will be available in a separate register (defined in Combined Angle register).
Integer Mode:
180 |
90 |
45 |
22.5 |
11.25 |
5.625 |
2.8125 |
1.40625 |
0.703125 |
0.351563 |
0.175781 |
0.087891 |
0.043945 |
0.021973 |
0.010986 |
0.005493 |
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
2.746582E-03 |
1.373291E-03 |
8.666455E-04 |
3.443228E-04 |
1.716614E-04 |
8.583096E-05 |
4.291534E-05 |
2.145767E-05 |
1.072884E-05 |
5.364418E-06 |
2.682209E-06 |
1.341105E-06 |
6.705523E-07 |
3.352761E-07 |
1.676381E-07 |
8.381930E-08 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754).
Velocity Data
Function: Reads the individual channel Clockwise and Counter-clockwise velocity in degrees per second (dps).
Type: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: +/-300,000 degrees / sec
Integer Mode (Enable Floating Point Mode register = 0)
32-bit two’s complement
0x7FFF FFFF being maximum CW rotation, and 0x8000 0000 being maximum CCW rotation.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: To convert a velocity word to revolutions per second (rps): Velocity in rps = value (dps) / 360
Integer Mode: The velocity register is read as a two’s complement word when in “integer” mode, with 0x7FFF FFFF being the maximum positive velocity, and 0x8000 0000 being the maximum negative velocity. Units are in degrees/second. LSB Value is 0.1 degree/second.
Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754).
Sine RMS
Function: Reads the individual channel RMS value of the “Sine” input (10 mV resolution).
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0.0 to 100.0
Read/Write: R
Initialized Value: N/A
Operational Settings: N/A
Cosine RMS
Function: Reads the individual channel RMS value of the “Cosine” input (10mV resolution).
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0.0 to 100.0
Read/Write: R
Initialized Value: N/A
Operational Settings: N/A
Sine+Cosine RMS
Function: Reads the individual channel total sum RMS value of the “Sine” and “Cosine” signals added together regardless of phase (10mV resolution).
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0.0 to 200.0
Read/Write: R
Initialized Value: N/A
Operational Settings: N/A
Measured Reference (RMS)
Function: Measures individual channel input reference voltage (10mV Resolution).
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0-140
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings:
Integer Mode: Read integer value and multiply value by LSB (10 mV) to compute the reference voltage.
Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754).
Measured Signal (RMS)
Function: Measures RMS value (Square root of the sum of the squares) (Vsine^2 + Vcosine^2 )1/2
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0.0 to 100.0
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The input signal voltages “Vsine + Vcosine” are measured, squared & summed
Integer Mode: Read integer value and multiply value by LSB (10 mV) to compute the signal voltage.
Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754).
Measured Frequency (Hz)
Function: Measures individual channel input reference frequency.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0-20 kHz
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 1 Hz.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: Each individual channel input reference frequency is measured, and the value is reported to a corresponding register.
Integer Mode: The integer value represents the reference frequency in Hz.
Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754).
Combined Angle
Function: Reads the multi-speed combined angle for increased accuracy.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0 to 359.9999 degrees
Integer Mode (Enable Floating Point Mode register = 0)
LSB is 360/232 or approximately 8.3819 x 10-8 degrees
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings:
Integer Mode:
For multispeed operation, the pairs are defined as Ch.1 & 2 and Ch. 3 & 4.
180 |
90 |
45 |
22.5 |
11.25 |
5.625 |
2.8125 |
1.40625 |
0.703125 |
0.351563 |
0.175781 |
0.087891 |
0.043945 |
0.021973 |
0.010986 |
0.005493 |
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
2.746582E-03 |
1.373291E-03 |
8.666455E-04 |
3.443228E-04 |
1.716614E-04 |
8.583096E-05 |
4.291534E-05 |
2.145767E-05 |
1.072884E-05 |
5.364418E-06 |
2.682209E-06 |
1.341105E-06 |
6.705523E-07 |
3.352761E-07 |
1.676381E-07 |
8.381930E-08 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Floating Point Mode:
Read as Single Precision Floating Point Value (IEEE-754).
Sine Detect Value
Function: Reports a numeric value based on the connection status of the Sine input from the SD/RD.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0 to 200,000 (typical range)
Read/Write: R
Initialized Value: N/A
Operational Settings: This register will display a value typically in the hundreds when the is connected normally and is functional. If one of the inputs, Sine(hi) or Cosine(lo) is disconnected from the SD/RD, this value will increase into the thousands. If the Sine and Cosine winding is shorted, the value will be close to “0”. This value is used in comparison with the Open and Short Detect threshold values to alert the user of a faulty connection.
Cosine Detect Value
Function: Reports a numeric value based on the connection status of the Cosine input from the SD/RD.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0 to 200,000 (typical range)
Read/Write: R
Initialized Value: N/A
Operational Settings: Refer to Sine Detect Value register description.
SD/RD Control Registers
The SD/RD control registers provide the ability to specify the mode, bandwidth, bandwidth select mode, multi-speed mode, delta angle value, initiate delta angle setting, channel status enable setting, track/hold setting, and inverse signal control setting.
Mode Select
Function: Configures for Synchro or Resolver measurement.
Type: unsigned binary word (32-bit)
Data Range: See table.
Read/Write: R/W
Initialized Value: 0
Operational Settings: Set the Mode as specified in the table.
Mode Select Value |
Description |
0 |
Resolver |
3 |
Synchro |
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Mode |
Mode |
Bandwidth Select
Function: Sets the bandwidth control to use. Bandwidth settings can be set manually or automatically by the module’s internal processor.
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: R/W
Initialized Value: 0
Operational Settings: Set to Manual (0) to use the value in the Bandwidth register. Set to Automatic (1) to have the module automatically set the bandwidth will be set to 1/10 of the excitation frequency up to 1280 Hz. The Bandwidth register will contain the calculated bandwidth when in Bandwidth Select is set to automatic. The bandwidth setting will only update when there is a 12.5% change in frequency. For example, if the frequency is at 1Khz and the bandwidth is set to 100hz, a change in frequency less than 125Hz will result in no change to the bandwidth setting.
Bandwidth Select Value |
Description |
0 |
Manual |
1 |
Automatic |
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Bandwidth (Hz)
Function: Sets the bandwidth when the Bandwidth Select register is set for “Manual” or contains the bandwidth set by the module’s internal processor when the Bandwidth Select register is set for “Automatic”.
Type: unsigned binary word (32-bit)
Data Range: 2 to 1280 Hz
Read/Write: R/W
Initialized Value: 40 Hz
Operational Settings: When the Bandwidth Select register is set for “Manual” mode, the bandwidth is programmable, between 2 and 1280 Hz. The LSB is 1 Hz. The resolution is 2Hz. All values greater than 1280 will be processed as 1280Hz. All values less than 2 will be processed as 2 Hz.
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Note
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the bandwidth should not be set to more than ¼ of the reference frequency. A higher BW setting will result in a quicker response to a change in angular position but will be at the expense of greater noise in the reading. A lower BW value will result in a much quieter reading but will take longer to settle. |
When the Bandwidth Select register is set for “Automatic” mode, the bandwidth will be internally calculated and written to this register. The bandwidth value will be set to 1/10 the carrier frequency with a minimum BW of 2 Hz, and a maximum BW of 1280 Hz. The change will occur only when a frequency change of 12.5% or greater is detected as illustrated in the table.
Example: Bandwidth Select = Automatic
Reference Frequency |
Bandwidth Value |
Description |
Current Reference frequency at 400 Hz |
Bandwidth sets to 40Hz |
a 12.5% change would be 50 Hz |
Reference Frequency changes to 12Khz |
Bandwidth sets to 1200Hz |
3000% change from 400Hz |
Reference Frequency changes to 13Khz |
Bandwidth sets to 1200Hz |
8.333% change from 12Khz (not enough to trigger a change) |
Reference Frequency changes to 14Khz |
Bandwidth sets to 1280Hz |
16.666% change from 12Khz |
Multi-Speed Ratio
Function: Sets single, or multi-speed configuration for channel pairs Ch. 1 & 2, and Ch. 3 & 4.
Type: unsigned binary word (32-bit)
Data Range: 1 to 255
Read/Write: R/W
Initialized Value: 1 (Single-Speed)
Operational Settings: Selected in pairs; Ch 1 and 2, and Ch 3 and 4. Set the desired ratio corresponding to the pair of channels to be used for a two-speed or multi-speed configuration. Example, 36:1, set Multi-speed Ratio = 36. Default is for single-speed applications where Multi-speed Ratio = 1.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D |
D |
D |
D |
D |
D |
D |
Delta Angle
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0x0009 1A2B to 0x7FED CBA9 (Integer mode) or 0.05 to 179.9 degrees (Floating Point Mode)
Read/Write: R/W
Initialized Value: 0
Operational Settings: Set the minimum differential angle to trigger an angle change alert.
Integer Mode: Set the Delta Angle based on the bit weighs shown in the table.
180 |
90 |
45 |
22.5 |
11.25 |
5.625 |
2.8125 |
1.40625 |
0.703125 |
0.351563 |
0.175781 |
0.087891 |
0.043945 |
0.021973 |
0.010986 |
0.005493 |
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
2.746582E-03 |
1.373291E-03 |
6.866455E-04 |
3.443228E-04 |
1.716614E-04 |
8.583096E-05 |
4.291534E-05 |
2.145767E-05 |
1.072884E-05 |
5.364418E-06 |
2.682209E-06 |
1.341105E-06 |
6.705523E-07 |
3.352761E-07 |
1.676381E-07 |
8.381930E-08 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Note
|
The per bit angle values in the following table are approximate. |
Floating Point Mode: Set as Single Precision Floating Point Value (IEEE-754).
Initiate Delta Angle
Function: Initiates the monitored for angle change alert.
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: W
Initialized Value: 0
Operational Settings: Used in conjunction with the Delta Angle register. Writing a “1” to the Initiate Delta Angle register will capture the current angle and use this value to detect a change of +/- the value written in the Delta Angle register. If the angle exceeds this limit, the corresponding bit in the Delta Angle Status registers (Dynamic and Latched) will be set.
|
Note
|
Since the dynamic registers in general give you the current state of the channel, the bit will be set and then cleared within 4.096 µs and might not be observed in the dynamic register. The bit in the Delta Angle Latched Status register, however, will remain set until cleared. |
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Track/Hold
Function: Latches channels.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R/W
Initialized Value: 0
Operational Settings: Setting the bit for the associated channel to a “1” will latch the data for the corresponding channel. Internally, the channel will continue to track the input, but the data in the Angle Data register for the corresponding channel will be latched at the SD/RD angle when the latch was initiated. Once the Angle Data register is read, the hardware will disengage the latch for that channel and will continue to update the current Synchro/Resolver angle. It will automatically clear the bit associated with the channel. Once set, you can always return to updating the angle by clearing the corresponding channel bit. Note, this feature can be used to acquire a snapshot of all channels simultaneously.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Inverse Signal Control
Function: Enables the inversion of the phase of the Sine, Cosine and Reference signals.
Type: unsigned binary word (32-bit)
Data Range: See table.
Read/Write: R/W
Initialized Value: 0
Operational Settings: The feature provides the ability to invert the phase of the Sine, Cosine and Reference signals.
Inverse Signal Control Value |
Description |
0 |
Do not invert phase of signal. |
1 |
Invert phase of signal. |
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
REF |
COS |
SIN |
Threshold Programming Registers
The Signal Fault Low Threshold, Signal Fault High Threshold, Reference Fault Low Threshold, Reference Fault High Threshold, and Open Detect Threshold registers set the threshold limits to the Signal Fault Low Status, Signal Fault High Status, Reference Fault Low Status, Reference Fault High Status, and Open Detect Status registers respectively.
Signal Fault Low Threshold
Function: Sets the “under-voltage” threshold at which a fault will be reported in the Signal Fault Low Status register.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0 - 130Vrms
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 826 decimal (8.26 VLL)(SD1-SD4); 6300 decimal (63.00 VLL)(SD5)
Operational Settings: The signal fault detection circuitry will report a fault in the Signal Fault Low Status register when the measured signal is below the value set in Signal Fault Low Threshold register.
Signal Fault High Threshold
Function: Sets the “over-voltage” threshold at which a fault will be reported in the Signal Fault High Status register.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0 - 130Vrms
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 1685 decimal (16.85 VLL)(SD1-SD4); 11700 decimal (117.00 VLL)(SD5)
Operational Settings: The signal fault detection circuitry will report a fault in the Signal Fault High Status register when the measured signal is above the value set in Signal Fault High Threshold register.
Reference Fault Low Threshold
Function: Sets the “under-voltage” threshold at which a fault will be reported in the Reference Fault Low Status register.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0-135 Vrms
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 1820 decimal (18.2 V)(SD1-SD4); 8050 decimal (80.5 V)(SD5)
Operational Settings: The reference fault detection circuitry will report a fault in the Reference Fault Low Status register when the measured reference signal is below the value set in Reference Fault Low Threshold register.
Reference Fault High Threshold
Function: Sets the “over-voltage” threshold at which a fault will be reported in the Reference Fault High Status register.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0-135 Vrms
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 3380 decimal (33.8 V)(SD1-SD4); 14950 decimal (149.5 V)(SD5)
Operational Settings: The reference fault detection circuitry will report a fault in the Reference Fault High Status register when the measured reference signal is above the value set in Reference Fault High Threshold register.
Open Detect Threshold
Function: Sets the threshold at which “open” signal will be reported in the Open Detect Status register.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0.0 - 100,000.0
Read/Write: R/W
Initialized Value: 10,000.0
Operational Settings: This register value is used as a comparison for the Sine Detect Value and Cosine Detect Value register values. Since SD/RDs vary, this value will need to be “tuned” and will be described in the Sine Detect Value and Cosine Detect Value registers section.
SD/RD Test Registers
Three different tests, one on-line (CBIT) and two off-line (UBIT, IBIT), can be selected. External reference voltage is not required for any of these tests.
Test Enabled
Function: Set bit in this register to enable associated Built-In Self-Test IBIT, CBIT and UBIT.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 to 0x000D
Read/Write: R/W
Initialized Value: 0x4 (CBIT Test Enabled)
Operational Settings: BIT tests include an on-line (CBIT) test and two off-line (UBIT, IBIT) tests. Failures in the BIT tests are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects a failure. UBIT and IBIT will not operate concurrently. When UBIT is enabled, the IBIT should not be enabled, and vice versa. CBIT can be set with either UBIT or IBIT enabled. Note, IBIT when enabled will run until the test completes (within 5 seconds).
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
IBIT Test D |
CBIT Test 1 |
0 |
UBIT Test D |
Test CBIT Verify
Function: Allows user to verify if the CBIT test is running.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: User can write any value to this register. If CBIT test is running, after a minimum of 10ms the value read back will be 0x0000 0055, otherwise the value read back will be the value written.
UBIT Test Angle
Function: Specifies the angle to be applied by the Synchro/Resolver UBIT test.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0 to 359.9945
Integer Mode (Enable Floating Point Mode register = 0)
LSB : 360/232
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 30.0 deg
Operational Settings:
Integer Mode: Set the Test Angle based on the bit weighs shown in the table.
180 |
90 |
45 |
22.5 |
11.25 |
5.625 |
2.8125 |
1.40625 |
0.703125 |
0.351563 |
0.175781 |
0.087891 |
0.043945 |
0.021973 |
0.010986 |
0.005493 |
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
2.746582E-03 |
1.373291E-03 |
6.866455E-04 |
3.443228E-04 |
1.716614E-04 |
8.583096E-05 |
4.291534E-05 |
2.145767E-05 |
1.072884E-05 |
5.364418E-06 |
2.682209E-06 |
1.341105E-06 |
6.705523E-07 |
3.352761E-07 |
1.676381E-07 |
8.381930E-08 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Note
|
The per bit angle values in the following table are approximate. |
Floating Point Mode: Set the Test Angle as a Single Precision Floating Point Value (IEEE-754).
BIT Error Limit
Function: Allows the user to set the error limit for the CBIT, UBIT and IBIT tests.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Positive value - setting this value to zero will most likely result in a BIT Status failure.
Read/Write: R/W
Initialized Value: 0.050
Operational Settings: The default error limit that the BIT tests check to is 0.050 degrees. In some systems the noise characteristics may result in larger errors than the default error limit. Setting BIT Error Limit registers with a value that is better suited for these systems may help lower the possibility of reporting “false-positives” for the channel in the BIT Status registers during BIT testing.
FIFO Registers
The FIFO registers are configurable for each channel.
FIFO Buffer Data
Function: Available data in the FIFO buffer can be retrieved, one word at a time (32-bits).
Type:
Angle and Velocity: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Timestamp: unsigned binary word (32-bit)
Data Range: Varies based on Data type. Reading Angle & Velocity can be either integer or float format. Time stamp will always be in integer format.
Integer Mode (Enable Floating Point Mode register = 0)
32-bit two’s complement
-Full Scale (0x8000 0000) to +Full Scale (0x7FFF FFFF)
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: 0
Operational Settings: Data for the Angle & Velocity will be stored in either the integer format or IEEE floating point standard based on the state of the Enable Floating Point Mode register.
FIFO Word Count
Function: This is a counter that reports the number of 32-bit words currently in the FIFO Buffer Data register.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R
Initialized Value: 0
Operational Settings: Each time the module writes to the FIFO, the word count will be incremented by 1. Any read operations made from the FIFO Buffer Data memory address; its corresponding Words in FIFO counter will be decremented by one. The maximum number of words that can be stored in the FIFO is 4,194,304 (4 Meg) (0x0040 0000).
FIFO Thresholds
The FIFO Almost Empty Threshold, FIFO Low Watermark Threshold, FIFO High Watermark Threshold, FIFO Almost Full Threshold and FIFO Buffer Size registers set the threshold limits that are used to set the bits in the FIFO Status registers.
|
Note
|
It is important that the almost empty threshold/low watermark threshold be set less than the almost full threshold/high watermark threshold, respectively, for valid operation. |
FIFO Almost Empty
Function: The FIFO Almost Empty threshold level is used as a comparison value to determine when to set the “almost empty” bit in the FIFO Status register.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R/W
Initialized Value: 0x0000 0032
Operational Settings: When the number of words in the FIFO Word Count register is less than or equal to the value stored in this register, the “almost empty” bit (D1) of the FIFO Status register will be set. When the number of words in FIFO Word Count is greater than the value stored in this register, the “almost empty” bit (D1) of the FIFO Status register will be reset.
FIFO Low Watermark
Function: The FIFO Low Watermark threshold level is used as a comparison value to determine when to set the “low watermark” bit in the FIFO Status register.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R/W
Initialized Value: 0x0000 0064
Operational Settings: When the number of words in FIFO Word Count register is less than or equal to the value stored in this register, the “low watermark” bit (D2) of the FIFO Status register will be set. When the number of words in FIFO Word Count is greater than the value stored in this register, the “low watermark” bit (D2) of the FIFO Status register will be reset.
FIFO High Watermark
Function: The FIFO High Watermark threshold level is used as a comparison value to determine when to set the “high watermark” bit in the FIFO Status register.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R/W
Initialized Value: 0x003F 0000
Operational Settings: When the number of words in FIFO Word Count register is greater than or equal than the value stored in this register, the “high watermark” bit (D3) of the FIFO Status register will be set. When the number of words in FIFO Word Count is less than the value stored in the register, the “high watermark” bit (D3) of the FIFO Status register will be reset.
FIFO Almost Full
Function: The FIFO Almost Full threshold level is used as a comparison value to determine when to set the “almost full” bit in the FIFO Status register.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R/W
Initialized Value: 0x003F FF00
Operational Settings: When the number of words in the FIFO Word Count register is greater than or equal to the value stored in this register, the “almost full” bit (D4) of the FIFO Status register will be set. When the number of words in FIFO Word Count is less than the value stored in this register, the “almost full” bit (D4) of the FIFO Status register will be reset.
FIFO Buffer Size
Function: The FIFO Buffer Size sets the number of samples to be taken and placed into the FIFO when a trigger occurs.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R/W
Initialized Value: 0x0000 2000
Operational Settings: When the number of samples set in this register are sent to the FIFO, the “sample done” bit (D6) in the FIFO Status register is set. If another trigger is sent the “sample done” bit is cleared and set again once all data has been transferred. The largest number of samples that may be collected is 4,194,304 (0x0040 0000). If the buffer size is greater than the amount of words available in the FIFO, only the number of words that are available will be stored and the remaining words lost.
FIFO Buffer Control
Function: The FIFO Buffer Control register defines the type of data that is stored in the FIFO Buffer Data register for each channel.
Type: unsigned binary word (32-bit)
Data Range: See table
Read/Write: R/W
Initialized Value: 0
Operational Settings: The following data types are available:
D31:D3 |
Reserved - Set to 0. |
D2 |
Store Timestamp. An integer counter that counts from 0 to 4,194,304 and wraps around when it overflows |
D1 |
Store Velocity Data |
D0 |
Store Angle Data |
|
Note
|
Each data format (D0-D2) requires one word of storage from the FIFO buffer. For example: If D0, D1 and D2 are set (0x07) and the FIFO Buffer Size register is set to 1, a FIFO write will only put the Angle data to the FIFO memory. If the FIFO Buffer Size is set to 10, it will store 4 Angle values, 3 Velocity values & 3 timestamp values. Data will be stored in the order of Angle, Velocity then timestamp. Since the maximum physical size of FIFO is 4,194,304 for each channel, the value in the FIFO Buffer Size register could cause an overflow to the FIFO Word Count register. When an overflow occurs, any data not placed in the FIFO will be lost. |
FIFO Sample Rate
Function: The FIFO Sample Rate register sets the sampling rate for FIFO data collection for each channel.
Type: unsigned binary word (32-bit)
Data Range: 1 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 1
Operational Settings: Sample rate is based on the product of 4.096 µsec x the integer set in the register. For example: if the rate is set to 2, the FIFO buffer sample rate will be 4.096 µsec x 2 = 8.192 µsec
FIFO Sample Delay
Function: The FIFO Sample Delay register sets the number of delay samples before the actual FIFO data collection begins.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: The data collected during the delay period will be discarded.
|
Note
|
If timestamp is included as part of the FIFO data, it will begin as soon as the trigger is initiated. For example, if the FIFO Buffer Size register is set to 10, FIFO Sample Delay is set to 7, FIFO Sample Rate is at 1, and the Angle is also selected to be stored, the data written into the FIFO would be <angle>,8,<angle>,9,<angle>,10,< angle >,11,< angle >,12. |
FIFO Clear
Function: The FIFO Clear register clears FIFO data and sets the FIFO Word Count register to zero.
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: W
Initialized Value: N/A
Operational Settings: Write a '1' to this register to reset the FIFO Word Count register to zero and clear the FIFO of any data in the buffer. After writing a'1' to the FIFO Clear register, the FIFO Buffer will only stay empty if all data has been sent (DONE bit set in the FIFO Status register). If data is still in the process of being written to the FIFO, any current data will be cleared, but the FIFO will continue to fill with new data until the number of samples sent equals the number of samples that was set in the FIFO Buffer Size register.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
FIFO Trigger Control
Function: Sets the FIFO Buffer Triggering options. FIFO can be started/triggered by different sources.
Type: unsigned binary word (32-bit)
Data Range: See tables
Read/Write: R/W
Initialized Value: 2 (Software Trigger, Trigger Disabled)
Operational Settings: To Enable triggering, set D5 to “1”. When set up for software triggering, write a “1” to the FIFO Software Trigger register to start the transfer of data to the FIFO. If in external mode and Positive slope is set (D4 = “0”), a rising edge of the external trigger input will start the transfer of data to the FIFO. If in external mode and Negative slope is selected (D4 = “1”), a falling edge of the external trigger input will start the transfer of data to the FIFO.
|
Note
|
Disabling the trigger while data is being transferred, does NOT stop the data from being written to the FIFO. |
FIFO Trigger Control Description |
|
D31:D7 |
Reserved - Set to 0. |
D6 |
Enable Trigger Always (Contact Factory) |
D5 |
Trigger Enable |
D4 |
Trigger Slope (0 = Positive, 1 = Negative) |
D3:D2 |
Reserved - Set to 0. |
D1:D0 |
0:0 - External Trigger 0:1 - N/A 1:0 - Software Trigger 1:1 - N/A |
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D |
D |
D |
0 |
0 |
D |
D |
FIFO Software Trigger
Function: Software trigger is used to kick start the FIFO buffer and the collection of data.
Type: unsigned binary word (32-bit)
Data Range: 0 or 1
Read/Write: W
Initialized Value: 0 (Not Triggered)
Operational Settings: To use this operation, the FIFO Trigger Control register must be set up as software trigger (D1 = '1', D0 = '0') and Trigger Enable is enabled (D5 = '1'). Write a 1 to this register to trigger FIFO collection for all channels. This register will automatically be cleared.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Engineering Scaling Conversion Registers
The SD/RD Module Threshold and Measurement registers can be programmed to be utilized as IEEE-754 single-precision floating-point values or as 32-bit integer values.
Enable Floating Point Mode
Function: Sets all channels for floating point mode or integer mode.
Type: unsigned binary word (32-bit)
Data Range: 0 or 1
Read/Write: R/W
Initialized Value: 0 (Integer mode)
Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Floating Point Offset
Function: Sets the floating-point offset to add to data. There are separate floating-point offset registers for Angle and Velocity for each channel.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: N/A*
Read/Write: R/W
Initialized Value: 0.0
Operational Settings: Writing a value to one of these registers will add to the Angle or Velocity based on which register is chosen (when floating point mode is enabled). For example, if the angle is currently at 10.0 degrees, the angle floating-point offset register is at 0.000, and floating-point mode is enabled, writing a 2.00 to the angle floating-point offset register will result in the angle reading 12.0 degrees. If the value written is -1.7, then the angle will be at 8.30 degrees.
*Data range is any acceptable 32-bit IEEE-754 value. Usage is application dependent - see examples within this document.
Floating Point Scale
Function: Sets the floating-point scale to modify the data. There are separate floating-point scale registers for angle and velocity for each channel.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: NA*
Read/Write: R/W
Initialized Value: 1
Operational Settings: Writing a value to one of these registers will multiply the angle or velocity value by the register value which register is chosen (when floating-point mode is enabled). For example, if the angle is currently at 10.0 degrees, the angle floating-point scale register is at 2.000, and floating-point mode is enabled, will result in the angle reading 20.0 degrees.
*Data range is any acceptable 32-bit IEEE-754 value. Usage is application dependent - see examples within this document.
Floating Point State
Function: Indicates the state of the mode selected (Integer or Floating Point).
Type: unsigned binary word (32-bit)
Data Range: 0 or 1
Read/Write: R
Initialized Value: 0
Operational Settings: Indicates whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Module Common Registers
Refer to “Module Common Registers Module Manual” for the register descriptions.
Status and Interrupts Registers
The SD/RD Modules provide status registers for BIT, Signal Fault Low, Signal Fault High, Reference Fault Low, Reference Fault High, Delta Angle, FIFO and Open Detect.
Channel Status Enable
Function: Determines whether to update the Latched and Real-Time status states for the channels. The default is channel status enable off (no failure).
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 - 0x0000 000F
Read/Write: R/W
Initialized Value: 0x0000 0000
Operational Settings: When the bit corresponding to a given channel in the Channel Status Enable register is enabled (1), it will allow the statuses for that channel to be updated. When the bit corresponding to a given channel is disabled (0), the statuses for that channel will be masked and reported as “0” or “no failure”.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
BIT Status
There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
BIT Dynamic Status |
|||||||||||||||
BIT Latched Status |
|||||||||||||||
BIT Interrupt Enable |
|||||||||||||||
BIT Set Edge/Level Interrupt |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s BIT error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Signal Fault Low Status
There are four registers associated with the Signal Fault Low Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Signal Fault Low Dynamic Status |
|||||||||||||||
Signal Fault Low Latched Status |
|||||||||||||||
Signal Fault Low Interrupt Enable |
|||||||||||||||
Signal Fault Low Set Edge/Level Interrupt |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Signal Fault Low error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Signal Fault High Status
There are four registers associated with the Signal Fault High Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Signal Fault High Dynamic Status |
|||||||||||||||
Signal Fault High Latched Status |
|||||||||||||||
Signal Fault High Interrupt Enable |
|||||||||||||||
Signal Fault High Set Edge/Level Interrupt |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Signal Fault High error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Reference Fault Low Status
There are four registers associated with the Reference Fault Low Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Reference Fault Low Dynamic Status |
|||||||||||||||
Reference Fault Low Latched Status |
|||||||||||||||
Reference Fault Low Interrupt Enable |
|||||||||||||||
Reference Fault Low Set Edge/Level Interrupt |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Reference Fault Low error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Reference Fault High Status
There are four registers associated with the Reference Fault High Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Reference Fault High Dynamic Status |
|||||||||||||||
Reference Fault High Latched Status |
|||||||||||||||
Reference Fault High Interrupt Enable |
|||||||||||||||
Reference Fault High Set Edge/Level Interrupt |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Reference Fault High error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Lock Loss Status
There are four registers associated with the Lock Loss Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Lock Loss Dynamic Status |
|||||||||||||||
Lock Loss Latched Status |
|||||||||||||||
Lock Loss Interrupt Enable |
|||||||||||||||
Lock Loss Set Edge/Level Interrupt |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: When two Synchros are geared to each other to achieve higher accuracy, either electrically or mechanically, the misalignment of the Coarse and Fine Synchros must not exceed 90°/gear ratio or the digital angle output may not be valid and this register will indicate a fault.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Delta Angle Status
There are four registers associated with the Delta Angle Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Delta Angle Dynamic Status |
|||||||||||||||
Delta Angle Latched Status |
|||||||||||||||
Delta Angle Interrupt Enable |
|||||||||||||||
Delta Angle Set Edge/Level Interrupt |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Delta Angle change.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
FIFO Status
There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0-D6 is used to show the different conditions of the buffer.
Bit |
Description |
Configurable? |
D0 |
Empty; 1 when FIFO Count = 0 |
No |
D1 |
Almost Empty; 1 when FIFO Count ⇐ “FIFO Almost Empty” register |
Yes |
D2 |
Low Watermark; 1 when FIFO Count ⇐ “FIFO Low Watermark” register |
Yes |
D3 |
High Watermark; 1 when FIFO Count >= “FIFO High Watermark” register |
Yes |
D4 |
Almost Full; 1 when FIFO Count >= “FIFO Almost Full” register |
Yes |
D5 |
Full; 1 when FIFO Count = 4 Meg (0x0040 0000) |
No |
D6 |
Sample Done; 1 when all data has been sent to the FIFO |
No |
FIFO Dynamic Status |
|||||||||||||||
FIFO Latched Status |
|||||||||||||||
FIFO Interrupt Enable |
|||||||||||||||
FIFO Set Edge/Level Interrupt |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D |
D |
D |
D |
D |
D |
Function: Sets the corresponding bit associated with the FIFO status type; there are separate registers for each channel.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0000 007F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
|
Note
|
Shown below is an example of interrupts generated for the High Watermark. As shown, the interrupt is generated as the FIFO count crosses the High Watermark. The interrupt will not be generated a second time until the count goes below the watermark and then above it again. |
|
Note
|
The FIFO Latched Status register must be cleared for a 2nd interrupt to occur. |
Open Detect Status
There are four registers associated with the Open Detect Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Open Detect Status Dynamic Status |
|||||||||||||||
Open Detect Status Latched Status |
|||||||||||||||
Open Detect Status Interrupt Enable |
|||||||||||||||
Open Detect Status Set Edge/Level Interrupt |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Open Detect error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Summary Status
There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Summary Status Dynamic Status |
|||||||||||||||
Summary Status Latched Status |
|||||||||||||||
Summary Status Interrupt Enable |
|||||||||||||||
Summary Status Set Edge/Level Interrupt |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Indicates a summary of all failures per channel (BIT, Signal Fault Low, Signal Fault High, Reference Fault Low, Reference Fault High and Open Detect).
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value: 0
Interrupt Vector and Steering
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When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
|
Note
|
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map). |
Interrupt Vector
Function: Set an identifier for the interrupt.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function: Sets where to direct the interrupt.
Type: unsigned binary word (32-bit)
Data Range: See table Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME |
1 |
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) |
2 |
Direct Interrupt to PCIe Bus |
5 |
Direct Interrupt to cPCI Bus |
6 |
FUNCTION REGISTER MAP
Key:
Bold Italic = Configuration/Control
Bold Underline = Measurement/Status
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a '1' to a bit set to '1' will set the bit to '0').
**Data is available in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode.
~ Data is always in Floating Point.
SD/RD Measurement Registers
0x1000 |
Angle Data Ch 1** |
R |
0x1050 |
Angle Data Ch 2** |
R |
0x10A0 |
Angle Data Ch 3** |
R |
0x10F0 |
Angle Data Ch 4** |
R |
0x1004 |
Velocity Ch 1** |
R |
0x1054 |
Velocity Ch 2** |
R |
0x10A4 |
Velocity Ch 3** |
R |
0x10F4 |
Velocity Ch 4** |
R |
0x1040 |
Sine RMS Ch 1~ |
R |
0x1090 |
Sine RMS Ch 2~ |
R |
0x10E0 |
Sine RMS Ch 3~ |
R |
0x1130 |
Sine RMS Ch 4~ |
R |
0x1044 |
Cosine RMS Ch 1~ |
R |
0x1094 |
Cosine RMS Ch 2~ |
R |
0x10E4 |
Cosine RMS Ch 3~ |
R |
0x1134 |
Cosine RMS Ch 4~ |
R |
0x1048 |
Sine+Cosine Ch 1~ |
R |
0x1098 |
Sine+Cosine Ch 2~ |
R |
0x10E8 |
Sine+Cosine Ch 3~ |
R |
0x1138 |
Sine+Cosine Ch 4~ |
R |
0x1024 |
Measured Reference (RMS) Ch 1** |
R |
0x1074 |
Measured Reference (RMS) Ch 2** |
R |
0x10C4 |
Measured Reference (RMS) Ch 3** |
R |
0x1114 |
Measured Reference (RMS) Ch 4** |
R |
0x1028 |
Measured Signal (RMS) Ch 1** |
R |
0x1078 |
Measured Signal (RMS) Ch 2** |
R |
0x10C8 |
Measured Signal (RMS) Ch 3** |
R |
0x1118 |
Measured Signal (RMS) Ch 4** |
R |
0x102C |
Measured Frequency (Hz) Ch 1** |
R |
0x107C |
Measured Frequency (Hz) Ch 2** |
R |
0x10CC |
Measured Frequency (Hz) Ch 3** |
R |
0x111C |
Measured Frequency (Hz) Ch 4** |
R |
0x1070 |
Combined Angle Ch 1-2** |
R |
0x1110 |
Combined Angle Ch 3-4** |
R |
0x11A0 |
Sine Detect Value Ch 1~ |
R |
0x11A8 |
Sine Detect Value Ch 2~ |
R |
0x11B0 |
Sine Detect Value Ch 3~ |
R |
0x11B8 |
Sine Detect Value Ch 4~ |
R |
0x11A4 |
Cosine Detect Value Ch 1~ |
R |
0x11AC |
Cosine Detect Value Ch 2~ |
R |
0x11B4 |
Cosine Detect Value Ch 3~ |
R |
0x11BC |
Cosine Detect Value Ch 4~ |
R |
SD/RD Control Registers
0x1038 |
Mode Select Ch 1 |
R/W |
0x1088 |
Mode Select Ch 2 |
R/W |
0x10D8 |
Mode Select Ch 3 |
R/W |
0x1128 |
Mode Select Ch 4 |
R/W |
0x1064 |
Multi-Speed Ratio Ch 1-2** |
R/W |
0x1104 |
Multi-Speed Ratio Ch 3-4** |
R/W |
0x1010 |
Bandwidth Select Ch 1 |
R/W |
0x1060 |
Bandwidth Select Ch 2 |
R/W |
0x10B0 |
Bandwidth Select Ch 3 |
R/W |
0x1100 |
Bandwidth Select Ch 4 |
R/W |
0x100C |
Bandwidth (Hz) Ch 1 |
R/W |
0x105C |
Bandwidth (Hz) Ch 2 |
R/W |
0x10AC |
Bandwidth (Hz) Ch 3 |
R/W |
0x10FC |
Bandwidth (Hz) Ch 4 |
R/W |
0x1018 |
Delta Angle Ch 1** |
R/W |
0x1068 |
Delta Angle Ch 2** |
R/W |
0x10B8 |
Delta Angle Ch 3** |
R/W |
0x1108 |
Delta Angle Ch 4** |
R/W |
0x101C |
Initiate Delta Angle Ch 1 |
W |
0x106C |
Initiate Delta Ch 2 |
W |
0x10BC |
Initiate Delta Ch 3 |
W |
0x110C |
Initiate Delta Angle Ch 4 |
W |
0x11E0 |
Track / Hold |
R/W |
0x104C |
Inverse Signal Control Ch 1 |
R/W |
0x109C |
Inverse Signal Control Ch 2 |
R/W |
0x10EC |
Inverse Signal Control Ch 3 |
R/W |
0x113C |
Inverse Signal Control Ch 4 |
R/W |
Threshold Programming Registers
0x1030 |
Signal Fault Low Threshold Ch 1** |
R/W |
0x1080 |
Signal Fault Low Threshold Ch 2** |
R/W |
0x10D0 |
Signal Fault Low Threshold Ch 3** |
R/W |
0x1120 |
Signal Fault Low Threshold Ch 4** |
R/W |
0x1160 |
Signal Fault High Threshold Ch 1** |
R/W |
0x1164 |
Signal Fault High Threshold Ch 2** |
R/W |
0x1168 |
Signal Fault High Threshold Ch 3** |
R/W |
0x116C |
Signal Fault High Threshold Ch 4** |
R/W |
0x1034 |
Reference Fault Low Threshold Ch 1** |
R/W |
0x1084 |
Reference Fault Low Threshold Ch 2** |
R/W |
0x10D4 |
Reference Fault Low Threshold Ch 3** |
R/W |
0x1124 |
Reference Fault Low Threshold Ch 4** |
R/W |
0x1170 |
Reference Fault High Threshold Ch 1** |
R/W |
0x1174 |
Reference Fault High Threshold Ch 2** |
R/W |
0x1178 |
Reference Fault High Threshold Ch 3** |
R/W |
0x117C |
Reference Fault High Threshold Ch 4** |
R/W |
0x1180 |
Open Detect Threshold Ch 1 |
R/W |
0x1188 |
Open Detect Threshold Ch 2 |
R/W |
0x1190 |
Open Detect Threshold Ch 3 |
R/W |
0x1198 |
Open Detect Threshold Ch 4 |
R/W |
FIFO Registers
0x1200 |
FIFO Buffer Data Ch 1** |
R |
0x1240 |
FIFO Buffer Data Ch 2** |
R |
0x1280 |
FIFO Buffer Data Ch 3** |
R |
0x12C0 |
FIFO Buffer Data Ch 4** |
R |
0x1204 |
FIFO Word Count Ch 1 |
R |
0x1244 |
FIFO Word Count Ch 2 |
R |
0x1284 |
FIFO Word Count Ch 3 |
R |
0x12C4 |
FIFO Word Count Ch 4 |
R |
0x121C |
FIFO Sample Rate Ch 1 |
R/W |
0x125C |
FIFO Sample Rate Ch 2 |
R/W |
0x129C |
FIFO Sample Rate Ch 3 |
R/W |
0x12DC |
FIFO Sample Rate Ch 4 |
R/W |
0x1214 |
FIFO Sample Delay Ch 1 |
R/W |
0x1254 |
FIFO Sample Delay Ch 2 |
R/W |
0x1294 |
FIFO Sample Delay Ch 3 |
R/W |
0x12D4 |
FIFO Sample Delay Ch 4 |
R/W |
0x1224 |
FIFO Buffer Control Ch 1 |
R/W |
0x1264 |
FIFO Buffer Control Ch 2 |
R/W |
0x12A4 |
FIFO Buffer Control Ch 3 |
R/W |
0x12E4 |
FIFO Buffer Control Ch 4 |
R/W |
0x1228 |
FIFO Trigger Control Ch 1 |
R/W |
0x1268 |
FIFO Trigger Control Ch 2 |
R/W |
0x12A8 |
FIFO Trigger Control Ch 3 |
R/W |
0x12E8 |
FIFO Trigger Control Ch 4 |
R/W |
0x1220 |
FIFO Clear Ch 1 |
W |
0x1260 |
FIFO Clear Ch 2 |
W |
0x12A0 |
FIFO Clear Ch 3 |
W |
0x12E0 |
FIFO Clear Ch 4 |
W |
0x1300 |
FIFO Software Trigger |
W |
FIFO Thresholds
0x1210 |
FIFO Low Watermark Ch 1 |
R/W |
0x1250 |
FIFO Low Watermark Ch 2 |
R/W |
0x1290 |
FIFO Low Watermark Ch 3 |
R/W |
0x12D0 |
FIFO Low Watermark Ch 4 |
R/W |
0x120C |
FIFO High Watermark Ch 1 |
R/W |
0x124C |
FIFO High Watermark Ch 2 |
R/W |
0x128C |
FIFO High Watermark Ch 3 |
R/W |
0x12CC |
FIFO High Watermark Ch 4 |
R/W |
0x1230 |
FIFO Almost Empty Ch 1 |
R/W |
0x1270 |
FIFO Almost Empty Ch 2 |
R/W |
0x12B0 |
FIFO Almost Empty Ch 3 |
R/W |
0x12F0 |
FIFO Almost Empty Ch 4 |
R/W |
0x122C |
FIFO Almost Full Ch 1 |
R/W |
0x126C |
FIFO Almost Full Ch 2 |
R/W |
0x12AC |
FIFO Almost Full Ch 3 |
R/W |
0x12EC |
FIFO Almost Full Ch 4 |
R/W |
0x1218 |
FIFO Buffer Size Ch 1 |
R/W |
0x1258 |
FIFO Buffer Size Ch 2 |
R/W |
0x1298 |
FIFO Buffer Size Ch 3 |
R/W |
0x12D8 |
FIFO Buffer Size Ch 4 |
R/W |
Engineering Scaling Conversion Registers
0x02B4 |
Enable Floating Point Mode |
R/W |
0x0264 |
Floating Point State |
R |
0x1400 |
Angle Floating Point Scale Ch 1 |
R/W |
0x1404 |
Angle Floating Point Scale Ch 2 |
R/W |
0x1408 |
Angle Floating Point Scale Ch 3 |
R/W |
0x140C |
Angle Floating Point Scale Ch 4 |
R/W |
0x1410 |
Angle Floating Point Offset Ch 1 |
R/W |
0x1414 |
Angle Floating Point Offset Ch 2 |
R/W |
0x1418 |
Angle Floating Point Offset Ch 3 |
R/W |
0x141C |
Angle Floating Point Offset Ch 4 |
R/W |
0x1420 |
Velocity Floating Point Scale Ch 1 |
R/W |
0x1424 |
Velocity Floating Point Scale Ch 2 |
R/W |
0x1428 |
Velocity Floating Point Scale Ch 3 |
R/W |
0x142C |
Velocity Floating Point Scale Ch 4 |
R/W |
0x1430 |
Velocity Floating Point Offset Ch 1 |
R/W |
0x1434 |
Velocity Floating Point Offset Ch 2 |
R/W |
0x1438 |
Velocity Floating Point Offset Ch 3 |
R/W |
0x143C |
Velocity Floating Point Offset Ch 4 |
R/W |
Module Common Registers
Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map
SD Status Registers
0x02B0 |
Channel Status Enable |
R/W |
BIT Registers
BIT
0x0800 |
Dynamic Status |
R |
0x0804 |
Latched Status* |
R/W |
0x0808 |
Interrupt Enable |
R/W |
0x080C |
Set Edge/Level Interrupt |
R/W |
0x0294 |
UBIT Test Angle** |
R/W |
0x0248 |
Test Enabled |
R/W |
0x024C |
Test CBIT Verify |
R/W |
0x1330 |
BIT Error Limit Ch 1 |
R/W |
0x1334 |
BIT Error Limit Ch 2 |
R/W |
0x1338 |
BIT Error Limit Ch 3 |
R/W |
0x133C |
BIT Error Limit Ch 4 |
R/W |
0x02AC |
Power-on BIT Complete++ |
R |
++After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.
Status Registers
Signal Fault Low
0x0810 |
Dynamic Status |
R |
0x0814 |
Latched Status* |
R/W |
0x0818 |
Interrupt Enable |
R/W |
0x081C |
Set Edge/Level Interrupt |
R/W |
Reference Fault Low
0x0820 |
Dynamic Status |
R |
0x0824 |
Latched Status* |
R/W |
0x0828 |
Interrupt Enable |
R/W |
0x082C |
Set Edge/Level Interrupt |
R/W |
Signal Fault High
0x08B0 |
Dynamic Status |
R |
0x08B4 |
Latched Status* |
R/W |
0x08B8 |
Interrupt Enable |
R/W |
0x08BC |
Set Edge/Level Interrupt |
R/W |
Reference Fault High
0x08C0 |
Dynamic Status |
R |
0x08C4 |
Latched Status* |
R/W |
0x08C8 |
Interrupt Enable |
R/W |
0x08CC |
Set Edge/Level Interrupt |
R/W |
Lock Loss
0x0830 |
Dynamic Status |
R |
0x0834 |
Latched Status* |
R/W |
0x0838 |
Interrupt Enable |
R/W |
0x083C |
Set Edge/Level Interrupt |
R/W |
Delta Angle
0x0840 |
Dynamic Status |
R |
0x0844 |
Latched Status* |
R/W |
0x0848 |
Interrupt Enable |
R/W |
0x084C |
Set Edge/Level Interrupt |
R/W |
Open Detect
0x0890 |
Dynamic Status |
R |
0x0894 |
Latched Status* |
R/W |
0x0898 |
Interrupt Enable |
R/W |
0x089C |
Set Edge/Level Interrupt |
R/W |
Summary
0x09A0 |
Dynamic Status |
R |
0x09A4 |
Latched Status* |
R/W |
0x09A8 |
Interrupt Enable |
R/W |
0x09AC |
Set Edge/Level Interrupt |
R/W |
Channel 1 FIFO Status
0x0850 |
Dynamic Status |
R |
0x0854 |
Latched Status* |
R/W |
0x0858 |
Interrupt Enable |
R/W |
0x085C |
Set Edge/Level Interrupt |
R/W |
Channel 2 FIFO Status
0x0860 |
Dynamic Status |
R |
0x0864 |
Latched Status* |
R/W |
0x0868 |
Interrupt Enable |
R/W |
0x086C |
Set Edge/Level Interrupt |
R/W |
Channel 3 FIFO Status
0x0870 |
Dynamic Status |
R |
0x0874 |
Latched Status* |
R/W |
0x0878 |
Interrupt Enable |
R/W |
0x087C |
Set Edge/Level Interrupt |
R/W |
Channel 4 FIFO Status
0x0880 |
Dynamic Status |
R |
0x0884 |
Latched Status* |
R/W |
0x0888 |
Interrupt Enable |
R/W |
0x088C |
Set Edge/Level Interrupt |
R/W |
Interrupt Registers
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.
0x0500 |
Module 1 Interrupt Vector 1 - BIT |
R/W |
0x0600 |
Module 1 Interrupt Steering 1 - BIT |
R/W |
|
0x0504 |
Module 1 Interrupt Vector 2 - Signal Fault Low |
R/W |
0x0604 |
Module 1 Interrupt Steering 2 - Signal Fault Low |
R/W |
|
0x0508 |
Module 1 Interrupt Vector 3 - Reference Fault Low |
R/W |
0x0608 |
Module 1 Interrupt Steering 3 - Reference Fault Low |
R/W |
|
0x050C |
Module 1 Interrupt Vector 4 - Lock Loss |
R/W |
0x060C |
Module 1 Interrupt Steering 4 - Lock Loss |
R/W |
|
0x0510 |
Module 1 Interrupt Vector 5 - Delta Angle |
R/W |
0x0610 |
Module 1 Interrupt Steering 5 - Delta Angle |
R/W |
|
0x0514 |
Module 1 Interrupt Vector 6 - FIFO Ch 1 |
R/W |
0x0614 |
Module 1 Interrupt Steering 6 - FIFO Ch 1 |
R/W |
|
0x0518 |
Module 1 Interrupt Vector 7 - FIFO Ch 2 |
R/W |
0x0618 |
Module 1 Interrupt Steering 7 - FIFO Ch 2 |
R/W |
|
0x051C |
Module 1 Interrupt Vector 8 - FIFO Ch 3 |
R/W |
0x061C |
Module 1 Interrupt Steering 8 - FIFO Ch 3 |
R/W |
|
0x0520 |
Module 1 Interrupt Vector 9 - FIFO Ch 4 |
R/W |
0x0620 |
Module 1 Interrupt Steering 9 - FIFO Ch 4 |
R/W |
|
0x0524 |
Module 1 Interrupt Vector 10 - Open Detect |
R/W |
0x0624 |
Module 1 Interrupt Steering 10 - Open Detect |
R/W |
|
0x0528 |
Module 1 Interrupt Vector 11 - Reserved |
R/W |
0x0628 |
Module 1 Interrupt Steering 11 - Reserved |
R/W |
|
0x052C |
Module 1 Interrupt Vector 12 - Signal Fault High |
R/W |
0x062C |
Module 1 Interrupt Steering 12 - Signal Fault High |
R/W |
|
0x0530 |
Module 1 Interrupt Vector 13 - Reference Fault High |
R/W |
0x0630 |
Module 1 Interrupt Steering 13 - Reference Fault High |
R/W |
|
0x0534 to 0x0564 |
Module 1 Interrupt Vector 14-26 - Reserved |
R/W |
0x0634 to 0x0664 |
Module 1 Interrupt Steering 14-26 - Reserved |
R/W |
|
0x0568 |
Module 1 Interrupt Vector 27 - Summary |
R/W |
0x0668 |
Module 1 Interrupt Steering 27 - Summary |
R/W |
|
0x056C to 0x057C |
Module 1 Interrupt Vector 28-32 - Reserved |
R/W |
0x066C to 0x067C |
Module 1 Interrupt Steering 28-32 - Reserved |
R/W |
0x0700 |
Module 2 Interrupt Vector 1 - BIT |
R/W |
0x0800 |
Module 2 Interrupt Steering 1 - BIT |
R/W |
|
0x0704 |
Module 2 Interrupt Vector 2 - Signal Fault Low |
R/W |
0x0804 |
Module 2 Interrupt Steering 2 - Signal Fault Low |
R/W |
|
0x0708 |
Module 2 Interrupt Vector 3 - Reference Fault Low |
R/W |
0x0808 |
Module 2 Interrupt Steering 3 - Reference Fault Low |
R/W |
|
0x070C |
Module 2 Interrupt Vector 4 - Lock Loss |
R/W |
0x080C |
Module 2 Interrupt Steering 4 - Lock Loss |
R/W |
|
0x0710 |
Module 2 Interrupt Vector 5 - Delta Angle |
R/W |
0x0810 |
Module 2 Interrupt Steering 5 - Delta Angle |
R/W |
|
0x0714 |
Module 2 Interrupt Vector 6 - FIFO Ch 1 |
R/W |
0x0814 |
Module 2 Interrupt Steering 6 - FIFO Ch 1 |
R/W |
|
0x0718 |
Module 2 Interrupt Vector 7 - FIFO Ch 2 |
R/W |
0x0818 |
Module 2 Interrupt Steering 7 - FIFO Ch 2 |
R/W |
|
0x071C |
Module 2 Interrupt Vector 8 - FIFO Ch 3 |
R/W |
0x081C |
Module 2 Interrupt Steering 8 - FIFO Ch 3 |
R/W |
|
0x0720 |
Module 2 Interrupt Vector 9 - FIFO Ch 4 |
R/W |
0x0820 |
Module 2 Interrupt Steering 9 - FIFO Ch 4 |
R/W |
|
0x0724 |
Module 2 Interrupt Vector 10 - Open Detect |
R/W |
0x0824 |
Module 2 Interrupt Steering 10 - Open Detect |
R/W |
|
0x0728 |
Module 2 Interrupt Vector 11 - Reserved |
R/W |
0x0828 |
Module 2 Interrupt Steering 11 - Reserved |
R/W |
|
0x072C |
Module 2 Interrupt Vector 12 - Signal Fault High |
R/W |
0x082C |
Module 2 Interrupt Steering 12 - Signal Fault High |
R/W |
|
0x0730 |
Module 2 Interrupt Vector 13 - Reference Fault High |
R/W |
0x0830 |
Module 2 Interrupt Steering 13 - Reference Fault High |
R/W |
|
0x0734 to 0x0764 |
Module 2 Interrupt Vector 14-26 - Reserved |
R/W |
0x0834 to 0x0864 |
Module 2 Interrupt Steering 14-26 - Reserved |
R/W |
|
0x0768 |
Module 2 Interrupt Vector 27 - Summary |
R/W |
0x0868 |
Module 2 Interrupt Steering 27 - Summary |
R/W |
|
0x076C to 0x077C |
Module 2 Interrupt Vector 28-32 - Reserved |
R/W |
0x086C to 0x087C |
Module 2 Interrupt Steering 28-32 - Reserved |
R/W |
0x0900 |
Module 3 Interrupt Vector 1 - BIT |
R/W |
0x0A00 |
Module 3 Interrupt Steering 1 - BIT |
R/W |
|
0x0904 |
Module 3 Interrupt Vector 2 - Signal Fault Low |
R/W |
0x0A04 |
Module 3 Interrupt Steering 2 - Signal Fault Low |
R/W |
|
0x0908 |
Module 3 Interrupt Vector 3 - Reference Fault Low |
R/W |
0x0A08 |
Module 3 Interrupt Steering 3 - Reference Fault Low |
R/W |
|
0x090C |
Module 3 Interrupt Vector 4 - Lock Loss |
R/W |
0x0A0C |
Module 3 Interrupt Steering 4 - Lock Loss |
R/W |
|
0x0910 |
Module 3 Interrupt Vector 5 - Delta Angle |
R/W |
0x0A10 |
Module 3 Interrupt Steering 5 - Delta Angle |
R/W |
|
0x0914 |
Module 3 Interrupt Vector 6 - FIFO Ch 1 |
R/W |
0x0A14 |
Module 3 Interrupt Steering 6 - FIFO Ch 1 |
R/W |
|
0x0918 |
Module 3 Interrupt Vector 7 - FIFO Ch 2 |
R/W |
0x0A18 |
Module 3 Interrupt Steering 7 - FIFO Ch 2 |
R/W |
|
0x091C |
Module 3 Interrupt Vector 8 - FIFO Ch 3 |
R/W |
0x0A1C |
Module 3 Interrupt Steering 8 - FIFO Ch 3 |
R/W |
|
0x0920 |
Module 3 Interrupt Vector 9 - FIFO Ch 4 |
R/W |
0x0A20 |
Module 3 Interrupt Steering 9 - FIFO Ch 4 |
R/W |
|
0x0924 |
Module 3 Interrupt Vector 10 - Open Detect |
R/W |
0x0A24 |
Module 3 Interrupt Steering 10 - Open Detect |
R/W |
|
0x0928 |
Module 3 Interrupt Vector 11 - Reserved |
R/W |
0x0A28 |
Module 3 Interrupt Steering 11 - Reserved |
R/W |
|
0x092C |
Module 3 Interrupt Vector 12 - Signal Fault High |
R/W |
0x0A2C |
Module 3 Interrupt Steering 12 - Signal Fault High |
R/W |
|
0x0930 |
Module 3 Interrupt Vector 13 - Reference Fault High |
R/W |
0x0A30 |
Module 3 Interrupt Steering 13 - Reference Fault High |
R/W |
|
0x0934 to 0x0964 |
Module 3 Interrupt Vector 14-26 - Reserved |
R/W |
0x0A34 to 0x0A64 |
Module 3 Interrupt Steering 14-26 - Reserved |
R/W |
|
0x0968 |
Module 3 Interrupt Vector 27 - Summary |
R/W |
0x0A68 |
Module 3 Interrupt Steering 27 - Summary |
R/W |
|
0x096C to 0x097C |
Module 3 Interrupt Vector 28-32 - Reserved |
R/W |
0x0A6C to 0x0A7C |
Module 3 Interrupt Steering 28-32 - Reserved |
R/W |
0x0B00 |
Module 4 Interrupt Vector 1 - BIT |
R/W |
0x0C00 |
Module 4 Interrupt Steering 1 - BIT |
R/W |
|
0x0B04 |
Module 4 Interrupt Vector 2 - Signal Fault Low |
R/W |
0x0C04 |
Module 4 Interrupt Steering 2 - Signal Fault Low |
R/W |
|
0x0B08 |
Module 4 Interrupt Vector 3 - Reference Fault Low |
R/W |
0x0C08 |
Module 4 Interrupt Steering 3 - Reference Fault Low |
R/W |
|
0x0B0C |
Module 4 Interrupt Vector 4 - Lock Loss |
R/W |
0x0C0C |
Module 4 Interrupt Steering 4 - Lock Loss |
R/W |
|
0x0B10 |
Module 4 Interrupt Vector 5 - Delta Angle |
R/W |
0x0C10 |
Module 4 Interrupt Steering 5 - Delta Angle |
R/W |
|
0x0B14 |
Module 4 Interrupt Vector 6 - FIFO Ch 1 |
R/W |
0x0C14 |
Module 4 Interrupt Steering 6 - FIFO Ch 1 |
R/W |
|
0x0B18 |
Module 4 Interrupt Vector 7 - FIFO Ch 2 |
R/W |
0x0C18 |
Module 4 Interrupt Steering 7 - FIFO Ch 2 |
R/W |
|
0x0B1C |
Module 4 Interrupt Vector 8 - FIFO Ch 3 |
R/W |
0x0C1C |
Module 4 Interrupt Steering 8 - FIFO Ch 3 |
R/W |
|
0x0B20 |
Module 4 Interrupt Vector 9 - FIFO Ch 4 |
R/W |
0x0C20 |
Module 4 Interrupt Steering 9 - FIFO Ch 4 |
R/W |
|
0x0B24 |
Module 4 Interrupt Vector 10 - Open Detect |
R/W |
0x0C24 |
Module 4 Interrupt Steering 10 - Open Detect |
R/W |
|
0x0B28 |
Module 4 Interrupt Vector 11 - Reserved |
R/W |
0x0C28 |
Module 4 Interrupt Steering 11 - Reserved |
R/W |
|
0x0B2C |
Module 4 Interrupt Vector 12 - Signal Fault High |
R/W |
0x0C2C |
Module 4 Interrupt Steering 12 - Signal Fault High |
R/W |
|
0x0B30 |
Module 4 Interrupt Vector 13 - Reference Fault High |
R/W |
0x0C30 |
Module 4 Interrupt Steering 13 - Reference Fault High |
R/W |
|
0x0B34 to 0x0B64 |
Module 4 Interrupt Vector 14-26 - Reserved |
R/W |
0x0C34 to 0x0C64 |
Module 4 Interrupt Steering 14-26 - Reserved |
R/W |
|
0x0B68 |
Module 4 Interrupt Vector 27 - Summary |
R/W |
0x0C68 |
Module 4 Interrupt Steering 27 - Summary |
R/W |
|
0x0B6C to 0x0B7C |
Module 4 Interrupt Vector 28-32 - Reserved |
R/W |
0x0C6C to 0x0C7C |
Module 4 Interrupt Steering 28-32 - Reserved |
R/W |
0x0D00 |
Module 5 Interrupt Vector 1 - BIT |
R/W |
0x0E00 |
Module 5 Interrupt Steering 1 - BIT |
R/W |
|
0x0D04 |
Module 5 Interrupt Vector 2 - Signal Fault Low |
R/W |
0x0E04 |
Module 5 Interrupt Steering 2 - Signal Fault Low |
R/W |
|
0x0D08 |
Module 5 Interrupt Vector 3 - Reference Fault Low |
R/W |
0x0E08 |
Module 5 Interrupt Steering 3 - Reference Fault Low |
R/W |
|
0x0D0C |
Module 5 Interrupt Vector 4 - Lock Loss |
R/W |
0x0E0C |
Module 5 Interrupt Steering 4 - Lock Loss |
R/W |
|
0x0D10 |
Module 5 Interrupt Vector 5 - Delta Angle |
R/W |
0x0E10 |
Module 5 Interrupt Steering 5 - Delta Angle |
R/W |
|
0x0D14 |
Module 5 Interrupt Vector 6 - FIFO Ch 1 |
R/W |
0x0E14 |
Module 5 Interrupt Steering 6 - FIFO Ch 1 |
R/W |
|
0x0D18 |
Module 5 Interrupt Vector 7 - FIFO Ch 2 |
R/W |
0x0E18 |
Module 5 Interrupt Steering 7 - FIFO Ch 2 |
R/W |
|
0x0D1C |
Module 5 Interrupt Vector 8 - FIFO Ch 3 |
R/W |
0x0E1C |
Module 5 Interrupt Steering 8 - FIFO Ch 3 |
R/W |
|
0x0D20 |
Module 5 Interrupt Vector 9 - FIFO Ch 4 |
R/W |
0x0E20 |
Module 5 Interrupt Steering 9 - FIFO Ch 4 |
R/W |
|
0x0D24 |
Module 5 Interrupt Vector 10 - Open Detect |
R/W |
0x0E24 |
Module 5 Interrupt Steering 10 - Open Detect |
R/W |
|
0x0D28 |
Module 5 Interrupt Vector 11 - Reserved |
R/W |
0x0E28 |
Module 5 Interrupt Steering 11 - Reserved |
R/W |
|
0x0D2C |
Module 5 Interrupt Vector 12 - Signal Fault High |
R/W |
0x0E2C |
Module 5 Interrupt Steering 12 - Signal Fault High |
R/W |
|
0x0D30 |
Module 5 Interrupt Vector 13 - Reference Fault High |
R/W |
0x0E30 |
Module 5 Interrupt Steering 13 - Reference Fault High |
R/W |
|
0x0D34 to 0x0D64 |
Module 5 Interrupt Vector 14-26 - Reserved |
R/W |
0x0E34 to 0x0E64 |
Module 5 Interrupt Steering 14-26 - Reserved |
R/W |
|
0x0D68 |
Module 5 Interrupt Vector 27 - Summary |
R/W |
0x0E68 |
Module 5 Interrupt Steering 27 - Summary |
R/W |
|
0x0D6C to 0x0D7C |
Module 5 Interrupt Vector 28-32 - Reserved |
R/W |
0x0E6C to 0x0E7C |
Module 5 Interrupt Steering 28-32 - Reserved |
R/W |
0x0F00 |
Module 6 Interrupt Vector 1 - BIT |
R/W |
0x1000 |
Module 6 Interrupt Steering 1 - BIT |
R/W |
|
0x0F04 |
Module 6 Interrupt Vector 2 - Signal Fault Low |
R/W |
0x1004 |
Module 6 Interrupt Steering 2 - Signal Fault Low |
R/W |
|
0x0F08 |
Module 6 Interrupt Vector 3 - Reference Fault Low |
R/W |
0x1008 |
Module 6 Interrupt Steering 3 - Reference Fault Low |
R/W |
|
0x0F0C |
Module 6 Interrupt Vector 4 - Lock Loss |
R/W |
0x100C |
Module 6 Interrupt Steering 4 - Lock Loss |
R/W |
|
0x0F10 |
Module 6 Interrupt Vector 5 - Delta Angle |
R/W |
0x1010 |
Module 6 Interrupt Steering 5 - Delta Angle |
R/W |
|
0x0F14 |
Module 6 Interrupt Vector 6 - FIFO Ch 1 |
R/W |
0x1014 |
Module 6 Interrupt Steering 6 - FIFO Ch 1 |
R/W |
|
0x0F18 |
Module 6 Interrupt Vector 7 - FIFO Ch 2 |
R/W |
0x1018 |
Module 6 Interrupt Steering 7 - FIFO Ch 2 |
R/W |
|
0x0F1C |
Module 6 Interrupt Vector 8 - FIFO Ch 3 |
R/W |
0x101C |
Module 6 Interrupt Steering 8 - FIFO Ch 3 |
R/W |
|
0x0F20 |
Module 6 Interrupt Vector 9 - FIFO Ch 4 |
R/W |
0x1020 |
Module 6 Interrupt Steering 9 - FIFO Ch 4 |
R/W |
|
0x0F24 |
Module 6 Interrupt Vector 10 - Open Detect |
R/W |
0x1024 |
Module 6 Interrupt Steering 10 - Open Detect |
R/W |
|
0x0F28 |
Module 6 Interrupt Vector 11 - Reserved |
R/W |
0x1028 |
Module 6 Interrupt Steering 11 - Reserved |
R/W |
|
0x0F2C |
Module 6 Interrupt Vector 12 - Signal Fault High |
R/W |
0x102C |
Module 6 Interrupt Steering 12 - Signal Fault High |
R/W |
|
0x0F30 |
Module 6 Interrupt Vector 13 - Reference Fault High |
R/W |
0x1030 |
Module 6 Interrupt Steering 13 - Reference Fault High |
R/W |
|
0x0F34 to 0x0F64 |
Module 6 Interrupt Vector 14-26 - Reserved |
R/W |
0x1034 to 0x1064 |
Module 6 Interrupt Steering 14-26 - Reserved |
R/W |
|
0x0F68 |
Module 6 Interrupt Vector 27 - Summary |
R/W |
0x1068 |
Module 6 Interrupt Steering 27 - Summary |
R/W |
|
0x0F6C to 0x0F7C |
Module 6 Interrupt Vector 28-32 - Reserved |
R/W |
0x106C to 0x107C |
Module 6 Interrupt Steering 28-32 - Reserved |
R/W |
APPENDIX A: INTEGER/FLOATING POINT MODE PROGRAMMING
Integer Mode Programming
Angle, Velocity, and FIFO Buffer Data Programming
Angle: The value read in the Angle or FIFO Buffer Data (angle data) register, while in Integer Mode, is dependent on an “LSB” value. The LSB value is defined as 360 / 2^32 .
|
Note
|
The per bit angle values in the following table are approximate. |
Angle Data Calculation:
Angle Data Register Value (Decimal Value/Hex Value) |
LSB |
Angle (degrees) |
536870912 (0x2000 0000) |
8.381903e-8 |
536870912 * LSB = 45.0 |
4026531840 (0xF000 0000) |
8.381903e-8 |
4026531840 * LSB = 337.5 |
4194304 (0x0400 0000) |
8.381903e-8 |
4194304 * LSB = 0.3515625 |
Velocity: The value read in the Velocity or FIFO Buffer Data (velocity data) register, while in Integer Mode, has an LSB weight of 0.1 deg/sec.
Velocity Data Calculation:
Velocity Data Register Value (Decimal Value/Hex Value) |
LSB |
Velocity |
218 (0x0000 00DA) |
0.1 |
218 * LSB = 21.8 deg/ sec |
-2 (0xFFFF FFFE) |
0.1 |
-2 * LSB = -0.2 deg/ sec |
50 (0x0000 0032) |
0.1 |
50 * LSB = 5.0 deg/ sec |
FIFO Buffer Data:
|
Note
|
An additional item that can be stored in the FIFO Buffer Data register is a Timestamp. This value will always be represented as an integer even when the Enable Floating Point Mode register is set to “1” (Floating point mode). |
Timestamp value from FIFO Data Buffer:
FIFO Buffer Data Timestamp Value (Decimal Value/Hex Value) |
Value |
77 (0x0000 004D) |
77 |
UBIT Test Programming
The value to set in the UBIT Test Data register, while in Integer Mode, is dependent on an “LSB” value. The LSB value is defined as 360 / 2^32.
|
Note
|
Engineering Scaling Conversions will not be used for Test Angle in UBIT mode. |
Test Angle:
UBIT Test Angle (degrees) |
LSB |
Binary Value Integer Mode |
45.0 |
8.381903e-8 |
45.0 / LSB = 536870912 = 0x2000 0000 |
337.5 |
8.381903e-8 |
337.5 / LSB = 4026531840 = 0xF000 0000 |
0.3515625 |
8.381903e-8 |
0.3515625 / LSB = 4194304 = 0x0040 0000 |
Threshold and Delta Angle Programming
To set the threshold value for Signal and Reference Faults, divide the value desired by the LSB weight (0.01) and write it to the corresponding threshold register.
Signal and Reference Fault Low and High Thresholds:
Example:
You want to be alerted when the reference voltage either drops below 6.00Vrms or exceeds 10.00Vrms. In addition, you also want to be alerted when the signal drops below 1.00Vrms or exceeds 5.00Vrms. Write the following values to the corresponding threshold registers. See table below.
Register |
Value written to the register (Decimal Value/Hex Value) |
LSB |
Voltage(rms |
Reference Fault Low Threshold |
600 (0x0000 0258) |
0.01 |
600 * LSB = 6.00 Vrms |
Reference Fault High Threshold |
1000 (0x0000 03E8) |
0.01 |
1000 * LSB = 10.00 Vrms |
Signal Fault Low Threshold |
100 (0x0000 0064) |
0.01 |
100 * LSB = 1.00 Vrms |
Signal Fault High Threshold |
500 (0x000 001F4) |
0.01 |
500 * LSB = 5.00 Vrms |
Delta Angle:
Example:
To be alerted when the angle changes more than 3 degrees, write the following value to the Delta Angle register. See table below.
|
Note
|
For this detection to function properly, you must set a “trigger” angle by setting the Initiate Delta Angle register. |
Register |
Value written to the register (Decimal Value/Hex Value) |
LSB |
Delta Angle (degrees |
Delta Angle |
64463616 (0x03D7 A300) |
8.381903e-8 |
64463616 * LSB = 5.4032 |
Open Detect Thresholds:
|
Note
|
Open Detect Threshold programming is not valid in integer mode and will be described in the Floating-Point Mode section. |
RMS Voltage Reading
The value read in the Signal and Reference RMS Voltage registers is a 32-bit unsigned value. To calculate the RMS voltage, you must multiply this value by an LSB weight. The LSB = 0.01 (10 mv). For example, if the value read is 2600 (0x0A28), the RMS value will be 26.00Vrms.
Value read from Measured Signal or Measured Reference registers (Decimal Value/Hex Value) |
LSB |
RMS Voltage (Volts) |
2600 (0x0000 0A28) |
0.01 |
26.00 |
1150 (0x0000 047E) |
0.01 |
11.50 |
275 (0x0000 0113) |
0.01 |
2.75 |
Frequency Reading
The value read in the Frequency registers is a 32-bit unsigned value. To calculate the frequency, you must multiply this value by an LSB weight. The LSB = 1 (1Hz). For example, if the value read is 2500 (0x09C4), the frequency value will be 2500Hz.
Value read from Measured Frequency registers (Decimal Value/Hex Value) |
LSB |
Frequency (Hz) |
2500 (0x0000 09C4) |
1.0 |
2500 |
1000 (0x0000 03E8) |
1.0 |
1000 |
400 (0x0000 0190) |
1.0 |
400 |
Floating Point Mode Angle/Velocity Programming
Angle, Velocity, and FIFO Data Buffer Programming
Angle: The value read in the Angle or FIFO Buffer Data (angle data) register, while in Floating Point Mode, is represented in Single Precision Floating Point Value (IEEE-754) format.
Angle Data Register Value Single Precision Floating Point Value (IEEE-754) |
Angle Data (degrees) |
0x41C8 0000 |
25.0 |
0x43B1 8000 |
355.0 |
0x42A3 8000 |
81.75 |
Velocity: The value read in the Velocity or FIFO Buffer Data (velocity data) register, while in Floating Point Mode, is simply the IEEE-754 single precision formatted value.
Velocity Data Register Value Single Precision Floating Point Value (IEEE-754) |
Velocity Data |
0x41AE 6666 |
21.8 deg/sec |
0xBE4C CCCD |
-0.2 deg/sec |
0x40A0 0000 |
5.0 deg/sec |
Timestamp value from FIFO Data Buffer:
|
Note
|
Timestamp is always represented as an Integer and cannot be read as a Floating-Point value. |
UBIT Programming Testing
The value to set in the UBIT Test Data register, while in Floating-Point Mode, is simply the IEEE-754 floating point value for the angle desired.
Test Angle:
UBIT Test Angle (degrees) |
Test Angle Register Value Single Precision Floating Point Value (IEEE-754) |
25.0 |
0x41C8 0000 |
355.0 |
0x43B1 8000 |
81.75 |
0x42A3 8000 |
Threshold and Delta Angle Programming
The value to set in the Threshold registers, while in Floating-Point Mode, is represented in Single Precision Floating Point Value (IEEE-754) format.
Signal and Reference Fault Low and High Thresholds:
Example:
You want to be alerted when the reference voltage either drops below 6.00Vrms or exceeds 10.00Vrms. In addition, you also want to be alerted when the signal drops below 1.00Vrms or exceeds 5.00Vrms. Write the following values to the corresponding threshold registers. See table below.
Register |
Value written to the register Single Precision Floating Point Value (IEEE-754) |
Voltage(rms) |
Reference Fault Low Threshold |
0x40C0 |
0000 6.00 Vrms |
Reference Fault High Threshold |
0x4120 |
0000 10.00 Vrms |
Signal Fault Low Threshold |
0x3F80 |
0000 1.00 Vrms |
Signal Fault High Threshold |
0x40A0 |
0000 5.00 Vrms |
Delta Angle:
Example:
To be alerted when the angle changes more than 3 degrees, write the following value to the Delta Angle register. See table below. Note: For this detection to function properly, you must set a “trigger” angle by setting the Initiate Delta Angle register.
Register |
Value written to the register Single Precision Floating Point Value (IEEE-754) |
Delta Angle (degrees) |
Delta Angle |
0x4040 0000 |
3.00 |
Open Detect Thresholds:
Example:
To be alerted when an OPEN winding occurs.
Register |
Value written to the register Single Precision Floating Point Value (IEEE-754) |
Delta Angle (degrees) |
Open Detect Threshold |
0x455A C000 |
3500 |
RMS Voltage Reading
The value read in the Signal and Reference RMS Voltage registers is in Single Precision Floating Point Value (IEEE-754) format.
Value read from Measured Signal or Measured Reference registers Single Precision Floating Point Value (IEEE-754) |
RMS Voltage (Volts |
0x41D0 0000 |
26.00 |
0x4138 0000 |
11.50 |
0x4030 0000 |
2.75 |
APPENDIX B: REGISTER NAME CHANGES FROM PREVIOUS REVISIONS
This section provides a mapping of the register names used in this document against register names used in previous releases.
Rev C - Register Names |
Rev A - Register Names |
SD/RD Measurement Registers |
|
Angle Data |
Angle/Position Data |
Velocity Data |
Velocity |
Sine RMS |
|
Cosine RMS |
|
Sine+Cosine RMS |
|
Measured Reference (RMS) |
Measured Reference (RMS) |
Measured Signal (RMS) |
Measured Signal (RMS) |
Measured Frequency (Hz) |
Measured Frequency (Hz) |
Combined Angle |
Combined Angle (Ch. 1-2), (Ch. 3-4) |
Sine Detect Value |
|
Cosine Detect Value |
|
SD/RD Control Registers |
|
Mode Select |
Mode Select |
Bandwidth Select |
Bandwidth Select |
Bandwidth (Hz) |
Bandwidth (Hz) |
Multi-speed Ratio |
Ratio (Ch. 1-2), (Ch. 3-4) |
Delta Angle |
Delta Angle |
Initiate Delta Angle |
Init Delta Angle |
Channel Status Enable |
Status Enable |
Track/Hold |
Track/Hold |
Inverse Signal Control |
|
Threshold Programming Registers |
|
Signal Fault Low Threshold |
Signal Loss Threshold |
Signal Fault High Threshold |
|
Reference Fault Low Threshold |
Reference Loss Threshold |
Reference Fault High Threshold |
|
Open Detect Threshold |
|
SD/RD Test Registers |
|
Test Enabled |
Test Enable (D0, D2, D3) |
Test CBIT Verify |
Test D2 Verify |
UBIT Test Position |
Test Angle/Position |
BIT Error Limit |
|
FIFO Registers |
|
FIFO Buffer Data |
FIFO Buffer Data (per channel) |
FIFO Word Count |
FIFO Word Count (per channel) |
FIFO Almost Empty |
|
FIFO Low Watermark |
FIFO Lo Threshold (per channel) |
FIFO High Watermark |
FIFO Hi Threshold (per channel) |
FIFO Almost Full |
|
FIFO Buffer Size |
FIFO Number of Samples (per channel) |
FIFO Buffer Control |
FIFO Data Type (per channel) |
FIFO Sample Rate |
FIFO Sample Rate (per channel) |
FIFO Sample Delay |
FIFO Sample Delay (per channel) |
FIFO Clear |
FIFO Clear (per channel) |
FIFO Trigger Control |
FIFO Trigger Mode (per channel) |
FIFO Software Trigger |
|
Engineering Scaling Conversions Registers |
|
Enable Floating Point Mode |
|
Floating Point Offset |
|
Floating Point Scale |
|
Floating Point State |
|
Status and Interrupt Registers |
|
BIT Dynamic Status |
BIT Dynamic Status |
BIT Latched Status |
BIT Latched Status |
BIT Interrupt Enable |
BIT Interrupt Enable |
BIT Set Edge/Level Interrupt |
BIT Set Edge/Level Interrupt |
Signal Fault Low Dynamic Status |
Signal Loss Dynamic Status) |
Signal Fault Low Latched Status |
Signal Loss Latched Status) |
Signal Fault Low Interrupt Enable |
Signal Loss Interrupt Enable) |
Signal Fault Low Set Edge/Level Interrupt |
*Signal Loss Set Edge/Level )*Interrupt |
Signal Fault High Dynamic Status |
|
Signal Fault High Latched Status |
|
Signal Fault High Interrupt Enable |
|
Signal Fault High Set Edge/Level Interrupt |
|
Reference Fault Low Dynamic Status |
Reference Loss Dynamic Status) |
Reference Fault Low Latched Status |
Reference Loss Latched Status) |
Reference Fault Low Interrupt Enable |
Reference Loss Interrupt Enable) |
Reference Fault Low Set Edge/Level Interrupt |
Reference Loss Set Edge/Level Interrupt) |
Reference Fault High Dynamic Status |
|
Reference Fault High Latched Status |
|
Reference Fault High Interrupt Enable |
|
Reference Fault High Set Edge/Level Interrupt |
|
Lock Loss Dynamic Status |
Lock Loss Dynamic Status |
Lock Loss Latched Status |
Lock Loss Latched Status |
Lock Loss Interrupt Enable |
Lock Loss Interrupt Enable |
Lock Loss Set Edge/Level Interrupt |
Lock Loss Set Edge/Level Interrupt |
Delta Angle Dynamic Status |
Delta Angle Dynamic Status |
Delta Angle Latched Status |
Delta Angle Latched Status |
Delta Angle Interrupt Enable |
Delta Angle Interrupt Enable |
Delta Angle Set Edge/Level Interrupt |
Delta Angle Set Edge/Level Interrupt |
FIFO Dynamic Status |
FIFO Dynamic Status |
FIFO Latched Status |
FIFO Latched Status |
FIFO Interrupt Enable |
FIFO Interrupt Enable |
FIFO Set Edge/Level Interrupt |
FIFO Set Edge/Level Interrupt |
Open Detect Dynamic Status |
|
Open Detect Latched Status |
|
Open Detect Interrupt Enable |
|
Open Detect Set Edge/Level Interrupt |
|
Summary Dynamic Status |
|
Summary Latched Status |
|
Summary Interrupt Enable |
|
Summary Set Edge/Level Interrupt |
|
Interrupt Vector |
|
Interrupt Steering |
|
APPENDIX C: PIN-OUT DETAILS
Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals
Module Signal (Ref Only) |
SD-4Ch (SDx) |
DATIO1 |
S1-CH1 |
DATIO2 |
S3-CH1 |
DATIO3 |
S2-CH1 |
DATIO4 |
S4-CH1 |
DATIO5 |
RHI-CH1 |
DATIO6 |
RLO-CH1 |
DATIO7 |
S1-CH2 |
DATIO8 |
S3-CH2 |
DATIO9 |
S2-CH2 |
DATIO10 |
S4-CH2 |
DATIO11 |
RHI-CH2 |
DATIO12 |
RLO-CH2 |
DATIO13 |
S1-CH3 |
DATIO14 |
S3-CH3 |
DATIO15 |
S2-CH3 |
DATIO16 |
S4-CH3 |
DATIO17 |
RHI-CH3 |
DATIO18 |
RLO-CH3 |
DATIO19 |
S1-CH4 |
DATIO20 |
S3-CH4 |
DATIO21 |
S2-CH4 |
DATIO22 |
S4-CH4 |
DATIO23 |
RHI-CH4 |
DATIO24 |
RLO-CH4 |
DATIO25 |
|
DATIO26 |
|
DATIO27 |
|
DATIO28 |
|
DATIO29 |
|
DATIO30 |
|
DATIO31 |
|
DATIO32 |
|
DATIO33 |
|
DATIO34 |
|
DATIO35 |
|
DATIO36 |
|
DATIO37 |
|
DATIO38 |
|
DATIO39 |
|
DATIO40 |
|
N/A |
STATUS AND INTERRUPTS
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Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.
For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.
Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.
Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).
Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.
Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).
-
Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edgetriggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
-
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Interrupt Trigger Types
In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.
Example 1: Fault detection
This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.
Example 2: Threshold detection
This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.
Dynamic and Latched Status Registers Examples
The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.
Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States
No Clearing of Latched Status |
Clearing of Latched Status (Edge-Triggered) |
Clearing of Latched Status (Level-Triggered) |
||||
Time |
Dynamic Status |
Latched Status |
Action |
Latched Status |
Action |
Latched |
T0 |
0x0 |
0x0 |
Read Latched Register |
0x0 |
Read Latched Register |
0x0 |
T1 |
0x1 |
0x1 |
Read Latched Register |
0x1 |
0x1 |
|
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
|||||
0x0 |
0x1 |
|||||
T2 |
0x0 |
0x1 |
Read Latched Register |
0x0 |
Read Latched Register |
0x1 |
Write 0x1 to Latched Register |
||||||
0x0 |
||||||
T3 |
0x2 |
0x3 |
Read Latched Register |
0x2 |
Read Latched Register |
0x2 |
Write 0x2 to Latched Register |
Write 0x2 to Latched Register |
|||||
0x0 |
0x2 |
|||||
T4 |
0x2 |
0x3 |
Read Latched Register |
0x1 |
Read Latched Register |
0x3 |
Write 0x1 to Latched Register |
Write 0x3 to Latched Register |
|||||
0x0 |
0x2 |
|||||
T5 |
0xC |
0xF |
Read Latched Register |
0xC |
Read Latched Register |
0xE |
Write 0xC to Latched Register |
Write 0xE to Latched Register |
|||||
0x0 |
0xC |
|||||
T6 |
0xC |
0xF |
Read Latched Register |
0x0 |
Read Latched |
0xC |
Write 0xC to Latched Register |
||||||
0xC |
||||||
T7 |
0x4 |
0xF |
Read Latched Register |
0x0 |
Read Latched Register |
0xC |
Write 0xC to Latched Register |
||||||
0x4 |
||||||
T8 |
0x4 |
0xF |
Read Latched Register |
0x0 |
Read Latched Register |
0x4 |
Interrupt Examples
The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.
Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled
Time |
Latched Status (Edge-Triggered – Clear Multi-Channel) |
Latched Status (Edge-Triggered – Clear Single Channel) |
Latched Status (Level-Triggered – Clear Multi-Channel) |
|||
Action |
Latched |
Action |
Latched |
Action |
Latched |
|
T1 (Int 1) |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x1 |
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
||||
0x0 |
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear until T2. |
0x1 |
|||
T3 (Int 2) |
Interrupt Generated Read Latched Registers |
0x2 |
Interrupt Generated Read Latched Registers |
0x2 |
Interrupt Generated Read Latched Registers |
0x2 |
Write 0x2 to Latched Register |
Write 0x2 to Latched Register |
Write 0x2 to Latched Register |
||||
0x0 |
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear until T7. |
0x2 |
|||
T4 (Int 3) |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x3 |
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
Write 0x3 to Latched Register |
||||
0x0 |
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5. |
0x3 |
|||
Interrupt re-triggers Note, interrupt re-triggers after each clear until T7. |
0x2 |
|||||
T6 (Int 4) |
Interrupt Generated Read Latched Registers |
0xC |
Interrupt Generated Read Latched Registers |
0xC |
Interrupt Generated Read Latched Registers |
0xE |
Write 0xC to Latched Register |
Write 0x4 to Latched Register |
Write 0xE to Latched Register |
||||
0x0 |
Interrupt re-triggers Write 0x8 to Latched Register |
0x8 |
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7. |
0xE |
||
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8. |
0xC |
||||
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always. |
0x4 |
|||||
MODULE COMMON REGISTERS
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The registers described in this document are common to all NAI Generation 5 modules.
Module Information Registers
The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.
FPGA Version Registers
The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.
FPGA Revision
Function: FPGA firmware revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the revision of the board’s FPGA
Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
FPGA Compile Timestamp
Function: Compile Timestamp for the FPGA firmware.
Type: unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Value corresponding to the compile timestamp of the board’s FPGA
Operational Settings: The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
day (5-bits) |
month (4-bits) |
year (6-bits) |
hr |
||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
hour (5-bits) |
minutes (6-bits) |
seconds (6-bits) |
|||||||||||||
FPGA SerDes Revision
Function: FPGA SerDes revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the SerDes revision of the board’s FPGA
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
FPGA Template Revision
Function: FPGA Template revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the template revision of the board’s FPGA
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
FPGA Zynq Block Revision
Function: FPGA Zynq Block revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Zynq block revision of the board’s FPGA
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
Bare Metal Version Registers
The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.
Bare Metal Revision
Function: Bare Metal firmware revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the revision of the board’s Bare Metal
Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
Bare Metal Compile Time
Function: Provides an ASCII representation of the Date/Time for the Bare Metal compile time.
Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Value corresponding to the ASCII representation of the compile time of the board’s Bare Metal
Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32
Word 1 (Ex. 0x2079614D) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Space (0x20) |
Month ('y' - 0x79) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Month ('a' - 0x61) |
Month ('M' - 0x4D) |
||||||||||||||
Word 2 (Ex. 0x32203731) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Year ('2' - 0x32) |
Space (0x20) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Day ('7' - 0x37) |
Day ('1' - 0x31) |
||||||||||||||
Word 3 (Ex. 0x20393130) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Space (0x20) |
Year ('9' - 0x39) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Year ('1' - 0x31) |
Year ('0' - 0x30) |
||||||||||||||
Word 4 (Ex. 0x31207461) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Hour ('1' - 0x31) |
Space (0x20) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
'a' (0x74) |
't' (0x61) |
||||||||||||||
Word 5 (Ex. 0x38333A35) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Minute ('8' - 0x38) |
Minute ('3' - 0x33) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
':' (0x3A) |
Hour ('5' - 0x35) |
||||||||||||||
Word 6 (Ex. 0x0032333A) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
NULL (0x00) |
Seconds ('2' - 0x32) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Seconds ('3' - 0x33) |
':' (0x3A) |
||||||||||||||
FSBL Version Registers
The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).
FSBL Revision
Function: FSBL firmware revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the revision of the board’s FSBL
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
FSBL Compile Time
Function: Provides an ASCII representation of the Date/Time for the FSBL compile time.
Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Value corresponding to the ASCII representation of the Compile Time of the board’s FSBL
Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time.
The hexadecimal values in the field below represent: May 17 2019 at 15:38:32
Word 1 (Ex. 0x2079614D) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Space (0x20) |
Month ('y' - 0x79) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Month ('a' - 0x61) |
Month ('M' - 0x4D) |
||||||||||||||
Word 2 (Ex. 0x32203731) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Year ('2' - 0x32) |
Space (0x20) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Day ('7' - 0x37) |
Day ('1' - 0x31) |
||||||||||||||
Word 3 (Ex. 0x20393130) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Space (0x20) |
Year ('9' - 0x39) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Year ('1' - 0x31) |
Year ('0' - 0x30) |
||||||||||||||
Word 4 (Ex. 0x31207461) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Hour ('1' - 0x31) |
Space (0x20) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
'a' (0x74) |
't' (0x61) |
||||||||||||||
Word 5 (Ex. 0x38333A35) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Minute ('8' - 0x38) |
Minute ('3' - 0x33) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
':' (0x3A) |
Hour ('5' - 0x35) |
||||||||||||||
Word 6 (Ex. 0x0032333A) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
NULL (0x00) |
Seconds ('2' - 0x32) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Seconds ('3' - 0x33) |
':' (0x3A) |
||||||||||||||
Module Serial Number Registers
The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.
Interface Board Serial Number
Function: Unique 128-bit identifier used to identify the interface board.
Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Serial number of the interface board
Operational Settings: This register is for information purposes only.
Functional Board Serial Number
Function: Unique 128-bit identifier used to identify the functional board.
Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Serial number of the functional board
Operational Settings: This register is for information purposes only.
Module Capability
Function: Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 0107
Read/Write: R
Initialized Value: 0x0000 0103
Operational Settings: A “1” in the bit associated with the capability indicates that it is supported.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Flt-Pt |
0 |
0 |
0 |
0 |
0 |
Pack |
FIFO Blk |
Blk |
Module Memory Map Revision
Function: Module Memory Map revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Module Memory Map Revision
Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major Revision Number |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor Revision Number |
|||||||||||||||
Module Measurement Registers
The registers in this section provide module temperature measurement information.
Temperature Readings Registers
The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.
Interface Board Current Temperature
Function: Measured PCB and Zynq Core temperatures on Interface Board.
Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB and Zynq core temperatures based on the table below
Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
PCB Temperature |
Zynq Core Temperature |
||||||||||||||
Functional Board Current Temperature
Function: Measured PCB temperature on Functional Board.
Type: signed byte (8-bits) for PCB
Data Range: 0x0000 0000 to 0x0000 00FF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB on the table below
Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PCB Temperature |
|||||||
Interface Board Maximum Temperature
Function: Maximum PCB and Zynq Core temperatures on Interface Board since power-on.
Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
PCB Temperature |
Zynq Core Temperature |
||||||||||||||
Interface Board Minimum Temperature
Function: Minimum PCB and Zynq Core temperatures on Interface Board since power-on.
Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
PCB Temperature |
Zynq Core Temperature |
||||||||||||||
Functional Board Maximum Temperature
Function: Maximum PCB temperature on Functional Board since power-on.
Type: signed byte (8-bits) for PCB
Data Range: 0x0000 0000 to 0x0000 00FF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB on the table below
Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PCB Temperature |
|||||||
Functional Board Minimum Temperature
Function: Minimum PCB temperature on Functional Board since power-on.
Type: signed byte (8-bits) for PCB
Data Range: 0x0000 0000 to 0x0000 00FF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB on the table below
Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PCB Temperature |
|||||||
Higher Precision Temperature Readings Registers
These registers provide higher precision readings of the current Zynq and PCB temperatures.
Higher Precision Zynq Core Temperature
Function: Higher precision measured Zynq Core temperature on Interface Board.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Zynq Core temperature on Interface Board
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Signed Integer Part of Temperature |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional Part of Temperature |
|||||||||||||||
Higher Precision Interface PCB Temperature
Function: Higher precision measured Interface PCB temperature.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Interface PCB temperature
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Signed Integer Part of Temperature |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional Part of Temperature |
|||||||||||||||
Higher Precision Functional PCB Temperature
Function: Higher precision measured Functional PCB temperature.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Functional PCB temperature
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Signed Integer Part of Temperature |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional Part of Temperature |
|||||||||||||||
Module Health Monitoring Registers
The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.
Module Sensor Summary Status
Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds.
Type: unsigned binary word (32-bits)
Data Range: See table below
Read/Write: R
Initialized Value: 0
Operational Settings: This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.
Bit(s) |
Sensor |
D31:D6 |
Reserved |
D5 |
Functional Board PCB Temperature |
D4 |
Interface Board PCB Temperature |
D3:D0 |
Reserved |
Module Sensor Registers
The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.
Sensor Threshold Status
Function: Reflects which threshold has been crossed
Type: unsigned binary word (32-bits)
Data Range: See table below
Read/Write: R
Initialized Value: 0
Operational Settings: The associated bit is set when the sensor reading exceed the corresponding threshold settings.
Bit(s) |
Description |
D31:D4 |
Reserved |
D3 |
Exceeded Upper Critical Threshold |
D2 |
Exceeded Upper Warning Threshold |
D1 |
Exceeded Lower Critical Threshold |
D0 |
Exceeded Lower Warning Threshold |
Sensor Current Reading
Function: Reflects current reading of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Minimum Reading
Function: Reflects minimum value of temperature sensor since power up
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Maximum Reading
Function: Reflects maximum value of temperature sensor since power up
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Lower Warning Threshold
Function: Reflects lower warning threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default lower warning threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.
Sensor Lower Critical Threshold
Function: Reflects lower critical threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default lower critical threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.
Sensor Upper Warning Threshold
Function: Reflects upper warning threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default upper warning threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.
Sensor Upper Critical Threshold
Function: Reflects upper critical threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default upper critical threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.
FUNCTION REGISTER MAP
Key
Bold Underline |
= Measurement/Status/Board Information |
Bold Italic |
= Configuration/Control |
Module Information Registers
0x003C |
FPGA Revision |
R |
0x0030 |
FPGA Compile Timestamp |
R |
0x0034 |
FPGA SerDes Revision |
R |
0x0038 |
FPGA Template Revision |
R |
0x0040 |
FPGA Zynq Block Revision |
R |
0x0074 |
Bare Metal Revision |
R |
0x0080 |
Bare Metal Compile Time (Bit 0-31) |
R |
0x0084 |
Bare Metal Compile Time (Bit 32-63) |
R |
0x0088 |
Bare Metal Compile Time (Bit 64-95) |
R |
0x008C |
Bare Metal Compile Time (Bit 96-127) |
R |
0x0090 |
Bare Metal Compile Time (Bit 128-159) |
R |
0x0094 |
Bare Metal Compile Time (Bit 160-191) |
R |
0x007C |
FSBL Revision |
R |
0x00B0 |
FSBL Compile Time (Bit 0-31) |
R |
0x00B4 |
FSBL Compile Time (Bit 32-63) |
R |
0x00B8 |
FSBL Compile Time (Bit 64-95) |
R |
0x00BC |
FSBL Compile Time (Bit 96-127) |
R |
0x00C0 |
FSBL Compile Time (Bit 128-159) |
R |
0x00C4 |
FSBL Compile Time (Bit 160-191) |
R |
0x0000 |
Interface Board Serial Number (Bit 0-31) |
R |
0x0004 |
Interface Board Serial Number (Bit 32-63) |
R |
0x0008 |
Interface Board Serial Number (Bit 64-95) |
R |
0x000C |
Interface Board Serial Number (Bit 96-127) |
R |
0x0010 |
Functional Board Serial Number (Bit 0-31) |
R |
0x0014 |
Functional Board Serial Number (Bit 32-63) |
R |
0x0018 |
Functional Board Serial Number (Bit 64-95) |
R |
0x001C |
Functional Board Serial Number (Bit 96-127) |
R |
0x0070 |
Module Capability |
R |
0x01FC |
Module Memory Map Revision |
R |
Module Measurement Registers
0x0200 |
Interface Board PCB/Zynq Current Temperature |
R |
0x0208 |
Functional Board PCB Current Temperature |
R |
0x0218 |
Interface Board PCB/Zynq Max Temperature |
R |
0x0228 |
Interface Board PCB/Zynq Min Temperature |
R |
0x0218 |
Functional Board PCB Max Temperature |
R |
0x0228 |
Functional Board PCB Min Temperature |
R |
0x02C0 |
Higher Precision Zynq Core Temperature |
R |
0x02C4 |
Higher Precision Interface PCB Temperature |
R |
0x02E0 |
Higher Precision Functional PCB Temperature |
R |
Module Manual - SD1-SD5 Revision History
Revision |
Revision Date |
Description |
C |
2023-11- 13 |
ECO C10950, transition to docbuilder format. Replaced 'Specifications' with 'Data Sheet'. Pg.7, updated Tracking Rate/Bandwidth/Reference Zin specs. Pg.8, updated introduction; added 'SD1- SD5 Overview'. Pg.9, added Multi-Speed Operation; changed AC Measurements to Signal/Reference. Pg.9, revised BIT/Diagnostic Capability. Pg.10, added SD/RD Threshold Programming, FIFO Buffering, Status and Interrupts, Engineering Scaling Conversions. Pg.11/30/41, added Module Common Registers. Reorganized 'Register Descriptions' by register group headings. Pg.13, added Sine/Cosine/Sine+Cosine RMS. Pg.16, added Sine/Cosine Detect Value. Pg.18, added Multi-Speed Ratio. Pg.20, added Inverse Signal Control. Pg.21-22, added Threshold Programming Registers. Pg.24, added BIT Error Limit. Pg.27, updated FIFO buffer sample rate. Pg.28, added FIFO Trigger Control. Pg.29, added FIFO Software Trigger. Pg.29-30, added Engineering Scaling Conversion Registers. Pg.31, added Channel Status Enable. Pg.32, added Signal Fault Low & High Status registers. Pg.33, added Reference Fault Low & High Status registers. Pg.36, added Open Detect and Summary Status registers. Pg.37, added Interrupt Vector and Steering. Pg.38, added Sine/Cosine/Sine+Cosine register offsets. Pg.39, added Multi-Speed Ratio and Inverse Signal Control register offsets. Pg.39, added Threshold Programming Registers. Pg.40, added FIFO Trigger Control and Software Trigger register offsets. Pg.40, added Engineering Scaling Conversion Registers. Pg.41, added Channel Status Enable. Pg.41, added Signal & Reference Fault Low register offsets. Pg.41, added Signal & Reference Fault High register offsets. Pg.42, added Open Detect and Summary Status register offsets. Pg.43-45, added Interrupt Registers. Added Appendices A-C. |
Module Manual - Status and Interrupts Revision History
Revision |
Revision Date |
Description |
C |
2021-11-30 |
C08896; Transition manual to docbuilder format - no technical info change. |
Module Manual - Module Common Registers Revision History
Revision |
Revision Date |
Description |
C |
2023-08-11 |
ECO C10649, initial release of module common registers manual. |
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