The 68INT5 supports options for Power-On-Self-Test (POST) testing (memory, peripherals, etc.). The 68INT5 also supports function modules with NAI’s flexible, leading-edge, fully programmable and continuous background built-in-test (BIT) enabled function. BIT tests both 68INT5 on board functions and functions contained on expansion modules, making it a useful field service tool.

The 68INT5 utilizes the Insyde Unified Extensible Firmware Interface (UEFI) BIOS. The BIOS provides for low level functions required by the processor core and chipset. The BIOS also controls many configuration options. The BIOS configuration controls many details concerning the behavior of the hardware from the moment power is applied.

The user’s BIOS configuration options are saved in the Serial Peripheral Interface (SPI) Flash memory. Both the BIOS and BIOS configuration data is stored in the SPI Flash device. The SPI Flash is non-volatile, and the BIOS configuration settings are saved without system or battery power. There is no battery on the 68INT5.

The BIOS supports several modes for booting, including remote booting from any of the Ethernet ports.

The 68INT5 hardware supports CentOS/Linux and Microsoft® Windows® operating systems. Contact NAI for availability of other operating systems.

NAI provides BSP support for the above operating systems, as defined by the operating system vendors.

The 68INT5 requires up to 30 Watts from the power supply. For exact values, see 68INT5 Environmental/Power Specifications section. The PCI power supply must be capable of 750 mA @ 5 V rail, 720 mA @ 12 V rail and 100 mA @ 3.3_Aux V. The +12 V and -12 V supplies are required only by the optional expansion modules.

Dependent on how the 68INT5 was configured at the factory, a keyboard and mouse may be required to set your BIOS configuration options. A mouse and keyboard can be connected to the 68INT5 for initial system setup. Your mouse and keyboard should be attached to Mini-HDMI connector J5, using the optional NAI “breakout” adapter board (NAI P/N 75SBC4-BB). Connect your devices to the USB connector on the breakout board. A USB hub may be used to attach more one than one USB device.

Refer to the 68INT5 ordering code for the video configuration option (see Part Number Designation section in this manual). Any VGA or compatible HDMI/DVI monitor may be used for initial setup. Note that the Video outputs are configured as rear I/O.

Each time the 68INT5 boots, it must pass the BIOS Power-On-Self-Test (POST), which is summarized below.

The 68INT5 provides a total of 32 GB of ECC DDR4 memory. This memory is organized as 2 channels of 8 2Gb x 8 MT40A2G8 devices (parts may vary), with a ninth device on each channel providing storage for ECC data. The E-2276ME has an on chip 64-bit DDR4 memory controller. The controller has full ECC error-correction support, with the ability to detect multi-bit errors and correct single-bit errors within a nibble. Please consult the Micron data sheet for DDR4 device specific details.

The 68INT5 supports 2 x 16 MB of serial flash, which is connected through the CM246 SPI interface via a jumper. The flash memory consists of two, soldered W25Q128FV SPI flash devices. The flash memory is organized as 65,526 pages of 256 bytes each. Up to 256 bytes can be programmed at a time. The flash memory is used to store the BIOS configuration setting. The flash memory has an erase capacity of 100,000 cycles per sector and typical data retention of 20 years.

SATA Port 1

The SATA port 1 controller interface on the CM246 is directly connected to an on-board, solid-state drive. The SSD contains a single level cell NAND Flash together with a controller in a single multi-chip package. This multi-chip packaged device is soldered directly to the printed circuit board, for reliable electrical and mechanical connection.

The onboard SATA drive conforms to the follow specifications:

The standard ordering code for the 68INT5 includes a 64GB SSD drive. Smaller devices are available; please consult the factory for availability.

SATA Port 2

A configurable SATA III or PCI port is routed to the Function Module Slot (e.g. for additional Gig-E ports or on-board NVM storage).

The 68INT5 has two Intel® I210 Ethernet controllers that supports two 10/100/1000 Ethernet ports. The Intel® I210 features:

Ethernet port 1 as a build option may be routed as 10/100/1000Base-T to the front board edge connector J5 or 10/100/1000Base-T or -KX to the rear PCIe connector P1. Standard ordering codes route Ethernet port 1 to the rear I/O.

Ethernet port 2 as a build option may be routed as 10/100/1000Base-T or -KX to rear I/O connector P1.

I/O pin outs can be found in the PCIe P1 and Front I/O J5 section of this document.

The 68INT5 supports two USB 2.0 and one USB 3.0 ports. Contact factory for availability. USB port 1 is available at the rear of 68INT5, on connector P1. USB port 2 is available at the rear of 68INT5, on connector P2. USB port 3 is available at the front of 68INT5, on connector J5. Each USB port can operate as a standalone host.

The 68INT5 uses Intel® E-2276ME mobile processor integrated UHD Graphics P630. This provides HDMI/DVI output with 4K support (at 60 Hz), as well as OpenGl and DirectX support. The HDMI/DVI signals are routed to the rear P1 I/O connector (see pin-out table).

The HDMI video option uses Display Port B of the CM246 chipset. The maximum resolution is 60Hz at 4096 x 2034.

Real-Time Clock/Calendar (RTC/C) is part of the CM246. The RTC/C is MC146818B compatible, with 256 bytes of battery-backed RAM. It is used to provide a system time and date function or can be used as an event timer.

To maintain the RTCC and RAM functions when the 5 V power is off, the RTC_STDBY pin must be connected to an external battery or power supply. The RTC_STDBY supply voltage should be between 1.4 V to 3.3 V. A typical RTC_STDBY supply requirement is 3.0 V @ 5 µA.

Serial Peripheral Interface Bus or SPI is a synchronous serial data link standard. SPI operates in full duplex mode. SPI devices communicate in master/slave mode where the master device starts a frame and sources the clock. The CM246 has one SPI controller. The SPI port is attached to a SLB9670XQ2. The SLB9670XQ2 is a Trusted Platform Module that is based on advanced hardware security technology.

The 68INT5 has one asynchronous serial port. The interface uses a two-wire, TXD-RXD interface (system/power GND referenced). The SER-TXD and SER-RXD RS-232 signals are routed in parallel to J5 at the front and P1 at the rear of the 68INT5.

Function: Specifies the Base Address for the module in the specific slot position.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Based on board’s module configuration.

Operational Settings: 0x0000 0000 indicates no Module found.

Function: Specifies the Memory Size (in bytes) allocated for the module in the specific slot position.

Type: unsigned binary word (32-bit)

Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Assigned by factory for the module.

Operational Settings: 0x0000 0000 indicates no Module found.

Function: Specifies the Model ID for the module in the specified slot position.

Type: 4-character ASCII string

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Assigned by factory for the module.

Operational Settings: The Module ID is formatted as four ASCII bytes: three characters followed by a space. Module IDs are in little-endian order with a single space following the first three characters. For example, 'TL1' is '1LT', 'SC1' is '1CS' and so forth. Example below is for “TL1” (MSB justified). All value of 0000 0000 indicates no Module found.

Function: Specifies the Board Serial Number.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Serial number assigned by factory for the board.

Operational Settings: N/A

Function: Specifies the Board Platform Identifier. Values are for the ASCII characters for the NAI valid platforms (Identifiers).

Type: 4-character ASCII string

Data Range: See table below.

Read/Write: R

Initialized Value: ASCII code is for the Platform Identifier of the board

Operational Settings: NAI platform for this board is shown below:

Function: Specifies the Board Model Identifier. Values are for the ASCII characters for the NAI valid models.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Initialized Value: ASCII code is for the Model Identifier of the board

Operational Settings: Examples of NAI models and the associated values for these models are shown below:

Function: Specifies the Board Generation. Identifier values are for the ASCII characters for the NAI valid generation identifiers.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Initialized Value: ASCII code is for the Generation Identifier of the board

Operational Settings: Examples of NAI generations and the associated values for these generations are shown below:

Function: Specifies the Ethernet Interface Count and Processor Count

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Operational Settings:

Ethernet Interface Count - Indicates the number of Ethernet interfaces on the product motherboard.

Processor Count - Indicates the number of unique processor types on the motherboard

Function: Specifies the ARM Platform Type and Maximum Module Slot Count.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Operational Settings:

Maximum Module Slot Count - Indicates the number of modules that can be installed on the product

ARM Platform Type - Altera = 1; Xilinx X1 = 2; Xilinx X2 = 3; UltraScale+ = 4

Function: Specifies the Version of the NAI factory provided Motherboard Core Application installed on the board.

Type: Two (2) unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Operational Settings: The motherboard firmware version consists of four components: Major, Minor, Minor 2 and Minor 3.

Function: Specifies the Build Date/Time of the NAI factory provided Motherboard Core Application installed on the board.

Type: Two (2) unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Operational Settings: The motherboard firmware time consists of the Build Date and Build Time.

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) for the processor and PCB for Zynq processor.

These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).

Function: Specifies the Measured Temperatures on Motherboard.

Type: signed byte (8-bits) for each temperature reading - Six (6) 32-bit words

Data Range: 0x0000 0000 to 0xFFFF 0000

Read/Write: R

Initialized Value: Value corresponding to the measured temperatures based on the table below.

Operational Settings: The 8-bit temperature readings are signed bytes. For example, if the following register contains the value 0x6955 0000:

Example:

The values would represent the following temperatures:

These registers provide higher precision readings of the current Zynq and PCB temperatures.

Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds.

Type: unsigned binary word (32-bits)

Data Range: See table below

Read/Write: R

Initialized Value: 0

Operational Settings: This register provides a summary for motherboard sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.

The registers listed in this section apply to each module sensor listed for the Motherboard Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring motherboard temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Zynq Core Temperature sensor as an example.

Function: Set an identifier for the interrupt.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Function: Sets where to direct the interrupt.

Type: unsigned binary word (32-bit)

Data Range: See table Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, the interrupt is sent as specified:

Function: Provides the ability to monitor factors may effect communication status of a Module.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Operational Settings: The Module Communications registers provide the ability to monitor factors that may effect the Communications Status of individual Modules. There is one register per Module. Each communication factor is bit mapped to the register as shown in the table below:

Module Powered-down: The user can request an individual Module be powered-down (see Module Control Command Requests). Once the request is detected and acted upon, this bit will be set. Once powered-down, you will not be able to communicate with the Module.

Module Not Detected: If a Module in this slot has not been detected, you will not be able to communicate with the Module.

Module LinkInit Not Done: Module communications is accomplished via SERDES. LinkInit is required to establish a connection to the Module. If the LinkInit has not been successfully completed, you will not be able to communicate with the Module.

Module Firmware Not Ready: Each Module has Firmware that is ready from Module QSPI and loaded for execution. If this Firmware was not loaded and started successfully, you may not be able to communicate with the Module.

Module Communications Error Detected: If at some point during run-time, communications with the Module has failed, this bit will be set.

Signals defined as N/C currently have no functionality associated and are not required for general operation.

P0 - Utility plane. Contains the following signal definitions:

P1 - Defined as Data/Control Planes (User defined I/O secondary)

P2 - User defined I/O (primary)

The P0 (Utility) Plane contains the primary power, bus and utility signals for the OpenVPX board. Additionally, several of the user defined pins can be utilized for Geographical Addressing and a parallel SYSRST# signal. Signals defined as N/C currently have no functionality associated and is not required for general operation.

The 68INT5 has two Fat (data plane) pipes and two Ultra-Thin (control plane) pipes. Additionally, the 68INT5 can be commanded/controlled via GigE (options for either 10/100/1000Base-T and/or 1000Base-KX (SerDes) Interfaces). HDMI is also defined on the P1 user defined plane. Signals defined as N/C currently have no functionality associated or are considered optional and are not required for general operation.

The following pages contain the 'user defined' I/O data area front and rear panel pin-outs with their respective signal designations for all module types currently offered/configured for the 68INT5 platform. The card is designed to route the function module I/O signals to the front and rear I/O connector. The following I/O connector pin-out is based upon the function module designated in the module slot. Signals defined as N/C currently have no functionality associated or are considered optional and are not required for general operation.

Commercial Equivalent RJ45-type Ethernet cabling/wiring (for reference only):

Outline, General, Conduction Cooled

Outline, General, Air Cooled, Front Panel I/O, 0.8" Pitch