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Three-Channel LVDT Simulation

DLx DATA SHEET

INTRODUCTION

Modules DLx are Linear (and Rotary) Variable Differential Transformer (D/L®VDT) Simulation Modules. L®VDT are transformer-type voltage/current transducers that convert a linear/rotary movement of a core/shaft to a multi-wire differential AC electrical signal. Both deliver signals linearly proportional to the position of the shaft (magnetic induction core). A LVDT/RVDT simulator is used to convert digital positional commands to corresponding AC signals.

A wide variety of DLx modules are available to cover the range of excitation (noted in this manual as ‘reference') voltages/frequency, include extensive field-parameter programmability, and provide a full operating envelope choice for simulating virtually any type of LVDT or RVDT. By eliminating the need for external transformers and operating with lower AC reference frequencies, these solid-state designs offer huge space savings.

See Model Designations table below for a description of the available DLx configurations.

Module ID

Linear

No. of Channels

Full Scale Output Voltage (RMS VL-L)

Output Load

Frequency Range (Hz)

DL1

2-28

3 VA @ 28 VRMS

47-1k

DL2

2-28

3 VA @ 28 VRMS

1k-5k

DL3

2-28

3 VA @ 28 VRMS

5k-10k

DL4

2-28

3 VA @ 28 VRMS

10k-20k

DL5

28-90

3 VA @ 90 VRMS

47-1k

DLA

2-28

1.5 VA @ 28 VRMS

47-1k

DLB

2-28

1.5 VA @ 28 VRMS

1k-5k

DLC

2-28

1.5 VA @ 28 VRMS

5k-10k

DLD

2-28

1.5 VA @ 28 VRMS

10k-20k

DLE

28-90

2.2 VA @ 90RMS

V 47-1k

DLJ

2-28

0.5 VA @ 28 VRMS

47-1k

DLK

2-28

0.5 VA @ 28 VRMS

1k-5k

DLL

2-28

0.5 VA @ 28 VRMS

5k-10k

DLM

2-28

0.5 VA @ 28 VRMS

10k-20k

DLN

28-90

0.5 VA @ 90 VRMS

47-1k

There are three types of D/L modules:

3-Channel Modules: These high-density modules have a lower power output drive (0.5 VA per channel, maximum). The lower power output drive is ideal for driving solid-state input instruments, gauges (most LVDT/RVDT measurement circuits are high input impedance, as “real” LVDTs/RVDTs do not supply a large amount of current).
2-Channel Modules: The 2-channel modules have a standard power output drive of 1.5 VA (2.2 VA for DLE) per channel, maximum.
Single-Channel Modules: The single-channel modules have a high-power output drive capability (3 VA per channel, maximum).

* Contact factory for single channel availability

PRINCIPLE OF OPERATION

The Digital-to-LVDT/RVDT (DLV) Simulation Module provides up to three channels of individual two/three/four-wire “programmable” outputs. It is designed for wide field-programmability of both excitation (reference) and output signal voltage.

The DLx allows the user to program the module for either ratio or fixed output mode. When set to ratio mode, each channel utilizes a transformation ratio (TR) which sets the maximum output signal voltage in relation to the input reference voltage (TR = Max Output Voltage/Reference Voltage). This ratiometric design eliminates errors caused by variations in reference voltage by allowing the output voltage to adjust with it. When set to fixed mode, the output voltage is absolute and does not change with reference voltage variations.

The DLx also features a wrap-around self-test for measuring the output position, current and carrier frequency of each channel.

Programmable Output Format

The output format can be programmed to simulate two-wire or three/four-wire LVDTs. Each channel features its own isolated 'A' and 'B' high/low line output pair. An independent reference input voltage is supplied to each 'A' and 'B' output pair.

When set to four-wire mode, the module has one commanded position that sets the voltage levels of each output pair. For example, setting the position to 0% will make both the 'A' and 'B' pair outputs the same output voltage. If the position is set to 100%, the 'A' output will be the maximum output voltage while the 'B' output will be 0 VL-L.

When set to three-wire mode, the 'A' and 'B' low lines are paired at the external load. This will give the channel a common low line, one 'A' high line and one 'B' high line. If the commanded position is set to 100%, the 'A' high line will be the maximum output voltage while the 'B' high line will be 0 VL-L.

When set to two-wire mode, the channel is split into independent position control. Each output ('A' and 'B') will have its own commanded position.

Voltage Feedback Sense Lines

The DLx Simulation Module includes two voltage feedback sense lines for each output channel A/B pair. They provide automatic output drive voltage compensation during higher current applications that may induce voltage drops in the wiring. They also provide compensation for lower voltage applications (which are more susceptible to voltage drops).

It is always recommended that the sense lines be utilized and connected at the external load to provide maximum measurement accuracy (which ensures that the commanded voltage is applied at the load). Sense (Hi) should be connected to Output (Hi), and Sense (Lo) should be connected to Output (Lo). If additional wiring is prohibitive in the application, the sense lines may instead be terminated at the connector (note: accuracy will not be as good as “remote sensing” at the load).

Built-In Test (BIT)/Diagnostic Capability

The board supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are logically ORed together and stored in the BIT Dynamic Status and BIT Latched Status registers.

Power-On Self-Test (POST)/Power-on BIT/Start-up BIT (SBIT)

This board features a power-on self-test that will do an accuracy check of each channel and report the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Latched Status.

Continuous Background Built-In Test

The background Built-In-Test or Continuous BIT (CBIT) (“D2”) runs in the background where each channel is checked to a test accuracy of 0.2% FS. The testing is totally transparent to the user, requires no external programming, and has no effect on the operation of the module or card.

The technique used by the continuous background BIT (CBIT) test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. Note, the interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained; i.e. at a ten second interval, not a 10-millisecond interval). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and a fail state.

Initiate Built-In Test

The DLx module supports an off-line Initiated Built-In Test (IBIT) (“D3”).

IBIT test starts an initiated BIT test that utilizes an internal stimulus to generate and test the full-scale positional range to a default test accuracy of 0.1% full scale range. IBIT test cycle is completed within 30 seconds and the result can be read from the BIT status registers when IBIT bit changes from 1 to 0.

Status and Interrupts

The DLx Simulation Module provide registers that indicate faults or events. Refer to "Status and Interrupts Module Manual" for the Principle of Operation description.

Module Common Registers

The DLx Simulation Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

REGISTER DESCRIPTIONS

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Control Registers

Power On/Off

Function: Turns on the selected channel and initiates output.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 - 0x0000 0007 (for supporting up to 3 channels)

Read/Write: R/W

Initialized Value: 0x0000 0000

Operational Settings: To turn on the selected channel, set the bit to 1.

Table 1. Power On/Off
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1

Output Format

Function: Select between two-wire or three/four-wire mode.

Type: unsigned binary word (32-bit)

Range: 1 or 2

Read/Write: R/W

Initialized Value: 1 (three/four wire)

Operational Settings: Sets the output format of the DLV channel. Set register to a 0x1 for three/four wire mode or a 0x2 for two wire mode.

Set Position A/B

Function: Sets position of each channel.

Type: unsigned binary word (32-bit)

Range: -100% to +99.999%

Read/Write: R/W

Initialized Value: 0%

Operational Settings: Write a 32-bit integer to the corresponding channel DLV Position Register. Even though the output resolution is 16 bits, the position setting is up to 24 bits and written into a 32-bit register.

WORD = Position / (200/ 2^32)

LSB is 200/2 or approximately 0.000000046566%. The upper 24 bits define the position, while the lower 8 bits are at zero.

Example 1: For a position of 78.125

WORD = 78.125 / (200 / 2^32) = 0x6400_0000

Example 2: For a position of -78.125

WORD = -78.125 / (200 / 2^32) = 0x9C00_0000

Table 2. Set Position
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
100	50	25	12.5	6.25	3.125	1.5625	0.78125	0.39063	0.19531	0.09766	0.04883	0.02441	0.01221	0.00610	0.00305
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
.00153	.00076	.00038	.00019	.000095	.000048	.000023	.000012	0	0	0	0	0	0	0	0

Set Voltage

Function: Sets signal voltage “VL-L” to a corresponding register.

Type: unsigned binary word (32-bit)

Range: 2-28 or 28-90 VL-L depending on model

Read/Write: R/W

Initialized Value: 28 VL-L for low voltage modules and 90 VL-L for high voltage modules.

Operational Settings: The output voltage is set with a resolution of 10 mV . The setting is in integer decimal format.

For example, if channel 1 Signal (VL-L) voltage is to be 11.8 V , the set word to the corresponding register would be 1180.

Expected Reference

Function: Sets reference voltage “V ” to a corresponding register.

Type: unsigned binary word (32-bit) Range: 2-115 V Read/Write: R/W

Initialized Value: 26 or 115 V depending on model

Operational Settings: The input voltage is set with a resolution of 10 mV. The setting is in integer decimal format.

For example, if channel 1 expected input REF voltage is 26.0 V , the set word to the corresponding register would be 2600.

Set Phase Offset

Function: Enables setting the phase (in degrees) of each channel to an offset of the Reference.

Type: unsigned binary word (32-bit) Range: +/- 90° Read/Write: R/W

Initialized Value: 0°

Operational Settings: The phase offset has 24-bit resolution put into the MSBs of the 32-bit word.

Word = Phase / (360/2 )

Table 3. Set Phase Offset
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
180	90	45	22.5	11.25	5.625	2.813	1.406	.703	.352	.176	.088	.044	.022	.011	.0055
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D1
.00274	.00137	.00068	.00034	.00017	.00008	.00004	.00002	0	0	0	0	0	0	0	0

Output Mode (Ratio/Fixed)

Function: Enables selection of either ratiometric (ratio) or absolute (fixed) mode output voltages.

*Type:& unsigned binary word (32-bit)

Range: 0 or 1 (per channel; model dependent)

Read/Write: R/W

Initialized Value: Ratiometric

Operational Settings: Ratiometric Mode, when selected, will cause the output signal voltage of the channel to vary with the input Reference Voltage. Fixed Mode, when selected, will cause the output signal voltage of the channel NOT to vary with the input Reference Voltage. Set corresponding channel bit to 0 for Ratiometric Mode. Set corresponding channel bit to 1 for Fixed Mode.

Table 4. Output Mode (Ratio/Fixed)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Measurement Registers

Measured Position A/B

Function: Measures each channel’s position.

Type: unsigned binary word (32-bit)

Range: +/-100%

Read/Write: R

Initialized Value: 0%

Operational Settings: Measured position in percent = register value* (200/2 ).

Table 5. Set Position
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
-100	50	25	12.5	6.25	3.125	1.5625	0.78125	0.39063	0.19531	0.09766	0.04883	0.02441	0.01221	0.00610	0.00305
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
.00153	.00076	.00038	.00019	.000095	.000048	.000023	.000012	0	0	0	0	0	0	0	0

Measured Frequency

Function: Reads each channel’s input reference frequency.

Type: unsigned binary word (32-bit)

R*ange:* Depends on model

Read/Write: R

Initialized Value: 0 Hz

Operational Settings: The input reference frequency is reported to a resolution of 1 Hz. The output is in integer decimal format. For example, if channel 1 input excitation is 400 Hz, the output measurement word from the corresponding register would be 400.

Measured Signal Voltage A/B

Function: Reads each channel’s output signal voltage (V_L-L).

Type: unsigned binary word (32-bit)

Range: 2-28 or 28-90 VL-L depending on model

Read/Write: R

Initialized Value: 0 VLL on power up

*Operational Settings: The output voltage is reported to a resolution of 10 mV_RMS. The output is in integer decimal format. For example, if channel 1 output signal voltage is 11.8 V_RMS, the output measurement word from the corresponding register would be 1180.

Measured Reference Voltage

Function: Reads each channel’s input signal reference voltage (V_REF ).

Type: unsigned binary word (32-bit)

Range: 2-115 V_REF

Read/Write: R

Initialized Value: 0 V_REF on power up

Operational Settings: The input voltage is reported to a resolution of 10 mV_REF. The output is in integer decimal format. For example, if channel 1 input V voltage is 26.0 V_REF, the output measurement word from the corresponding register would be 2600.

Measured Current A/B

Function: Displays the measured current on the channel’s output.

Type: unsigned binary word (32-bit)

Range: NA

Read/Write: R

Initialized Value: 0

Operational Settings: Measures current in milliamps.

Threshold Programming Registers

The Signal Loss Threshold A/B and Reference Loss Threshold registers set the threshold limits to the Signal Loss Status and Reference Loss Status registers respectively.

Signal Loss Threshold A/B

Function: Programmable status threshold to indicate when the measured VLL falls below this value.

Type: unsigned binary word (32-bit)

Range: 10mVL-L up to 90 VL-L

Read/Write: R/W

Initialized Value: 80% of default output voltage.

Operational Settings: The signal loss detection circuitry can be tailored to report a signal loss (at Signal Loss Status register) at a user defined threshold. This threshold can be set to a resolution of 10 mVL-L. Program the threshold by writing the value of the voltage threshold in integer decimal format. For example, if Channel 1 signal loss voltage threshold is to be 7 VL-L, the programmed word to the corresponding register would be 700 (2BCh).

Reference Loss Threshold

Function: Programmable status threshold to indicate when the measured VREF falls below this value.

Type: unsigned binary word (32-bit) Range: 10m Vrms up to 115 Vrms

Read/Write: R/W

Initialized Value: 80% of the default expected reference

Operational Settings: The reference loss detection circuitry can be tailored to report a reference loss at a user defined threshold. This threshold can be set to a resolution of 10 mVrms. Program the threshold by writing the value of the voltage threshold in integer decimal format. For example, if channel 1 input reference loss voltage threshold is to be 20 Vrms, the programmed word to the corresponding register would be 2000 (7D0h).

Test Registers

Two different tests, one on-line (CBIT) and one off-line (IBIT), can be selected. External reference voltage is not required for any of these tests.

Test Enabled

Function: Set bit in this register to enable associated Built-In Self-Test IBIT and CBIT.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 to 0x000D

Read/Write: R/W

Initialized Value: 0x4 (CBIT Test Enabled)

Operational Settings: BIT tests include an on-line (CBIT) test and an off-line (IBIT) test. Failures in the BIT tests are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects a failure.

Table 6. Test Enabled
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	IBIT Test D	CBIT Test 1	0	0

Test CBIT Verify

Function: Allows user to verify if the CBIT test is running.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: User can write any value to this register. If CBIT test is running, after a minimum of 10ms the value read back will be 0x0000 0055, otherwise the value read back will be the value written.

Module Common Registers

Refer to “Module Common Registers Module Manual” for the register descriptions.

Status and Interrupt Registers

The DLx Module provides status registers for BIT, Signal Loss, Reference Loss, Phase Lock and Overcurrent.

Channel Status Enabled

Function: Determines whether to update the status for the channels. The feature can be used to “mask' status bits of unused channels in status registers that are bitmapped by channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 - 0x0000 FFFF

Read/Write: R/W

Initialized Value: 0x0000 FFFF

Operational Settings: When the bit corresponding to a given channel in the Channel Status Enabled register is not enabled (0), the statuses will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status, Signal Loss Status, Reference Loss Status, Phase Lock Status and Overcurrent Status). When the bit corresponding to a given channel is enabled (1), it will allow the statuses for that channel to be updated.

Table 7. Channel Status Enabled
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 8. BIT Status
BIT Dynamic Status
BIT Latched Status
BIT Interrupt Enable
BIT Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	*Ch3B	*Ch2B	*Ch1B
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3 *Ch3A	Ch2 *Ch2A	Ch1 *Ch1A

Note	*for two-wire output mode only ('A' and 'B' output in each channel has its own commanded position)

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0007 (two-wire mode only: 0x0000 0000 to 0x0007 0007)

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Signal Loss Status

There are four registers associated with the Signal Loss Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 9. Signal Loss Status
Signal Loss Dynamic Status
Signal Loss Latched Status
Signal Loss Interrupt Enable
Signal Loss Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	*Ch3B	*Ch2B	*Ch1B
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3*Ch3A	Ch2*Ch2A	Ch1*Ch1A

Note	*for two-wire output mode only ('A' and 'B' output in each channel has its own commanded position)

Function: Sets the corresponding bit associated with the channel’s Signal Loss error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0007 (two-wire mode only: 0x0000 0000 to 0x0007 0007)

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Reference Loss Status

There are four registers associated with the Reference Loss Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 10. Reference Loss Status
Reference Loss Dynamic Status
Reference Loss Latched Status
Reference Loss Interrupt Enable
Reference Loss Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1

Function: Sets the corresponding bit associated with the channel’s Reference Fault Low error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Phase Lock Status

There are four registers associated with the Phase Lock Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 11. Phase Lock Status
Phase Lock Dynamic Status
Phase Lock Latched Status
Phase Lock Interrupt Enable
Phase Lock Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1

Function: Sets the corresponding bit associated with the channel’s Phase Lock error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Overcurrent Status

There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Table 12. Overcurrent Status
Overcurrent Dynamic Status
Overcurrent Latched Status
Overcurrent Interrupt Enable
Overcurrent Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1

Function: Sets the corresponding bit associated with the channel’s Overcurrent error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Interrupt Vector and Steering

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When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note	The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector

Function: Set an identifier for the interrupt.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering

Function: Sets where to direct the interrupt.

Type: unsigned binary word (32-bit)

Data Range: See table Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME	1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)	2
Direct Interrupt to PCIe Bus	5
Direct Interrupt to cPCI Bus	6

FUNCTION REGISTER MAP

Key:

Bold Italic = Configuration/Control

Bold Underline = Measurement/Status

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a ‘1' to a bit set to ‘1' will set the bit to ‘0'). ~ Data is always in Floating Point.

Control Registers

0x0250

Power On/Off⁺⁺

R/W

⁺⁺After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.

0x10E0

Output Format Ch 1

R/W

0x10E4

Output Format Ch 2

R/W

0x10E8

Output Format Ch 3

R/W

0x1000

Set Position A Ch 1

R/W

0x1004

Set Position A Ch 2

R/W

0x1008

Set Position A Ch 3

R/W

0x1180

Set Position B Ch 1

R/W

0x1184

Set Position B Ch 2

R/W

0x1188

Set Position B Ch 3

R/W

0x1010

Set Voltage Ch 1

R/W

0x1014

Set Voltage Ch 2

R/W

0x1018

Set Voltage Ch 3

R/W

0x1020

Expected Reference Ch 1

R/W

0x1024

Expected Reference Ch 2

R/W

0x1028

Expected Reference Ch 3

R/W

0x1030

Set Phase Offset Ch 1

R/W

0x1034

Set Phase Offset Ch 2

R/W

0x1038

Set Phase Offset Ch 3

R/W

0x1040

Output Mode (Ratio/Fixed) Ch 1

R/W

0x1044

Output Mode (Ratio/Fixed) Ch 2

R/W

0x1048

Output Mode (Ratio/Fixed) Ch 3

R/W

Measurement Registers

Measured Position A/B

0x1050

Measured Position A Ch 1

R/W

0x1054

Measured Position A Ch 2

R/W

0x1058

Measured Position A Ch 3

R/W

0x1190

Measured Position B Ch 1

R/W

0x1194

Measured Position B Ch 2

R/W

0x1198

Measured Position B Ch 3

R/W

0x1070

Measured Frequency Ch 1

R/W

0x1074

Measured Frequency Ch 2

R/W

0x1078

Measured Frequency Ch 3

R/W

0x1080

Measured Signal Voltage A Ch 1

R/W

0x1084

Measured Signal Voltage A Ch 2

R/W

0x1088

Measured Signal Voltage A Ch 3

R/W

0x11B0

Measured Signal Voltage B Ch 1

R/W

0x11B4

Measured Signal Voltage B Ch 2

R/W

0x11B8

Measured Signal Voltage B Ch 3

R/W

0x1090

Measured Reference Voltage Ch 1

R/W

0x1094

Measured Reference Voltage Ch 2

R/W

0x1098

Measured Reference Voltage Ch 3

R/W

0x10A0

Measured Current A Ch 1

R/W

0x10A4

Measured Current A Ch 2

R/W

0x10A8

Measured Current A Ch 3

R/W

0x11C0

Measured Current B Ch 1

R/W

0x11C4

Measured Current B Ch 2

R/W

0x11C8

Measured Current B Ch 3

R/W

Threshold Programming Registers

0x10B0

Signal Loss Threshold A Ch 1

R/W

0x10B4

Signal Loss Threshold A Ch 2

R/W

0x10B8

Signal Loss Threshold A Ch 3

R/W

0x11D0

Signal Loss Threshold B Ch 1

R/W

0x11D4

Signal Loss Threshold B Ch 2

R/W

0x11D8

Signal Loss Threshold B Ch 3

R/W

0x10C0

Reference Loss Threshold Ch 1

R/W

0x10C4

Reference Loss Threshold Ch 2

R/W

0x10C8

Reference Loss Threshold Ch 3

R/W

Module Common Registers

Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.

Test Registers

0x0248

Test Enabled

R/W

0x024C

Test Verify

R/W

Status and Interrupt Registers

0x02B0

Channel Status Enabled

R/W

BIT Status

0x0800

Dynamic Status

0x0804

Latched Status*

R/W

0x0808

*_Interrupt Enable

R/W

0x080C

*_Set Edge/Level Interrupt

R/W

Signal Loss

0x0810

Dynamic Status

0x0814

Latched Status*

R/W

0x0818

Interrupt Enable

R/W

0x081C

Set Edge/Level Interrupt

R/W

Reference Loss Status

0x0820

Dynamic Status

0x0824

Latched Status*

R/W

0x0828

Interrupt Enable

R/W

0x082C

Set Edge/Level Interrupt

R/W

Phase Lock Status

0x0830

Dynamic Status

0x0834

Latched Status*

R/W

0x0838

Interrupt Enable

R/W

0x083C

Set Edge/Level Interrupt

R/W

Overcurrent Status

0x0850

Dynamic Status

0x0854

Latched Status*

R/W

0x0858

Interrupt Enable

R/W

0x085C

Set Edge/Level Interrupt

R/W

Interrupt Registers

The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below

0x0500

Module 1 Interrupt Vector 1 - BIT

R/W

0x0504

Module 1 Interrupt Vector 2 - Signal Loss

R/W

0x0508

Module 1 Interrupt Vector 3 - Reference Loss

R/W

0x050C

Module 1 Interrupt Vector 4 - Phase Lock

R/W

0x0510

Module 1 Interrupt Vector 5 - Reserved

R/W

0x0514

Module 1 Interrupt Vector 6 - Overcurrent

R/W

0x0518 to 0x057C

Module 1 Interrupt Vector 7-32 - Reserved

R/W

0x0600

Module 1 Interrupt Steering 1 - BIT

R/W

0x0604

Module 1 Interrupt Steering 2 - Signal Loss

R/W

0x0608

Module 1 Interrupt Steering 3 - Reference Loss

R/W

0x060C

Module 1 Interrupt Steering 4 - Phase Lock

R/W

0x0610

Module 1 Interrupt Steering 5 - Reserved

R/W

0x0614

Module 1 Interrupt Steering 6 - Overcurrent

R/W

0x0618 to 0x067C

Module 1 Interrupt Steering 7-32 - Reserved

R/W

0x0700

Module 2 Interrupt Vector 1 - BIT

R/W

0x0704

Module 2 Interrupt Vector 2 - Signal Loss

R/W

0x0708

Module 2 Interrupt Vector 3 - Reference Loss

R/W

0x070C

Module 2 Interrupt Vector 4 - Phase Lock

R/W

0x0710

Module 2 Interrupt Vector 5 - Reserved

R/W

0x0714

Module 2 Interrupt Vector 6 - Overcurrent

R/W

0x0718 to 0x077C

Module 2 Interrupt Vector 7-32 - Reserved

R/W

0x0800

Module 2 Interrupt Steering 1 - BIT

R/W

0x0804

Module 2 Interrupt Steering 2 - Signal Loss

R/W

0x0808

Module 2 Interrupt Steering 3 - Reference Loss

R/W

0x080C

Module 2 Interrupt Steering 4 - Phase Lock

R/W

0x0810

Module 2 Interrupt Steering 5 - Reserved

R/W

0x0814

Module 2 Interrupt Steering 6 - Overcurrent

R/W

0x0818 to 0x087C

Module 2 Interrupt Steering 7-32 - Reserved

R/W

0x0900

Module 3 Interrupt Vector 1 - BIT

R/W

0x0904

Module 3 Interrupt Vector 2 - Signal Loss

R/W

0x0908

Module 3 Interrupt Vector 3 - Reference Loss

R/W

0x090C

Module 3 Interrupt Vector 4 - Phase Lock

R/W

0x0910

Module 3 Interrupt Vector 5 - Reserved

R/W

0x0914

Module 3 Interrupt Vector 6 - Overcurrent

R/W

0x0918 to 0x097C

Module 3 Interrupt Vector 7-32 - Reserved

R/W

0x0A00

Module 3 Interrupt Steering 1 - BIT

R/W

0x0A04

Module 3 Interrupt Steering 2 - Signal Loss

R/W

0x0A08

Module 3 Interrupt Steering 3 - Reference Loss

R/W

0x0A0C

Module 3 Interrupt Steering 4 - Phase Lock

R/W

0x0A10

Module 3 Interrupt Steering 5 - Reserved

R/W

0x0A14

Module 3 Interrupt Steering 6 - Overcurrent

R/W

0x0A18 to 0x0A7C

Module 3 Interrupt Steering 7-32 - Reserved

R/W

0x0B00

Module 4 Interrupt Vector 1 - BIT

R/W

0x0B04

Module 4 Interrupt Vector 2 - Signal Loss

R/W

0x0B08

Module 4 Interrupt Vector 3 - Reference Loss

R/W

0x0B0C

Module 4 Interrupt Vector 4 - Phase Lock

R/W

0x0B10

Module 4 Interrupt Vector 5 - Reserved

R/W

0x0B14

Module 4 Interrupt Vector 6 - Overcurrent

R/W

0x0B18 to 0x0B7C

Module 4 Interrupt Vector 7-32 - Reserved

R/W

0x0C00

Module 4 Interrupt Steering 1 - BIT

R/W

0x0C04

Module 4 Interrupt Steering 2 - Signal Loss

R/W

0x0C08

Module 4 Interrupt Steering 3 - Reference Loss

R/W

0x0C0C

Module 4 Interrupt Steering 4 - Phase Lock

R/W

0x0C10

Module 4 Interrupt Steering 5 - Reserved

R/W

0x0C14

Module 4 Interrupt Steering 6 - Overcurrent

R/W

0x0C18 to 0x0C7C

_Module 4 Interrupt Steering 7-32 - Reserved _

R/W

0x0D00

Module 5 Interrupt Vector 1 - BIT

R/W

0x0D04

Module 5 Interrupt Vector 2 - Signal Loss

R/W

0x0D08

Module 5 Interrupt Vector 3 - Reference Loss

R/W

0x0D0C

Module 5 Interrupt Vector 4 - Phase Lock

R/W

0x0D10

Module 5 Interrupt Vector 5 - Reserved

R/W

0x0D14

Module 5 Interrupt Vector 6 - Overcurrent

R/W

0x0D18 to 0x0D7C

Module 5 Interrupt Vector 7-32 - Reserved

R/W

0x0E00

Module 5 Interrupt Steering 1 - BIT

R/W

0x0E04

Module 5 Interrupt Steering 2 - Signal Loss

R/W

0x0E08

Module 5 Interrupt Steering 3 - Reference Loss

R/W

0x0E0C

Module 5 Interrupt Steering 4 - Phase Lock

R/W

0x0E10

Module 5 Interrupt Steering 5 - Reserved

R/W

0x0E14

Module 5 Interrupt Steering 6 - Overcurrent

R/W

0x0E18 to 0x0E7C

Module 5 Interrupt Steering 7-32 - Reserved

R/W

0x0F00

Module 6 Interrupt Vector 1 - BIT

R/W

0x0F04

Module 6 Interrupt Steering 2 - Signal Loss

R/W

0x0F08

Module 6 Interrupt Steering 3 - Reference Loss

R/W

0x0F0C

Module 6 Interrupt Steering 4 - Phase Lock

R/W

0x0F10

Module 6 Interrupt Steering 5 - Reserved

R/W

0x0F14

Module 6 Interrupt Steering 6 - Overcurrent

R/W

0x0F18 to 0x0F7C

Module 6 Interrupt Vector 7-32 - Reserved

R/W

0x1000

Module 6 Interrupt Steering 1 - BIT

R/W

0x1004

Module 6 Interrupt Steering 2 - Signal Loss

R/W

0x1008

Module 6 Interrupt Steering 3 - Reference Loss

R/W

0x100C

Module 6 Interrupt Steering 4 - Phase Lock

R/W

0x1010

Module 6 Interrupt Steering 5 - Reserved

R/W

0x1014

Module 6 Interrupt Steering 6 - Overcurrent

R/W

0x1018 to 0x107C

Module 6 Interrupt Steering 7-32 - Reserved

R/W

APPENDIX: PIN-OUT DETAILS

Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals

Module Signal (Ref Only)

D/L( R )VDT-2CH (DLX)

D/L( R )VDT-3CH (DLX)

DATIO1

CH1_A-Lo

CH1_A-Hi

DATIO2

RHI-CH1

DATIO3

CH1_SNS_A-Lo

CH1_SNS_A-Hi

DATIO4

RLO-CH1

DATIO5

CH1_A-Hi

CH1_A-Lo

DATIO6

CH1_B-Hi

CH2_A-Lo

DATIO7

CH1_SNS_A-Hi

CH1_SNS_B-Hi

DATIO8

CH1_SNS_B-Hi

RHI-CH2

DATIO9

CH1_B-Hi

DATIO10

CH1_SNS_B-Lo

RLO-CH2

DATIO11

CH1_B-Lo

DATIO12

CH1_B-Lo

CH2_A-Hi

DATIO13

CH2_B-Lo

CH3_A-Hi

DATIO14

CH2_A-Lo

RHI-CH3

DATIO15

CH2_SNS_B-Lo

CH3_SNS_A-Hi

DATIO16

CH2_SNS_A-Lo

RLO-CH3

DATIO17

CH2_B-Hi

CH3_A-Lo

DATIO18

CH2_A-Hi

CH2_B-Hi

DATIO19

CH2_SNS_B-Hi

CH3_B-Lo

DATIO20

CH2_SNS_A-Hi

CH2_B-Lo

DATIO21

CH3_SNS_B-Lo

DATIO22

RHI-CH2

CH2_SNS_B-Lo

DATIO23

CH3_B-Hi

DATIO24

RLO-CH2

DATIO25

CH1_SNS_A-Lo

DATIO26

CH2_SNS_A-Lo

DATIO27

CH1_SNS_B-Lo

DATIO28

CH2_SNS_A-Hi

DATIO29

CH3_SNS_A-Lo

DATIO30

CH2_SNS_B-Hi

DATIO31

CH3_SNS_B-Hi

DATIO32

DATIO33

DATIO34

DATIO35

DATIO36

DATIO37

DATIO38

DATIO39

DATIO40

N/A

STATUS AND INTERRUPTS

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Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.

For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.

Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.

Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).

Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.

Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).

Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edgetriggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Interrupt Trigger Types

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

Dynamic and Latched Status Registers Examples

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

No Clearing of Latched Status

Clearing of Latched Status (Edge-Triggered)

Clearing of Latched Status (Level-Triggered)

Time

Dynamic Status

Latched Status

Action

Latched Status

Action

Latched

0x0

Read Latched Register

0x0

Read Latched Register

0x0

0x1

Read Latched Register

0x1

Write 0x1 to Latched Register

0x0

0x1

0x0

0x1

Read Latched Register

0x0

Read Latched Register

0x1

Write 0x1 to Latched Register

0x0

0x2

0x3

Read Latched Register

0x2

Read Latched Register

0x2

Write 0x2 to Latched Register

0x0

0x2

0x2

0x3

Read Latched Register

0x1

Read Latched Register

0x3

Write 0x1 to Latched Register

Write 0x3 to Latched Register

0x0

0x2

0xC

0xF

Read Latched Register

0xC

Read Latched Register

0xE

Write 0xC to Latched Register

Write 0xE to Latched Register

0x0

0xC

0xC

0xF

Read Latched Register

0x0

Read Latched

0xC

Write 0xC to Latched Register

0xC

0x4

0xF

Read Latched Register

0x0

Read Latched Register

0xC

Write 0xC to Latched Register

0x4

0x4

0xF

Read Latched Register

0x0

Read Latched Register

0x4

Interrupt Examples

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

Time

Latched Status (Edge-Triggered – Clear Multi-Channel)

Latched Status (Edge-Triggered – Clear Single Channel)

Latched Status (Level-Triggered – Clear Multi-Channel)

Action

Latched

Action

Latched

Action

Latched

T1 (Int 1)

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Write 0x1 to Latched Register

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T2.

0x1

T3 (Int 2)

Interrupt Generated Read Latched Registers

0x2

Interrupt Generated Read Latched Registers

0x2

Interrupt Generated Read Latched Registers

0x2

Write 0x2 to Latched Register

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.

0x2

T4 (Int 3)

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x3

Write 0x1 to Latched Register

Write 0x3 to Latched Register

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.

0x3

Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.

0x2

T6 (Int 4)

Interrupt Generated Read Latched Registers

0xC

Interrupt Generated Read Latched Registers

0xC

Interrupt Generated Read Latched Registers

0xE

Write 0xC to Latched Register

Write 0x4 to Latched Register

Write 0xE to Latched Register

0x0

Interrupt re-triggers Write 0x8 to Latched Register

0x8

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.

0xE

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.

0xC

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.

0x4

MODULE COMMON REGISTERS

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The registers described in this document are common to all NAI Generation 5 modules.

Module Information Registers

The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.

FPGA Version Registers

The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.

FPGA Revision

Function: FPGA firmware revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the revision of the board’s FPGA

Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

Table 13. FPGA Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

FPGA Compile Timestamp

Function: Compile Timestamp for the FPGA firmware.

Type: unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: Value corresponding to the compile timestamp of the board’s FPGA

Operational Settings: The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:

Table 14. FPGA Compile Timestamp
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
day (5-bits)					month (4-bits)				year (6-bits)						hr
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
hour (5-bits)				minutes (6-bits)						seconds (6-bits)

FPGA SerDes Revision

Function: FPGA SerDes revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the SerDes revision of the board’s FPGA

Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

Table 15. FPGA SerDes Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

FPGA Template Revision

Function: FPGA Template revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the template revision of the board’s FPGA

Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

Table 16. FPGA Template Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

FPGA Zynq Block Revision

Function: FPGA Zynq Block revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the Zynq block revision of the board’s FPGA

Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

Table 17. FPGA Zynq Block Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

Bare Metal Version Registers

The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.

Bare Metal Revision

Function: Bare Metal firmware revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the revision of the board’s Bare Metal

Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

Table 18. Bare Metal Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

Bare Metal Compile Time

Function: Provides an ASCII representation of the Date/Time for the Bare Metal compile time.

Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: Value corresponding to the ASCII representation of the compile time of the board’s Bare Metal

Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Table 19. Bare Metal Compile Time (Note: little-endian order of ASCII values)
Word 1 (Ex. 0x2079614D)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Space (0x20)								Month ('y' - 0x79)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Month ('a' - 0x61)								Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Year ('2' - 0x32)								Space (0x20)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Day ('7' - 0x37)								Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Space (0x20)								Year ('9' - 0x39)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Year ('1' - 0x31)								Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Hour ('1' - 0x31)								Space (0x20)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
'a' (0x74)								't' (0x61)
Word 5 (Ex. 0x38333A35)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Minute ('8' - 0x38)								Minute ('3' - 0x33)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
':' (0x3A)								Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
NULL (0x00)								Seconds ('2' - 0x32)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Seconds ('3' - 0x33)								':' (0x3A)

FSBL Version Registers

The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).

FSBL Revision

Function: FSBL firmware revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the revision of the board’s FSBL

Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

Table 20. FSBL Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

FSBL Compile Time

Function: Provides an ASCII representation of the Date/Time for the FSBL compile time.

Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: Value corresponding to the ASCII representation of the Compile Time of the board’s FSBL

Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time.

The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Table 21. FSBL Compile Time (Note: little-endian order of ASCII values)
Word 1 (Ex. 0x2079614D)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Space (0x20)								Month ('y' - 0x79)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Month ('a' - 0x61)								Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Year ('2' - 0x32)								Space (0x20)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Day ('7' - 0x37)								Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Space (0x20)								Year ('9' - 0x39)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Year ('1' - 0x31)								Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Hour ('1' - 0x31)								Space (0x20)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
'a' (0x74)								't' (0x61)
Word 5 (Ex. 0x38333A35)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Minute ('8' - 0x38)								Minute ('3' - 0x33)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
':' (0x3A)								Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
NULL (0x00)								Seconds ('2' - 0x32)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Seconds ('3' - 0x33)								':' (0x3A)

Module Serial Number Registers

The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.

Interface Board Serial Number

Function: Unique 128-bit identifier used to identify the interface board.

Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: Serial number of the interface board

Operational Settings: This register is for information purposes only.

Functional Board Serial Number

Function: Unique 128-bit identifier used to identify the functional board.

Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: Serial number of the functional board

Operational Settings: This register is for information purposes only.

Module Capability

Function: Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0107

Read/Write: R

Initialized Value: 0x0000 0103

Operational Settings: A “1” in the bit associated with the capability indicates that it is supported.

Table 22. Module Capability
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	Flt-Pt	0	0	0	0	0	Pack	FIFO Blk	Blk

Module Memory Map Revision

Function: Module Memory Map revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the Module Memory Map Revision

Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

Table 23. Module Memory Map Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

Module Measurement Registers

The registers in this section provide module temperature measurement information.

Temperature Readings Registers

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.

Interface Board Current Temperature

Function: Measured PCB and Zynq Core temperatures on Interface Board.

Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R

Initialized Value: Value corresponding to the measured PCB and Zynq core temperatures based on the table below

Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.

Table 24. Interface Board Current Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
PCB Temperature								Zynq Core Temperature

Functional Board Current Temperature

Function: Measured PCB temperature on Functional Board.

Type: signed byte (8-bits) for PCB

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R

Initialized Value: Value corresponding to the measured PCB on the table below

Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.

Table 25. Functional Board Current Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Interface Board Maximum Temperature

Function: Maximum PCB and Zynq Core temperatures on Interface Board since power-on.

Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R

Initialized Value: Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below

Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.

Table 26. Interface Board Maximum Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
PCB Temperature								Zynq Core Temperature

Interface Board Minimum Temperature

Function: Minimum PCB and Zynq Core temperatures on Interface Board since power-on.

Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R

Initialized Value: Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below

Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.

Table 27. Interface Board Minimum Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
PCB Temperature								Zynq Core Temperature

Functional Board Maximum Temperature

Function: Maximum PCB temperature on Functional Board since power-on.

Type: signed byte (8-bits) for PCB

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R

Initialized Value: Value corresponding to the measured PCB on the table below

Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.

Table 28. Functional Board Maximum Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Functional Board Minimum Temperature

Function: Minimum PCB temperature on Functional Board since power-on.

Type: signed byte (8-bits) for PCB

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R

Initialized Value: Value corresponding to the measured PCB on the table below

Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.

Table 29. Functional Board Minimum Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Higher Precision Temperature Readings Registers

These registers provide higher precision readings of the current Zynq and PCB temperatures.

Higher Precision Zynq Core Temperature

Function: Higher precision measured Zynq Core temperature on Interface Board.

Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Measured Zynq Core temperature on Interface Board

Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.

Table 30. Higher Precision Zynq Core Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Signed Integer Part of Temperature
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Fractional Part of Temperature

Higher Precision Interface PCB Temperature

Function: Higher precision measured Interface PCB temperature.

Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Measured Interface PCB temperature

Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.

Table 31. Higher Precision Interface PCB Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Signed Integer Part of Temperature
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Fractional Part of Temperature

Higher Precision Functional PCB Temperature

Function: Higher precision measured Functional PCB temperature.

Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Measured Functional PCB temperature

Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.

Table 32. Higher Precision Functional PCB Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Signed Integer Part of Temperature
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Fractional Part of Temperature

Module Health Monitoring Registers

The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.

Module Sensor Summary Status

Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds.

Type: unsigned binary word (32-bits)

Data Range: See table below

Read/Write: R

Initialized Value: 0

Operational Settings: This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.

Table 33. Module Sensor Summary Status
Bit(s)	Sensor
D31:D6	Reserved
D5	Functional Board PCB Temperature
D4	Interface Board PCB Temperature
D3:D0	Reserved

Module Sensor Registers

The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.

Sensor Threshold Status

Function: Reflects which threshold has been crossed

Type: unsigned binary word (32-bits)

Data Range: See table below

Read/Write: R

Initialized Value: 0

Operational Settings: The associated bit is set when the sensor reading exceed the corresponding threshold settings.

Table 34. Sensor Threshold Status
Bit(s)	Description
D31:D4	Reserved
D3	Exceeded Upper Critical Threshold
D2	Exceeded Upper Warning Threshold
D1	Exceeded Lower Critical Threshold
D0	Exceeded Lower Warning Threshold

Sensor Current Reading

Function: Reflects current reading of temperature sensor

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings: The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Minimum Reading

Function: Reflects minimum value of temperature sensor since power up

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings: The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Maximum Reading

Function: Reflects maximum value of temperature sensor since power up

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings: The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Lower Warning Threshold

Function: Reflects lower warning threshold of temperature sensor

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: Default lower warning threshold (value dependent on specific sensor)

Operational Settings: The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.

Sensor Lower Critical Threshold

Function: Reflects lower critical threshold of temperature sensor

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: Default lower critical threshold (value dependent on specific sensor)

Operational Settings: The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.

Sensor Upper Warning Threshold

Function: Reflects upper warning threshold of temperature sensor

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: Default upper warning threshold (value dependent on specific sensor)

Operational Settings: The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.

Sensor Upper Critical Threshold

Function: Reflects upper critical threshold of temperature sensor

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: Default upper critical threshold (value dependent on specific sensor)

Operational Settings: The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.

FUNCTION REGISTER MAP

Key

Bold Underline

= Measurement/Status/Board Information

Bold Italic

= Configuration/Control

Module Information Registers

0x003C

FPGA Revision

0x0030

FPGA Compile Timestamp

0x0034

FPGA SerDes Revision

0x0038

FPGA Template Revision

0x0040

FPGA Zynq Block Revision

0x0074

Bare Metal Revision

0x0080

Bare Metal Compile Time (Bit 0-31)

0x0084

Bare Metal Compile Time (Bit 32-63)

0x0088

Bare Metal Compile Time (Bit 64-95)

0x008C

Bare Metal Compile Time (Bit 96-127)

0x0090

Bare Metal Compile Time (Bit 128-159)

0x0094

Bare Metal Compile Time (Bit 160-191)

0x007C

FSBL Revision

0x00B0

FSBL Compile Time (Bit 0-31)

0x00B4

FSBL Compile Time (Bit 32-63)

0x00B8

FSBL Compile Time (Bit 64-95)

0x00BC

FSBL Compile Time (Bit 96-127)

0x00C0

FSBL Compile Time (Bit 128-159)

0x00C4

FSBL Compile Time (Bit 160-191)

0x0000

Interface Board Serial Number (Bit 0-31)

0x0004

Interface Board Serial Number (Bit 32-63)

0x0008

Interface Board Serial Number (Bit 64-95)

0x000C

Interface Board Serial Number (Bit 96-127)

0x0010

Functional Board Serial Number (Bit 0-31)

0x0014

Functional Board Serial Number (Bit 32-63)

0x0018

Functional Board Serial Number (Bit 64-95)

0x001C

Functional Board Serial Number (Bit 96-127)

0x0070

Module Capability

0x01FC

Module Memory Map Revision

Module Measurement Registers

0x0200

Interface Board PCB/Zynq Current Temperature

0x0208

Functional Board PCB Current Temperature

0x0218

Interface Board PCB/Zynq Max Temperature

0x0228

Interface Board PCB/Zynq Min Temperature

0x0218

Functional Board PCB Max Temperature

0x0228

Functional Board PCB Min Temperature

0x02C0

Higher Precision Zynq Core Temperature

0x02C4

Higher Precision Interface PCB Temperature

0x02E0

Higher Precision Functional PCB Temperature

Module Health Monitoring Registers

0x07F8

Module Sensor Summary Status

Revision History

Module Manual - DL1-DLN Revision History

Revision

Revision Date

Description

2022-07-12

ECO C09303, transition to docbuilder format. Replaced 'Specifications' section with 'Data Sheet' section. Pg.6, defined Number of Channels. Pg.6, added additional Linearity details for DLL. Pg.6, defined Output Voltage specs. Pg.6, defined Output Load specs and added derating note. Pg.10, added Power On/Off register description. Pg.19, moved Power On/Off register offset to Control Registers section. Pg.24, added Appendix: Pin-Out Details.

Module Manual - Status and Interrupts Revision History

Revision

Revision Date

Description

2021-11-30

C08896; Transition manual to docbuilder format - no technical info change.

NAI Cares

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North Atlantic Industries (NAI) is a leading independent supplier of Embedded I/O Boards, Single Board Computers, Rugged Power Supplies, Embedded Systems and Motion Simulation and Measurement Instruments for the Military, Aerospace and Industrial Industries. We accelerate our clients’ time-to-mission with a unique approach based on a Configurable Open Systems Architecture™ (COSA®) that delivers the best of both worlds: custom solutions from standard COTS components.

We have built a reputation by listening to our customers, understanding their needs, and designing, testing and delivering board and system-level products for their most demanding air, land and sea requirements. If you have any applications or questions regarding the use of our products, please contact us for an expedient solution.

Please visit us at: www.naii.com or select one of the following for immediate assistance:

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https://www.docs.naii.com

FAQ

http://www.naii.com/faq/

Application Notes

http://www.naii.com/appNotes/

Calibration and Repairs

http://www.naii.com/calibration/

Call Us

(631) 567-1100

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1

Integrator Resources

Three-Channel LVDT Simulation

DLx DATA SHEET

INTRODUCTION

PRINCIPLE OF OPERATION

Programmable Output Format

Voltage Feedback Sense Lines

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Ch3	Ch2	Ch1