3U OpenVPX ARM Computer
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INTRODUCTION
North Atlantic Industries (NAI) is a leading independent supplier of rugged COTS embedded computing products for industrial, commercial aerospace, and defense markets. Aligned with MOSA, SOSA and FACE standards, NAI’s Configurable Open System Architecture™ (COSA®) accelerates a customer’s time-to-mission by providing the most modular, agile, and rugged COTS portfolio of embedded smart modules, I/O boards, Single Board Computers (SBCs), Power Supplies and Ruggedized Systems of its kind. COSA products are pre-engineered to work together, enabling easy changes, reuses, or repurposing down the road. By utilizing FPGAs and SoCs, NAI has created smart modules that enable the rapid creation of configurable mission systems while reducing or eliminating SBC overhead.
NAI’s 68ARM1 3U OpenVPX Single Board Computer (SBC) is a rugged processing board which provides low power, cost-sensitive processing capabilities designed for demanding aerospace, defense, and industrial applications. When combined with NAI’s smart modules, the board’s modular I/O approach makes it a highly flexible and integrable solution for demanding computing environments.
68ARM1 Overview
The 68ARM1 3U OpenVPX Single Board Computer (SBC) offers a variety of features designed to meet the needs of complex requirements for integrated multifunction I/O-intensive, mission-critical applications. Some of the key features include:
3U Profiles supported:
This board is aligned with both VPX and OpenVPX standards, with module and slot profiles specified as
-
MOD3-PAY-1F2U-16.2.11-2
-
SLT3-PAY-1F2U-14.2.12
-
This compatibility ensures interoperability with other components and promote system-level integration for efficient optimized performance.
Connection Flexibility:
The SBC provides flexibility in connectivity options, with the ability to connect to devices via the front panel, rear panel, or both. This feature is particularly useful in different mounting or space-constrained scenarios.
2x 10/100/1000 Base-T and 2x 1000Base-KX Ethernet:
The 68ARM1 provides optional 10/100/1000 Base-T Ethernet ports to the front and rear of the board and 1000Base-KX Ethernet ports to the rear of the board. These ports provide data communication capabilities and network connectivity for advanced control and data acquisition applications.
ARM® Cortex®-A9 Dual Core 800 MHz Processor:
The 68ARM1 offers a significant advantage by providing enhanced processing power and efficiency. With its dual-core configuration and 800 MHz clock speed, it enables advanced computational tasks and real-time processing capabilities, making it an ideal choice for applications requiring high performance computing within a compact form factor.
512 MB DDR3 SDRAM:
The SBC features a 512 MB DDR3 SDRAM, which offers users a dependable memory solution for demanding military, industrial, and aerospace environments:
-
DDR3 SDRAM’s capacity enables efficient data storage and retrieval for critical applications, while its DDR3 architecture ensures high-speed and low latency operation (crucial for real-time processing in dynamic environments).
-
DDR3 SDRAM’s ruggedized design and resistance to extreme temperatures/shock/vibration make it well-suited for deployment in demanding conditions, ensuring consistent and dependable performance in mission-critical scenarios.
32 GB SATA II NAND Flash:
The 68ARM1 utilizes a SATA II NAND Flash memory capable of providing up to 32 GB of storage, offering high-capacity, durable, reliable, and rugged data storage. It is well suited for applications where data must be securely stored and accessed in challenging environmental conditions while providing a cost-effective storage solution.
Less than 10 Watts Motherboard Power Dissipation:
With a power dissipation of less than 10 watts, the 68ARM1 proves a highly efficient solution, offering superior energy conservation, effective thermal management, extended mission endurance, and heightened reliability for demanding military, industrial, and aerospace applications.
Support for three independent, smart function:
The SBC can support up to three independent, smart function modules based on the COSA® architecture. With over 100 modules to choose from, this allows for a wide range of input and output capabilities, including analog and digital I/O, signal generation and acquisition, and communication interfaces. Each function module slot has an independent x1 SerDes interface for motherboard-to-smart module interface, to offload the host processor from I/O management.
-
The 68ARM1’s function slot #2 supports high-speed I/O via rear I/O while function slot #3 supports on-board module or independent external SATA II port access over the VPX backplane. These interfaces facilitate the expansion of external host SBC functions, which enables engineers and system architects to easily configure the board with the necessary modules and accelerate SWaPoptimized system deployment.
Peripheral I/O:
The 68ARM1 board features several sophisticated on-board (on motherboard) peripheral I/O interfaces, all of which are rear accessed. Designed to meet the diverse requirements of complex projects, this comprehensive I/O suite includes:
-
One USB 2.0 interface to front maintenance J5 or to the rear I/O, enabling users to transfer data quickly and reliably.
-
An RS-232 console/maintenance port (front and rear) that provides a standard interface for communicating with the board for maintenance and debugging purposes. This serial port can be used for configuring the board or accessing diagnostic information and logs.
Continuous Background Built-In-Test (BIT):
Continuously monitoring the board’s health and functionality during operation, this feature allows for proactive maintenance, minimizing downtime and facilitating early issue resolution for uninterrupted performance in demanding operational environments.
Software Support Kits (SSKs):
SSKs are provided ‘free of charge' and include base motherboard and function module API libraries and documentation. Sample and source code are also available, as well as support for real-time operating systems (RTOS) such as Wind River® VxWorks®, Xilinx® PetaLinux, and DDC-I Deos™, providing developers with flexibility and customization options for their specific application needs.
VICTORY Interface Services:
NAI offers VICTORY Interface Services as an option, providing an open industry-standard approach for integrating different components in a system.
Commercial and rugged mechanical options:
The 68ARM1 is available in both commercial and rugged models, making it suitable for a wide range of applications.
-
Operating temperature:
The board has a wide operating temperature range, with models operating from:
-
0° C to 70° C (commercial model)
-
-40° C to +85° C (rugged model)
SOFTWARE SUPPORT
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The ENAIBL Software Support Kit (SSK) is supplied with all system platform based board level products. This platform’s SSK contents include html format help documentation which defines board specific library functions and their respective parameter requirements. A board specific library and its source code is provided (module level ‘C’ and header files) to facilitate function implementation independent of user operating system (O/S). Portability files are provided to identify Board Support Package (BSP) dependent functions and help port code to other common system BSPs. With the use of the provided help documentation, these libraries are easily ported to any 32-bit O/S such as RTOS or Linux.
The latest version of a board specific SSK can be downloaded from our website www.naii.com in the software downloads section. A Quick-Start Software Manual is also available for download where the SSK contents are detailed, Quick-Start Instructions provided and GUI applications are described therein. For other operating system support, contact factory.
Specifications
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General for the Motherboard
Signal Logic Level: |
Supports LVDS PCIe ver. 3.0 bus (x1) |
Power (Motherboard): |
+12 VDC @ <1 A (est. typical) +3.3V_AUX @ <100 mA (typical) Then add power for each individual module |
Temperature, Operating: |
"C" =0° C to +70° C, "H" =-40° C to +85° C (see part number) |
Storage Temperature: |
-55° C to +105° C |
Temperature Cycling: |
Each board is cycled from -40° C to +85° C for option “H” |
General size: Height: |
3.94" / 100 mm (3U) |
Width: |
1.0” / 25.4 mm (5 HP) air cooled front panel options |
Depth: |
6.3“ / 160 mm deep |
Weight: |
21.5 oz. (610 g) unpopulated (approx.) (convection or conduction cooled) >> then add weight for each module (typically 1.5 oz. (42 g) each) |
Specifications are subject to change without notice.
Environmental
Unless otherwise specified, the following table outlines the general Environmental Specifications design guidelines for board level products of North Atlantic Industries. All our cPCI, VME and OpenVPX boards are designed for either air or conduction cooling. All boards also incorporate appropriate stiffening to ensure performance during shock and vibration but also to assure reliable operation (lower fatigue stresses) over the service life of the product.
Parameters |
Level |
||
1 / Commercial-AC (Air Cooled) |
2 / Rugged-AC (Air Cooled) |
3 / Rugged-CC (Conduction Cooled) |
|
Temperature – Operating |
0° C to 70° C, Ambient |
-40° C to 85° C, Ambient |
-40° C to 85° C, at wedge lock thermal interface |
Temperature - Storage |
-40° C to 85° C |
-55° C to 105° C |
-55° C to 105° C |
Humidity – Operating |
0 to 95%, non-condensing |
0 to 95%, non-condensing |
0 to 95%, non-condensing |
Humidity - Storage |
0 to 95%, non-condensing |
0 to 95%, non-condensing |
0 to 95%, non-condensing |
Vibration – Sine |
2 g peak, 15 Hz – 2 kHz |
6 g peak, 15 Hz – 2 kHz |
10 g peak, 15 Hz – 2 kHz |
Vibration – Random |
.002 g /Hz, 15 Hz – 2 kHz |
0.04 g /Hz, 15 Hz – 2 kHz |
0.1 g /Hz, 15 Hz – 2 kHz |
Shock |
20 g peak, half-sine, 11 ms |
30 g peak, half-sine 11 ms |
40 g peak, half-sine, 11 ms |
Low Pressure |
Up to 15,000 ft. |
Up to 50,000 ft. |
Up to 50,000 ft. |
Notes:
-
Based on sweep duration of ten minutes per axis on each of the three mutually perpendicular axes.
-
Displacement limited to 0.10 D.A. from 15 to 44 Hz.
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Displacement limited to 0.436 D.A. from 15 to 21 Hz.
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60 minutes per axis on each of the three mutually perpendicular axes.
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Per MIL-STD-810G, Method 5.14.6 Procedure I, Fig.514.6C-6 Category 7 tailored (11.65 Grms): 15 Hz – 2 kHz; ASD (PSD) at 0.04 g2/Hz between 15 Hz - 150 Hz, increasing @ 4 dB/octave from 0.04 g2/Hz to 0.1 g /Hz between 150 Hz – 300 Hz, 0.1 g2/Hz between 300 Hz - 1000 Hz, decreasing @ 6 dB/octave from 0.1 g2/Hz to 0.025 g2/Hz between 1000 Hz – 2000 Hz. Three hits per direction per axis (total of 18 hits).
-
Three hits per direction per axis (total of 18 hits).
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For altitudes higher than 50,000 ft., contact NAI.
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High temperature operation requires 350 lfm minimum air flow across cover/heatsink (module dependent).
-
High temperature operation requires 600 lfm minimum air flow across cover/heatsink (module dependent).
Specifications subject to change without notice
REGISTER MEMORY MAP ADDRESSING
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The register map address consists of the following:
-
cPCI/PCIe BAR or Base Address for the Board
-
Module Slot Base Address
-
Function Offset Address
Board Base Address
The table below lists the BAR used for access to the motherboard and module registers. The second BAR is used internally for motherboard and module firmware updates. The other cPCI/PCIe BARs not listed are not used.
NAI Boards |
Device ID |
Bus |
Motherboard and Module Register Access |
Motherboard and Module Firmware Updates |
Slave Boards |
||||
75G5 |
0x7581 |
cPCI |
BAR 0 Size: Module Dependent (minimum 64K Bytes) |
BAR 1 Size: 1M Bytes |
79G5 |
0x7981 |
PCIe |
BAR 1 Size: Module Dependent (minimum 64K Bytes) |
BAR 2 Size: 1M Bytes |
68G5/68G5P/68DT1/68CB6 |
0x6881 |
PCIe |
||
68SDP |
0x6805 |
PCIe |
||
67G6 |
0x6781 |
PCIe |
||
64G5 |
N/A |
VME |
Slave Window 1 Size: 8M Bytes Addressing: Geographical Addressing or DIP Switches on board. |
Slave Window 2 Size: 8M Bytes |
74SD5 |
0x7405 |
PMC |
64K Bytes |
N/A |
Controller/Master Boards |
||||
75G5/75ARM1 |
0x7581 |
cPCI |
BAR 0 Size: Module Dependent (minimum 64K bytes) |
BAR 1 Size: 1M bytes |
75INT2 |
0x7584 |
cPCI |
BAR 1 Size: Module Dependent (minimum 64K bytes) |
BAR 2 Size: 1M Bytes |
75PPC1 |
0x7584 |
cPCI |
||
68ARM1 |
0x6884 |
PCIe |
||
68ARM2 |
0x6886 |
PCIe |
||
68PPC2 |
0x6884 |
PCIe |
||
67PPC2 |
0x6784 |
PCIe |
||
64ARM1 |
N/A |
VME |
Slave Window 1 Size: 8M Bytes |
Slave Window 2 Size: 8M Bytes |
NANO |
||||
NIU1A |
N/A |
N/A |
Direct Memory Access |
Internal Direct Memory Access |
NIU2A |
N/A |
N/A |
||
Module Slot and Function Addresses
The memory map for the modules are dependent on the types of modules on the board and the order in which the modules are installed on the board as well as the firmware installed on the motherboard. The function modules are enumerated allowing for dynamic memory space allocation and therefore the “start” address of the module function register area is factory pre-defined (and read from) the Module Address register. Refer to Figure 1 for an example.
Motherboard Registers:
Read/Write access to the motherboard registers starts with the base address for the board and then the motherboard base offset address.
For example, to address Module Slot 1 Start Address register (i.e. register address = 0x0400):
-
Start with the base address for the board.
-
Add the motherbase register address offset.
Motherboard Address = |
Base Address + Motherboard Address Offset |
= 0x0000 0400 |
0x0000 0000 + 0x0400 |
Module Registers:
Read/Write access to the Function module’s registers start with the base address of the board. Add the “content” for the Module Start Address and then, add the specific module function register offset.
For example, to address an appropriate/specific function module with a register offset:
-
Start with the base address for the board.
-
Add the value (contents) from the module base address offset register (contents/value of Motherboard Memory register for Module 1 (i.e., @ 0x0400) = 0x4000.
-
Then add the specific module function Register Offset of interest (i.e., A/D Reading Ch 1 @ 0x1000)
(Function Specific) Address = |
Base Address |
Module Base Address Offset |
Function Register Offset |
= 0x0000 5000 |
0x0000 0000 |
0x4000 |
0x1000 |
REGISTER DESCRIPTIONS
Module Information Registers
The Module Slot Addressing Ready, Module Slot Address, Module Slot Size and Module Slot ID provide information about the modules detected on the board.
Module Slot Addressing Ready
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Function: Indicates that the module slots are ready to be addressed.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: 0xA5A5A5A5
Operational Settings: This register will contain the value of 0xA5A5A5A5 when the module addresses have been determined.
Module Slot Address
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Function: Specifies the Base Address for the module in the specific slot position.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Based on board’s module configuration.
Operational Settings: 0x0000 0000 indicates no Module found.
Module Slot Size
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Function: Specifies the Memory Size (in bytes) allocated for the module in the specific slot position.
Type: unsigned binary word (32-bit)
Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Assigned by factory for the module.
Operational Settings: 0x0000 0000 indicates no Module found.
Module Slot ID
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Function: Specifies the Model ID for the module in the specified slot position.
Type: 4-character ASCII string
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Assigned by factory for the module.
Operational Settings: The Module ID is formatted as four ASCII bytes: three characters followed by a space. Module IDs are in little-endian order with a single space following the first three characters. For example, 'TL1' is '1LT', 'SC1' is '1CS' and so forth. Example below is for “TL1” (MSB justified). All value of 0000 0000 indicates no Module found.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
ASCII Character (ex: 'T' - 0x54) |
ASCII Character (ex: 'L' - 0x4C) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
ASCII Character (ex: '1' - 0x31) |
ASCII Space (' ' - 0x20) |
||||||||||||||
Hardware Information Registers
The registers identified in this section provide information about the board’s hardware.
Product Serial Number
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Function: Specifies the Board Serial Number.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Serial number assigned by factory for the board.
Operational Settings: N/A
Platform
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Function: Specifies the Board Platform Identifier. Values are for the ASCII characters for the NAI valid platforms (Identifiers).
Type: 4-character ASCII string
Data Range: See table below.
Read/Write: R
Initialized Value: ASCII code is for the Platform Identifier of the board
Operational Settings: NAI platform for this board is shown below:
NAI Platform |
Platform Identifier |
ASCII Binary Values (Note: little-endian order of ascii values) |
6U VME |
64 |
0x0000 3436 |
6U VPX |
67 |
0x0000 3736 |
3U VPX |
68 |
0x0000 3836 |
3U VPX |
67 |
0x0000 3736 |
ARM |
N/A |
0x004D 5241 |
cPCI |
75 |
0x0000 3537 |
NIU |
00 |
0x0000 0303 |
Model
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Function: Specifies the Board Model Identifier. Values are for the ASCII characters for the NAI valid models.
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Initialized Value: ASCII code is for the Model Identifier of the board
Operational Settings: Examples of NAI models and the associated values for these models are shown below:
| NAI Model | ASCII Binary Values (Note: little-endian order of ascii values) |
|---|---|
ARM |
0x004D 5241 |
G |
0x0000 0047 |
PPC |
0x0043 5050 |
CB |
0x0000 4243 |
DT |
0x0000 5444 |
INT |
0x0054 4E49 |
NIU |
0x0055 494E |
Generation
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Function: Specifies the Board Generation. Identifier values are for the ASCII characters for the NAI valid generation identifiers.
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Initialized Value: ASCII code is for the Generation Identifier of the board
Operational Settings: Examples of NAI generations and the associated values for these generations are shown below:
| NAI Generation | ASCII Binary Values (Note: little-endian order of ascii values) |
|---|---|
1 |
0x0000 0031 |
2 |
0x0000 0032 |
3E |
0x0000 4533 |
5 |
0x0000 0035 |
6 |
0x0000 0036 |
Processor Count/Ethernet Count
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Function: Specifies the Processor Count and Ethernet Count
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Operational Settings: Processor Count - Integer: indicates the number of unique processor types on the motherboard.
| NAI Board | Processor Count | Description | |
|---|---|---|---|
VME |
64ARM1 |
1 |
Xilinx Zynq 7015 with Dual Core Cortex A9 |
64G5 |
1 |
Xilinx Zynq 7015 with Dual Core Cortex A9 |
|
3U-VPX |
68PPC2 |
2 |
NXP QorIQ T2080 Quad-Core e6500 Processor |
68ARM1 |
1 |
Xilinx Zynq 7015 with Dual Core Cortex A9 |
|
68G5 |
1 |
Xilinx Zynq 7015 |
|
68G5P |
1 |
Xilinx Zynq 7015 |
|
68ARM2 |
1 |
Xilinx Zynq UltraScale+ |
|
Ethernet Interface Count - Indicates the number of Ethernet interfaces on the product motherboard. For example, Single Ethernet = 1; Dual Ethernet = 2.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Processor Count (See Table) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ethernet Count (Based on Part Number Ethernet Options) |
|||||||||||||||
Maximum Module Slot Count/ARM Platform Type
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Function: Specifies the Maximum Module Slot Count and ARM Platform Type.
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Operational Settings:
Maximum Module Slot Count - Indicates the number of modules that can be installed on the product.
ARM Platform - Altera = 1; Xilinx X1 = 2; Xilinx X2 = 3; UltraScale = 4
| NAI Board | Maximum Module Slot Count | ARM Platform Type | |
|---|---|---|---|
VME |
64ARM1 |
6 |
Xilinx X1 = 2; Xilinx X2 = 3 |
64G5 |
6 |
Xilinx X2 = 3 |
|
3U-VPX |
68PPC2 |
2 |
Xilinx X2 = 3 |
68ARM1 |
3 |
Xilinx X2 = 3 |
|
68G5 |
3 |
Xilinx X1 = 2; Xilinx X2 = 3 |
|
68G5P |
3 |
Xilinx X2 = 3 |
|
68ARM2 |
3 |
UltraScale = 4 |
|
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Maximum Module Slot Count (See Table) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
ARM Platform Type (See Table) |
|||||||||||||||
Motherboard Firmware Information Registers
The registers in this section provide information on the revision of the firmware installed on the motherboard.
Motherboard Core (MBCore) Firmware Version
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Function: Specifies the Version of the NAI factory provided Motherboard Core Application installed on the board.
Type: Two (2) unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Operational Settings: The motherboard firmware version consists of four components: Major, Minor, Minor 2 and Minor 3.
Word 1 (Ex. 0007 0004 = 4.7 (Major.Minor) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Minor (ex: 0x0007 = 7) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Major (ex: 0x0004 = 4) |
|||||||||||||||
Word 2 (Ex. 0x0000 0000 = 0000 = 0.0 (Minor2.Minor3)) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Minor 3 (ex: 0x000 = 0) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor 2 (ex: 0x000 = 0) |
|||||||||||||||
Motherboard Firmware Build Time/Date
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Function: Specifies the Build Date/Time of the NAI factory provided Motherboard Core Application installed on the board.
Type: Two (2) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Operational Settings: The motherboard firmware time consists of the Build Date and Build Time.
|
Note
|
On some builds the the Date/Time fields are fixed to 0000 0000 to maintain binary consistency across builds. |
Word 1 - Build Date (ex. 0x030C 07E2 = 2018-12-03) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Day (ex: 0x03 = 3) |
Month (ex: 0x0C = 12) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Year (ex: 0x07E2 = 2018) |
|||||||||||||||
Word 2 - Build Time (ex. 0x001B 3B0A = 10:59:27) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
null (0x00) |
Seconds (ex: 0x1B = 27) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minutes (ex: 0x3B = 59) |
Hours (ex: 0x0A = 10) |
||||||||||||||
Motherboard Monitoring Registers
The registers in this provide motherboard voltage and temperature measurement information, and where applicable the host processor and slave processor measurements.
NAI Boards |
Bus |
Has Host Processor |
Has Slave Processor |
Controller/Master Boards |
68ARM1 |
PCIe |
No |
Zynq Core Voltage
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Function: Specifies the Measured Zynq Core Voltage.
Type: unsigned word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Measured Zynq Core Voltage (based on the conversion below)
Operational Settings: The upper 16-bits are the Integer part of the Voltage and the lower 16-bits is the Fractional part of the Voltage. For example, if the register contains the value 0x0000 03DE, this represents 0.990 Volts.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Integer part of Voltage |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional part of Voltage |
|||||||||||||||
Zynq Aux Voltage
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Function: Specifies the Measured Zynq Aux Voltage.
Type: unsigned word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Measured Zynq Aux Voltage (based on the conversion below)
Operational Settings: The upper 16-bits are the Integer part of the Voltage and the lower 16-bits is the Fractional part of the Voltage. For example, if the register contains the value 0x0001 0315, this represents 1.789 Volts.
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Integer part of Voltage |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional part of Voltage |
|||||||||||||||
Zynq DDR Voltage
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Function: Specifies the Measured Zynq DDR Voltage.
Type: unsigned word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Measured Zynq DDR Voltage (based on the conversion below)
Operational Settings: The upper 16-bits are the Integer part of the Voltage and the lower 16-bits is the Fractional part of the Voltage. For example, if the register contains the value 0x0001 00C5, this represents 1.197 Volts.
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Integer part of Voltage |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional part of Voltage |
|||||||||||||||
Slave Zynq Processor
The registers in this section apply to the boards that have slave processors (Refer to Motherboard Monitoring Registers table).
Slave Zynq Core Voltage
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Function: Specifies the Measured Zynq Core Voltage on Slave Zynq Processor.
Type: unsigned word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Measured Slave Zynq Core Voltage (based on the conversion below)
Operational Settings: The upper 16-bits are the Integer part of the Voltage and the lower 16-bits is the Fractional part of the Voltage. For example, if the register contains the value 0x0000 03DE, this represents 0.990 Volts.
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Integer part of Voltage |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional part of Voltage |
|||||||||||||||
Slave Zynq Aux Voltage
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Function: Specifies the Measured Zynq Aux Voltage on Slave Zynq Processor.
Type: unsigned word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Measured Slave Zynq Aux Voltage (based on the conversion below)
Operational Settings: The upper 16-bits are the Integer part of the Voltage and the lower 16-bits is the Fractional part of the Voltage. For example, if the register contains the value 0x0001 0315, this represents 1.789 Volts.
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Integer part of Voltage |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional part of Voltage |
|||||||||||||||
Slave Zynq DDR Voltage
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Function: Specifies the Measured Zynq DDR Voltage on Slave Zynq Processor.
Type: unsigned word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Measured Slave Zynq DDR Voltage (based on the conversion below)
Operational Settings: The upper 16-bits are the Integer part of the Voltage and the lower 16-bits is the Fractional part of the Voltage. For example, if the register contains the value 0x0001 00C5, this represents 1.197 Volts.
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Integer part of Voltage |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional part of Voltage |
|||||||||||||||
Temperature Readings Register
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The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) for the processor and PCB for Zynq processor, and Host and Slave processors measurements for boards that have these additional processors (Refer to Motherboard Monitoring Registers table).
Function: Specifies the Measured Temperatures on Motherboard.
Type: signed byte (8-bits) for each temperature reading – Six (6) 32-bit words
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the measured temperatures based on the table below.
Operational Settings: The 8-bit temperature readings are signed bytes. For example, if the following register contains the value 0x0000 5569:
Example:
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x00 |
0x00 |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Max Zynq PCB Temperature Max Zynq Core Temperature |
|||||||||||||||
The values would represent the following temperatures:
Temperature Measurements |
Data Bits |
Value |
Temperature (Celsius) |
Max Zynq PCB Temperature |
D15:D8 |
0x55 |
+85° |
Max Zynq Core Temperature |
D7:D0 |
0x69 |
+105° |
Temperature Readings
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Zynq Core Temperature |
Zynq PCB Temperature |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0x00 |
0x00 |
||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Slave Zynq Core Temperature |
Slave Zynq PCB Temperature |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0x00 |
0x00 |
||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Zynq Core Max Temp |
Zynq PCB Max Temp |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0x00 |
0x00 |
||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Max Slave Zynq Core Temperature |
Max Slave Zynq PCB Temperature |
||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Min Zynq Core Temperature |
Min Zynq Core Temperature |
||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Min Slave Zynq Core Temperature |
Min Slave Zynq Core Temperature |
||||||||||||||
Higher Precision Temperature Readings Register
These registers provide higher precision readings of the current Zynq and PCB temperatures.
Higher Precision Zynq Core Temperature
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Function: Specifies the Higher Precision Measured Zynq Core temperature on Interface Board.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Zynq Core temperature on Interface Board
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Signed Integer Part of Temperature |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional Part of Temperature |
|||||||||||||||
Higher Precision Motherboard PCB Temperature
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Function: Specifies the Higher Precision Measured Motherboard PCB temperature.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Motherboard PCB temperature
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Signed Integer Part of Temperature |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional Part of Temperature |
|||||||||||||||
Ethernet Configuration Registers
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The registers in this section provide information about the Ethernet Configuration for the two ports on the board.
Important: Regardless if the board is configured for one or two Ethernet ports, the second IP address cannot be on the same Subnet as the First IP Address. The table below provides examples of valid and invalid IP Addresses and Subnet Mask Addresses.
First Port (A) IP Address |
First Port (A) Subnet Mask |
Second Port (B) IP Address |
Second Port (B) Subnet Mask |
Result |
192.168.1.5 |
255.255.255.0 |
192.168.2.5 |
255.255.255.0 |
Good |
192.168.1.5 |
255.255.0.0 |
192.168.2.5 |
255.255.0.0 |
Conflict |
192.168.1.5 |
255.255.0.0 |
192.168.2.5 |
255.255.255.0 |
Conflict |
10.0.0.15 |
255.0.0.0 |
192.168.1.5 |
255.255.255.0 |
Good |
Ethernet MAC Address and Ethernet Settings
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Function: Specifies the Ethernet MAC Address and Ethernet Settings for the Ethernet port.
Type: Two (2) unsigned binary word (32-bit)
Data Range: See table.
Read/Write: R
Operational Settings: The Ethernet MAC Address consists of six octets. The Ethernet Settings are defined in table.
Bits |
Description |
Values |
D31:D23 |
Reserved |
0 |
D22:D21 |
Duplex |
00 = Not Specified, 01 = Half Duplex, 10 = Full Duplex, 11 = Reserved |
D20:D18 |
Speed |
000 = Not Specified, 001 = 10 Mbps, 010 = 100 Mbps, 011 = 1000 Mbps, 100 = 2500 Mbps, 101 = 10000 Mbps, 110 = Reserved, 111 = Reserved |
D17 |
Auto Negotiate |
0 = Enabled, 1 = Disabled |
D16 |
Static IP Address |
0 = Enabled, 1 = Disabled |
Word 1 (Ethernet MAC Address (Octets 1-4)) (ex: aa:bb:cc:dd:ee:ff) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
MAC Address Octet 4 (ex: 0xDD) |
MAC Address Octet 3 (ex: 0xCC) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
MAC Address Octet 2 (ex: 0xBB) |
MAC Address Octet 1 (ex: 0xAA) |
||||||||||||||
Word 2 (Ethernet MAC Address (Octets 5-6) and Ethernet Settings) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Ethernet Settings (See table) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
MAC Address Octet 6 (ex: 0xFF) |
MAC Address Octet 5 (ex: 0xEE) |
||||||||||||||
Ethernet Interface Name
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Function: Specifies the Ethernet Interface Name for the Ethernet port.
Type: 8-character ASCII string
Data Range: See table.
Read/Write: R
Operational Settings: The Ethernet Interface Name (eth0, eth1, etc) for the Ethernet port.
Word 1 (Bit 0-31) (ex: 0x3068 7465 = “0hte”) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
ASCII Character (ex: '0' - 0x30) |
ASCII Character (ex: 'h' - 0x68) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
ASCII Character (ex: 't' - 0x74) |
ASCII Character (ex: 'e' - 0x65) |
||||||||||||||
Word 2 (Bit 32-63) (ex: 0x0000 0000) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
ASCII Character (ex: null - 0x00) |
ASCII Character (ex: null - 0x00) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
ASCII Character (ex: null - 0x00) |
ASCII Character (ex: null - 0x00) |
||||||||||||||
Ethernet IPv4 Address
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Function: Specifies the Ethernet IPv4 Address for the Ethernet port.
Type: Three (3) unsigned binary word (32-bit)
Data Range: See table.
Read/Write: R
Operational Settings: The Ethernet IPv4 Address consists of three parts: IPv4 Address, IPv4 Subnet Mask and IPv4 Gateway.
Word 1 (Ethernet IPv4 Address) (ex: 0x1001 A8C0 = 192.168.1.16) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
IPv4 Address Octet 4 (ex: 0x10 = 16) |
IPv4 Address Octet 3 (ex: 0x01 = 1) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
IPv4 Address Octet 2 (ex: 0xA8 = 168) |
IPv4 Address Octet 1 (ex: 0xC0 = 192) |
||||||||||||||
Word 2 (Ethernet IPv4 Subnet) (ex: 0x00FF FFFF = 255.255.255.0) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
IPv4 Subnet Octet 4 (ex: 0x00 = 0) |
IPv4 Subnet Octet 3 (ex: 0xFF = 255) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
IPv4 Subnet Octet 2 (ex: 0xFF = 255) |
IPv4 Subnet Octet 1 (ex: 0xFF = 255) |
||||||||||||||
Word 3 (Ethernet IPv4 Gateway) (ex: 0x0101 A8C0 = 192.168.1.1) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
IPv4 Gateway Octet 4 (ex: 0x01 = 1) |
IPv4 Gateway Octet 3 (ex: 0x01 = 1) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
IPv4 Gateway Octet 2 (ex: 0xA8 = 168) |
IPv4 Gateway Octet 1 (ex: 0xC0 = 192) |
||||||||||||||
Ethernet IPv6 Address
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Function: Specifies the Ethernet IPv6 Address for the Ethernet port.
Type: Five (5) unsigned binary word (32-bit)
Data Range: See table.
Read/Write: R
Operational Settings: The IPv6 Prefix length indicates the network portion of an IPv6 address using the following format:
-
IPv6 address/prefix length
-
Prefix length can range from 0 to 128
-
Typical prefix length is 64
The following is an illustration of IPv6 addressing with IPv6 Prefix length of 64.
64 bits |
64 bits |
||||||
Prefix |
Interface ID |
||||||
Prefix 1 |
Prefix 2 |
Prefix 3 |
Subnet ID |
Interface ID 1 |
Interface ID 2 |
Interface ID 3 |
Interface ID 4 |
Example: 2002:c0a8:101:0:7c99:d118:9058:1235/64 |
|||||||
2002 |
C0A8 |
0101 |
0000 |
7C99 |
D118 |
9058 |
1235 |
Word 1 (Ethernet IPv6 Address (Prefix 1-2)) (ex:0xA8C0 0220 = 2002 C0A8) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Prefix 2 (ex: 0xA8C0 = C0A8) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Prefix 1 (ex: 0x0220 = 2002) |
|||||||||||||||
Word 2 (Ethernet IPv6 Address (Prefix 3/Subnet ID)) (ex:0x000 0101 = 0101 0000) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Subnet ID (ex: 0x0000 = 0000) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Prefix 3 (ex: 0x0101 = 0101) |
|||||||||||||||
Word 3 (Ethernet IPv6 Address (Interface ID 1-2)) (ex: 0x18D1 997C = 7C99 D118) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Interface ID 2 (ex: 0x18D1 = D118) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Interface ID 1 (ex: 0x997C = 7C99) |
|||||||||||||||
Word 4 (Ethernet IPv6 Address (Interface ID 3-4)) (ex: 0x3512 5890 = 9058 1235) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Interface ID 4 (ex: 0x3512 = 1235) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Interface ID 3 (ex: 0x5890 = 9058) |
|||||||||||||||
Word 5 (Ethernet IPv6 Prefix Length) (ex:0x0000 0040) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Prefix Length (ex: 0x0040 = 64) |
|||||||||||||||
Interrupt Vector and Steering
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When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
|
Note
|
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map). |
Interrupt Vector
Function: Set an identifier for the interrupt.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function: Sets where to direct the interrupt.
Type: unsigned binary word (32-bit)
Data Range: See table Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME |
1 |
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) |
2 |
Direct Interrupt to PCIe Bus |
5 |
Direct Interrupt to cPCI Bus |
6 |
Motherboard Health Monitoring Registers
The registers in this section provide motherboard voltage, current and temperature measurement information.
Motherboard Sensor Summary Status
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Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds.
Type: unsigned binary word (32-bits)
Data Range: See table below
Read/Write: R
Initialized Value: 0
Operational Settings: This register provides a summary for motherboard sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.
Bit(s) |
Sensor |
D31:D5 |
Reserved |
D4 |
Motherboard PCB Temperature |
D3 |
Zynq Core Temperature |
D2:D0 |
Reserved |
Motherboard Sensor Registers
The registers listed in this section apply to each module sensor listed for the Motherboard Sensor Summary Status register.
Sensor Threshold Status_
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Function: Reflects which threshold has been crossed
Type: unsigned binary word (32-bits)
Data Range: See table below
Read/Write: R
Initialized Value: 0
Operational Settings: The associated bit is set when the sensor reading exceed the corresponding threshold settings.
Bit(s) |
Description |
D31:4 |
Reserved |
D3 |
Exceeded Upper Critical Threshold |
D2 |
Exceeded Upper Warning Threshold |
D1 |
Exceeded Lower Critical Threshold |
D0 |
Exceeded Lower Warning Threshold |
Sensor Current Reading
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Function: Reflects current reading of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Minimum Reading
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Function: Reflects minimum value of temperature sensor since power up
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Maximum Reading
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Function: Reflects maximum value of temperature sensor since power up
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Lower Warning Threshold
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Function: Reflects lower warning threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default lower warning threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.
Sensor Lower Critical Threshold
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Function: Reflects lower critical threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default lower critical threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.
Sensor Upper Warning Threshold
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Function: Reflects upper warning threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default upper warning threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.
Sensor Upper Critical Threshold
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Function: Reflects upper critical threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default upper critical threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.
Module Control Command Registers
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Function: Provides the ability to command individual Modules to Reset, Power-down, or Power-up.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Operational Settings: The Module Control Commands registers provide the ability to request individual Modules to perform one of the following functions – Reset, Power-down, Power-up. Only one command can be requested at a time per Module. For example, one can’t request a Reset and a Power-down at the same time for the same Module. Once the command is recognized and handled, the bit will be cleared.
|
Note
|
Clearing of the command request bit only indicates the command has been recognized and initiated, it does not indicate that the command action has been completed. |
There is one Control Command Request register per Module. Each register is Bit-mapped as shown in the table below:
Bit(s) |
Description |
D31:D3 |
Reserved |
D2 |
Module Power-up |
D1 |
Module Power-down |
D0 |
Module Reset |
Modules Health Monitoring Registers
Module Communications Status
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Function: Provides the ability to monitor factors may effect communication status of a Module.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Operational Settings: The Module Communications registers provide the ability to monitor factors that may effect the Communications Status of individual Modules. There is one register per Module. Each communication factor is bit mapped to the register as shown in the table below:
Bit(s) |
Description |
D31:D5 |
Reserved |
D4 |
Module Communications Error Detected |
D3 |
Module Firmware Not Ready |
D2 |
Module LinkInit Not Done |
D1 |
Module Not Detected |
D0 |
Module Powered-down |
Module Powered-down: The user can request an individual Module be powered-down (see Module Control Command Requests). Once the request is detected and acted upon, this bit will be set. Once powered-down, you will not be able to communicate with the Module.
Module Not Detected: If a Module in this slot has not been detected, you will not be able to communicate with the Module.
Module LinkInit Not Done: Module communications is accomplished via SERDES. LinkInit is required to establish a connection to the Module. If the LinkInit has not been successfully completed, you will not be able to communicate with the Module.
Module Firmware Not Ready: Each Module has Firmware that is ready from Module QSPI and loaded for execution. If this Firmware was not loaded and started successfully, you may not be able to communicate with the Module.
Module Communications Error Detected: If at some point during run-time, communications with the Module has failed, this bit will be set.
Scratchpad Area
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Function: Registers reserved as scratch pad for customer use.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Operational Settings: This area in memory is reserved for customer use.
MOTHERBOARD FUNCTION REGISTER MAP
Key: Bold Underline = Measurement/Status/Board Information Bold Italic = Configuration/Control
Module Information Registers
0x03FC |
Module Slot Addressing Ready |
R |
0x0400 |
Module Slot 1 Address |
R |
0x0404 |
Module Slot 2 Address |
R |
0x0408 |
Module Slot 3 Address |
R |
0x0430 |
Module Slot 1 Size |
R |
0x0434 |
Module Slot 2 Size |
R |
0x0438 |
Module Slot 3 Size |
R |
0x0460 |
Module Slot 1 ID |
R |
0x0464 |
Module Slot 2 ID |
R |
0x0468 |
Module Slot 3 ID |
R |
Hardware Information Registers
0x0020 |
Product Serial Number |
R |
0x0024 |
Platform |
R |
0x0028 |
Model |
R |
0x002C |
Generation |
R |
0x0030 |
Processor Count/Ethernet Count |
R |
0x0034 |
Maximum Module Slot Count/ARM Platform Type |
R |
Motherboard Firmware Information Registers
0x0100 |
MBCore Major/Minor Version |
R |
0x0104 |
MBCore Minor 2/3 Version |
R |
0x0108 |
MBCore Build Date (Bit 0-31) |
R |
Motherboard Measurement Registers
0x0218 |
Zynq Core Voltage |
R |
0x021C |
Zynq Aux Voltage |
R |
0x0220 |
Zynq DDR Voltage |
R |
Boards with additional Slave Zynq Processor
0x0224 |
Slave Zynq Core Voltage |
R |
0x0228 |
Slave Zynq Aux Voltage |
R |
0x022C |
Slave DDR Voltage |
R |
Temperature Readings
| 0x0200 | Current Zynq Temperatures | R |
|---|---|---|
0x0204 |
Current Slave Zynq Temperatures |
R |
0x0208 |
Max Zynq Temperatures |
R |
0x020C |
Max Slave Zynq Temperatures |
R |
0x0210 |
Min Zynq Temperatures |
R |
0x0214 |
Min Slave Zynq Temperatures |
R |
Higher Precision Temperature Readings
0x0230 |
Current Zynq Core Temperature |
R |
0x0234 |
Current Motherboard PCB Temperture |
R |
Ethernet Configuration Registers
0x0070 |
Ethernet A MAC (Octets 1-4) |
R |
0x0074 |
Ethernet A MAC (Octets 5-6)/Misc Settings |
R |
0x0078 |
Ethernet A Interface Name (Bit 0-31) |
R |
0x007C |
Ethernet A Interface Name (Bit 32-63) |
R |
0x0080 |
Ethernet A IPv4 Address |
R |
0x0084 |
Ethernet A IPv4 Subnet Mask |
R |
0x0088 |
Ethernet A IPv4 Gateway |
R |
0x008C |
Ethernet A IPv6 Address (Prefix 1-2) |
R |
0x0090 |
Ethernet A IPv6 Address (Prefix 3/Subnet ID) |
R |
0x0094 |
Ethernet A IPv6 Address (Interface ID 1-2) |
R |
0x0098 |
Ethernet A IPv6 Address (Interface ID 3-4) |
R |
0x009C |
Ethernet A IPv6 Prefix Length |
R |
0x00A0 |
Ethernet B MAC (Octets 1-4) |
R |
0x00A4 |
Ethernet B MAC (Octets 5-6)/Misc Settings |
R |
0x00A8 |
Ethernet B Interface Name (Bit 0-31) |
R |
0x00AC |
Ethernet B Interface Name (Bit 32-63) |
R |
0x00B0 |
Ethernet B IPv4 Address |
R |
0x00B4 |
Ethernet B IPv4 Subnet Mask |
R |
0x00B8 |
Ethernet B IPv4 Gateway |
R |
0x00BC |
Ethernet B IPv6 Address (Prefix 1-2) |
R |
0x00C0 |
Ethernet B IPv6 Address (Prefix 3/Subnet ID) |
R |
0x00C4 |
Ethernet B IPv6 Address (Interface ID 1-2) |
R |
0x00C8 |
Ethernet B IPv6 Address (Interface ID 3-4) |
R |
0x00CC |
Ethernet B IPv6 Prefix Length |
R |
Interrupt Vector and Steering
0x0500 – 0x057C |
Module 1 Interrupt Vector 1 - 32 |
R/W |
0x0700 – 0x077C |
Module 2 Interrupt Vector 1 - 32 |
R/W |
0x0900 – 0x097C |
Module 3 Interrupt Vector 1 - 32 |
R/W |
0x0600 – 0x067C |
Module 1 Interrupt Steering 1 - 32 |
R/W |
0x0800 – 0x087C |
Module 2 Interrupt Steering 1 - 32 |
R/W |
0x0A00 – 0x0A7C |
Module 3 Interrupt Steering 1 - 32 |
R/W |
Motherboard Health Monitoring Registers
0x20F8 |
Motherboard/Power Supply Sensor Summary Status |
R |
0x01D8 |
Module Slot 1 Command Request |
R/W |
0x01DC |
Module Slot 2 Command Request |
R/W |
0x01E0 |
Module Slot 3 Command Request |
R/W |
Module Communications Status
0x01B8 |
Module Slot 1 Communications Status |
R |
0x01BC |
Module Slot 2 Communications Status |
R |
0x01C0 |
Module Slot 3 Communications Status |
R |
ETHERNET
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(For detailed supplement, please visit the NAI web-site specific product page and refer to: Ethernet Interface for Generation 5 SBC and Embedded IO Boards Specification)
The Ethernet Interface Option allows communications and control access to all function modules either via the system BUS or Ethernet ports 1 or 2.
Ethernet 1 |
Ethernet 2 |
|
The default IP address: |
192.168.1.16 |
192.168.2.16 |
The default subnet: |
255.255.255.0 |
255.255.255.0 |
The default gateway: |
192.168.1.1 |
192.168.2.1 |
|
Note
|
Actual "as shipped" card Ethernet default IP addresses may vary based upon final ATP configuration(s).) Ethernet Port IP addresses may be field re-flashed to new default programmed addressed via use of the “IP Configuring for Ethernet Supported Boards” FLASH software support kit, available/documented from the specific product web page. |
The NAI interface supports IPv4 and IPv6 and both the TCP and UDP protocols. The Ethernet Operation Mode Command Listener application running on the motherboard host processor implements the operation interface. The listener is operational on startup through the nai_MBStartup process and listen on specific ports for commands to process. The default ports are listed below:
-
TCP1 - Port 52801
-
TCP2 - Port 52802
-
UDP1 - Port 52801
-
UDP2 - Port 52802
While the listener is active, note that interrupts from the motherboard do not trigger. The listener can be disabled by turning off the nai_MBStartup process through the Motherboard EEPROM. To turn off nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 1 in the console, either by serial port or telnet to the motherboard, and then reboot the system. To turn on the nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 0 in the console, either by serial port or telnet to the motherboard, and then reboot the system.
Ethernet Message Framework
The interface uses a specific message framework for all commands and responses. All messages begin with a Preamble code and end with a Postamble code. The message framework is shown below.
|
Preamble 2 bytes Always 0xD30F |
SequenceNo 2 bytes |
Type Code 2 byte |
Message Length (2 bytes) |
Payload (0..1414 bytes) |
Postamble 2 bytes Always 0xF03D |
Message Elements
Preamble |
The Preamble is used to delineate the beginning of a message frame. The Preamble is always 0xD30F. |
SequenceNo |
The SequenceNo is used to associate Commands with Responses. |
Type Code |
Type Codes are used to define the type of Command or Response the message contains. |
Message Length |
The Message Length is the number of bytes in the complete message frame starting with and including the Preamble and ending with and including the Postamble. |
Payload |
The Payload contains the unique data that makes up the command or response. Payloads vary based on command type. |
Postamble |
The Postamble is use to delineate the end of a message frame. The Postamble is always 0xF03D. |
Notes
-
The messaging protocol applies only to card products.
-
Messaging is managed by the connected (client) computer. The client computer will send a single message and wait for a reply from the card. Multiple cards may be managed from a single computer, subject to channel and computer capacity.
Board Addressing
The interface provides two main addressing areas: Onboard and Off-board.
Onboard addressing refers to accessing resources located on the board that is implementing the operation interface (including its modules).
Off-board addressing refers to accessing resources located on another board reachable via VME, PCI, or other bus. Off-board addressing requires a Master/Slave configuration.
The user must always specify if a particular address is Onboard or Off-board. See the command descriptions for the onboard and off-board flags.
Within a particular board (Onboard or Off-board), the address space is broken up into two areas: Motherboard Common Address Space and Module Address Space. All addresses are 32-bit.
Motherboard Common Address Space starts at 0x00000000 and ends at 0x00004000. This is a 4Kx32-bit address space (16 kbytes).
Module Address Space starts at 0x00004000. Module addressing is dynamically configured at startup. NAI boards support between 1 and 6 modules. The minimum module address space size is 4Kx32 (16 kbytes) and module sizes are always a multiple of 4Kx32.
Module addressing is dynamic and cumulative. The first detected module (starting with Slot 1) is given an address of 0x00004000. The 2nd detected Module is given an address of:
First_Detected_Module_Address + First_Detected_Module_Size
|
Note
|
Slots do not define addresses. |
If no module is detected in a module slot, that slot is not given an address. Therefore, if the first detected Module is in Slot 2, then that module address will be 0x00004000. If the next detected module is in Slot 4, then the address of that Module will be:
Second_Detected_Module_Address = First_Detected_Module_Address + First_Detected_Module_Size
If a 3rd Module is detected in Slot 6, then the address of that Module will be:
Third_Detected_Module_Address = Second_Detected_Module_Address + Second_Detected_Module_Size
|
Note
|
Module addresses are calculated at each board startup when the modules are detected. Therefore, if a module should fail to be detected due to malfunction or because it was removed from the motherboard, the addresses of the modules that follow it in the slot sequence will be altered. This is important to note when programming to this interface. |
Users can always retrieve the Module Addresses, Module Sizes and Module IDs from the fixed Motherboard Common address area. This data is set upon each board startup. While the Module Addressing is dynamic, the address where these addresses are stored is fixed. For example, to find the startup address of the module location in Slot 3, refer to the MB Common Address 0x00000408 from the Motherboard Common Addresses table that follows.
Ethernet Wiring Convention
RJ-45 Pin |
T568A Color |
T568B Color |
10/100Base-T |
1000BASE-T |
NAI wiring convention |
1 |
white/green stripe |
white/orange stripe |
TX+ |
DA+ |
ETH-TP0+ |
2 |
green |
orange |
TX- |
DA- |
ETH-TP0- |
3 |
white/orange stripe |
white/green stripe |
RX+ |
DB+ |
ETH-TP1+ |
4 |
blue |
blue |
DC+ |
ETH-TP2+ |
|
5 |
white/blue stripe |
white/blue stripe |
DC- |
ETH-TP2- |
|
6 |
orange |
green |
RX- |
DB- |
ETH-TP1- |
7 |
white/brown stripe |
white/brown stripe |
DD+ |
ETH-TP3+ |
|
8 |
brown |
brown |
DD- |
ETH-TP3- |
68ARM1 CONNECTOR/PIN-OUT INFORMATION
Front and Rear Panel Connectors
The 68ARM1 3U OpenVPX SBC & Multifunction I/O board is available in two configurations: convection-cooled and conduction-cooled. The 68ARM1 follows the OpenVPX “Payload Slot Profile” configured as:
Slot profile: SLT3-PAY-1F2U-14.2.12
Module profile: MOD3-PAY-1F2U-16.2.11-2
User I/O is available through the (J3, J4) front panel connectors when card is configured with front panel I/O and through the OpenVPX user defined rear I/O connectors P1, P2 (see part number and pin-out information).
Notes The following notes apply unless otherwise specified:
Front Panel Connectors J3, J4 (Convection-Cooled)
50-pin male connectors, 2 mm, Harwin P/N M80-5S25022M3.
Mate kit: Harwin M80-486 product family (mating connector kit is available from Harwin as P/N M80-9415005). This mating connector may be purchased separately under NAI P/N 05-0118 (contact factory).
Utility Connector J5
Industry standard mini-HDMI type (type-C receptacle).
Panel LEDs
Front Panel LEDs indications (only available on air-cooled units).
LED |
ILLUMINATED |
EXTINGUISHED |
GRN |
Blinking: initializing Steady On: Power-On/Ready |
Power Off |
RED |
Module BIT error |
No BIT fault |
YELLOW (flashing)\ |
Card Access (bus or Gig-E activity) |
No card activity |
Chassis Ground
Front Panel: No dedicated chassis GND pins available. Jack screw sockets are chassis GND. Rear connector key guides are chassis ground.
Front Panel System (Power/Signal) Ground Reference
Front Panel: J3 pins 1, 26; J4 pins 25, 50 (connected to card power/system ground).
Front I/O Utility Connector J5 (Convection and Conduction-Cooled)
The 68ARM1 utilizes a Mini-HDMI (Type-C) type card edge connector J5, available on either convection or conduction-cooled configurations that provides the following signals:
-
USB
-
Serial (RS-232 debug/console only)
-
Ethernet port 1 (factory configuration option – Ethernet port1 may be redirected to rear I/O J2)
NAI also provides an optional “breakout” adapter board (NAI P/N 75SBC4-BB) with a mini-HDMI to mini-HDMI type cable. The “breakout” adapter board and a Micro-HDMI cable (NAI P/N 75SBC4-BB) allow for standard I/O connections to Ethernet and asynchronous serial (DB9). Consult the factory for availability.
| Front J5 | Standard Configuration |
|---|---|
J5-01 |
N/C |
J5-02 |
ETH1-TP0+ (option) |
J5-03 |
ETH1-TP0- (option) |
J5-04 |
N/C |
J5-05 |
ETH1-TP1+ (option) |
J5-06 |
ETH-TP1- (option) |
J5-07 |
N/C |
J5-08 |
ETH1-TP2+ (option) |
JT-09 |
ETH1-TP2- (option) |
J5-10 |
N/C |
J5-11 |
ETH1-TP3+ (option) |
J5-12 |
ETH1-TP3- (option) |
J5-13 |
GND |
J5-14 |
+5V-USB |
J5-15 |
USB-DP |
J5-16 |
USB-DM |
J5-17 |
SER1-RXD |
J5-18 |
SER1-TXD |
J5-19 |
GND |
|
Note
|
N/C = not connected |
Signal Name |
Description |
ETH1-TPx |
Ethernet port 1 signals (4 pair) 10/100/1000 twisted pair signals (Optional – available only if NOT re-directed to rear I/O (see part number configuration options) |
USB-DP |
Front Panel USB Data Plus |
USB-DM |
Front Panel USB Data Minus |
SER1-TXD |
Asynchronous transmit serial data port 1 (out) / RS232 debug/console port only |
SER1-RXD |
Asynchronous received serial data port 1 (in) / RS232 debug/console port only |
GND |
System Ground (return) |
Rear I/O VPX Connectors P0-P2 (Conduction-Cooled)
The 68ARM1 3U OpenVPX SBC and Multifunction I/O board provides interface via the rear VPX connectors.
Rear I/O Summary
P0 - Utility plane. Contains the following signal definitions:
-
Power: Primary +5V, +3.3V_AUX, +/- 12V and System GND
-
Geographical Address Pins: GA0# - GA4#, GAP#
-
Card reset: SYSRST# signal
-
VPX AUX/REF CLK (as/if applicable)
P1 - Defined as primarily Data/Control Planes (User defined I/O secondary)
-
High Speed Switched Fabric Interface: Root-complex ultra-thin pipes; four (4) PCIe ver. 2.0 (x1) ports.
-
Ethernet: Dual Gig-E port option(s) are available and defined (See Part Number Designation section)
P2 - User defined I/O (primary)
Rear I/O Utility Plane (P0)
UTILITY |
Row |
Row |
Row |
Row |
Row |
Row |
Row |
P0 |
G |
F |
E |
D |
C |
B |
A |
1 |
N/C (VS1_G1) |
N/C (VS1_F1) |
N/C (VS1_E1) |
N/C (NCD1) |
N/C (VS2_C1) |
N/C (VS2_B1) |
N/C (VS2_A1) |
2 |
N/C (VS1_G2) |
N/C (VS1_F2) |
N/C (VS1_E2) |
N/C (NCD2) |
N/C (VS2_C2) |
N/C (VS2_B2) |
N/C (VS2_A2) |
3 |
(+)VS3 (VS3) |
(+)VS3 (VS3) |
(+)VS3 (VS3) |
N/C (NCD3) |
(+)VS3 (VS3) |
(+)VS3 (VS3) |
(+)VS3 (VS3) |
4 |
IMPB-SCL-B (SM2) |
IMPB-SDA-B (SM3) |
GND |
(-)12V (-12V-AUX) |
GND |
P0-SYSRST# |
HDW_WP (NVMRO) |
5 |
GAP# |
GA4# |
GND |
N/C (+3.3V-AUX) |
GND |
IMPB-SCL-A (SM0) |
IMPB-SDA-A (SM1) |
6 |
GA3# |
GA2# |
GND |
(+)12V (+12V-AUX) |
GND |
GA1# |
GA0# |
7 |
N/C (TCK) |
GND |
N/C (TDO) |
N/C (TDI) |
GND |
N/C (TMS) |
N/C (TRST) |
8 |
GND |
N/C (REFCLK-25MHz-) |
N/C (REFCLK-25MHz+) |
GND |
N/C (AUX-CLK-) |
N/C (AUX-CLK+) |
GND |
Rear I/O Data/Control Planes (P1)
The 68ARM1 is a root-complex SBC with four (4) PCIe ver. 2.0 x1 high-speed serial interface fabric bus lanes. As defined in the OpenVPX payload slot specifications, the 68ARM1 provides four ‘ultra-thin pipe’ (one Tx and one Rx differential pair), which provides additional user I/O definition opportunity. Additionally, the 68ARM1 can be commanded/controlled via dual port Gig-E (options for either 10/100/1000Base-T and/or 1000Base-KX (SerDes) Interfaces). Additional module I/O is also defined on the P1 user defined plane. Signals defined as N/C currently have no functionality associated or are considered optional and are not required for general operation.
USER I/O - Defined Area (User Defined I/O) (P2)
The following pages contain the ‘user defined’ I/O data area front and rear panel pin-outs with their respective signal designations for all module types currently offered/configured for the 68ARM1 platform. The card is designed to route the function module I/O signals to the front and rear I/O connector. The following I/O connector pin-out is based upon the function module designated in the module slot. Signals defined as N/C currently have no functionality associated or are considered optional and are not required for general operation.
Data Plane |
Row |
Row |
Row |
Row |
Row |
Row |
Row |
P2 |
G |
F |
E |
D |
C |
B |
A |
1 |
MOD2-DATIO32 |
GND |
OFFBRD-SATA-TXN |
OFFBRD-SATA-TXP |
GND |
OFFBRD-SATA-RXN |
OFFBRD-SATA-RXP |
2 |
GND |
USB-GND |
+5V-USB |
GND |
USB-DM |
USB-DP |
GND |
3 |
MOD2-DATIO31 |
GND |
MOD2-DATIO24 |
MOD2-DATIO23 |
GND |
MOD2-DATIO22 |
MOD2-DATIO21 |
4 |
GND |
MOD2-DATIO20 |
MOD2-DATIO19 |
GND |
MOD2-DATIO18 |
MOD2-DATIO17 |
GND |
5 |
MOD2-DATIO30 |
GND |
MOD2-DATIO16 |
MOD2-DATIO15 |
GND |
MOD2-DATIO14 |
MOD2-DATIO13 |
6 |
GND |
MOD2-DATIO12 |
MOD2-DATIO11 |
GND |
MOD2-DATIO10 |
MOD2-DATIO09 |
GND |
7 |
MOD2-DATIO29 |
GND |
MOD2-DATIO08 |
MOD2-DATIO07 |
GND |
MOD2-DATIO06 |
MOD2-DATIO05 |
8 |
GND |
MOD2-DATIO04 |
MOD2-DATIO03 |
GND |
MOD2-DATIO02 |
MOD2-DATIO01 |
GND |
9 |
MOD2-DATIO28 |
GND |
MOD3-DATIO32 |
MOD3-DATIO31 |
GND |
MOD3-DATIO30 |
MOD3-DATIO29 |
10 |
GND |
MOD3-DATIO28 |
MOD3-DATIO27 |
GND |
MOD3-DATIO26 |
MOD3-DATIO25 |
GND |
11 |
MOD2-DATIO27 |
GND |
MOD3-DATIO24 |
MOD3-DATIO23 |
GND |
MOD3-DATIO22 |
MOD3-DATIO21 |
12 |
GND |
MOD3-DATIO20 |
MOD3-DATIO19 |
GND |
MOD3-DATIO18 |
MOD3-DATIO17 |
GND |
13 |
MOD2-DATIO26 |
GND |
MOD3-DATIO16 |
MOD3-DATIO15 |
GND |
MOD3-DATIO14 |
MOD3-DATIO13 |
14 |
GND |
MOD3-DATIO12 |
MOD3-DATIO11 |
GND |
MOD3-DATIO10 |
MOD3-DATIO09 |
GND |
15 |
MOD2-DATIO25 |
GND |
MOD3-DATIO08 |
MOD3-DATIO07 |
GND |
MOD3-DATIO06 |
MOD3-DATIO05 |
16 |
GND |
MOD3-DATIO04 |
MOD3-DATIO03 |
GND |
MOD3-DATIO02 |
MOD3-DATIO01 |
GND |
J3/J4 Front Panel Connector Pinout Mapping Summary (Convection-Cooled)
The following provides connector/pinout data for Front Panel connectors J3 and J4. Each connector provides 50 pins of I/O.
Front Panel Connectors J3/J4 Generic User I/O Mapping
(System Ground REF) |
GND |
1 |
26 |
GND |
(System Ground REF) |
M3_DAT01 |
S-MOD-M3-DAT01 |
2 |
27 |
S-MOD-M3-DAT02 |
M3_DAT02 |
M3_DAT03 |
S-MOD-M3-DAT03 |
3 |
28 |
S-MOD-M3-DAT04 |
M3_DAT04 |
M3_DAT25 |
S-MOD-M3-DAT25 |
4 |
29 |
S-MOD-M3-DAT26 |
M3_DAT26 |
M3_DAT05 |
S-MOD-M3-DAT05 |
5 |
30 |
S-MOD-M3-DAT06 |
M3_DAT06 |
M3_DAT07 |
S-MOD-M3-DAT07 |
6 |
31 |
S-MOD-M3-DAT08 |
M3_DAT08 |
M3_DAT09 |
S-MOD-M3-DAT09 |
7 |
32 |
S-MOD-M3-DAT10 |
M3_DAT10 |
M3_DAT27 |
S-MOD-M3-DAT27 |
8 |
33 |
S-MOD-M3-DAT28 |
M3_DAT28 |
M3_DAT11 |
S-MOD-M3-DAT11 |
9 |
34 |
S-MOD-M3-DAT12 |
M3_DAT12 |
M1_DAT01 |
S-MOD-M1-DAT01 |
10 |
35 |
S-MOD-M1-DAT02 |
M1_DAT02 |
M1_DAT03 |
S-MOD-M1-DAT03 |
11 |
36 |
S-MOD-M1-DAT04 |
M1_DAT04 |
M1_DAT25 |
S-MOD-M1-DAT25 |
12 |
37 |
S-MOD-M1-DAT26 |
M1_DAT26 |
M1_DAT05 |
S-MOD-M1-DAT05 |
13 |
38 |
S-MOD-M1-DAT06 |
M1_DAT06 |
M1_DAT07 |
S-MOD-M1-DAT07 |
14 |
39 |
S-MOD-M1-DAT08 |
M1_DAT08 |
M1_DAT09 |
S-MOD-M1-DAT09 |
15 |
40 |
S-MOD-M1-DAT10 |
M1_DAT10 |
M1_DAT27 |
S-MOD-M1-DAT27 |
16 |
41 |
S-MOD-M1-DAT28 |
M1_DAT28 |
M1_DAT11 |
S-MOD-M1-DAT11 |
17 |
42 |
S-MOD-M1-DAT12 |
M1_DAT12 |
M1_DAT13 |
S-MOD-M1-DAT13 |
18 |
43 |
S-MOD-M1-DAT14 |
M1_DAT14 |
M1_DAT15 |
S-MOD-M1-DAT15 |
19 |
44 |
S-MOD-M1-DAT16 |
M1_DAT16 |
M1_DAT29 |
S-MOD-M1-DAT29 |
20 |
45 |
S-MOD-M1-DAT30 |
M1_DAT30 |
M1_DAT17 |
S-MOD-M1-DAT17 |
21 |
46 |
S-MOD-M1-DAT18 |
M1_DAT18 |
M1_DAT19 |
S-MOD-M1-DAT19 |
22 |
47 |
S-MOD-M1-DAT20 |
M1_DAT20 |
M1_DAT21 |
S-MOD-M1-DAT21 |
23 |
48 |
S-MOD-M1-DAT22 |
M1_DAT22 |
M1_DAT31 |
S-MOD-M1-DAT31 |
24 |
49 |
S-MOD-M1-DAT32 |
M1_DAT32 |
M1_DAT23 |
S-MOD-M1-DAT23 |
25 |
50 |
S-MOD-M1-DAT24 |
M1_DAT24 |
M2_DAT01 |
S-MOD-M2-DAT01 |
1 |
26 |
S-MOD-M2-DAT02 |
M2_DAT02 |
M2_DAT03 |
S-MOD-M2-DAT03 |
2 |
27 |
S-MOD-M2-DAT04 |
M2_DAT04 |
M2_DAT25 |
S-MOD-M2-DAT25 |
3 |
28 |
S-MOD-M2-DAT26 |
M2_DAT26 |
M2_DAT05 |
S-MOD-M2-DAT05 |
4 |
29 |
S-MOD-M2-DAT06 |
M2_DAT06 |
M2_DAT07 |
S-MOD-M2-DAT07 |
5 |
30 |
S-MOD-M2-DAT08 |
M2_DAT08 |
M2_DAT09 |
S-MOD-M2-DAT09 |
6 |
31 |
S-MOD-M2-DAT10 |
M2_DAT10 |
M2_DAT27 |
S-MOD-M2-DAT27 |
7 |
32 |
S-MOD-M2-DAT28 |
M2_DAT28 |
M2_DAT11 |
S-MOD-M2-DAT11 |
8 |
33 |
S-MOD-M2-DAT12 |
M2_DAT12 |
M2_DAT13 |
S-MOD-M2-DAT13 |
9 |
34 |
S-MOD-M2-DAT14 |
M2_DAT14 |
M2_DAT15 |
S-MOD-M2-DAT15 |
10 |
35 |
S-MOD-M2-DAT16 |
M2_DAT16 |
M2_DAT29 |
S-MOD-M2-DAT29 |
11 |
36 |
S-MOD-M2-DAT30 |
M2_DAT30 |
M2_DAT17 |
S-MOD-M2-DAT17 |
12 |
37 |
S-MOD-M2-DAT18 |
M2_DAT18 |
M2_DAT19 |
S-MOD-M2-DAT19 |
13 |
38 |
S-MOD-M2-DAT20 |
M2_DAT20 |
M2_DAT21 |
S-MOD-M2-DAT21 |
14 |
39 |
S-MOD-M2-DAT22 |
M2_DAT22 |
M2_DAT31 |
S-MOD-M2-DAT31 |
15 |
40 |
S-MOD-M2-DAT32 |
M2_DAT32 |
M2_DAT23 |
S-MOD-M2-DAT23 |
16 |
41 |
S-MOD-M2-DAT24 |
M2_DAT24 |
M3_DAT13 |
S-MOD-M3-DAT13 |
17 |
42 |
S-MOD-M3-DAT14 |
M3_DAT14 |
M3_DAT15 |
S-MOD-M3-DAT15 |
18 |
43 |
S-MOD-M3-DAT16 |
M3_DAT16 |
M3_DAT29 |
S-MOD-M3-DAT29 |
19 |
44 |
S-MOD-M3-DAT30 |
M3_DAT30 |
M3_DAT17 |
S-MOD-M3-DAT17 |
20 |
45 |
S-MOD-M3-DAT18 |
M3_DAT18 |
M3_DAT19 |
S-MOD-M3-DAT19 |
21 |
46 |
S-MOD-M3-DAT20 |
M3_DAT20 |
M3_DAT21 |
S-MOD-M3-DAT21 |
22 |
47 |
S-MOD-M3-DAT22 |
M3_DAT22 |
M3_DAT31 |
S-MOD-M3-DAT31 |
23 |
48 |
S-MOD-M3-DAT32 |
M3_DAT32 |
M3_DAT23 |
S-MOD-M3-DAT23 |
24 |
49 |
S-MOD-M3-DAT24 |
M3_DAT24 |
(System Ground REF) |
GND |
25 |
50 |
GND |
(System Ground REF) |
Front and Rear User I/O Mapping
Front/Rear User I/O Mapping (for reference) is shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Module Operational Manuals.
Ethernet (Rear I/O)
Optional - See Part Number Designation section for specific configuration.
The 68ARM1 provides two optional Ethernet ports that can be configured as 10/100/1000Base-T or 1000Base-KX. The dual port interface option provides flexibility for OpenVPX embedded systems as the 1000-BaseKX ports can connect direct via the backplane to CPUs or Switches supporting that interface while also supporting legacy boards and external sensors or systems requiring 1000Base-T interfaces. Either Ethernet port can support either interface, however this must be configured at factory (See Part Number Designation section).
Data Plane |
Row |
Row |
Row |
Row |
Row |
Row |
Row |
P1 |
G |
F |
E |
D |
C |
B |
A |
11 |
(SER-TXD1) |
GND |
N/C (ETH2-TXN) |
N/C (ETH2-TXP) |
GND |
N/C (ETH2-RXN) |
N/C (ETH2-RXP) |
12 |
GND |
N/C (ETH1-TXN) |
N/C (ETH1-TXP) |
GND |
N/C (ETH1-RXN) |
N/C (ETH1-RXP) |
GND |
13 |
GND |
GND |
ETH2-TP1- |
ETH2-TP1+ |
GND |
ETH2-TP0- |
ETH2-TP0+ |
14 |
GND |
ETH2-TP3- |
ETH2-TP3+ |
GND |
ETH2-TP2- |
ETH2-TP2+ |
GND |
15 |
N/C |
GND |
ETH1-TP1- |
ETH1-TP1+ |
GND |
ETH1-TP0- |
ETH1-TP0+ |
16 |
GND |
ETH1-TP3- |
ETH1-TP3+ |
GND |
ETH1-TP2- |
ETH1-TP2+ |
GND |
Connector Signal/Pin outs Notes
NAI Synchro/Resolver Naming Convention
Signal |
Resolver |
Synchro |
S1 |
SIN(-) |
X |
S2 |
COS(+) |
Z |
S3 |
SIN(+) |
Y |
S4 |
COS(-) |
No connect |
Additional Pinout Notes
1. Isolated Discrete Module (DT2) |
For ‘differential' A/D; “P” designation considered ‘positive' input pin, “N” pin designation considered ‘negative' input pin. |
2. Discrete I/O Module (DT1) |
All GND pins are common within the module, but, isolated from system/power GND. Each pin should be individually wired for optimal power current distribution. |
3. TTL I/O Module (TL1) |
I/O referenced to system power GND. |
4. CMRP - A/D Module(s) (ADx) |
The Common Mode Reference Point (CMRP) is an isolated reference connection for all the A/D channels. For expected high common mode voltage applications, it is recommended that the pin designated as CMRP be referenced (direct or resistor coupled) to the signal source GND reference (must have current path between CMRP and signal source generator) to minimize common mode voltage within the acceptable specification range. All channels within the module are independent but share a CMRP, which is isolated from system/power GND. |
MECHANICAL DETAILS
General - Outline
Note: The following mechanical outline detail examples are provided for reference only. Dimensions are in inches unless otherwise specified.
SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES
Edit this on GitLab
Select the Digital-to-Synchro (DSx), Digital-to-Resolver (DRx) or Digital-to-LVDT/RVDT (DLx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. Frequency/voltage band tolerances +/- 10%. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.
-
Single Channel module pending availability (contact factory)
Module ID |
Format |
Channel(s) |
Output Voltage VL-L (Vrms) |
Reference Voltage (Vrms) |
Frequency Range (Hz) |
Power / CH maximum (VA) |
Notes |
DS1 |
SYN |
1* |
2 - 28 |
2 - 115 |
47 - 1 K |
3 |
|
DR1 |
RSL |
||||||
DL1 |
LVDT/RVDT |
||||||
DS2 |
SYN |
1* |
2 - 28 |
2 - 115 |
1 K - 5 K |
3 |
|
DR2 |
RSL |
||||||
DL2 |
LVDT/RVDT |
||||||
DS3 |
SYN |
1* |
2 - 28 |
2 - 115 |
5 K - 10 K |
3 |
|
DR3 |
RSL |
||||||
DL3 |
LVDT/RVDT |
||||||
DS4 |
SYN |
1* |
2 - 28 |
2 - 115 |
10 K - 20 K |
3 |
|
DR4 |
RSL |
||||||
DL4 |
LVDT/RVDT |
||||||
DS5 |
SYN |
1* |
28 - 90 |
2 - 115 |
47 - 1 K |
3 |
|
DR5 |
RSL |
||||||
DL5 |
LVDT/RVDT |
||||||
DSX |
SYN |
1* |
X |
X |
X |
X |
X = TBD; special configuration, requires special part number code designation, contact factory |
DRX |
RSL |
||||||
DLX |
LVDT/RVDT |
||||||
DSA |
SYN |
2 |
2 - 28 |
2 - 115 |
47 - 1 K |
1.5 |
|
DRA |
RSL |
||||||
DLA |
LVDT/RVDT |
||||||
DSB |
SYN |
2 |
2 - 28 |
2 - 115 |
1 K - 5 K |
1.5 |
|
DRB |
RSL |
||||||
DLB |
LVDT/RVDT |
||||||
DSC |
SYN |
2 |
2 - 28 |
2 - 115 |
5 K - 10 K |
1.5 |
|
DRC |
RSL |
||||||
DLC |
LVDT/RVDT |
||||||
DSD |
SYN |
2 |
2 - 28 |
2 - 115 |
10 K - 20 K |
1.5 |
|
DRD |
RSL |
||||||
DLD |
LVDT/RVDT |
||||||
DSE |
SYN |
2 |
28 - 90 |
2 - 115 |
47 - 1 K |
2.2 |
|
DRE |
RSL |
||||||
DLE |
LVDT/RVDT |
||||||
DSY |
SYN |
2 |
Y |
Y |
Y |
Y |
Y = TBD; special configuration, requires special part number code designation, contact factory |
DRY |
RSL |
||||||
DLY |
LVDT/RVDT |
||||||
DSJ |
SYN |
3 |
2 - 28 |
2 - 115 |
47 - 1 K |
0.5 |
|
DRJ |
RSL |
||||||
DLJ |
LVDT/RVDT |
||||||
DSK |
SYN |
3 |
2 - 28 |
2 - 115 |
1 K - 5 K |
0.5 |
|
DRK |
RSL |
||||||
DLK |
LVDT/RVDT |
||||||
DSL |
SYN |
3 |
2 - 28 |
2 - 115 |
5 K - 10 K |
0.5 |
|
DRL |
RSL |
||||||
DLL |
LVDT/RVDT |
||||||
DSM |
SYN |
3 |
2 - 28 |
2 - 115 |
10 K - 20 K |
0.5 |
|
DRM |
RSL |
||||||
DLM |
LVDT/RVDT |
||||||
DSN |
SYN |
3 |
28 - 90 |
2 - 115 |
47 - 1 K |
0.5 |
|
DRN |
RSL |
||||||
DLN |
LVDT/RVDT |
||||||
DSZ |
SYN |
3 |
Z |
Z |
Z |
Z |
Z = TBD; special configuration, requires special part number code designation, contact factory |
DRZ |
RSL |
||||||
DLZ |
LVDT/RVDT |
SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES
SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL)
Select the Synchro/Resolver-to-Digital (SDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.
Frequency/voltage band tolerances +/- 10%.
Module ID |
Input Voltage V (Vrms) |
Reference Voltage (Vrms) |
Frequency Range (Hz) |
Notes |
SD1 |
2 - 28 |
2 - 115 |
47 - 1 K |
|
SD2 |
2 - 28 |
2 - 115 |
1K - 5 K |
|
SD3 |
2 - 28 |
2 - 115 |
5K - 10 K |
|
SD4* |
2 - 28 |
2 - 115 |
10K - 20 K |
|
SD5 |
28 - 90 |
2 - 115 |
47 - 1 K |
|
SDX* |
X |
X |
X |
X = TBD; special configuration, requires special part number code designation, contact factory |
*Consult factory for availability
LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)
Select the LVDT/RVDT-to-Digital (LDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Excitation voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.
Frequency/voltage band tolerances +/- 10%.
Module ID |
Input Signal Voltage V (Vrms) |
Excitation Voltage (Vrms) |
Frequency Range (Hz) |
Notes |
LD1 |
2 - 28 |
2 - 115 |
47 - 1 K |
|
LD2 |
2 - 28 |
2 - 115 |
1K - 5 K |
|
LD3 |
2 - 28 |
2 - 115 |
5K - 10 K |
|
LD4* |
2 - 28 |
2 - 115 |
10K - 20 K |
|
LD5 |
28 - 90 |
2 - 115 |
47 - 1 K |
|
LDX* |
X |
X |
X |
X = TBD; special configuration, requires special part number code designation, contact factory |
*Consult factory for availability
APPENDIX: EMBEDDED ARM (XILINX® XC7Z015 SOC) OPTION DETAILS
If specified, the PLATFORM (e.g. NIU1A, 75G5, etc.) provides access to an ARM processor for embedded SBC-type applications. The platform uses a Xilinx® XC7Z015 SoC FPGA device. This device is a Single-die system on a Chip (SoC) that consists of two distinct parts: an application processor unit (APU) portion and an FPGA portion. The platform may be ordered with a configuration code, which provides access to the motherboards APU ARM processor. The application processor system can then be used for customer software development. The PLATFORM uses a Xilinx® XC7Z015 device with an ARM® Cortex®-A9 dual-core processor. The ARM processor, together with NAI’s unique architecture provides the embedded system programmer the following on- chip resources:
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APU subsystem featuring dual ARM Cortex-A9 MPCore CPUs
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DDR3 SDRAM controller with Transaction Scheduler
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DMA controller with scatter-gather
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Two Ethernet Media Access Controllers (EMACs)
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NAND flash controller ONFI specification 1.0
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Quad SPI flash controller
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Two serial peripheral interface (SPI) Master or Slave controllers
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256 KB on-chip RAM
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128 KB on-chip boot ROM
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Two UARTs with 64-byte receive and transmit FIFOs
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Two General Purpose Timers
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Two watchdog timers
Floating Point Unit (FPU)
The FPU is a VFPv3-D16 implementation of the ARMv7 floating-point architecture. It provides high performance, floating-point computation. The FPU supports all addressing modes and operations described in the “ARM Architecture Reference Manual”. The manual is available from several sources on the internet.
The FPU features are:
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Support for single-precision and double-precision floating-point formats
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Support for conversion between half-precision and single-precision
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High data transfer bandwidth through 64-bit split load and store buses
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Completion of load transfers can be performed out-of-order
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Normalized and denormalized data are all handled in hardware
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Trapless operation enabling fast execution
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Support for speculative execution
The FPU fully supports single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between floating-point data formats and ARM integer word format, with special operations to perform the conversion in round-towards-zero mode for high-level language support.
10/100/1000 Ethernet
The PLATFORM supports two 10/100/1000 base-T Ethernet connections using two Marvell Alaska 88E1510 Ethernet PHY devices and the Xilinx Gigabit Ethernet MACs. The PHY-to-MAC interface employs a Reduced Gigabit Media Independent Interface (RGMII) connection using four data lines at 250 Mbps each for a connection speed of 1 Gbps. The PLATFORM card contains internal magnetics and can directly drive copper CAT5e or CAT6 twisted pairs.
Memory
The PLATFORM supports the following memory interfaces:
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DDR3 SDRAM (APU)
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QSPI flash (APU)
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SPI flash memory I2C EEPROM
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I2C EEPROM
DDR3-SDRAM
The ARM DDR3 controller (part of the APU) is connected to a single x16-bit wide DDR3 SDRAM memory IS43TR16640 device. The IS43TR16640 is a 128 Mx16 device providing 256 Mbyte of SDRAM.
QSPI Flash (APU)
The PLATFORM supports one Spansion S25FL256S 32-MByte, Quad-SPI (QSPI) flash device. This device is used for nonvolatile storage of the ARM boot code, user data, and program. The device connects to the APU dedicated interface. The device interface may contain a secondary boot code. The device supports the Common Flash Interface (CFI). This 4-bit data memory interface can sustain burst read operations.
SPI
Serial Peripheral Interface Bus or SPI is a synchronous serial data link standard. SPI operates in full duplex mode. SPI devices communicate in master/slave mode where the master device starts a frame and sources the clock. The PLATFORM has one SPI controller. The SPI port is attached to an FM24CL64. The FM24CL64 is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process.
I2C Interface
The APU system has one I2C interface for communicating with an AT24CS02 (256 x 8) EEPROM, the PLATFORM and status LED’s.
SATA Solid-State Drive
The Xilinx APU is directly connected to an onboard Solid-State Drive (SSD). The SSD contains a single level cell NAND Flash together with a controller in a single Multi-Chip package. The Multi-Chip packaged device is soldered directly to the printed circuit board for reliable electrical and mechanical connection.
The SSD has an external write protect signal HDW_WP. The HDW_WP signal must be connected or switched to ground to enable any write to the SSD. The HDW_WP signal is pulled up on card by a 4.7 kΩ resistor to the internal 3.3 V supply.
The onboard SATA drive conforms to the follow specifications:
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Complies with Serial ATA 2.5 Specification
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Supports speeds: 1.5 Gbps (first-generation SATA), 3 Gbps (second-generation SATA and eSATA)
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Supports advanced technology attachment packet interface (ATAPI) devices
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Contains high-speed descriptor-based DMA controller
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Supports native command queuing (NCQ) commands
Application Development Overview
The FPGA uses PetaLinux Tools. PetaLinux Tools offers everything necessary to customize, build and deploy Embedded Linux solutions on Xilinx processing systems. The solution works with the Xilinx hardware design tools to ease the development of Linux systems for Zynq®-7000 SoCs.
PetaLinux Tools provides the following:
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Command-line interfaces
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Application, Device Driver & Library generators and development templates
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Bootable System image builder
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Debug agents
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GCC tools
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Integrated QEMU Full System Simulator Automated tools
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Support for Xilinx System Debugger
Linux Application Developer
As a Linux application developer, you can write code that targets the Linux OS running on the platform. PetaLinux provides a complete, reference Linux distribution that has been integrated and tested for Xilinx devices. The reference Linux distribution includes both binary and source Linux packages including:
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Boot loader
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CPU-optimized kernel
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Linux applications & libraries
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C & C++ application development
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Debug
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Thread and FPU support
Reference Manuals
Cortex-A9 Technical Reference Manual
Compiler manual
Assembler manual
Linker manual
GDB manual
Quick Start/Programmers Guide
The Quick Start Guide describes how to run an NAI sample application on an NAI ARM Linux target board and how to set up a development environment on a host PC to build a sample application using the NAI SSK Library.
Two guides are provided, one for a Linux based host and one for a Windows based host. The latest versions are provided on the NAI website.
Revision History
Motherboard Manual - 68ARM1 Revision History
Revision |
Revision Date |
Description |
C |
2024-02-21 |
ECO C11250, transition to docbuilder format. Pg.6 & 8, updated from 'over 40' to 'over 100'. Pg.6, updated general description. Pg.6, updated product image. Pg.6, updated block diagram. Pg.6, updated features; added Deos to OS support feature bullet. Pg.7-8, updated available module functions table. Pg.9-10, updated Introduction; added product overview section. Pg.11, added +3.3V_Aux to 'Power (Motherboard)'. Pg.11, removed 'E' from "Temperature Cycling". Pg.13-42, revised Addressing/Register Descriptions/Register Map sections. Pg.45, added Ethernet Wiring Convention. Pg.47/51, removed 'pending' from USB-DP/USB-DM. Pg.48, added +3.3V_Aux to 'Rear I/O Summary'. Pg.49-51, revised P0/P1/P2 & Ethernet pinout tables to meet VPX Standard format. Pg.50, added Ethernet option note. Pg.55, revised Front/Rear User I/O Mapping table to remove function modules. Pg.56, revised Ethernet pinout table to meet VPX Standard format. Pg.60, added Option 2 to 'ARM' option. Pg.61, added Single Channel note. Pg.61, changed DSE/DRE/DLE Power/CH maximum (VA) value from '1.5' to '2.2'. |
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