Rugged Mil-Aero SBC
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INTRODUCTION
North Atlantic Industries (NAI) is a leading independent supplier of rugged COTS embedded computing products for industrial, commercial aerospace, and defense markets. Aligned with MOSA, SOSA and FACE standards, NAI’s Configurable Open System Architecture™ (COSA®) accelerates a customer’s time-to-mission by providing the most modular, agile, and rugged COTS portfolio of embedded smart modules, I/O boards, Single Board Computers (SBCs), Power Supplies and Ruggedized Systems of its kind. COSA products are pre-engineered to work together, enabling easy changes, reuses, or repurposing down the road. By utilizing FPGAs and SoCs, NAI has created smart modules that enable the rapid creation of configurable mission systems while reducing or eliminating SBC overhead.
NAI’s 67PPC2 6U OpenVPX Single Board Computer (SBC) is a powerful, multifunctional processing board designed for use in mission-critical applications that require advanced I/O capabilities. When combined with these smart modules, the board’s modular I/O approach makes it a highly flexible and integrable solution for demanding computing environments.
67PPC2 Overview
The 67PPC2 6U OpenVPX Single Board Computer (SBC) offers a variety of features designed to meet the needs of complex requirements for integrated multifunction I/O-intensive, mission-critical applications. Some of the key features include:
6U Profiles supported:
This board is aligned with both VPX and OpenVPX standards, with module and slot profiles specified as
-
MOD6-PAY-2F2U2T-12.2.5-3
-
SLT6-PAY-2F2U2T-10.2.5
This compatibility ensures interoperability with other components and promote system-level integration for efficient optimized performance.
PCIe connectivity:
The 67PPC2 provides highly flexible and efficient high-speed connectivity between the board and data plane with 12 x1 PCIe interfaces (routed on the VPX (P1) connector). This feature facilitates rapid data transfer and enhances overall system efficiency. With this capability, the SBC delivers exceptional throughput and responsiveness, making it an ideal choice for applications demanding extensive data processing and communication tasks.
2x 10/100/1000 Base-T and 2x 1000Base-KX Ethernet:
The 67PPC2 provides optional 10/100/1000 Base-T Ethernet ports to the front and rear of the board and 1000Base-KX Ethernet ports to the rear of the board. These ports provide data communication capabilities and network connectivity for advanced control and data acquisition applications.
NXP® PowerPC™ QorIQ® T2080 Quad Core e6500 processor:
The 67PPC2 is powered by a NXP® PowerPC™ QorIQ® T2080 Quad Core e6500 processor which provides several benefits to applications in rugged environments such as military, aerospace, and industrial sectors:
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With four processing cores, the T2080 processor is well-suited for compute-intensive tasks. In the case of an SBC, this means the ability to handle complex data processing, real-time control, and mission-critical calculations efficiently.
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There is also support for multithreading, enabling each core to handle multiple tasks simultaneously. In applications like radar signal processing, image analysis, or communication systems, this ensures optimal utilization of the CPU, enhancing overall system performance.
-
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The processor is designed to offer a balance between performance and power consumption, making it suitable for applications that require low power consumption.
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The T2080 is designed to meet the reliability and ruggedness requirements of applications such as defense and aerospace, where the SBC may be exposed to harsh conditions.
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The T2080 includes hardware security features, which are essential for protecting sensitive military data and ensuring the integrity of mission-critical applications.
8 GB DDR3L SDRAM w/ECC memory:
The SBC features an 8 GB DDR3L SDRAM, which offers users a powerful memory solution for demanding military, industrial, and aerospace environments:
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The large memory capacity allows the 67PPC2 to handle extensive data sets, complex computations, and multitasking efficiently.
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The DDR3L SDRAM offers a good balance between performance and power efficiency, making it suitable for a range of applications, while also providing a cost-effective solution for budget-constrained projects.
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With ECC (Error Correcting Code), the SDRAM features real-time error detection and correction, which helps prevent data corruption and system crashes due to memory errors.
32 GB SATA II NAND Flash:
The 67PPC2 utilizes a SATA II NAND Flash memory capable of providing 32 GB of storage, offering high-capacity, durable, reliable, and rugged data storage. It is well suited for applications where data must be securely stored and accessed in challenging environmental conditions while providing a cost-effective storage solution.
Discrete Input (option):
The SBC features eight optional discrete input channels to the rear I/O, expanding the 67PPC’s I/O capabilities.
IPMC support (option):
The 67PPC2 has IPMC (Intelligent Platform Management Controller) support, which is VITA 46.11 Tier-2 compatible. This allows for advanced system monitoring and control from the host Chassis Manager.
Support for six independent, smart function:
The SBC can support up to six independent, smart function modules based on the COSA® architecture. With over 100 modules to choose from, this allows for a wide range of input and output capabilities, including analog and digital I/O, signal generation and acquisition, and communication interfaces. Each function module slot has an independent x1 SerDes interface for motherboard-to-smart module interface, to offload the host processor from I/O management.
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The 67PPC2’s function slots #3, 5, and 6 feature a PCIe interface that enables additional Gig-E ports while function slot #4 boasts an independent external SATA II interface that supports a 480 GB memory expansion over the VPX backplane. These interfaces facilitate the expansion of external host SBC functions, which enables engineers and system architects to easily configure the board with the necessary modules and accelerate SWaP-optimized system deployment.
Peripheral I/O:
The 67PPC2 features several sophisticated on-board (on motherboard) peripheral I/O interfaces, all of which are rear accessed. Designed to meet the diverse requirements of complex projects, this comprehensive I/O suite includes:
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One USB 2.0 interface to front maintenance J7 and two USB 3.0 interfaces to the rear I/O, enabling users to transfer data quickly and reliably.
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An optional I2C port provides a versatile serial communication interface for controlling, monitoring, and interacting with devices located at the rear of the chassis. It consists of two wires (clock and data) and allows for bidirectional communication.
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An RS-232 console/maintenance port (front and rear) that provides a standard interface for communicating with the board for maintenance and debugging purposes. This serial port can be used for configuring the board or accessing diagnostic information and logs.
Continuous Background Built-In-Test (BIT):
Continuously monitoring the board’s health and functionality during operation, this feature allows for proactive maintenance, minimizing downtime and facilitating early issue resolution for uninterrupted performance in demanding operational environments.
Software Support Kits (SSKs):
SSKs are provided 'free of charge' and include base motherboard and function module API libraries and documentation. Sample and source code are also available, as well as support for real-time operating systems (RTOS) such as Wind River® VxWorks®, DDC-I™ Deos OS, or Linux BSP/OS, providing developers with flexibility and customization options for their specific application needs.
VICTORY Interface Services:
NAI offers VICTORY Interface Services as an option, providing an open industry-standard approach for integrating different components in a system.
25 W MB power dissipation:
With an estimated typical power dissipation of 25 W (not including module power), the 67PPC2 ensures suitability for energy-sensitive applications. It minimizes heat generation, contributing to the SBC’s long-term reliability in rugged environments, in addition to making it compatible with legacy systems operating under specific power constraints.
Operating temperature and compliance:
The 67PPC2 is designed to meet system levels MIL-STD-461 (EMI) and MIL-STD-810 (vibration/shock).
Operating temperature:
The SBC has a wide operating temperature range, with models operating from:
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0° C to 70° C (commercial model)
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-40° C to +85° C (rugged model)
SOFTWARE SUPPORT
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The ENAIBL Software Support Kit (SSK) is supplied with all system platform based board level products. This platform’s SSK contents include html format help documentation which defines board specific library functions and their respective parameter requirements. A board specific library and its source code is provided (module level ‘C’ and header files) to facilitate function implementation independent of user operating system (O/S). Portability files are provided to identify Board Support Package (BSP) dependent functions and help port code to other common system BSPs. With the use of the provided help documentation, these libraries are easily ported to any 32-bit O/S such as RTOS or Linux.
The latest version of a board specific SSK can be downloaded from our website www.naii.com in the software downloads section. A Quick-Start Software Manual is also available for download where the SSK contents are detailed, Quick-Start Instructions provided and GUI applications are described therein. For other operating system support, contact factory.
SPECIFICATIONS
General for the Motherboard
Signal Logic Level: |
Supports LVDS PCIe ver. 2.0 bus (x1) |
Power (Motherboard): |
+5 VDC @ 6.3 A (typical) ±12 V @ 0 mA (certain modules may require +/-12 V for operation) +3.3V_AUX @ <100 mA (typical) Then add power for each individual module |
Temperature, Operating: |
"C" =0° C to +70° C, "H" =-40° C to +85° C (see part number) |
Storage Temperature: |
-55° C to +105° C |
Temperature Cycling: |
Each board is cycled from -40° C to +85° C for option “H” |
General size |
|
Height: |
9.2" / 233.7 mm (6U) |
Width: |
0.8” / 20.3 mm (4HP) or 1.0" / 25.4 mm (5 HP) air cooled front panel options |
Depth: |
6.3“ / 160 mm deep |
Weight: |
12.5 oz. (354 g) unpopulated (approx.) (convection or conduction cooled) >> then add weight for each module (typically 1.5 oz. (42 g) each) |
Specifications are subject to change without notice.
Environmental
Unless otherwise specified, the following table outlines the general Environmental Specifications design guidelines for board level products of North Atlantic Industries. All our cPCI, VME and OpenVPX boards are designed for either air or conduction cooling. All boards also incorporate appropriate stiffening to ensure performance during shock and vibration but also to assure reliable operation (lower fatigue stresses) over the service life of the product.
Parameters |
Level |
||
1 / Commercial-AC (Air Cooled) |
2 / Rugged-AC (Air Cooled) |
3 / Rugged-CC (Conduction Cooled) |
|
Temperature - Operating |
0° C to 70° C, AmbientH |
-40° C to 85° C, AmbientI |
-40° C to 85° C, at wedge lock thermal interface |
Temperature - Storage |
-40° C to 85° C |
-55° C to 105° C |
-55° C to 105° C |
Humidity - Operating |
0 to 95%, non-condensing |
0 to 95%, non-condensing |
0 to 95%, non-condensing |
Humidity - Storage |
0 to 95%, non-condensing |
0 to 95%, non-condensing |
0 to 95%, non-condensing |
Vibration - SineA |
2 g peak, 15 Hz - 2 kHzB |
6 g peak, 15 Hz - 2 kHzB |
10 g peak, 15 Hz - 2 kHzC |
Vibration - RandomD |
.002 g2 /Hz, 15 Hz - 2 kHz |
0.04 g2 /Hz, 15 Hz - 2 kHz |
0.1 g2 /Hz, 15 Hz - 2 kHzE |
ShockF |
20 g peak, half-sine, 11 ms |
30 g peak, half-sine 11 ms |
40 g peak, half-sine, 11 ms |
Low PressureG |
Up to 15,000 ft. |
Up to 50,000 ft. |
Up to 50,000 ft. |
Notes:
-
Based on sweep duration of ten minutes per axis on each of the three mutually perpendicular axes.
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Displacement limited to 0.10 D.A. from 15 to 44 Hz.
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Displacement limited to 0.436 D.A. from 15 to 21 Hz.
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60 minutes per axis on each of the three mutually perpendicular axes.
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Per MIL-STD-810G, Method 5.14.6 Procedure I, Fig.514.6C-6 Category 7 tailored (11.65 Grms): 15 Hz - 2 kHz; ASD (PSD) at 0.04 g2/Hz between 15 Hz - 150 Hz, increasing @ 4 dB/octave from 0.04 g2/Hz to 0.1 g /Hz between 150 Hz - 300 Hz, 0.1 g2/Hz between 300 Hz - 1000 Hz, decreasing @ 6 dB/octave from 0.1 g2/Hz to 0.025 g2/Hz between 1000 Hz - 2000 Hz. Three hits per direction per axis (total of 18 hits).
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Three hits per direction per axis (total of 18 hits).
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For altitudes higher than 50,000 ft., contact NAI.
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High temperature operation requires 350 lfm minimum air flow across cover/heatsink (module dependent).
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High temperature operation requires 600 lfm minimum air flow across cover/heatsink (module dependent).
Specifications subject to change without notice
67PPC2 OVERVIEW
The 67PPC2 is a 6U OpenVPX, low-power and high performance Single Board Computer (SBC). The 67PPC2 offers on-board I/O expansion through six (6) Generation-5 (GEN5) NAI smart I/O function modules. Powered by the NXP T2080 @ 1.8 GHz Power Architecture® processor, the 67PPC2 provides a balanced performance vs. power dissipation SBC solution, for today’s demanding, space constrained and resource limited embedded systems.
The 67PPC2 SBC, supplemented with a full complement of software I/O libraries and drivers, is ideally suited for integration within a multitude of commercial and rugged, military embedded processing and I/O systems. The 67PPC2 SBC provides a PCIe bus root-complex and/or Gigabit Ethernet (GbE) capability and may be utilized with other NAI high-density multifunction I/O boards to provide a complete, expandable, low power, high performance and programmable solution for sensor and communication data acquisition, management, processing and distribution. All I/O sensor data is available on the PCIe bus or GbE.
The 67PPC2 card provides high-density front or rear I/O for systems requiring closed chassis operation (i.e. embedded, conduction cooled applications) and simple card replacement. Using rear I/O minimizes the effort required to remove cards from a chassis improving maintainability and reliability.
The 67PPC2 card uses OpenVPX P0, P1, and P2 - P6 rear connectors. Rear I/O connectivity, via the P2 and P1 connectors, includes Ethernet, asynchronous serial, I2C, programmable TTL, USB and access to the on-board add-on Module I/O. Front I/O is limited to Expansion Module I/O.NXP QorIQ® T2080 Quad Core e6500 Processor.
The 67PPC2 utilizes the T2080 Quad Core e6500 processor with the following capabilities. Note: all processor capabilities may not be user accessible features at the end item level.
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Four e6500 cores sharing a 2MB L2 cache
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8GB of DDR3L SDRAM (plus ECC)
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2 Ethernet interfaces, supporting combinations of:
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Up to two 1 Gbps KX Ethernet MACs
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Up to two 1 Gbps TX Ethernet MACs
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Three PCIe interfaces
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12x1 PCIe ports for VPX communication
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1x1 PCIe to Module interface 3
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1x1 PCIe to switch to support Module interfaces 5 and 6 & the Zynq to R/W to module registers
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Two SATA 2.0 controllers
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32GB onboard ROM
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SATA switch for external storage or storage through Module Slot 4 (factory configured).
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Two high-speed USB 3.0 ports (Contact Factory)
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I2C port to the VPX backplane
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RS232 Serial debug port
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On-board TTL Digital I/O
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8 Discrete Input channels (0-60V)
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256 MB NOR Flash
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8 Kb FRAM
I/O Modules
Six I/O module slots enable integrators to mix-n-match a variety I/O and communication functions. The 67PPC2 uses a GEN5 high-speed SerDes Modbus. Some of the new modules are currently under development. Please consult the factory for updates on the availability of certain functions. Module I/O signals are available as both front and rear I/O.
Software
Built-In Test
The 67PPC2 supports options for Power-On-Self-Test (POST) testing (memory, peripherals, etc.). The 67PPC2 also supports function modules with NAI’s flexible, leading-edge, fully programmable and continuous background built-in-test (BIT) enabled function. BIT tests both 67PPC2 on board functions and functions contained on expansion modules, making it a useful field service tool.
U-Boot Firmware (Boot Utility/Linux®)
The U-boot firmware provides a foundation layer to interface between the raw board hardware. U-boot has programmable device set-up, setup flexibility, and supports booting supported Operating Systems with a straight-forward user interface. U-boot also allows booting from a number of different devices (check part numbering options).
Mechanicals
Heat Sink
CAUTION: The 67PPC2 contains an integrated heat sink and cover. Do not remove the heat sink. There are no user serviceable components, switches or programming jumpers under the heat sink. In the unlikely event the 67PPC2 becomes is inoperable, please return the unit to the factory for service.
67PPC2 Connector Interfaces
The 67PPC2 Conduction cooled version has eight I/O connectors P0, P1, P2 thru P6 and J7. Connectors P1, and P2 thru P6 at the rear of the module, are used for the OpenVPX interface and for user I/O. Connector J7 is utilized for GbE Ethernet interface option & RS-232 Serial debug/console access. J7 uses a Mini-HDMI connector for USB port1, asynchronous serial (debug port) and optionally Ethernet port 1. A J7 connector adapter cable/breakout board P/N 75SBC4-BB optional accessory kit is available for quick connect (contact factory).
The 67PPC2 may also be provided in an air-cooled version with front panel I/O accessibility. Please refer to part numbering options and contact factory for available mechanical options.
67PPC2 ENVIRONMENTAL/POWER SPECIFICATIONS
Conduction-Cooled/Rugged
Operating temperature |
-40 to 85° C (measured at card edge/rail) |
Storage temperature |
-55 to 105° C |
Relative humidity |
5 to 95% non-condensing |
MTBF |
TBD |
(see NAI card-level Environmental Specifications for other ruggedization & application environment levels)
Power Requirements
Power |
Tolerance |
Current requirement |
5 V |
±10% |
6.3 A typical |
+12 V-AUX |
±10% |
* |
-12 V-AUX |
±10% |
* |
3.3 V-AUX |
±10% |
100 mA typical |
RTC_STDBY |
1.5 V to 5 V ±10% |
5 µA @ 3 V Typical |
*The 67PPC2 without modules does not derive any power from the +12V and -12V backplane rail supplies. When calculating total power supply consumption, remember to add the +12, -12, and 5V power consumption for two optional modules.
67PPC2 OUTLINE DIMENSIONS
The 67PPC2 is compatible with the OpenVPX ANSI Vita 46 Specification. Conduction cooled 67PPC2 cards comply with ANSI/VITA 30.1-2002. The following diagram is for reference only. All dimensions are in inches.
67PPC2 ON BOARD RESOURCES
Memory
DDR3L SDRAM
The 67PPC2 provides a total of 8 GB of ECC DDR3L memory. This memory is organized as 8 1Gb x 8 MT41K1G8 devices (parts may vary), with a ninth device providing storage for ECC data. The T2080 has an on chip 64-bit DDR3 memory controller. The controller has full ECC error-correction support, with the ability to detect multi-bit errors and correct single-bit errors within a nibble. Please consult the Micron data sheet for DDR3 device specific details.
NOR Flash
Connected through the local bus, the 67PPC2 supports 256 Mbytes of flash. The Flash consists of a single soldered in Micron® Flash device MT28FW02GBBA1HPC device. Flash is configured as a 16-bit wide device, using the 16-bit asynchronous data access interface. The 256 MB flash is divided into two logical banks, one standard bank and one for recovery. The FPGA Local Bus controls which bank is accessible by setting the top bits of the address seen by the flash. The NOR Flash has an erase capacity of 100,000 cycles per sector and typical data retention of 20 years.
Banks
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The first bank (bank 0) is reserved for a recovery boot-loader. If the second bank is not accessible the first bank stores a full image for recovery of the system.
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The second bank (bank 1) is reserved for the boot-loader. In the default configuration, the SBC will boot from this area. The customer can modify the boot-loader if they want to and flash it in this area.
FRAM
The FM24CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. The ferroelectric random-access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years. The 67PPC2 FRAM 64K bits are organized as 8,192 x 8 bits random access memory, connected to the T2080 CPU through the SPI controller, SPI_CS [0].
SATA
The T2080 CPU has two available on-chip SATA 2 type controllers. SATA port 1 is supported with SerDes12, and SATA port 2 is supported with SerDes13. The 67PPC2 SATA port 2 is connected to an on board SATA 2 Solid State Drive. SATA2 is connected to Module Slot 4 (supports direct SATA 2 solid-state FLASH module, if fitted) or to an external storage device via a programmable switch.
SATA Port 1
The SATA port 1 controller interface on the T2080 CPU is directly connected to an on-board, solid-state drive. The SSD contains a single level cell NAND Flash together with a controller in a single multi-chip package. This multi-chip packaged device is soldered directly to the printed circuit board, for reliable electrical and mechanical connection.
The onboard SATA drive conforms to the follow specifications:
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Complies with Serial ATA 2.5 Specification
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Supports speeds: 1.5 Gbps (first-generation SATA), 3 Gbps (second-generation SATA and eSATA)
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Supports advanced technology attachment packet interface (ATAPI) devices
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Contains high-speed descriptor-based DMA controller
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Supports native command queuing (NCQ) commands
The standard ordering code for the 67PPC2 includes a 32GB SSD drive. Larger devices are available; please consult the factory for availability.
SATA Port 2
The SATA port 2 interface on the T2080 CPU is connected directly to a high-speed connector for Module Slot 4 or to an external storage device via a programmable switch. An optional SATA Flash drive is available for the 67PPC2; please consult the Factory for availability.
Peripheral I/O
Ethernet
The T2080 supports two 10/100/1000Base-TX or two 1000Base-KX Ethernet ports.
The 67PPC2 Ethernet ports support:
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Detection and correction of pair swaps (MDI crossover), and pair polarity
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MAC-side and line-side loopback
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Auto-negotiation
Ethernet port 1 can be routed as 10/100/1000Base-TX to the front, 10/100/1000Base-TX to the rear, or KX-Ethernet to the rear as build options.
Ethernet Port 2 can be routed as 10/100/1000Base-Tx to the rear or KX-Ethernet to the rear as build options.
I/O pin outs can be found in the Pinout Details section of this document.
USB
The 67PPC2 supports two USB 3.0 ports. Contact factory for availability.
USB port 0 is available at the front of 67PPC2, on connector J7. The USB port can operate as a standalone host.
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Compatible with USB specification, Rev. 2.0
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Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
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Supports operation as a standalone USB host controller
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Supports USB root hub with one downstream-facing port
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Enhanced host controller interface (EHCI)-compatible
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One controller supports operation as a standalone USB device
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Supports one upstream-facing port
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Supports six programmable USB endpoints
I2C
I2C is a two-wire, bidirectional single ended serial bus that provides efficient method of exchanging data between a master and slave device. The T2080 CPU contains three identical I2C controllers. The 67PPC2, I2C port 1 of the T2080 is connected to the die temperature monitor. I2C port 2 is connected to the real-time clock, and I2C port 3 is connected to the OpenVPX connector P2, and is available as rear I/O.
T2080 CPU I2C port |
Assignment |
I2C addresses |
Device |
Port 1 |
Onboard Devices |
0x08 & 0x70 |
Power Supply |
0x4C |
Temperature |
||
0x50 & 0x51 |
EEPROM |
||
0x57 & 6F |
RTC |
||
0x68 |
PCIe Switch |
||
Port 2 |
Rear I/O |
User Configurable |
|
Port 3 |
IPMI (contact factory) |
Not Applicable |
|
Real-Time Clock
Real-Time Clock/Calendar (RTCC) is used to provide a system time and date function or can be used as an event timer. In addition, the MCP79410 includes:
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64 Bytes SRAM, Battery Backed
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1 Kbits EEPROM (128x8)
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Power-Fail Time-Stamp for Battery Switchover
To maintain the RTCC and SRAM functions when the 5 V power is off, the RTC_STDBY pin must be connected to an external battery or power supply. The RTC_STDBY supply voltage should be between 1.4 V to 5.0 V. A typical RTC_STDBY supply requirement is 3.0 V @ 5 µA.
CAUTION: 5.5 V is the maximum allowable RTC_STDBY input voltage. Any voltage larger than 5.5 V on the RTC_STDBY pin will damage the RTCC.
Temperature Sensor
The T2080 processor has two pins that are connected to a thermal body diode on the processors die. This diode allows for direct die temperature measurements. The ADT7461 I2C device is used to measure the change in forward bias voltage (VBE) of the body diode. The ADT7461and thermal body diode together allow for direct reading of the die temperature, to an accuracy of ±1°C.
Device: |
On Semi, ADT7461ARMZ |
I2C address: |
0x4C |
SPI
Serial Peripheral Interface Bus or SPI is a synchronous serial data link standard. SPI operates in full duplex mode. SPI devices communicate in master/slave mode where the master device starts a frame and sources the clock. The T2080 CPU has one SPI controller with four device select pins (SPI_CS [3:0]). SPI_CS [0] is attached to an FRAM. SPI_C [1,2,3] are unconnected. Linux device drivers are available to access FRAM features.
T2080 CPU SPI CS |
Assignment |
Device |
SPI_CS0 |
FRAM |
FM25CL64 |
SPI_CS1 |
Not used |
|
SPI_CS2 |
Not used |
|
SPI_CS3 |
Not used |
Serial Ports
The 67PPC2 has one serial port to the front and to the rear of the card. Do not plug into the serial port from both the front and rear of the card at the same time. This will cause errors when communicating to the card through the serial port.
For U-boot, the console port is selected at compile time. The 67PPC2 is configured to use the first serial port (SER1), which is routed to the OpenVPX P1 connector at rear of the card.
For Linux, the console port is passed as a kernel parameter by U-boot when it loads Linux and so can be selected at run-time.
Inboard Discrete/TTL Options
Inboard Discrete Input & TTL I/O are available as a configuration options (see pin-outs/P/N configuration).
Discrete Input/TTL I/O Specifications
|
Note
|
The Discrete Input / TTL I/O signals are non-isolated. All grounds are common and are connected to a single Digital Ground and power return. |
REGISTER DESCRIPTIONS
The register descriptions provide the Register Name, Function Address Offset, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table. Refer also to the FPGA Local Bus Register Map.
FPGA Local Bus Register Map
Base address of FPGA Local Bus = 0xEA00 0000
Register address = Base 0xEA00 0000 + Register Offset
Name |
R/W |
Default |
|
0x00 |
SPARE |
N/A |
|
0x12 |
SPARE |
N/A |
|
0x02 |
SATA_MUX_SEL |
R/W |
1 |
0x04 |
BANK_SEL |
R/W |
0 |
0x06 |
FW_REV |
R |
REVISION |
0x08 |
TTL_DIR |
R/W |
0x"00" |
0x0A |
TTL_LPBK |
R |
0x"00" |
0x0C |
TTL_DATA |
R |
0x"XX" |
R/W |
0x"00" |
||
0x0E |
EN_PROC_RST |
W |
0 |
0x14 |
TTL_IRQ_EN |
W |
0x"00" |
0x16 |
TTL_IRQ_POL |
W |
0x"00" |
0x18 |
TTL_IRQ_STAT |
R/W |
0x"00" |
0x1A |
TEMP_ALARM_OVD |
W |
0 |
0x1C |
PWR_DWN_CMD |
W |
0x"0000" |
0x1E |
TEMP_INT_STAT |
R/W |
0 |
0x20 |
TEMP_INT_EN |
W |
0 |
0x22 |
WDT_ENABLE |
R/W |
0 |
0x24 |
WDT_TIME_SET |
R/W |
0 |
0x26 |
WDT_RESET |
W |
0 |
67PPC2 VxWorks Address Map
OFFSET (Byte) |
Name |
Size |
Function/Notes |
0x0000 0000 |
DDR3 |
2 GB |
DDR3 SDRAM |
0x7F40 0000 |
Reserved |
8 MB |
8 MB reserved memory for QMAN hardware |
0x7FC0 0000 |
Reserved |
4 MB |
4 MB reserved memory for BMAN hardware |
0x8000 0000 |
PCIe 1 prefetchable memory |
64 MB |
PCIe 1 prefetchable memory |
0x8400 0000 |
PCIe non-prefetchable memory |
64 MB |
*PCIe non-prefetchable memory |
0x8800 0000 |
PCIe 1 IO |
64 MB |
PCIe 1 I/O |
0x8C00 0000 |
PCIe 1 IO 32 |
64 MB |
PCIe 1 I/O 32 |
0x9000 0000 |
PCIe 2 non-prefetchable memory |
512 MB |
*PCIe 2 non-prefetchable memory |
0xB000 0000 |
PCIe 3 prefetchable memory |
64 MB |
PCIe 3 prefetchable memory |
0xB400 0000 |
PCIe 3 non-prefetchable memory |
128 MB |
*PCIe 3 non-prefetchable memory |
0xBC00 0000 |
PCIe 3 I/O |
32 MB |
PCIe 3 I/O |
0xBE00 0000 |
PCIe 3 I/O 32 |
32 MB |
*PCIe 3 I/O 32 |
0xC000 0000 |
PCIe 4 prefetchable memory |
64 MB |
PCIe 4 prefetchable memory |
0xC400 0000 |
PCIe non-prefetchable memory |
64 MB |
*PCIe non-prefetchable memory |
0xC800 0000 |
PCIe 4 I/O |
64 MB |
PCIe 4 I/O |
0xCC00 0000 |
PCIe 4 I/O 32 |
64 MB |
PCIe 4 I/O 32 |
0xE000 0000 |
BMAN |
32 MB |
|
0xE200 0000 |
QMAN |
32 MB |
|
0xE400 0000 |
DCSR |
4 MB |
|
0xEA00 0000 |
FPGA Registers |
4 KB |
|
0xEE00 0000 |
CCSBAR |
16 MB |
|
0xF800 0000 |
NOR FLASH |
128 MB |
|
Note
|
*Unassigned n/u |
67PPC2 U-Boot/Physical Address Map
OFFSET (Byte) |
Name |
Size |
Function/Notes |
0x0000'0000 |
DDR3 |
2GB |
Main T2080 CPU Memory |
0xE800 0000 |
NOR FLASH |
128 MB |
128 MB of NOR FLASH per bank |
0xFFDF 0000 |
FPGA Registers |
4 KB |
FPGA Registers |
0x8000 0000 |
PCIE 1 Mem |
512 MB |
* |
0xF800 0000 |
PCIe 1 I/O |
64 KB |
|
0xA000 0000 |
PCIe 2 Mem |
256 MB |
* |
0xF801 0000 |
PCIe 2 I/O |
64 KB |
|
0xB000 0000 |
PCIe 3 Mem |
256 MB |
* |
0xF802 0000 |
PCIe 3 I/O |
64 KB |
|
0xC000 0000 |
PCIe 4 Mem |
256 MB |
* |
0xF803 0000 |
PCIe 4 I/O |
64 KB |
|
0xF400 0000 |
BMAN |
32 MB |
* |
0xF600 0000 |
QMAN |
32 MB |
|
0xF000 0000 |
DCSR |
4 MB |
* |
0xFE00 0000 |
CCSRBAR |
16 MB |
|
Note
|
*Unassigned n/u |
Hardware Interrupts
The 67PPC2 uses eight external hardware interrupts. IRQ06, IRQ07, IRQ08, and IRQ09 are not available (n/a), these pins are used to support the USB ports. The T2080 hardware interrupts are assigned as indicated below.
T2080 CPU Hardware Interrupt |
Assignment |
Source |
IRQ0 |
RTC (real time clock) |
MCP79410 (MFP) |
IRQ1 |
Temperature warning |
ADT7461 (Alert#) |
IRQ2 |
ALT-INT1 |
FGPA (function TBD) |
IRQ03/GPIO21/DMA2_DREQ0 |
Ethernet PHY 1 |
BCM5482S (LED_P1_2_INTR#) |
IRQ04/GPIO22/DMA2_DACK0 |
Ethernet PHY 2 |
BCM5482S (LED_P2_2_INTR#) |
IRQ05/GPIO23/DMA2_DDONE0 |
ALT-INT2 |
PCI INTB |
IRQ06/GPIO24/USB1_DRVVBUS |
PCI INTC |
|
IRQ07/GPIO25/USB1_PWRFAULT |
PCI INTA |
|
IRQ08/GPIO26/USB2_DRVVBUS |
n/a |
|
IRQ09/GPIO27/USB2_PWRFAULT |
n/a |
|
IRQ10/GPIO28/EVT7 |
Over Temp & TTL I/O |
CLPD (temp-alarm) & TTL I/O |
IRQ11/GPIO29/EVT8 |
ALT-INT3 |
FGPA (function TBD) |
TTL Registers
Attached to the T2080 CPU via local bus is a portion of the FPGA. This logic provides miscellaneous “glue” functions and 8 programmable TTL I/O channels (TTL_CH [8:1]). (These TTL channels may be programmed as inputs or outputs as needed. Channels that are programmed as inputs may generate interrupts. Interrupts on input pins can be programmed to occur on (high to low) or (low to high) input pin transitions. TTL interrupts occur on the IRQ10 input of the T2080 CPU.
The 67PPC2 utilizes level shifting single ended bus transceivers, allowing the I/O pins to be 5 V tolerant. Each I/O pin is individually pulled up on card by a 4.7 KΩ resistor to the internal 3.3 V supply rail. External pull ups are not required for open collector operation. The TTL_CH [8:1] signals are pinned out as rear I/O on connector P2. As a factory option, the eight TTL_CH pins may be disconnected and their associated P2 pins used to support additional module I/O signals.
TTL Direction
Function: TTL direction. Sets channels as inputs or outputs. Bitmapped per TTL channel.
Function Address Offset(s): 0x08
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0x00
Operational Settings: Write 0 for input; 1 for output: Default is configured for Input. Data bits [7:0] correspond to one of eight channels TTL_CH [8:1] respectively.
D15-D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
X |
Ch.8 |
Ch.7 |
Ch.6 |
Ch.5 |
Ch.4 |
Ch.3 |
Ch.2 |
Ch.1 |
Channel |
0 |
D |
D |
D |
D |
D |
D |
D |
D |
D=DATA BIT |
TTL Data
Function: Reads the TTL state of a specific channel’s I/O pin. When configured as an output, write to this register to set the channel to drive high or low. Bitmapped per TTL channel.
Function Address Offset(s): 0x0C
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0x00
Operational Settings: When TTL_DIR register has channel configured as an input (0), read corresponding bit for the state of the TTL input. When TTL_DIR has channel configured as an output (1), write 0 for Low output/write 1 for High output: Data bits [7:0] correspond to one of eight channels TTL_CH [8:1] respectively.
|
Note
|
Reading this register returns the output to the I/O pin of a specific channel and does not return the value set to the register. Because of this, if there is impedance to the pin it may not return the proper setting. For example, if the channel is set to drive high and some impedance causes it to drive low, then this register will read low (0). To guarantee the correct setting is read, please refer to the TTL Loopback register. |
D15-D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
X |
Ch.8 |
Ch.7 |
Ch.6 |
Ch.5 |
Ch.4 |
Ch.3 |
Ch.2 |
Ch.1 |
Channel |
0 |
D |
D |
D |
D |
D |
D |
D |
D |
D=DATA BIT |
TTL Loopback
Function: Reads back TTL output channel(s) register contents. Bitmapped per TTL channel.
Function Address Offset(s): 0x0A
Type: binary word (16-bit)
Read/Write: R
Initialized Value: 0x00
Operational Settings: Reads the state of output register for each channel, regardless of the state of the I/O channel. Note
This provides the last commanded/written output value, which may differ from the TTL Data 'read' status (if there is a problem, can be used for BIT status).
D15-D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
X |
Ch.8 |
Ch.7 |
Ch.6 |
Ch.5 |
Ch.4 |
Ch.3 |
Ch.2 |
Ch.1 |
Channel |
0 |
D |
D |
D |
D |
D |
D |
D |
D |
D=DATA BIT |
TTL IRQ Enable
Function: To configure a channel as in interrupt, its corresponding TTL_DIR register must be set for inputs (0). Setting the channel’s bit in this register selects the channel to be enabled for as an interrupt. Bitmapped per TTL channel. Function Address Offset(s): 0x14
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0x00
Operational Settings: Write 1 to enable interrupts for selected channel. Write 0 for interrupts not enabled, is default.
D15-D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
X |
Ch.8 |
Ch.7 |
Ch.6 |
Ch.5 |
Ch.4 |
Ch.3 |
Ch.2 |
Ch.1 |
Channel |
0 |
D |
D |
D |
D |
D |
D |
D |
D |
D=DATA BIT |
TTL IRQ Polarity
Function: When a channel TTL IRQ Enable register bit is enabled, this register determines whether the interrupt will be generated for either a “rising edge” or “falling edge” event detection. Bitmapped per TTL channel.
Function Address Offset(s): 0x16
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0x00
Operational Settings: Write a 1 to sense on a rising edge and a 0 to sense on a falling edge
D15-D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
X |
Ch.8 |
Ch.7 |
Ch.6 |
Ch.5 |
Ch.4 |
Ch.3 |
Ch.2 |
Ch.1 |
Channel |
0 |
D |
D |
D |
D |
D |
D |
D |
D |
D=DATA BIT |
TTL IRQ Status
Function: When an interrupt for a channel or channels occurs, the corresponding bit for that channel will be set High in this register. Bitmapped.
Function Address Offset(s): 0x18
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0x00
Operational Settings: When a TTL input channel generates an interrupt, the corresponding bit in the TTL_IRQ_STAT is set High (1). Once a bit is set by a transition on the input pin, the bit remains set until cleared by a register write. Writing a (1) to the corresponding bit resets the interrupt status to (0).
D15-D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
X |
Ch.8 |
Ch.7 |
Ch.6 |
Ch.5 |
Ch.4 |
Ch.3 |
Ch.2 |
Ch.1 |
Channel |
0 |
D |
D |
D |
D |
D |
D |
D |
D |
D=DATA BIT |
Discrete Registers
On the 67PPC2, there is an option for 8 General Purpose Input signals. These signals are designed to sense grounded and open/floating inputs. They use the same channels as the TTL I/O signals, and the registers must be configured the same way as the input TTLs. The Discrete option shares the same register descriptions as the TTL input, with the addition of the Discrete Data register.
The typical input circuit is in the figure below.
Each input has a 5 K resistor in series with it, to provide input protection.
Inputs can tolerate voltages from -48 v to + 48 v.
Output logic is the inversion of the input state. An Input voltage below 3.0 volts is a valid Low input and produces a valid High output state. An Input voltage above 3.5 volts is a valid High input and produces a valid Low output state.
Each input is pulled up to 5 volts through a 14 K resistor (5 K + 9 K), with a Diode in series.
If the input is open or loaded with impedance greater than 100 K to GND, it will produce a logic Low output state.
If the input is shorted to GND or loaded with impedance to GND less than 100 Ohms, it will produce a logic High output state. In addition, each input has a bi-directional 48 v transient voltage suppressor to GND.
Discrete Data
Function: Reads the discrete input of all channel’s I/O pin.
Function Address Offset(s): 0x0C
Type: binary word (16-bit)
Read/Write: R
Initialized Value: 0x00
Operational Settings: Each GPI backplane input pin is connected to two input circuits.
Redundant input states (In xR) can also be read.
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
In 8R |
In 7R |
In 6R |
In 5R |
In 4R |
In 3R |
In 2R |
In 1R |
In 8 |
In 7 |
In 6 |
In 5 |
In 4 |
In 3 |
In 2 |
In 1 |
D=DATA BIT |
Temperature Sensing
Temperature Alarm Override Select
Function: Overrides temperature alarm auto shutdown.
Function Address Offset(s): 0x1A
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0x0000
Operational Settings: Write a 1 to override the temperature alarm automatic shutdown. Default value = 0.
D15-D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D=DATA BIT |
Temperature Alarm Interrupt Status
Function: Clears latched temperature alarm status.
Function Address Offset(s): 0x1E
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0x0000
Operational Settings: Write a 1 to clear the interrupt status. Default value = 0.
D15-D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D=DATA BIT |
Temperature Alarm Interrupt Enable
Function: Enables temperature alarm interrupt.
Function Address Offset(s): 0x20
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0x0000
Operational Settings: Write a 1 to enable the temperature alarm interrupt. Default value = 0.
D15-D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D=DATA BIT |
Power Shutdown
Power Down Command
Function: Shuts down power to the board.
Function Address Offset(s): 0x1C
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0x000
Operational Settings: Write the proper sequence of words “0xDEAD” followed by "0xC0DE" to initiate a power shutdown.
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D=DATA BIT |
Bank Select
Function: Selects the Bank to boot from.
Function Address Offset(s): 0x04
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0
Operational Settings: By default, the motherboard will boot from the second bank (bank 1). If you cannot boot the board remove the NOR jumper to force the board to boot from the first bank (bank 0). Bank 0 contains a recovery image for the board. Please view this flowchart to see how the setting of this register affects how your board boots.
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D=DATA BIT |
Processor Restart Enable
Function: Selects whether the Processor can restart the board.
Function Address Offset(s): 0x0E
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0
Operational Settings: Write a 1 to this register to enable processor restarts. If the Reset jumper is installed a reset cannot occur. Please view this flowchart to see how the setting of this register affects the operation of the board.
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D=DATA BIT |
SATA Location Select
Function: Selects whether to use external SATA storage through the backplane or module two SATA storage.
Function Address Offset(s): 0x02
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0
Operational Settings: Write a 0 to this register to use module two SATA storage. Write a 1 to use external SATA storage through the backplane.
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D=DATA BIT |
Watchdog
Watchdog Enable
Function: Enables the hardware Watchdog Timer.
Function Address Offset(s): 0x22
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0
Operational Settings: Write a 0 to this register to disable the Watchdog Timer. Write a 1 to enable the Watchdog Timer
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D=DATA BIT |
Watchdog Time Set
Function: Set the duration of the hardware Watchdog Time in “counts”. (524uS per count)
Function Address Offset(s): 0x24
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0
Operational Settings: Write a 0 to this register to disable the Watchdog Timer. Write a 1 to enable the Watchdog Timer
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D=DATA BIT |
Watchdog Reset
Function: Resets the hardware Watchdog elapsed time.
Function Address Offset(s): 0x26
Type: binary word (16-bit)
Read/Write: R/W
Initialized Value: 0
Operational Settings: Write a 1 to this register to reset the Watchdog elapsed time. This will “pet” the watchdog.
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
FUNCTION |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D=DATA BIT |
67PPC2 SOFTWARE LIBRARIES/ASSOCIATED DOCUMENTS
67PPC2 BSP processor Module Library
The 67PPC2 Processor library package provides function interfaces to the on-module functionality as well as the OpenVPX interface. This package contains Help documentation (in html format) that explains all the functions available in the library. The package also contains the source code (*.h, *.c) files as well as the files needed to build the library using Wind River Linux or other supported operating systems similar. Example programs are also provided to demonstrate the usage of the libraries in typical applications of the module.
Associated Documents
NAI Documents
*Programmer’s Reference Guide for NAI 67PPC2 Single Board Computer (TBD)
*67PPC2 Ethernet Download (TBD)
*67PPC2 USB Download (TBD)
*Standalone documents “pending/TBD”; currently, all reference documentation required are embedded within the specific OS 67PPC2 BSP/Support documentation (i.e. BSPx.x.x \ layers \ nai_bsp \ templates \ board \ nai67PPC2 \ (README) files (where x.x.x is the BSP version/revision available).
REGISTER MEMORY MAP ADDRESSING
The register map address consists of the following:
-
cPCI/PCIe BAR or Base Address for the Board
-
Module Slot Base Address
-
Function Offset Address
Board Base Address
The table below lists the BAR used for access to the motherboard and module registers. The second BAR is used internally for motherboard and module firmware updates. The other cPCI/PCIe BARs not listed are not used.
NAI Boards |
Device ID |
Bus |
Motherboard and Module Register Access |
Motherboard and Module Firmware Updates |
Controller/Master Boards |
||||
67PPC2 |
0x6784 |
PCIe |
BAR 1 Size: Module Dependent (minimum 64K Bytes) |
BAR 2 Size: 1M Bytes |
Module Slot and Function Addresses
The memory map for the modules are dependent on the types of modules on the board and the order in which the modules are installed on the board as well as the firmware installed on the motherboard. The function modules are enumerated allowing for dynamic memory space allocation and therefore the “start” address of the module function register area is factory pre-defined (and read from) the Module Address register. Refer to Figure 1 for an example.
Figure 1. Register Memory Map Addressing for Motherboards with 6 Modules
Address Calculation
Motherboard Registers
Read/Write access to the motherboard registers starts with the base address for the board and then the motherboard base offset address.
For example, to address Module Slot 1 Start Address register (i.e. register address = 0x0400):
-
Start with the base address for the board.
-
Add the motherboard base register address offset.
Motherboard Address = |
Base Address + Motherboard Address Offset |
= 0x9000 0400 |
0x9000 0000 + 0x0400 |
Module Registers:
Read/Write access to the Function module’s registers start with the base address of the board. Add the “content” for the Module Start Address and then, add the specific module function register offset.
For example, to address an appropriate/specific function module with a register offset:
-
Start with the base address for the board.
-
Add the value (contents) from the module base address offset register (contents/value of Motherboard Memory register for Module 1 (i.e., @ 0x0400) = 0x4000.
-
Then add the specific module function Register Offset of interest (i.e., A/D Reading Ch 1 @ 0x1000)
(Function Specific) Address = |
Base Address |
Module Base Address Offset |
Function Register Offset |
= 0x9000 5000 |
0x9000 0000 |
0x4000 |
0x1000 |
MOTHERBOARD COMMON REGISTER DESCRIPTIONS
Module Information Registers
The Module Slot Addressing Ready, Module Slot Address, Module Slot Size and Module Slot ID registers provide information about the modules detected on the board.
Module Slot Addressing Ready
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Function: Indicates that the module slots are ready to be addressed.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: 0xA5A5A5A5
Operational Settings: This register will contain the value of 0xA5A5A5A5 when the module addresses have been determined.
Module Slot Address
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Function: Specifies the Base Address for the module in the specific slot position.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Based on board’s module configuration.
Operational Settings: 0x0000 0000 indicates no Module found.
Module Slot Size
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Function: Specifies the Memory Size (in bytes) allocated for the module in the specific slot position.
Type: unsigned binary word (32-bit)
Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Assigned by factory for the module.
Operational Settings: 0x0000 0000 indicates no Module found.
Module Slot ID
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Function: Specifies the Model ID for the module in the specified slot position.
Type: 4-character ASCII string
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Assigned by factory for the module.
Operational Settings: The Module ID is formatted as four ASCII bytes: three characters followed by a space. Module IDs are in little-endian order with a single space following the first three characters. For example, 'TL1' is '1LT', 'SC1' is '1CS' and so forth. Example below is for “TL1” (MSB justified). All value of 0000 0000 indicates no Module found.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
ASCII Character (ex: 'T' - 0x54) |
ASCII Character (ex: 'L' - 0x4C) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
ASCII Character (ex: '1' - 0x31) |
ASCII Space (' ' - 0x20) |
||||||||||||||
Hardware Information Registers
The registers identified in this section provide information about the board’s hardware.
Product Serial Number
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Function: Specifies the Board Serial Number.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Serial number assigned by factory for the board.
Operational Settings: N/A
Platform
Function: Specifies the Board Platform Identifier. Values are for the ASCII characters for the NAI valid platforms (Identifiers).
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Initialized Value: ASCII code is for the Platform Identifier of the board
Operational Settings: Valid NAI platform and the associated value for the platform is shown below:
NAI Platform |
Platform Identifier |
ASCII Binary Values (Note: little-endian order of ascii values) |
3U VPX |
67 |
0x0000 3736 |
Model
Function: Specifies the Board Model Identifier. Value is for the ASCII characters for the NAI valid model.
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Initialized Value: ASCII code is for the Model Identifier of the board
Operational Settings: Example of NAI model and the associated value for the model is shown below:
NAI Model |
ASCII Binary Values (Note: little-endian order of ascii values) |
PPC |
0x0043 5050 |
Generation
Function: Specifies the Board Generation. Identifier values are for the ASCII characters for the NAI valid generation identifiers.
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Initialized Value: ASCII code is for the Generation Identifier of the board
Operational Settings: Example of NAI generation and the associated value for the generation is shown below:
NAI Generation |
ASCII Binary Values (Note: little-endian order of ascii values) |
2 |
0x0000 0032 |
Processor Count/Ethernet Count
Function: Specifies the Processor Count and Ethernet Count
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Operational Settings:
Processor Count - Integer: indicates the number of unique processor types on the motherboard.
NAI Board |
Processor Count |
Description |
|
6U-VPX |
67PPC2 |
2 |
NXP QorIQ T2080 Quad-Core e6500 Processor+ Xilinx Zynq UltraScale+ |
Ethernet Interface Count - Indicates the number of Ethernet interfaces on the product motherboard. For the 67PPC2, the Ethernet Count is set for Dual Ethernet = 2.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Processor Count (See Table) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ethernet Count (0x0002) |
|||||||||||||||
Maximum Module Slot Count/ARM Platform Type
Function: Specifies the Maximum Module Slot Count and ARM Platform Type.
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Operational Settings:
Maximum Module Slot Count - Indicates the number of modules that can be installed on the product.
ARM Platform - Altera = 1; Xilinx X1 = 2; Xilinx X2 = 3; UltraScale = 3
NAI Board |
Maximum Module Slot Count |
ARM Platform Type |
|
6U-VPX |
67PPC2 |
6 |
UltraScale = 3 |
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
ARM Platform Type (See Table) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Maximum Module Slot Count (See Table) |
|||||||||||||||
Processor Operating System Registers
The registers in this section provide information about the Operating System that is running on the host processor on the motherboard. For boards that have more than one processor (ex. 75PPC1, 75INT2, 68PPC2, etc), the host processor would be the Power-PC or Intel processor.
ARM Processor Platform
Function: Specifies the ARM Processor on the motherboard. Values are for the ASCII characters for the NAI host processor platforms specified by the Operating System.
Type: 8-character ASCII string - Two (2) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: ASCII code is for the Host Platform Identifier of the board
Operational Settings: Valid NAI platforms based on Operating System loaded to host processor.
Word 1 (0x6372 6161 = “craa”) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
'c' (0x63) |
'r' (0x72) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
'a' (0x61) |
'a' (0x61) |
||||||||||||||
Word 2 (0x0034 3668 = “ 46h”) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
null (0x00) |
'4' (0x34) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
'6' (0x36) |
'h' (0x68) |
||||||||||||||
Processor Operating System
Function: Specifies the Operating System installed for the host processor. Values are for the ASCII characters for the NAI supported operating systems.
Type: 12-character ASCII string - Three (3) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Operational Settings: ASCII, 12 characters; ('Linux', 'VxWorks', 'RTOS', …)
Word 1 (0x756E 694C = “uniL”) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
'u' (0x75) |
'n' (0x6E) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
'i' (0x69) |
'L' (0x4C) |
||||||||||||||
Word 2 (0x0000 0078 = “ x”) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
null (0x00) |
null (0x00) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
null (0x00) |
'x' (0x78) |
||||||||||||||
Word 3 (0x0000 0000 = “ ”) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
null (0x00) |
null (0x00) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
null (0x00) |
null (0x00) |
||||||||||||||
Processor Operating System Version
Function: Specifies the Version of Operating System installed for the host processor.
Type: 8-character ASCII string - Two (2) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Operational Settings: ASCII, 8 characters
Word 1 (Ex. 0x3431 2E34 = “41.4”) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
'4' (0x34) |
'1' (0x31) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
'.' (0x2E) |
'3' (0x34) |
||||||||||||||
Word 2 (Ex.0x 0000 302E = “0.”) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
null (0x00) |
null (0x00) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
'0' (0x30) |
'.' (0x2E) |
||||||||||||||
Motherboard Firmware Information Registers
The registers in this section provide information on the revision of the firmware installed on the motherboard.
Motherboard Core (MBCore) Firmware Version
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Function: Specifies the Version of the NAI factory provided Motherboard Core Application installed on the board.
Type: Two (2) unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Operational Settings: The motherboard firmware version consists of four components: Major, Minor, Minor 2 and Minor 3.
Word 1 (Ex. 0007 0004 = 4.7 (Major.Minor) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Minor (ex: 0x0007 = 7) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Major (ex: 0x0004 = 4) |
|||||||||||||||
Word 2 (Ex. 0x0000 0000 = 0000 = 0.0 (Minor2.Minor3)) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Minor 3 (ex: 0x000 = 0) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor 2 (ex: 0x000 = 0) |
|||||||||||||||
Motherboard Firmware Build Time/Date
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Function: Specifies the Build Date/Time of the NAI factory provided Motherboard Core Application installed on the board.
Type: Two (2) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Operational Settings: The motherboard firmware time consists of the Build Date and Build Time.
|
Note
|
On some builds the the Date/Time fields are fixed to 0000 0000 to maintain binary consistency across builds. |
Word 1 - Build Date (ex. 0x030C 07E2 = 2018-12-03) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Day (ex: 0x03 = 3) |
Month (ex: 0x0C = 12) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Year (ex: 0x07E2 = 2018) |
|||||||||||||||
Word 2 - Build Time (ex. 0x001B 3B0A = 10:59:27) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
null (0x00) |
Seconds (ex: 0x1B = 27) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minutes (ex: 0x3B = 59) |
Hours (ex: 0x0A = 10) |
||||||||||||||
Motherboard FPGA Firmware Version
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Function: Specifies the Version of the NAI factory provided Motherboard FPGA installed on the board.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Operational Settings: The motherboard FPGA firmware version consists of two components: Major, Minor.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Major (ex: 0x0005 = 5) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Minor (ex: 0x0008 = 8) |
|||||||||||||||
Motherboard FPGA Compile Date/Time
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Function: Specifies the Compile Date/Time of the NAI factory provided Motherboard FPGA installed on the board.
Type: unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Operational Settings: The motherboard firmware time consists of the Build Date and Time in the following format:
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Day (D31:D27) |
Month (D26:D23) |
Year (D22:D17) |
|||||||||||||
ex. 0xD |
ex. 0x1 |
0x2 |
0xA |
||||||||||||
1 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
Day = 0x1A = 26 |
Month = 0x2 = 2 |
Year = 0x15 = 21 |
|||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Hour (D16:D12) |
Minutes (D11:D6) |
Seconds (D5:D0) |
|||||||||||||
ex. 0x0 |
ex. 0x1 |
ex. 0xB |
ex. 0x8 |
||||||||||||
Hour = 0x00 = 0 |
Minutes = 0x06 = 06 |
Seconds = 0x38 = 56 |
|||||||||||||
Motherboard Monitoring Registers
The registers in this provide motherboard temperature measurement information, and where applicable the host processor processor measurements.
Temperature Readings Register
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The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) for the processor and PCB for Zynq processor, and for the Slave processor.
These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).
Function: Specifies the Measured Temperatures on Motherboard.
Type: signed byte (8-bits) for each temperature reading - Six (6) 32-bit words
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the measured temperatures based on the table below.
Operational Settings: The 8-bit temperature readings are signed bytes. For example, if the following register contains the value 0x6955 E7D8:
Example:
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UltraScale Core Temperature |
UltraScale PCB Temperature |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Host Core Temperature |
Host PCB Temperature |
||||||||||||||
The values would represent the following temperatures:
Temperature Measurements |
Data Bits |
Value |
Temperature (Celsius) |
UltraScale Core Temperature |
D31:D24 |
0x69 |
+105° |
UltraScale PCB Temperature |
D23:D16 |
0x55 |
+85° |
Host Core Temperature |
D15:D8 |
0xE7 |
-25° |
Host PCB Temperature |
D7:D0 |
0xD8 |
-40° |
Temperature Readings
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UltraScale Core Temperature |
UltraScale PCB Temperature |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Host Core Temperature |
Host PCB Temperature |
||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x00 |
0x00 |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Max Host Core Temperature |
Max Host PCB Temperature |
||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Max UltraScale Core Temperature |
Max UltraScale PCB Temperature |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Min Host Core Temperature |
Min Host PCB Temperature00 |
||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x00 |
0x00 |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0x00 |
0x00 |
||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min UltraScale Core Temperature |
Min UltraScale PCB Temperature |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0x00 |
0x00 |
||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x00 |
0x00 |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0x00 |
0x00 |
||||||||||||||
Higher Precision Temperature Readings Registers
These registers provide higher precision readings of the current UltraScale and PCB temperatures.
Higher Precision UltraScale Core Temperature
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Function: Specifies the Higher Precision Measured UltraScale Core temperature on Motherboard Board.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured UltraScale Core temperature on Motherboard Board
Operational Settings: The upper 16-bits represent the signed integer part of the temperature, and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents UltraScale Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Signed Integer Part of Temperature |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional Part of Temperature |
|||||||||||||||
Higher Precision Motherboard PCB Temperature
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Function: Specifies the Higher Precision Measured Motherboard PCB temperature.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Motherboard PCB temperature
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Signed Integer Part of Temperature |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Fractional Part of Temperature |
|||||||||||||||
Motherboard Health Monitoring Registers
The registers in this section provide motherboard voltage, current and temperature measurement information.
Motherboard Sensor Summary Status
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Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds.
Type: unsigned binary word (32-bits)
Data Range: See table below
Read/Write: R
Initialized Value: 0
Operational Settings: This register provides a summary for motherboard sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.
Bit(s) |
Sensor |
D31:D5 |
Reserved |
D4 |
Motherboard PCB Temperature |
D3 |
US+ Core Temperature |
D2:D0 |
Reserved |
Motherboard Sensor Registers
The registers listed in this section apply to each module sensor listed for the Motherboard Sensor Summary Status register.
Sensor Threshold Status_
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Function: Reflects which threshold has been crossed
Type: unsigned binary word (32-bits)
Data Range: See table below
Read/Write: R
Initialized Value: 0
Operational Settings: The associated bit is set when the sensor reading exceed the corresponding threshold settings.
Bit(s) |
Description |
D31:4 |
Reserved |
D3 |
Exceeded Upper Critical Threshold |
D2 |
Exceeded Upper Warning Threshold |
D1 |
Exceeded Lower Critical Threshold |
D0 |
Exceeded Lower Warning Threshold |
Motherboard Sensor Registers
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The registers listed in this section apply to each module sensor listed for the Motherboard Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring motherboard temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Zynq Core Temperature sensor as an example.
Sensor Current Reading
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Function: Reflects current reading of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Minimum Reading
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Function: Reflects minimum value of temperature sensor since power up
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Maximum Reading
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Function: Reflects maximum value of temperature sensor since power up
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Lower Warning Threshold
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Function: Reflects lower warning threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default lower warning threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.
Sensor Lower Critical Threshold
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Function: Reflects lower critical threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default lower critical threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.
Sensor Upper Warning Threshold
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Function: Reflects upper warning threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default upper warning threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.
Sensor Upper Critical Threshold
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Function: Reflects upper critical threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default upper critical threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.
Ethernet Configuration Registers
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The registers in this section provide information about the Ethernet Configuration for the two ports on the board.
Important: Regardless if the board is configured for one or two Ethernet ports, the second IP address cannot be on the same Subnet as the First IP Address. The table below provides examples of valid and invalid IP Addresses and Subnet Mask Addresses.
First Port (A) IP Address |
First Port (A) Subnet Mask |
Second Port (B) IP Address |
Second Port (B) Subnet Mask |
Result |
192.168.1.5 |
255.255.255.0 |
192.168.2.5 |
255.255.255.0 |
Good |
192.168.1.5 |
255.255.0.0 |
192.168.2.5 |
255.255.0.0 |
Conflict |
192.168.1.5 |
255.255.0.0 |
192.168.2.5 |
255.255.255.0 |
Conflict |
10.0.0.15 |
255.0.0.0 |
192.168.1.5 |
255.255.255.0 |
Good |
Ethernet MAC Address and Ethernet Settings
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Function: Specifies the Ethernet MAC Address and Ethernet Settings for the Ethernet port.
Type: Two (2) unsigned binary word (32-bit)
Data Range: See table.
Read/Write: R
Operational Settings: The Ethernet MAC Address consists of six octets. The Ethernet Settings are defined in table.
Bits |
Description |
Values |
D31:D23 |
Reserved |
0 |
D22:D21 |
Duplex |
00 = Not Specified, 01 = Half Duplex, 10 = Full Duplex, 11 = Reserved |
D20:D18 |
Speed |
000 = Not Specified, 001 = 10 Mbps, 010 = 100 Mbps, 011 = 1000 Mbps, 100 = 2500 Mbps, 101 = 10000 Mbps, 110 = Reserved, 111 = Reserved |
D17 |
Auto Negotiate |
0 = Enabled, 1 = Disabled |
D16 |
Static IP Address |
0 = Enabled, 1 = Disabled |
Word 1 (Ethernet MAC Address (Octets 1-4)) (ex: aa:bb:cc:dd:ee:ff) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
MAC Address Octet 4 (ex: 0xDD) |
MAC Address Octet 3 (ex: 0xCC) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
MAC Address Octet 2 (ex: 0xBB) |
MAC Address Octet 1 (ex: 0xAA) |
||||||||||||||
Word 2 (Ethernet MAC Address (Octets 5-6) and Ethernet Settings) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Ethernet Settings (See table) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
MAC Address Octet 6 (ex: 0xFF) |
MAC Address Octet 5 (ex: 0xEE) |
||||||||||||||
Ethernet Interface Name
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Function: Specifies the Ethernet Interface Name for the Ethernet port.
Type: 8-character ASCII string
Data Range: See table.
Read/Write: R
Operational Settings: The Ethernet Interface Name (eth0, eth1, etc) for the Ethernet port.
Word 1 (Bit 0-31) (ex: 0x3068 7465 = “0hte”) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
ASCII Character (ex: '0' - 0x30) |
ASCII Character (ex: 'h' - 0x68) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
ASCII Character (ex: 't' - 0x74) |
ASCII Character (ex: 'e' - 0x65) |
||||||||||||||
Word 2 (Bit 32-63) (ex: 0x0000 0000) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
ASCII Character (ex: null - 0x00) |
ASCII Character (ex: null - 0x00) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
ASCII Character (ex: null - 0x00) |
ASCII Character (ex: null - 0x00) |
||||||||||||||
Ethernet IPv4 Address
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Function: Specifies the Ethernet IPv4 Address for the Ethernet port.
Type: Three (3) unsigned binary word (32-bit)
Data Range: See table.
Read/Write: R
Operational Settings: The Ethernet IPv4 Address consists of three parts: IPv4 Address, IPv4 Subnet Mask and IPv4 Gateway.
Word 1 (Ethernet IPv4 Address) (ex: 0x1001 A8C0 = 192.168.1.16) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
IPv4 Address Octet 4 (ex: 0x10 = 16) |
IPv4 Address Octet 3 (ex: 0x01 = 1) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
IPv4 Address Octet 2 (ex: 0xA8 = 168) |
IPv4 Address Octet 1 (ex: 0xC0 = 192) |
||||||||||||||
Word 2 (Ethernet IPv4 Subnet) (ex: 0x00FF FFFF = 255.255.255.0) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
IPv4 Subnet Octet 4 (ex: 0x00 = 0) |
IPv4 Subnet Octet 3 (ex: 0xFF = 255) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
IPv4 Subnet Octet 2 (ex: 0xFF = 255) |
IPv4 Subnet Octet 1 (ex: 0xFF = 255) |
||||||||||||||
Word 3 (Ethernet IPv4 Gateway) (ex: 0x0101 A8C0 = 192.168.1.1) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
IPv4 Gateway Octet 4 (ex: 0x01 = 1) |
IPv4 Gateway Octet 3 (ex: 0x01 = 1) |
||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
IPv4 Gateway Octet 2 (ex: 0xA8 = 168) |
IPv4 Gateway Octet 1 (ex: 0xC0 = 192) |
||||||||||||||
Ethernet IPv6 Address
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Function: Specifies the Ethernet IPv6 Address for the Ethernet port.
Type: Five (5) unsigned binary word (32-bit)
Data Range: See table.
Read/Write: R
Operational Settings: The IPv6 Prefix length indicates the network portion of an IPv6 address using the following format:
-
IPv6 address/prefix length
-
Prefix length can range from 0 to 128
-
Typical prefix length is 64
The following is an illustration of IPv6 addressing with IPv6 Prefix length of 64.
64 bits |
64 bits |
||||||
Prefix |
Interface ID |
||||||
Prefix 1 |
Prefix 2 |
Prefix 3 |
Subnet ID |
Interface ID 1 |
Interface ID 2 |
Interface ID 3 |
Interface ID 4 |
Example: 2002:c0a8:101:0:7c99:d118:9058:1235/64 |
|||||||
2002 |
C0A8 |
0101 |
0000 |
7C99 |
D118 |
9058 |
1235 |
Word 1 (Ethernet IPv6 Address (Prefix 1-2)) (ex:0xA8C0 0220 = 2002 C0A8) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Prefix 2 (ex: 0xA8C0 = C0A8) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Prefix 1 (ex: 0x0220 = 2002) |
|||||||||||||||
Word 2 (Ethernet IPv6 Address (Prefix 3/Subnet ID)) (ex:0x000 0101 = 0101 0000) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Subnet ID (ex: 0x0000 = 0000) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Prefix 3 (ex: 0x0101 = 0101) |
|||||||||||||||
Word 3 (Ethernet IPv6 Address (Interface ID 1-2)) (ex: 0x18D1 997C = 7C99 D118) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Interface ID 2 (ex: 0x18D1 = D118) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Interface ID 1 (ex: 0x997C = 7C99) |
|||||||||||||||
Word 4 (Ethernet IPv6 Address (Interface ID 3-4)) (ex: 0x3512 5890 = 9058 1235) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Interface ID 4 (ex: 0x3512 = 1235) |
|||||||||||||||
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Interface ID 3 (ex: 0x5890 = 9058) |
|||||||||||||||
Word 5 (Ethernet IPv6 Prefix Length) (ex:0x0000 0040) |
|||||||||||||||
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Prefix Length (ex: 0x0040 = 64) |
|||||||||||||||
Interrupt Vector and Steering
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When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
|
Note
|
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map). |
Interrupt Vector
Function: Set an identifier for the interrupt.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function: Sets where to direct the interrupt.
Type: unsigned binary word (32-bit)
Data Range: See table Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME |
1 |
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) |
2 |
Direct Interrupt to PCIe Bus |
5 |
Direct Interrupt to cPCI Bus |
6 |
Modules Health Monitoring Registers
Module BIT Status
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Function: Provides the ability to monitor the individual Module BIT Status.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Operational Settings: The Module BIT Status registers provide the ability to monitor individual Module BIT results as Latched and current value. A 1 is any bit field indicates BIT failure for the Module in that slot.
Module BIT Status
Bit(s) |
Description |
D31:23 |
Reserved |
D22 |
Module Slot 6 BIT Failure (current value) |
D21 |
Module Slot 5 BIT Failure (current value) |
D20 |
Module Slot 4 BIT Failure (current value) |
D19 |
Module Slot 3 BIT Failure (current value) |
D18 |
Module Slot 2 BIT Failure (current value) |
D17 |
Module Slot 1 BIT Failure (current value) |
D16 |
Reserved |
D7-15 |
Reserved |
D6 |
Module Slot 6 BIT Failure – Latched |
D5 |
Module Slot 5 BIT Failure – Latched |
D4 |
Module Slot 4 BIT Failure – Latched |
D3 |
Module Slot 3 BIT Failure – Latched |
D2 |
Module Slot 2 BIT Failure – Latched |
D1 |
Module Slot 1 BIT Failure – Latched |
D0 |
Reserved |
Scratchpad Area
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Function: Registers reserved as scratch pad for customer use.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Operational Settings: This area in memory is reserved for customer use.
MOTHERBOARD FUNCTION REGISTER MAP
Key:
Bold Underline = Measurement/Status/Board Information
Bold Italic = Configuration/Control
Module Information Registers
0x03FC |
Module Slot Addressing Ready |
R |
0x0400 |
Module Slot 1 Address |
R |
0x0404 |
Module Slot 2 Address |
R |
0x0408 |
Module Slot 3 Address |
R |
0x040C |
Module Slot 4 Address |
R |
0x0410 |
Module Slot 5 Address |
R |
0x0414 |
Module Slot 6 Address |
R |
0x0430 |
Module Slot 1 Size |
R |
0x0434 |
Module Slot 2 Size |
R |
0x0438 |
Module Slot 3 Size |
R |
0x043C |
Module Slot 4 Size |
R |
0x0440 |
Module Slot 5 Size |
R |
0x0444 |
Module Slot 6 Size |
R |
0x0460 |
Module Slot 1 ID |
R |
0x0464 |
Module Slot 2 ID |
R |
0x0468 |
Module Slot 3 ID |
R |
0x046C |
Module Slot 4 ID |
R |
0x0470 |
Module Slot 5 ID |
R |
0x0474 |
Module Slot 6 ID |
R |
Hardware Information Registers
0x0020 |
Product Serial Number |
R |
0x0024 |
Platform |
R |
0x0028 |
Model |
R |
0x002C |
Generation |
R |
0x0030 |
Processor Count/Ethernet Count |
R |
0x0034 |
Maximum Module Slot Count/ARM Platform Type |
R |
0x0038 |
Processor Platform (Bit 0-31) |
R |
0x003C |
Processor Platform (Bit 32-63) |
R |
0x0040 |
Processor Operating System (Bit 0-31) |
R |
0x0044 |
Processor Operating System (Bit 32-63) |
R |
0x0048 |
Processor Operating System (Bit 64-95) |
R |
0x004C |
Processor Operating System Version (Bit 0-31) |
R |
0x0050 |
Processor Operating System Version (Bit 32-63) |
R |
Motherboard Firmware Information Registers
Motherboard Core Information
0x0100 |
MB Core Major/Minor Version |
R |
0x0104 |
MB Core Minor 2/3 Version |
R |
0x0108 |
MB Core Build Date (Bit 0-31) |
R |
0x010C |
MB Core Build Date (Bit 32-63) |
R |
Higher Precision Temperature Readings
0x0230 |
Current UltraScale Core Temperature |
R |
0x0234 |
Current UltraScale PCB Temperature |
R |
Ethernet Configuration Registers
0x0070 |
Ethernet A MAC (Octets 1-4) |
R |
0x0074 |
Ethernet A MAC (Octets 5-6)/Misc Settings |
R |
0x0078 |
Ethernet A Interface Name (Bit 0-31) |
R |
0x007C |
Ethernet A Interface Name (Bit 32-63) |
R |
0x0080 |
Ethernet A IPv4 Address |
R |
0x0084 |
Ethernet A IPv4 Subnet Mask |
R |
0x0088 |
Ethernet A IPv4 Gateway |
R |
0x008C |
Ethernet A IPv6 Address (Prefix 1-2) |
R |
0x0090 |
Ethernet A IPv6 Address (Prefix 3/Subnet ID) |
R |
0x0094 |
Ethernet A IPv6 Address (Interface ID 1-2) |
R |
0x0098 |
Ethernet A IPv6 Address (Interface ID 3-4) |
R |
0x009C |
Ethernet A IPv6 Prefix Length |
R |
0x00A0 |
Ethernet B MAC (Octets 1-4) |
R |
0x00A4 |
Ethernet B MAC (Octets 5-6)/Misc Settings |
R |
0x00A8 |
Ethernet B Interface Name (Bit 0-31) |
R |
0x00AC |
Ethernet B Interface Name (Bit 32-63) |
R |
0x00B0 |
Ethernet B IPv4 Address |
R |
0x00B4 |
Ethernet B IPv4 Subnet Mask |
R |
0x00B8 |
Ethernet B IPv4 Gateway |
R |
0x00BC |
Ethernet B IPv6 Address (Prefix 1-2) |
R |
0x00C0 |
Ethernet B IPv6 Address (Prefix 3/Subnet ID) |
R |
0x00C4 |
Ethernet B IPv6 Address (Interface ID 1-2) |
R |
0x00C8 |
Ethernet B IPv6 Address (Interface ID 3-4) |
R |
0x00CC |
Ethernet B IPv6 Prefix Length |
R |
Interrupt Vector and Steering
0x0500 - 0x057C |
Module 1 Interrupt Vector 1 - 32 |
R/W |
0x0600 - 0x067C |
Module 1 Interrupt Steering 1 - 32 |
R/W |
0x0700 - 0x077C |
Module 2 Interrupt Vector 1 - 32 |
R/W |
0x0800 - 0x087C |
Module 2 Interrupt Steering 1 - 32 |
R/W |
0x0900 - 0x097C |
Module 3 Interrupt Vector 1 - 32 |
R/W |
0x0A00 - 0x0A7C |
Module 3 Interrupt Steering 1 - 32 |
R/W |
0x0B00 - 0x0B7C |
Module 4 Interrupt Vector 1 - 32 |
R/W |
0x0C00 - 0x0C7C |
Module 4 Interrupt Steering 1 - 32 |
R/W |
0x0D00 - 0x0D7C |
Module 5 Interrupt Vector 1 - 32 |
R/W |
0x0E00 - 0x0E7C |
Module 5 Interrupt Steering 1 - 32 |
R/W |
0x0F00 - 0x0F7C |
Module 6 Interrupt Vector 1 - 32 |
R/W |
0x1000 - 0x107C |
Module 6 Interrupt Steering 1 - 32 |
R/W |
ETHERNET
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(For detailed supplement, please visit the NAI web-site specific product page and refer to: Ethernet Interface for Generation 5 SBC and Embedded IO Boards Specification)
The Ethernet Interface Option allows communications and control access to all function modules either via the system BUS or Ethernet ports 1 or 2.
Ethernet 1 |
Ethernet 2 |
|
The default IP address: |
192.168.1.16 |
192.168.2.16 |
The default subnet: |
255.255.255.0 |
255.255.255.0 |
The default gateway: |
192.168.1.1 |
192.168.2.1 |
|
Note
|
Actual "as shipped" card Ethernet default IP addresses may vary based upon final ATP configuration(s).) Ethernet Port IP addresses may be field re-flashed to new default programmed addressed via use of the “IP Configuring for Ethernet Supported Boards” FLASH software support kit, available/documented from the specific product web page. |
The NAI interface supports IPv4 and IPv6 and both the TCP and UDP protocols. The Ethernet Operation Mode Command Listener application running on the motherboard host processor implements the operation interface. The listener is operational on startup through the nai_MBStartup process and listen on specific ports for commands to process. The default ports are listed below:
-
TCP1 - Port 52801
-
TCP2 - Port 52802
-
UDP1 - Port 52801
-
UDP2 - Port 52802
While the listener is active, note that interrupts from the motherboard do not trigger. The listener can be disabled by turning off the nai_MBStartup process through the Motherboard EEPROM. To turn off nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 1 in the console, either by serial port or telnet to the motherboard, and then reboot the system. To turn on the nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 0 in the console, either by serial port or telnet to the motherboard, and then reboot the system.
Ethernet Message Framework
The interface uses a specific message framework for all commands and responses. All messages begin with a Preamble code and end with a Postamble code. The message framework is shown below.
|
Preamble 2 bytes Always 0xD30F |
SequenceNo 2 bytes |
Type Code 2 byte |
Message Length (2 bytes) |
Payload (0..1414 bytes) |
Postamble 2 bytes Always 0xF03D |
Message Elements
Preamble |
The Preamble is used to delineate the beginning of a message frame. The Preamble is always 0xD30F. |
SequenceNo |
The SequenceNo is used to associate Commands with Responses. |
Type Code |
Type Codes are used to define the type of Command or Response the message contains. |
Message Length |
The Message Length is the number of bytes in the complete message frame starting with and including the Preamble and ending with and including the Postamble. |
Payload |
The Payload contains the unique data that makes up the command or response. Payloads vary based on command type. |
Postamble |
The Postamble is use to delineate the end of a message frame. The Postamble is always 0xF03D. |
Notes
-
The messaging protocol applies only to card products.
-
Messaging is managed by the connected (client) computer. The client computer will send a single message and wait for a reply from the card. Multiple cards may be managed from a single computer, subject to channel and computer capacity.
Board Addressing
The interface provides two main addressing areas: Onboard and Off-board.
Onboard addressing refers to accessing resources located on the board that is implementing the operation interface (including its modules).
Off-board addressing refers to accessing resources located on another board reachable via VME, PCI, or other bus. Off-board addressing requires a Master/Slave configuration.
The user must always specify if a particular address is Onboard or Off-board. See the command descriptions for the onboard and off-board flags.
Within a particular board (Onboard or Off-board), the address space is broken up into two areas: Motherboard Common Address Space and Module Address Space. All addresses are 32-bit.
Motherboard Common Address Space starts at 0x00000000 and ends at 0x00004000. This is a 4Kx32-bit address space (16 kbytes).
Module Address Space starts at 0x00004000. Module addressing is dynamically configured at startup. NAI boards support between 1 and 6 modules. The minimum module address space size is 4Kx32 (16 kbytes) and module sizes are always a multiple of 4Kx32.
Module addressing is dynamic and cumulative. The first detected module (starting with Slot 1) is given an address of 0x00004000. The 2nd detected Module is given an address of:
First_Detected_Module_Address + First_Detected_Module_Size
|
Note
|
Slots do not define addresses. |
If no module is detected in a module slot, that slot is not given an address. Therefore, if the first detected Module is in Slot 2, then that module address will be 0x00004000. If the next detected module is in Slot 4, then the address of that Module will be:
Second_Detected_Module_Address = First_Detected_Module_Address + First_Detected_Module_Size
If a 3rd Module is detected in Slot 6, then the address of that Module will be:
Third_Detected_Module_Address = Second_Detected_Module_Address + Second_Detected_Module_Size
|
Note
|
Module addresses are calculated at each board startup when the modules are detected. Therefore, if a module should fail to be detected due to malfunction or because it was removed from the motherboard, the addresses of the modules that follow it in the slot sequence will be altered. This is important to note when programming to this interface. |
Users can always retrieve the Module Addresses, Module Sizes and Module IDs from the fixed Motherboard Common address area. This data is set upon each board startup. While the Module Addressing is dynamic, the address where these addresses are stored is fixed. For example, to find the startup address of the module location in Slot 3, refer to the MB Common Address 0x00000408 from the Motherboard Common Addresses table that follows.
Ethernet Wiring Convention
RJ-45 Pin |
T568A Color |
T568B Color |
10/100Base-T |
1000BASE-T |
NAI wiring convention |
1 |
white/green stripe |
white/orange stripe |
TX+ |
DA+ |
ETH-TP0+ |
2 |
green |
orange |
TX- |
DA- |
ETH-TP0- |
3 |
white/orange stripe |
white/green stripe |
RX+ |
DB+ |
ETH-TP1+ |
4 |
blue |
blue |
DC+ |
ETH-TP2+ |
|
5 |
white/blue stripe |
white/blue stripe |
DC- |
ETH-TP2- |
|
6 |
orange |
green |
RX- |
DB- |
ETH-TP1- |
7 |
white/brown stripe |
white/brown stripe |
DD+ |
ETH-TP3+ |
|
8 |
brown |
brown |
DD- |
ETH-TP3- |
67PPC2 CONNECTOR/PIN-OUT INFORMATION
Front and Rear Panel Connectors
The 67PPC2 6U OpenVPX Multifunction I/O board is available in two configurations: convection-cooled and conduction-cooled. The 67PPC2 follows the OpenVPX “Payload Slot Profile” configured as:
| Slot profile: | SLT6-PAY-2F2U2T-10.2.5 |
|---|---|
Module profile: |
MOD6-PAY-2F2U2T-12.2.5-3 |
User I/O is available through the (J1, J2, J3, J4, J5, J6) front panel connectors when the card is configured with front panel I/O and through the OpenVPX user defined rear I/O connectors P1, P2, P3, P4, P5, P6 (see part number and pin-out information).
Front Panel Connectors J1-J6 (Convection Cooled)
44-pin male connectors, 2mm, Harwin P/N M80-5114422.
Mate kit: "Custom Hood Kit" part # M80C108448C (or equivalent); Includes connector, backshell, pins & jackscrews. This mating connector kit may be purchased separately as NAI P/N 05-0119 (contact factory).
Panel LEDs
Front Panel LEDs indications (only available on air-cooled units).
LED |
ILLUMINATED |
EXTINGUISHED |
GRN: |
Blinking: Initializing Steady On: Power-On/Ready |
Power off |
RED: |
Module BIT error |
No BIT fault |
YEL: (flash) |
Card access (bus or Gig-E activity) |
No card activity |
Chassis Ground
Front Panel Connectors: J1 - J6 pin-1 is chassis GND. Jack screw sockets are chassis GND.
Rear Connectors: Not available.
Front Panel System (Power/Signal) Ground Reference
Front Panel: J1 - J6 pin-23 is System (SYS) GND (referenced to card power/system ground).
Front I/O Utility Connector J7
The 67PPC2 utilizes a Mini-HDMI type card edge connector J7, available on either convection or conduction-cooled configurations that provides the following signals:
-
Serial (port 1)
-
USB 2.0
-
Ethernet port 1 (factory configuration option – Ethernet port1 may be redirected to rear I/O J2)
NAI also provides an optional “breakout” adapter board (NAI P/N 75SBC4-BB) with a mini-HDMI to mini-HDMI type cable. The “breakout” adapter board and a Micro-HDMI cable (NAI P/N 75SBC4-BB) allow for standard I/O connections to Ethernet and asynchronous serial (DB9). Consult the factory for availability.
| Front J7 | Standard Configuration | Option |
|---|---|---|
J7-01 |
N/C |
N/C |
J7-02 |
N/C |
ETH1-TP0+ |
J7-03 |
N/C |
ETH-TP0- |
J7-04 |
N/C |
N/C |
J7-05 |
N/C |
ETH1-TP1+ |
J7-06 |
N/C |
ETH1-TP1- |
J7-07 |
N/C |
N/C |
J7-08 |
N/C |
ETH1-TP2+ |
J7-09 |
N/C |
ETH1-TP2- |
J7-10 |
N/C |
N/C |
J7-11 |
N/C |
ETH1-TP3+ |
J7-12 |
N/C |
ETH1-TP3- |
J7-13 |
GND |
GND |
J7-14 |
N/C |
+5V-UBSF |
J7-15 |
N/C |
USBF-DP |
J7-16 |
N/C |
USBF-DM |
J7-17 |
SER1-RXD |
SER1-RXD |
J7-18 |
SER1-TXD |
SER1-TXD |
J7-19 |
GND |
GND |
Signal Descriptions J7
Signal Name |
Description |
ETH1-TPx |
Ethernet port 1 signals (4 pair) 10/100/1000 twisted pair signals (Optional – available only if NOT re-directed to rear I/O (see part number configuration options) |
USBF-DP |
Front Panel USB Data Positive |
USBF-DN |
Front Panel USB Data Minus |
SER1-TXD |
Asynchronous transmit serial data port 1 (out) / RS232 debug/console port only |
SER1-RXD |
Asynchronous received serial data port 1 (in) / RS232 debug/console port only |
GND |
System Ground (return) |
Rear I/O VPX Connectors P0-P6 (Conduction-Cooled)
The 67PPC2 6U OpenVPX multifunction I/O board provides interface via the rear VPX connectors.
Rear I/O Summary
Signals defined as N/C currently have no functionality associated and are not required for general operation.
| P0 - Utility plane. Contains the following signal definitions: | |
|---|---|
Power |
Primary +5V, +3.3V_AUX, +/- 12V and System GND |
Geographical Address Pins |
GA0# - GA4#, GAP# |
Card reset |
SYSRST# signal |
Non-Volatile Memory Read Only |
NVMRO |
IPMC |
IMPB-SDA-A, IMPB-SDA-B, IMPB-SCL-A, IMPB-SCL-B |
VPX AUX/REF CLK |
(Not used) |
| P1 - Defined as Data/Control Planes (User defined I/O secondary) | |
|---|---|
High Speed Switched Fabric Interface |
12 x1 PCIe (end point only) |
Ethernet |
Gig-E port option(s) are available and defined (See Part Number Designation section) |
P2 - User defined I/O (primary) |
P3 - User defined I/O (primary) |
P4 - Defined as Control Plane (User defined I/O secondary) |
P5 - User defined I/O (primary) |
P6 - User defined I/O (primary) |
Rear I/O Utility Plane (P0)
The P0 (Utility) Plane contains the primary power, bus and utility signals for the OpenVPX board. Additionally, several of the user defined pins can be utilized for Geographical Addressing and a parallel SYSRST# signal. Signals defined as N/C currently have no functionality associated and is not required for general operation.
| UTILITY | Row | Row | Row | Row | Row | Row | Row |
|---|---|---|---|---|---|---|---|
P0 |
G |
F |
E |
D |
C |
B |
A |
1 |
N/C (VS1_G1) |
N/C (VS1_F1) |
N/C (VS1_E1) |
N/C (NCD1) |
N/C (VS2_C1) |
N/C (VS2_B1) |
N/C (VS2_A1) |
2 |
N/C (VS1_G2) |
N/C (VS1_F2) |
N/C (VS1_E2) |
N/C (NCD2) |
N/C (VS2_C2) |
N/C (VS2_B2) |
N/C (VS2_A2) |
3 |
(+)5V (VS3) |
(+)5V (VS3) |
(+)5V (VS3) |
N/C (NCD3) |
(+)5V (VS3) |
(+)5V (VS3) |
(+)5V (VS3) |
4 |
N/C (NVMRO) |
N/C (SM3) |
GND |
(-)12V (-12V-AUX) |
GND |
SYSRST# |
N/C (NVMRO) |
5 |
GAP# |
GA4# |
GND |
N/C (+3.3V-AUX) |
GND |
N/C (SM0) |
N/C (SM1) |
6 |
GA3# |
GA2# |
GND |
(+)12V (+12V-AUX) |
GND |
GA1# |
GA0# |
7 |
N/C (TCK) |
GND |
N/C (TDO) |
N/C (TDI) |
GND |
N/C (TMS) |
N/C (TRST) |
8 |
GND |
N/C (REFCLK-25MHz-) |
N/C (REFCLK-25MHz+) |
GND |
N/C (AUX-CLK-) |
N/C (AUX-CLK+) |
GND |
Rear I/O Data/Control Planes (P1)
The 67PPC2 has twelve PCIe ver 2.0 Ultra-Thin pipes. Additionally, the 67PPC2 can be commanded/controlled via Gig-E (options for either 10/100/1000Base-T and/or 1000Base-KX (SerDes) Interfaces). Additional module I/O is also defined on the P1 user defined plane. Signals defined as N/C currently have no functionality associated or are considered optional and are not required for general operation.
Data Plane |
Row |
Row |
Row |
Row |
Row |
Row |
Row |
P1 |
G |
F |
E |
D |
C |
B |
A |
1 |
N/C |
GND |
PCIe / Tx0- |
PCIe / Tx0+ |
GND |
PCIe / Rx0- |
PCIe / Rx0+ |
2 |
GND |
PCIe / Tx1- |
PCIe / Tx1+ |
GND |
PCIe / Rx1- |
PCIe / Rx1+ |
GND |
3 |
VBAT |
GND |
PCIe / Tx2- |
PCIe / Tx2+ |
GND |
PCIe / Rx2- |
PCIe / Rx2+ |
4 |
GND |
PCIe / Tx3- |
PCIe / Tx3+ |
GND |
PCIe / Rx3- |
PCIe / Rx3+ |
GND |
5 |
P1-SYSCON |
GND |
PCIe / Tx4- |
PCIe / Tx4+ |
GND |
PCIe / Rx4- |
PCIe / Rx4+ |
6 |
GND |
PCIe / Tx5- |
PCIe / Tx5+ |
GND |
PCIe / Rx5- |
PCIe / Rx5+ |
GND |
7 |
N/C |
GND |
PCIe / Tx6- |
PCIe / Tx6+ |
GND |
PCIe / Rx6- |
PCIe / Rx6+ |
8 |
GND |
PCIe / Tx7- |
PCIe / Tx7+ |
GND |
PCIe / Rx7- |
PCIe / Rx7+ |
GND |
9 |
(SER-RXD1) |
GND |
PCIe / Tx8- |
PCIe / Tx8+ |
GND |
PCIe / Rx8- |
PCIe / Rx8+ |
10 |
GND |
PCIe / Tx9- |
PCIe / Tx9+ |
GND |
PCIe / Rx9- |
PCIe / Rx9+ |
GND |
11 |
(SER-TXD1) |
GND |
PCIe / Tx10- |
PCIe / Tx10+ |
GND |
PCIe / Rx10- |
PCIe / Rx10+ |
12 |
GND |
PCIe / Tx11- |
PCIe / Tx11+ |
GND |
PCIe / Rx11- |
PCIe / Rx11+ |
GND |
13 |
(SER-GND) |
GND |
XFI9-Tx- |
XFI9-Tx+ |
GND |
XFI9-Rx- |
XFI9-Rx+ |
14 |
GND |
XFI10-Tx- |
XFI10-Tx+ |
GND |
XFI10-Rx- |
XFI10-Rx+ |
GND |
15 |
MRST |
GND |
SATA-Tx- |
SATA-Tx+ |
GND |
SATA-Rx- |
SATA-Rx+ |
16 |
GND |
I2C |
DATA |
I2C |
CLOCK |
GND |
N/C |
USER I/O - Defined Area (User Defined I/O) (P2-P6)
The following pages contain the 'user defined' I/O data area front and rear panel pin-outs with their respective signal designations for all module types currently offered/configured for the 67PPC2 platform. The card is designed to route the function module I/O signals to the front and rear I/O connector. The following I/O connector pin-out is based upon the function module designated in the module slot. Signals defined as N/C currently have no functionality associated or are considered optional and are not required for general operation.
User Defined Plane |
Row |
Row |
Row |
Row |
Row |
Row |
Row |
P2 |
G |
F |
E |
D |
C |
B |
A |
1 |
S-MOD-M6-DAT33 |
GND |
S-MOD-M6-DAT30 |
S-MOD-M6-DAT29 |
GND |
S-MOD-M6-DAT32 |
S-MOD-M6-DAT31 |
2 |
GND |
S-MOD-M6-DAT26 |
S-MOD-M6-DAT25 |
GND |
S-MOD-M6-DAT28 |
S-MOD-M6-DAT27 |
GND |
3 |
S-MOD-M6-DAT34 |
GND |
S-MOD-M6-DAT22 |
S-MOD-M6-DAT21 |
GND |
S-MOD-M6-DAT24 |
S-MOD-M6-DAT23 |
4 |
GND |
S-MOD-M6-DAT18 |
S-MOD-M6-DAT17 |
GND |
S-MOD-M6-DAT20 |
S-MOD-M6-DAT19 |
GND |
5 |
S-MOD-M6-DAT35 |
GND |
S-MOD-M6-DAT14 |
S-MOD-M6-DAT13 |
GND |
S-MOD-M6-DAT16 |
S-MOD-M6-DAT15 |
6 |
GND |
S-MOD-M6-DAT10 |
S-MOD-M6-DAT09 |
GND |
S-MOD-M6-DAT12 |
S-MOD-M6-DAT11 |
GND |
7 |
S-MOD-M6-DAT36 |
GND |
S-MOD-M6-DAT06 |
S-MOD-M6-DAT05 |
GND |
S-MOD-M6-DAT08 |
S-MOD-M6-DAT07 |
8 |
GND |
S-MOD-M6-DAT02 |
S-MOD-M6-DAT01 |
GND |
S-MOD-M6-DAT04 |
S-MOD-M6-DAT03 |
GND |
9 |
S-MOD-M6-DAT37 |
GND |
S-MOD-M5-DAT38 |
S-MOD-M5-DAT37 |
GND |
S-MOD-M5-DAT40 |
S-MOD-M5-DAT39 |
10 |
GND |
S-MOD-M5-DAT34 |
S-MOD-M5-DAT33 |
GND |
S-MOD-M5-DAT36 |
S-MOD-M5-DAT35 |
GND |
11 |
S-MOD-M6-DAT38 |
GND |
S-MOD-M5-DAT30 |
S-MOD-M5-DAT29 |
GND |
S-MOD-M5-DAT32 |
S-MOD-M5-DAT31 |
12 |
GND |
S-MOD-M5-DAT26 |
S-MOD-M5-DAT25 |
GND |
S-MOD-M5-DAT28 |
S-MOD-M5-DAT27 |
GND |
13 |
S-MOD-M6-DAT39 |
GND |
S-MOD-M5-DAT22 |
S-MOD-M5-DAT21 |
GND |
S-MOD-M5-DAT24 |
S-MOD-M5-DAT23 |
14 |
GND |
S-MOD-M5-DAT18 |
S-MOD-M5-DAT17 |
GND |
S-MOD-M5-DAT20 |
S-MOD-M5-DAT19 |
GND |
15 |
S→MOD-M6-DAT40 |
GND |
S-MOD-M5-DAT14 |
S-MOD-M5-DAT13 |
GND |
S-MOD-M5-DAT16 |
S-MOD-M5-DAT15 |
16 |
GND |
S-MOD-M5-DAT10 |
S-MOD-M5-DAT09 |
GND |
S-MOD-M5-DAT12 |
S-MOD-M5-DAT11 |
GND |
User Defined Plane |
Row |
Row |
Row |
Row |
Row |
Row |
Row |
P3 |
G |
F |
E |
D |
C |
B |
A |
1 |
S-MOD-M4-DAT33 |
GND |
S-MOD-M5-DAT06 |
S-MOD-M5-DAT05 |
GND |
S-MOD-M5-DAT08 |
S-MOD-M5-DAT07 |
2 |
GND |
S-MOD-M5-DAT02 |
S-MOD-M5-DAT01 |
GND |
S-MOD-M5-DAT04 |
S-MOD-M5-DAT03 |
GND |
3 |
S-MOD-M4-DAT34 |
GND |
S-MOD-M5-DAT30 |
S-MOD-M5-DAT29 |
GND |
S-MOD-M5-DAT32 |
S-MOD-M5-DAT31 |
4 |
GND |
S-MOD-M5-DAT26 |
S-MOD-M5-DAT25 |
GND |
S-MOD-M5-DAT28 |
S-MOD-M5-DAT27 |
GND |
5 |
S-MOD-M4-DAT35 |
GND |
S-MOD-M5-DAT22 |
S-MOD-M5-DAT21 |
GND |
S-MOD-M5-DAT24 |
S-MOD-M5-DAT23 |
6 |
GND |
S-MOD-M5-DAT18 |
S-MOD-M5-DAT17 |
GND |
S-MOD-M5-DAT20 |
S-MOD-M5-DAT19 |
GND |
7 |
S-MOD-M4-DAT36 |
GND |
S-MOD-M5-DAT14 |
S-MOD-M5-DAT13 |
GND |
S-MOD-M5-DAT16 |
S-MOD-M5-DAT15 |
8 |
GND |
S-MOD-M5-DAT10 |
S-MOD-M5-DAT09 |
GND |
S-MOD-M5-DAT12 |
S-MOD-M5-DAT11 |
GND |
9 |
S-MOD-M4-DAT37 |
GND |
S-MOD-M5-DAT06 |
S-MOD-M5-DAT05 |
GND |
S-MOD-M5-DAT08 |
S-MOD-M5-DAT07 |
10 |
GND |
S-MOD-M5-DAT02 |
S-MOD-M5-DAT01 |
GND |
S-MOD-M5-DAT04 |
S-MOD-M5-DAT03 |
GND |
11 |
S-MOD-M4-DAT38 |
GND |
S-MOD-M4-DAT30 |
S-MOD-M4-DAT29 |
GND |
S-MOD-M4-DAT32 |
S-MOD-M4-DAT31 |
12 |
GND |
S-MOD-M4-DAT26 |
S-MOD-M4-DAT25 |
GND |
S-MOD-M4-DAT28 |
S-MOD-M4-DAT27 |
GND |
13 |
S-MOD-M4-DAT39 |
GND |
S-MOD-M4-DAT22 |
S-MOD-M4-DAT21 |
GND |
S-MOD-M4-DAT24 |
S-MOD-M4-DAT23 |
14 |
GND |
S-MOD-M4-DAT18 |
S-MOD-M4-DAT17 |
GND |
S-MOD-M4-DAT20 |
S-MOD-M4-DAT19 |
GND |
15 |
S-MOD-M4-DAT40 |
GND |
S-MOD-M4-DAT14 |
S-MOD-M4-DAT13 |
GND |
S-MOD-M4-DAT16 |
S-MOD-M4-DAT15 |
16 |
GND |
S-MOD-M4-DAT10 |
S-MOD-M4-DAT09 |
GND |
S-MOD-M4-DAT12 |
S-MOD-M4-DAT11 |
GND |
User Defined Plane |
Row |
Row |
Row |
Row |
Row |
Row |
Row |
P4 |
G |
F |
E |
D |
C |
B |
A |
1 |
DT-IN1 (TTL-1) |
GND |
S-MOD-M4-DAT04 |
S-MOD-M4-DAT03 |
GND |
S-MOD-M4-DAT02 |
S-MOD-M4-DAT01 |
2 |
GND |
S-MOD-M4-DAT08 |
S-MOD-M4-DAT07 |
GND |
S-MOD-M4-DAT06 |
S-MOD-M4-DAT05 |
GND |
3 |
DT-IN2 (TTL-2) |
GND |
USB3_SSRXN_DN2 |
USB3_SSRXP_DN2 |
GND |
USB3_SSTXN_DN2 |
USB3_SSTXP_DN2 |
4 |
GND |
USB3-2_GND |
+5V-USB3_2 |
GND |
USB3_2N |
USB3_2P |
GND |
5 |
DT-IN3 (TTL-3) |
GND |
USB3-1_GND |
+5V-USB3_1 |
GND |
USB3-1N |
USB3_1P |
6 |
GND |
USB3_SSRXN_DN1 |
USB3_SSRXP_DN1 |
GND |
USB3_SSTXN_DN1 |
USB3_SSTXP_DN1 |
GND |
7 |
DT-IN4 (TTL-4) |
GND |
N/C |
N/C |
GND |
N/C |
N/C |
8 |
GND |
N/C |
N/C |
GND |
N/C |
N/C |
GND |
9 |
DT-IN5 (TTL-5) |
GND |
SER-ETH0-TXN |
SER-ETH0-TXP |
GND |
SER-ETH0-RXN |
SER-ETH0-RXP |
10 |
GND |
SER-ETH1-TXN |
SER-ETH1-TXP |
GND |
SER-ETH1-RXN |
SER-ETH1-RXP |
GND |
11 |
DT-IN6 (TTL-6) |
GND |
SER-ETH3-RXN |
SER-ETH3-RXP |
GND |
SER-ETH3-TXN |
SER-ETH3-TXP |
12 |
GND |
SER-ETH2-RXN |
SER-ETH2-RXP |
GND |
SER-ETH2-TXN |
SER-ETH2-TXP |
GND |
13 |
DT-IN7 (TTL-7) |
GND |
ETH1-TP1- |
ETH1-TP1+ |
GND |
ETH1-TP0- |
ETH1-TP0+ |
14 |
GND |
ETH1-TP3- |
ETH1-TP3+ |
GND |
ETH1-TP2- |
ETH1-TP2+ |
GND |
15 |
DT-IN8 (TTL-8) |
GND |
ETH0-TP1- |
ETH0-TP1+ |
GND |
ETH0-TP0- |
ETH0-TP0+ |
16 |
GND |
ETH0-TP3- |
ETH0-TP3+ |
GND |
ETH0-TP2- |
ETH0-TP2+ |
GND |
User Defined Plane |
Row |
Row |
Row |
Row |
Row |
Row |
Row |
P5 |
G |
F |
E |
D |
C |
B |
A |
1 |
S-MOD-M2-DAT24* |
GND |
-12V-AUX |
+12V-AUX |
GND |
-12V-AUX |
+12V-AUX |
2 |
GND |
N/C |
N/C |
GND |
N/C |
N/C |
GND |
3 |
S-MOD-M2-DAT23* |
GND |
S-MOD-M3-DAT38 |
S-MOD-M3-DAT37 |
GND |
S-MOD-M3-DAT40 |
S-MOD-M3-DAT39 |
4 |
GND |
S-MOD-M3-DAT34 |
S-MOD-M3-DAT33 |
GND |
S-MOD-M3-DAT36 |
S-MOD-M3-DAT35 |
GND |
5 |
S-MOD-M2-DAT18* |
GND |
S-MOD-M3-DAT30 |
S-MOD-M3-DAT29 |
GND |
S-MOD-M3-DAT32 |
S-MOD-M3-DAT31 |
6 |
GND |
S-MOD-M3-DAT26 |
S-MOD-M3-DAT25 |
GND |
S-MOD-M3-DAT28 |
S-MOD-M3-DAT27 |
GND |
7 |
S-MOD-M1-DAT17* |
GND |
S-MOD-M3-DAT22 |
S-MOD-M3-DAT21 |
GND |
S-MOD-M3-DAT24 |
S-MOD-M3-DAT23 |
8 |
GND |
S-MOD-M3-DAT18 |
S-MOD-M3-DAT17 |
GND |
S-MOD-M3-DAT20 |
S-MOD-M3-DAT19 |
GND |
9 |
S-MOD-M2-DAT12* |
GND |
S-MOD-M3-DAT14 |
S-MOD-M3-DAT13 |
GND |
S-MOD-M3-DAT16 |
S-MOD-M3-DAT15 |
10 |
GND |
S-MOD-M3-DAT10 |
S-MOD-M3-DAT09 |
GND |
S-MOD-M3-DAT12 |
S-MOD-M3-DAT11 |
GND |
11 |
S-MOD-M2-DAT11* |
GND |
S-MOD-M3-DAT06 |
S-MOD-M3-DAT05 |
GND |
S-MOD-M3-DAT08 |
S-MOD-M3-DAT07 |
12 |
GND |
S-MOD-M3-DAT02 |
S-MOD-M3-DAT01 |
GND |
S-MOD-M3-DAT04 |
S-MOD-M3-DAT03 |
GND |
13 |
S-MOD-M2-DAT06* |
GND |
S-MOD-M2-DAT38 |
S-MOD-M2-DAT37 |
GND |
S-MOD-M2-DAT40 |
S-MOD-M2-DAT39 |
14 |
GND |
S-MOD-M2-DAT34 |
S-MOD-M2-DAT33 |
GND |
S-MOD-M2-DAT36 |
S-MOD-M2-DAT35 |
GND |
15 |
S-MOD-M2-DAT05* |
GND |
S-MOD-M2-DAT30 |
S-MOD-M2-DAT29 |
GND |
S-MOD-M2-DAT32 |
S-MOD-M2-DAT31 |
16 |
GND |
S-MOD-M2-DAT26 |
S-MOD-M2-DAT25 |
GND |
S-MOD-M2-DAT28 |
S-MOD-M2-DAT27 |
GND |
User Defined Plane |
Row |
Row |
Row |
Row |
Row |
Row |
Row |
P6 |
G |
F |
E |
D |
C |
B |
A |
1 |
S-MOD-M1-DAT24* |
GND |
S-MOD-M2-DAT22 |
S-MOD-M2-DAT21 |
GND |
S-MOD-M2-DAT24* |
S-MOD-M2-DAT23* |
2 |
GND |
S-MOD-M2-DAT18* |
S-MOD-M2-DAT17* |
GND |
S-MOD-M2-DAT20 |
S-MOD-M2-DAT19 |
GND |
3 |
S-MOD-M1-DAT23* |
GND |
S-MOD-M2-DAT14 |
S-MOD-M2-DAT13 |
GND |
S-MOD-M2-DAT16 |
S-MOD-M2-DAT15 |
4 |
GND |
S-MOD-M2-DAT10 |
S-MOD-M2-DAT09 |
GND |
S-MOD-M2-DAT12* |
S-MOD-M2-DAT11* |
GND |
5 |
S-MOD-M1-DAT18* |
GND |
S-MOD-M2-DAT06* |
S-MOD-M2-DAT05* |
GND |
S-MOD-M2-DAT08 |
S-MOD-M2-DAT07 |
6 |
GND |
S-MOD-M2-DAT02 |
S-MOD-M2-DAT01 |
GND |
S-MOD-M2-DAT04 |
S-MOD-M2-DAT03 |
GND |
7 |
S-MOD-M1-DAT17* |
GND |
S-MOD-M1-DAT38 |
S-MOD-M1-DAT37 |
GND |
S-MOD-M1-DAT40 |
S-MOD-M1-DAT39 |
8 |
GND |
S-MOD-M1-DAT34 |
S-MOD-M1-DAT33 |
GND |
S-MOD-M1-DAT36 |
S-MOD-M1-DAT35 |
GND |
9 |
S-MOD-M1-DAT12* |
GND |
S-MOD-M1-DAT30 |
S-MOD-M1-DAT29 |
GND |
S-MOD-M1-DAT32 |
S-MOD-M1-DAT31 |
10 |
GND |
S-MOD-M1-DAT26 |
S-MOD-M1-DAT25 |
GND |
S-MOD-M1-DAT28 |
S-MOD-M1-DAT27 |
GND |
11 |
S-MOD-M1-DAT11* |
GND |
S-MOD-M1-DAT22 |
S-MOD-M1-DAT21 |
GND |
S-MOD-M1-DAT24* |
S-MOD-M1-DAT23* |
12 |
GND |
S-MOD-M1-DAT18* |
S-MOD-M1-DAT17* |
GND |
S-MOD-M1-DAT20 |
S-MOD-M1-DAT19 |
GND |
13 |
S-MOD-M1-DAT06* |
GND |
S-MOD-M1-DAT14 |
S-MOD-M1-DAT13 |
GND |
S-MOD-M1-DAT16 |
S-MOD-M1-DAT15 |
14 |
GND |
S-MOD-M1-DAT10 |
S-MOD-M1-DAT09 |
GND |
S-MOD-M1-DAT12* |
S-MOD-M1-DAT11* |
GND |
15 |
S-MOD-M1-DAT05* |
GND |
S-MOD-M1-DAT06* |
S-MOD-M1-DAT05* |
GND |
S-MOD-M1-DAT08 |
S-MOD-M1-DAT07 |
16 |
GND |
S-MOD-M1-DAT02 |
S-MOD-M1-DAT01 |
GND |
S-MOD-M1-DAT04 |
S-MOD-M1-DAT03 |
GND |
|
Note
|
Row “G” pins on P5 & P6 are duplicated to support higher current requirements; both connection points should be used. |
Front Panel Connectors J1-J6 Generic User I/O Mapping
(System Ground REF) |
GND |
1 |
23 |
GND |
(System Ground REF) |
M1_DAT01 |
S-MOD-M1-DAT01 |
2 |
24 |
S-MOD-M1-DAT02 |
M1_DAT02 |
M1_DAT03 |
S-MOD-M1-DAT03 |
3 |
25 |
S-MOD-M1-DAT04 |
M1_DAT04 |
M1_DAT25 |
S-MOD-M1-DAT25 |
4 |
26 |
S-MOD-M1-DAT26 |
M1_DAT26 |
M1_DAT05 |
S-MOD-M1-DAT05 |
5 |
27 |
S-MOD-M1-DAT06 |
M1_DAT06 |
M1_DAT33 |
S-MOD-M1-DAT33 |
6 |
28 |
S-MOD-M1-DAT34 |
M1_DAT34 |
M1_DAT07 |
S-MOD-M1-DAT07 |
7 |
29 |
S-MOD-M1-DAT08 |
M1_DAT08 |
M1_DAT09 |
S-MOD-M1-DAT09 |
8 |
30 |
S-MOD-M1-DAT10 |
M1_DAT10 |
M1_DAT27 |
S-MOD-M1-DAT27 |
9 |
31 |
S-MOD-M1-DAT28 |
M1_DAT28 |
M1_DAT11 |
S-MOD-M1-DAT11 |
10 |
32 |
S-MOD-M1-DAT12 |
M1_DAT12 |
M1_DAT35 |
S-MOD-M1-DAT35 |
11 |
33 |
S-MOD-M1-DAT36 |
M1_DAT36 |
M1_DAT13 |
S-MOD-M1-DAT13 |
12 |
34 |
S-MOD-M1-DAT14 |
M1_DAT14 |
M1_DAT15 |
S-MOD-M1-DAT15 |
13 |
35 |
S-MOD-M1-DAT16 |
M1_DAT16 |
M1_DAT29 |
S-MOD-M1-DAT29 |
14 |
36 |
S-MOD-M1-DAT30 |
M1_DAT30 |
M1_DAT17 |
S-MOD-M1-DAT17 |
15 |
37 |
S-MOD-M1-DAT18 |
M1_DAT18 |
M1_DAT37 |
S-MOD-M1-DAT37 |
16 |
38 |
S-MOD-M1-DAT38 |
M1_DAT38 |
M1_DAT19 |
S-MOD-M1-DAT19 |
17 |
39 |
S-MOD-M1-DAT20 |
M1_DAT20 |
M1_DAT21 |
S-MOD-M1-DAT21 |
18 |
40 |
S-MOD-M1-DAT22 |
M1_DAT22 |
M1_DAT31 |
S-MOD-M1-DAT31 |
19 |
41 |
S-MOD-M1-DAT32 |
M1_DAT32 |
M1_DAT23 |
S-MOD-M1-DAT23 |
20 |
42 |
S-MOD-M1-DAT24 |
M1_DAT24 |
M1_DAT39 |
S-MOD-M1-DAT39 |
21 |
43 |
S-MOD-M1-DAT40 |
M1_DAT40 |
N/C |
22 |
44 |
N/C |
(System Ground REF) |
GND |
1 |
23 |
GND |
(System Ground REF) |
M2_DAT01 |
S-MOD-M2-DAT01 |
2 |
24 |
S-MOD-M2-DAT02 |
M2_DAT02 |
M2_DAT03 |
S-MOD-M2-DAT03 |
3 |
25 |
S-MOD-M2-DAT04 |
M2_DAT04 |
M2_DAT25 |
S-MOD-M2-DAT25 |
4 |
26 |
S-MOD-M2-DAT26 |
M2_DAT26 |
M2_DAT05 |
S-MOD-M2-DAT05 |
5 |
27 |
S-MOD-M2-DAT06 |
M2_DAT06 |
M2_DAT33 |
S-MOD-M2-DAT33 |
6 |
28 |
S-MOD-M2-DAT34 |
M2_DAT34 |
M2_DAT07 |
S-MOD-M2-DAT07 |
7 |
29 |
S-MOD-M2-DAT08 |
M2_DAT08 |
M2_DAT09 |
S-MOD-M2-DAT09 |
8 |
30 |
S-MOD-M2-DAT10 |
M2_DAT10 |
M2_DAT27 |
S-MOD-M2-DAT27 |
9 |
31 |
S-MOD-M2-DAT28 |
M2_DAT28 |
M2_DAT11 |
S-MOD-M2-DAT11 |
10 |
32 |
S-MOD-M2-DAT12 |
M2_DAT12 |
M2_DAT35 |
S-MOD-M2-DAT35 |
11 |
33 |
S-MOD-M2-DAT36 |
M2_DAT36 |
M2_DAT13 |
S-MOD-M2-DAT13 |
12 |
34 |
S-MOD-M2-DAT14 |
M2_DAT14 |
M2_DAT15 |
S-MOD-M2-DAT15 |
13 |
35 |
S-MOD-M2-DAT16 |
M2_DAT16 |
M2_DAT29 |
S-MOD-M2-DAT29 |
14 |
36 |
S-MOD-M2-DAT30 |
M2_DAT30 |
M2_DAT17 |
S-MOD-M2-DAT17 |
15 |
37 |
S-MOD-M2-DAT18 |
M2_DAT18 |
M2_DAT37 |
S-MOD-M2-DAT37 |
16 |
38 |
S-MOD-M2-DAT38 |
M2_DAT38 |
M2_DAT19 |
S-MOD-M2-DAT19 |
17 |
39 |
S-MOD-M2-DAT20 |
M2_DAT20 |
M2_DAT21 |
S-MOD-M2-DAT21 |
18 |
40 |
S-MOD-M2-DAT22 |
M2_DAT22 |
M2_DAT31 |
S-MOD-M2-DAT31 |
19 |
41 |
S-MOD-M2-DAT32 |
M2_DAT32 |
M2_DAT23 |
S-MOD-M2-DAT23 |
20 |
42 |
S-MOD-M2-DAT24 |
M2_DAT24 |
M2_DAT39 |
S-MOD-M2-DAT39 |
21 |
43 |
S-MOD-M2-DAT40 |
M2_DAT40 |
N/C |
22 |
44 |
N/C |
(System Ground REF) |
GND |
1 |
23 |
GND |
(System Ground REF) |
M3_DAT01 |
S-MOD-M3-DAT01 |
2 |
24 |
S-MOD-M3-DAT02 |
M3_DAT02 |
M3_DAT03 |
S-MOD-M3-DAT03 |
3 |
25 |
S-MOD-M3-DAT04 |
M3_DAT04 |
M3_DAT25 |
S-MOD-M3-DAT25 |
4 |
26 |
S-MOD-M3-DAT26 |
M3_DAT26 |
M3_DAT05 |
S-MOD-M3-DAT05 |
5 |
27 |
S-MOD-M3-DAT06 |
M3_DAT06 |
M3_DAT33 |
S-MOD-M3-DAT33 |
6 |
28 |
S-MOD-M3-DAT34 |
M3_DAT34 |
M3_DAT07 |
S-MOD-M3-DAT07 |
7 |
29 |
S-MOD-M3-DAT08 |
M3_DAT08 |
M3_DAT09 |
S-MOD-M3-DAT09 |
8 |
30 |
S-MOD-M3-DAT10 |
M3_DAT10 |
M3_DAT27 |
S-MOD-M3-DAT27 |
9 |
31 |
S-MOD-M3-DAT28 |
M3_DAT28 |
M3_DAT11 |
S-MOD-M3-DAT11 |
10 |
32 |
S-MOD-M3-DAT12 |
M3_DAT12 |
M3_DAT35 |
S-MOD-M3-DAT35 |
11 |
33 |
S-MOD-M3-DAT36 |
M3_DAT36 |
M3_DAT13 |
S-MOD-M3-DAT13 |
12 |
34 |
S-MOD-M3-DAT14 |
M3_DAT14 |
M3_DAT15 |
S-MOD-M3-DAT15 |
13 |
35 |
S-MOD-M3-DAT16 |
M3_DAT16 |
M3_DAT29 |
S-MOD-M3-DAT29 |
14 |
36 |
S-MOD-M3-DAT30 |
M3_DAT30 |
M3_DAT17 |
S-MOD-M3-DAT17 |
15 |
37 |
S-MOD-M3-DAT18 |
M3_DAT18 |
M3_DAT37 |
S-MOD-M3-DAT37 |
16 |
38 |
S-MOD-M3-DAT38 |
M3_DAT38 |
M3_DAT19 |
S-MOD-M3-DAT19 |
17 |
39 |
S-MOD-M3-DAT20 |
M3_DAT20 |
M3_DAT21 |
S-MOD-M3-DAT21 |
18 |
40 |
S-MOD-M3-DAT22 |
M3_DAT22 |
M3_DAT31 |
S-MOD-M3-DAT31 |
19 |
41 |
S-MOD-M3-DAT32 |
M3_DAT32 |
M3_DAT23 |
S-MOD-M3-DAT23 |
20 |
42 |
S-MOD-M3-DAT24 |
M3_DAT24 |
M3_DAT39 |
S-MOD-M3-DAT39 |
21 |
43 |
S-MOD-M3-DAT40 |
M3_DAT40 |
N/C |
22 |
44 |
N/C |
(System Ground REF) |
GND |
1 |
23 |
GND |
(System Ground REF) |
M4_DAT01 |
S-MOD-M4-DAT01 |
2 |
24 |
S-MOD-M4-DAT02 |
M4_DAT02 |
M4_DAT03 |
S-MOD-M4-DAT03 |
3 |
25 |
S-MOD-M4-DAT04 |
M4_DAT04 |
M4_DAT25 |
S-MOD-M4-DAT25 |
4 |
26 |
S-MOD-M4-DAT26 |
M4_DAT26 |
M4_DAT05 |
S-MOD-M4-DAT05 |
5 |
27 |
S-MOD-M4-DAT06 |
M4_DAT06 |
M4_DAT33 |
S-MOD-M4-DAT33 |
6 |
28 |
S-MOD-M4-DAT34 |
M4_DAT34 |
M4_DAT07 |
S-MOD-M4-DAT07 |
7 |
29 |
S-MOD-M4-DAT08 |
M4_DAT08 |
M4_DAT09 |
S-MOD-M4-DAT09 |
8 |
30 |
S-MOD-M4-DAT10 |
M4_DAT10 |
M4_DAT27 |
S-MOD-M4-DAT27 |
9 |
31 |
S-MOD-M4-DAT28 |
M4_DAT28 |
M4_DAT11 |
S-MOD-M4-DAT11 |
10 |
32 |
S-MOD-M4-DAT12 |
M4_DAT12 |
M4_DAT35 |
S-MOD-M4-DAT35 |
11 |
33 |
S-MOD-M4-DAT36 |
M4_DAT36 |
M4_DAT13 |
S-MOD-M4-DAT13 |
12 |
34 |
S-MOD-M4-DAT14 |
M4_DAT14 |
M4_DAT15 |
S-MOD-M4-DAT15 |
13 |
35 |
S-MOD-M4-DAT16 |
M4_DAT16 |
M4_DAT29 |
S-MOD-M4-DAT29 |
14 |
36 |
S-MOD-M4-DAT30 |
M4_DAT30 |
M4_DAT17 |
S-MOD-M4-DAT17 |
15 |
37 |
S-MOD-M4-DAT18 |
M4_DAT18 |
M4_DAT37 |
S-MOD-M4-DAT37 |
16 |
38 |
S-MOD-M4-DAT38 |
M4_DAT38 |
M4_DAT19 |
S-MOD-M4-DAT19 |
17 |
39 |
S-MOD-M4-DAT20 |
M4_DAT20 |
M4_DAT21 |
S-MOD-M4-DAT21 |
18 |
40 |
S-MOD-M4-DAT22 |
M4_DAT22 |
M4_DAT31 |
S-MOD-M4-DAT31 |
19 |
41 |
S-MOD-M4-DAT32 |
M4_DAT32 |
M4_DAT23 |
S-MOD-M4-DAT23 |
20 |
42 |
S-MOD-M4-DAT24 |
M4_DAT24 |
M4_DAT39 |
S-MOD-M4-DAT39 |
21 |
43 |
S-MOD-M4-DAT40 |
M4_DAT40 |
N/C |
22 |
44 |
N/C |
(System Ground REF) |
GND |
1 |
23 |
GND |
(System Ground REF) |
M5_DAT01 |
S-MOD-M5-DAT01 |
2 |
24 |
S-MOD-M5-DAT02 |
M5_DAT02 |
M5_DAT03 |
S-MOD-M5-DAT03 |
3 |
25 |
S-MOD-M5-DAT04 |
M5_DAT04 |
M5_DAT25 |
S-MOD-M5-DAT25 |
4 |
26 |
S-MOD-M5-DAT26 |
M5_DAT26 |
M5_DAT05 |
S-MOD-M5-DAT05 |
5 |
27 |
S-MOD-M5-DAT06 |
M5_DAT06 |
M5_DAT33 |
S-MOD-M5-DAT33 |
6 |
28 |
S-MOD-M5-DAT34 |
M5_DAT34 |
M5_DAT07 |
S-MOD-M5-DAT07 |
7 |
29 |
S-MOD-M5-DAT08 |
M5_DAT08 |
M5_DAT09 |
S-MOD-M5-DAT09 |
8 |
30 |
S-MOD-M5-DAT10 |
M5_DAT10 |
M5_DAT27 |
S-MOD-M5-DAT27 |
9 |
31 |
S-MOD-M5-DAT28 |
M5_DAT28 |
M5_DAT11 |
S-MOD-M5-DAT11 |
10 |
32 |
S-MOD-M5-DAT12 |
M5_DAT12 |
M5_DAT35 |
S-MOD-M5-DAT35 |
11 |
33 |
S-MOD-M5-DAT36 |
M5_DAT36 |
M5_DAT13 |
S-MOD-M5-DAT13 |
12 |
34 |
S-MOD-M5-DAT14 |
M5_DAT14 |
M5_DAT15 |
S-MOD-M5-DAT15 |
13 |
35 |
S-MOD-M5-DAT16 |
M5_DAT16 |
M5_DAT29 |
S-MOD-M5-DAT29 |
14 |
36 |
S-MOD-M5-DAT30 |
M5_DAT30 |
M5_DAT17 |
S-MOD-M5-DAT17 |
15 |
37 |
S-MOD-M5-DAT18 |
M5_DAT18 |
M5_DAT37 |
S-MOD-M5-DAT37 |
16 |
38 |
S-MOD-M5-DAT38 |
M5_DAT38 |
M5_DAT19 |
S-MOD-M5-DAT19 |
17 |
39 |
S-MOD-M5-DAT20 |
M5_DAT20 |
M5_DAT21 |
S-MOD-M5-DAT21 |
18 |
40 |
S-MOD-M5-DAT22 |
M5_DAT22 |
M5_DAT31 |
S-MOD-M5-DAT31 |
19 |
41 |
S-MOD-M5-DAT32 |
M5_DAT32 |
M5_DAT23 |
S-MOD-M5-DAT23 |
20 |
42 |
S-MOD-M5-DAT24 |
M5_DAT24 |
M5_DAT39 |
S-MOD-M5-DAT39 |
21 |
43 |
S-MOD-M5-DAT40 |
M5_DAT40 |
N/C |
22 |
44 |
N/C |
(System Ground REF) |
GND |
1 |
23 |
GND |
(System Ground REF) |
M6_DAT01 |
S-MOD-M6-DAT01 |
2 |
24 |
S-MOD-M6-DAT02 |
M6_DAT02 |
M6_DAT03 |
S-MOD-M6-DAT03 |
3 |
25 |
S-MOD-M6-DAT04 |
M6_DAT04 |
M6_DAT25 |
S-MOD-M6-DAT25 |
4 |
26 |
S-MOD-M6-DAT26 |
M6_DAT26 |
M6_DAT05 |
S-MOD-M6-DAT05 |
5 |
27 |
S-MOD-M6-DAT06 |
M6_DAT06 |
M6_DAT33 |
S-MOD-M6-DAT33 |
6 |
28 |
S-MOD-M6-DAT34 |
M6_DAT34 |
M6_DAT07 |
S-MOD-M6-DAT07 |
7 |
29 |
S-MOD-M6-DAT08 |
M6_DAT08 |
M6_DAT09 |
S-MOD-M6-DAT09 |
8 |
30 |
S-MOD-M6-DAT10 |
M6_DAT10 |
M6_DAT27 |
S-MOD-M6-DAT27 |
9 |
31 |
S-MOD-M6-DAT28 |
M6_DAT28 |
M6_DAT11 |
S-MOD-M6-DAT11 |
10 |
32 |
S-MOD-M6-DAT12 |
M6_DAT12 |
M6_DAT35 |
S-MOD-M6-DAT35 |
11 |
33 |
S-MOD-M6-DAT36 |
M6_DAT36 |
M6_DAT13 |
S-MOD-M6-DAT13 |
12 |
34 |
S-MOD-M6-DAT14 |
M6_DAT14 |
M6_DAT15 |
S-MOD-M6-DAT15 |
13 |
35 |
S-MOD-M6-DAT16 |
M6_DAT16 |
M6_DAT29 |
S-MOD-M6-DAT29 |
14 |
36 |
S-MOD-M6-DAT30 |
M6_DAT30 |
M6_DAT17 |
S-MOD-M6-DAT17 |
15 |
37 |
S-MOD-M6-DAT18 |
M6_DAT18 |
M6_DAT37 |
S-MOD-M6-DAT37 |
16 |
38 |
S-MOD-M6-DAT38 |
M6_DAT38 |
M6_DAT19 |
S-MOD-M6-DAT19 |
17 |
39 |
S-MOD-M6-DAT20 |
M6_DAT20 |
M6_DAT21 |
S-MOD-M6-DAT21 |
18 |
40 |
S-MOD-M6-DAT22 |
M6_DAT22 |
M6_DAT31 |
S-MOD-M6-DAT31 |
19 |
41 |
S-MOD-M6-DAT32 |
M6_DAT32 |
M6_DAT23 |
S-MOD-M6-DAT23 |
20 |
42 |
S-MOD-M6-DAT24 |
M6_DAT24 |
M6_DAT39 |
S-MOD-M6-DAT39 |
21 |
43 |
S-MOD-M6-DAT40 |
M6_DAT40 |
N/C |
22 |
44 |
N/C |
|
Note
|
*High Speed Modules are Rear I/O, Only |
Front & Rear User I/O Mapping (Global)
Front/Rear User I/O Mapping (for reference) is shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Module Operational Manuals.
Slot 1 |
Slot 2 |
Slot 3 |
||||||||
Module Signal (Ref Only) |
Front I/O J1 44-pin |
Rear I/O P6 |
Global (MB) |
Front I/O J2 44-pin |
Rear I/O P6 |
Rear I/O P5 |
Global (MB) |
Front I/O J3 44-pin |
Rear I/O P5 |
Global (MB) |
DATIO1 |
2 |
E16 |
2 |
E6 |
2 |
E12 |
||||
DATIO2 |
24 |
F16 |
24 |
F6 |
24 |
F12 |
||||
DATIO3 |
3 |
B16 |
3 |
B6 |
3 |
B12 |
||||
DATIO4 |
25 |
C16 |
25 |
C6 |
25 |
C12 |
||||
DATIO5 |
5 |
D15 |
5 |
D5 |
5 |
D11 |
||||
DATIO6 |
27 |
E15 |
27 |
E5 |
27 |
E11 |
||||
DATIO7 |
7 |
A15 |
7 |
A5 |
7 |
A11 |
||||
DATIO8 |
29 |
B15 |
29 |
B5 |
29 |
B11 |
||||
DATIO9 |
8 |
E14 |
8 |
E4 |
8 |
E10 |
||||
DATIO10 |
30 |
F14 |
30 |
F4 |
30 |
F10 |
||||
DATIO11 |
10 |
B14 |
10 |
B4 |
10 |
B10 |
||||
DATIO12 |
32 |
C14 |
32 |
C4 |
32 |
C10 |
||||
DATIO13 |
12 |
D13 |
12 |
D3 |
12 |
D9 |
||||
DATIO14 |
34 |
E13 |
34 |
E3 |
34 |
E9 |
||||
DATIO15 |
13 |
A13 |
13 |
A3 |
13 |
A9 |
||||
DATIO16 |
35 |
B13 |
35 |
B3 |
35 |
B9 |
||||
DATIO17 |
15 |
E12 |
15 |
E2 |
15 |
E8 |
||||
DATIO18 |
37 |
F12 |
37 |
F2 |
37 |
F8 |
||||
DATIO19 |
17 |
B12 |
17 |
B2 |
17 |
B8 |
||||
DATIO20 |
39 |
C12 |
39 |
C2 |
39 |
C8 |
||||
DATIO21 |
18 |
D11 |
18 |
D1 |
18 |
D7 |
||||
DATIO22 |
40 |
E11 |
40 |
E1 |
40 |
E7 |
||||
DATIO23 |
20 |
A11 |
20 |
A1 |
20 |
A7 |
||||
DATIO24 |
42 |
B11 |
42 |
B1 |
42 |
B7 |
||||
DATIO25 |
4 |
E10 |
4 |
E16 |
4 |
E6 |
||||
DATIO26 |
26 |
F10 |
26 |
F16 |
26 |
F6 |
||||
DATIO27 |
9 |
B10 |
9 |
B16 |
9 |
B6 |
||||
DATIO28 |
31 |
C10 |
31 |
C16 |
31 |
C6 |
||||
DATIO29 |
14 |
D9 |
14 |
D15 |
14 |
D5 |
||||
DATIO30 |
36 |
E9 |
36 |
E15 |
36 |
E5 |
||||
DATIO31 |
19 |
A9 |
19 |
A15 |
19 |
A5 |
||||
DATIO32 |
41 |
B9 |
41 |
B15 |
41 |
B5 |
||||
DATIO33 |
6 |
E8 |
6 |
E14 |
6 |
E4 |
||||
DATIO34 |
28 |
F8 |
28 |
F14 |
28 |
F4 |
||||
DATIO35 |
11 |
B8 |
11 |
B14 |
11 |
B4 |
||||
DATIO36 |
33 |
C8 |
33 |
C14 |
33 |
C4 |
||||
DATIO37 |
16 |
D7 |
16 |
D13 |
16 |
D3 |
||||
DATIO38 |
38 |
E7 |
38 |
E13 |
38 |
E3 |
||||
DATIO39 |
21 |
A7 |
21 |
A13 |
21 |
A3 |
||||
DATIO40 |
43 |
B7 |
43 |
B13 |
43 |
B3 |
||||
N/A |
23 |
SYS GND |
23 |
SYS GND |
23 |
SYS GND |
||||
1 |
CHASSIS |
1 |
CHASSIS |
1 |
CHASSIS |
|||||
22, 44 |
N/C |
22, 44 |
N/C |
22, 44 |
N/C |
|||||
Slot 4 |
Slot 5 |
Slot 6 |
||||||||||
Module Signal (Ref Only) |
Front I/O J4 44-pin |
Rear I/O P4 |
Rear I/O P3 |
Global (MB) |
Front I/O J5 44-pin |
Rear I/O P3 |
Rear I/O P2 |
Global (MB) |
Front I/O J6 44-pin |
Rear I/O P2 |
Rear I/O P1 |
Global (MB) |
DATIO1 |
2 |
A1 |
2 |
E2 |
2 |
E8 |
||||||
DATIO2 |
24 |
B1 |
24 |
F2 |
24 |
F8 |
||||||
DATIO3 |
3 |
D1 |
3 |
B2 |
3 |
B8 |
||||||
DATIO4 |
25 |
E1 |
25 |
C2 |
25 |
C8 |
||||||
DATIO5 |
5 |
B2 |
5 |
D1 |
5 |
D7 |
||||||
DATIO6 |
27 |
C2 |
27 |
E1 |
27 |
E7 |
||||||
DATIO7 |
7 |
E2 |
7 |
A1 |
7 |
A7 |
||||||
DATIO8 |
29 |
F2 |
29 |
B1 |
29 |
B7 |
||||||
DATIO9 |
8 |
E16 |
8 |
E16 |
8 |
E6 |
||||||
DATIO10 |
30 |
F16 |
30 |
F16 |
30 |
F6 |
||||||
DATIO11 |
10 |
B16 |
10 |
B16 |
10 |
B6 |
||||||
DATIO12 |
32 |
C16 |
32 |
C16 |
32 |
C6 |
||||||
DATIO13 |
12 |
D15 |
12 |
D15 |
12 |
D5 |
||||||
DATIO14 |
34 |
E15 |
34 |
E15 |
34 |
E5 |
||||||
DATIO15 |
13 |
A15 |
13 |
A15 |
13 |
A5 |
||||||
DATIO16 |
35 |
B15 |
35 |
B15 |
35 |
B5 |
||||||
DATIO17 |
15 |
E14 |
15 |
E14 |
15 |
E4 |
||||||
DATIO18 |
37 |
F14 |
37 |
F14 |
37 |
F4 |
||||||
DATIO19 |
17 |
B14 |
17 |
B14 |
17 |
B4 |
||||||
DATIO20 |
39 |
C14 |
39 |
C14 |
39 |
C4 |
||||||
DATIO21 |
18 |
D13 |
18 |
D13 |
18 |
D3 |
||||||
DATIO22 |
40 |
E13 |
40 |
E13 |
40 |
E3 |
||||||
DATIO23 |
20 |
A13 |
20 |
A13 |
20 |
A3 |
||||||
DATIO24 |
42 |
B13 |
42 |
B13 |
42 |
B3 |
||||||
DATIO25 |
4 |
E12 |
4 |
E12 |
4 |
E2 |
||||||
DATIO26 |
26 |
F12 |
26 |
F12 |
26 |
F2 |
||||||
DATIO27 |
9 |
B12 |
9 |
B12 |
9 |
B2 |
||||||
DATIO28 |
31 |
C12 |
31 |
C12 |
31 |
C2 |
||||||
DATIO29 |
14 |
D11 |
14 |
D11 |
14 |
D1 |
||||||
DATIO30 |
36 |
E11 |
36 |
E11 |
36 |
E1 |
||||||
DATIO31 |
19 |
A11 |
19 |
A11 |
19 |
A1 |
||||||
DATIO32 |
41 |
B11 |
41 |
B11 |
41 |
B1 |
||||||
DATIO33 |
6 |
G1 |
6 |
E10 |
6 |
G1 |
||||||
DATIO34 |
28 |
G3 |
28 |
F10 |
28 |
G3 |
||||||
DATIO35 |
11 |
G5 |
11 |
B10 |
11 |
G5 |
||||||
DATIO36 |
33 |
G7 |
33 |
C10 |
33 |
G7 |
||||||
DATIO37 |
16 |
G9 |
16 |
D9 |
16 |
G9 |
||||||
DATIO38 |
38 |
G11 |
38 |
E9 |
38 |
G11 |
||||||
DATIO39 |
21 |
G13 |
21 |
A9 |
21 |
G13 |
||||||
DATIO40 |
43 |
G15 |
43 |
B9 |
43 |
G15 |
||||||
N/A |
23 |
SYS GND |
23 |
SYS GND |
23 |
SYS GND |
||||||
1 |
CHASSIS |
1 |
CHASSIS |
1 |
CHASSIS |
|||||||
High Speed I/O Modules
Slot 5 |
Slot 6 |
|||||||
Module Signal (Ref Only) |
Front I/O J5 44-pin |
Front I/O J5 44-pin |
Rear I/O P3 |
Global (MB) |
Front I/O J6 44-pin |
Front I/O J6 44-pin |
Rear I/O P1 |
Global (MB) |
DATIO1 |
E10 |
ETH1 TP0P |
A9 |
ETH1 TP0P |
||||
DATIO2 |
F10 |
ETH1 TP0N |
B9 |
ETH1 TP0N |
||||
DATIO3 |
B10 |
ETH1 TP1P |
D9 |
ETH1 TP1P |
||||
DATIO4 |
C10 |
ETH1 TP1N |
E9 |
ETH1 TP1N |
||||
DATIO5 |
D9 |
ETH1 TP2P |
B10 |
ETH1 TP2P |
||||
DATIO6 |
E9 |
ETH1 TP2N |
C10 |
ETH1 TP2N |
||||
DATIO7 |
A9 |
ETH1 TP3P |
E10 |
ETH1 TP3P |
||||
DATIO8 |
B9 |
ETH1 TP3N |
F10 |
ETH1 TP3N |
||||
DATIO9 |
E8 |
ETH2 TP0P |
A11 |
ETH2 TP0P |
||||
DATIO10 |
F8 |
ETH2 TP0N |
B11 |
ETH2 TP0N |
||||
DATIO11 |
B8 |
ETH2 TP1P |
D11 |
ETH2 TP1P |
||||
DATIO12 |
C8 |
ETH2 TP1N |
E11 |
ETH2 TP1N |
||||
DATIO13 |
D7 |
ETH2 TP2P |
B12 |
ETH2 TP2P |
||||
DATIO14 |
E7 |
ETH2 TP2N |
C12 |
ETH2 TP2N |
||||
DATIO15 |
A7 |
ETH2 TP3P |
E12 |
ETH2 TP3P |
||||
DATIO16 |
B7 |
ETH2 TP3N |
F12 |
ETH2 TP3N |
||||
DATIO17 |
E6 |
ETH3 TP0P |
A13 |
ETH3 TP0P |
||||
DATIO18 |
F6 |
ETH3 TP0N |
B13 |
ETH3 TP0N |
||||
DATIO19 |
B6 |
ETH3 TP1P |
D13 |
ETH3 TP1P |
||||
DATIO20 |
C6 |
ETH3 TP1N |
E13 |
ETH3 TP1N |
||||
DATIO21 |
D5 |
ETH3 TP2P |
B14 |
ETH3 TP2P |
||||
DATIO22 |
E5 |
ETH3 TP2N |
C14 |
ETH3 TP2N |
||||
DATIO23 |
A5 |
ETH3 TP3P |
E14 |
ETH3 TP3P |
||||
DATIO24 |
B5 |
ETH3 TP3N |
F14 |
ETH3 TP3N |
||||
DATIO25 |
E4 |
ETH4 TP0P |
A15 |
ETH4 TP0P |
||||
DATIO26 |
F4 |
ETH4 TP0N |
B15 |
ETH4 TP0N |
||||
DATIO27 |
B4 |
ETH4 TP1P |
D15 |
ETH4 TP1P |
||||
DATIO28 |
C4 |
ETH4 TP1N |
E15 |
ETH4 TP1N |
||||
DATIO29 |
D3 |
ETH4 TP2P |
B16 |
ETH4 TP2P |
||||
DATIO30 |
E3 |
ETH4 TP2N |
C16 |
ETH4 TP2N |
||||
DATIO31 |
A3 |
ETH4 TP3P |
E16 |
ETH4 TP3P |
||||
DATIO32 |
B3 |
ETH4 TP3N |
F16 |
ETH4 TP3N |
||||
Connector Signal/Pin-Out Notes
NAI Synchro / Resolver Naming Convention
Signal |
Resolver |
Synchro |
S1 |
SIN(-) |
X |
S2 |
COS(+) |
Z |
S3 |
SIN(+) |
Y |
S4 |
COS(-) |
No connect |
Additional Pinout Notes
1. Isolated Discrete Module (DT2) |
For 'differential' A/D; “P” designation considered 'positive' input pin, “N” pin designation considered 'negative' input pin. |
2. Discrete I/O Module (DT1) |
All GND pins are common within the module, but, isolated from system/power GND. Each pin should be individually wired for optimal power current distribution. |
3. TTL I/O Module (TL1) |
I/O referenced to system power GND. |
4. CMRP - A/D Module(s) (ADx) |
The Common Mode Reference Point (CMRP) is an isolated reference connection for all the A/D channels. For expected high common mode voltage applications, it is recommended that the pin designated as CMRP be referenced (direct or resistor coupled) to the signal source GND reference (must have current path between CMRP and signal source generator) to minimize common mode voltage within the acceptable specification range. All channels within the module are independent but share a common CMRP, which is isolated from system/power GND. |
SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES
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Select the Digital-to-Synchro (DSx), Digital-to-Resolver (DRx) or Digital-to-LVDT/RVDT (DLx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. Frequency/voltage band tolerances +/- 10%. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.
-
Single Channel module pending availability (contact factory)
Module ID |
Format |
Channel(s) |
Output Voltage VL-L (Vrms) |
Reference Voltage (Vrms) |
Frequency Range (Hz) |
Power / CH maximum (VA) |
Notes |
DS1 |
SYN |
1* |
2 - 28 |
2 - 115 |
47 - 1 K |
3 |
|
DR1 |
RSL |
||||||
DL1 |
LVDT/RVDT |
||||||
DS2 |
SYN |
1* |
2 - 28 |
2 - 115 |
1 K - 5 K |
3 |
|
DR2 |
RSL |
||||||
DL2 |
LVDT/RVDT |
||||||
DS3 |
SYN |
1* |
2 - 28 |
2 - 115 |
5 K - 10 K |
3 |
|
DR3 |
RSL |
||||||
DL3 |
LVDT/RVDT |
||||||
DS4 |
SYN |
1* |
2 - 28 |
2 - 115 |
10 K - 20 K |
3 |
|
DR4 |
RSL |
||||||
DL4 |
LVDT/RVDT |
||||||
DS5 |
SYN |
1* |
28 - 90 |
2 - 115 |
47 - 1 K |
3 |
|
DR5 |
RSL |
||||||
DL5 |
LVDT/RVDT |
||||||
DSX |
SYN |
1* |
X |
X |
X |
X |
X = TBD; special configuration, requires special part number code designation, contact factory |
DRX |
RSL |
||||||
DLX |
LVDT/RVDT |
||||||
DSA |
SYN |
2 |
2 - 28 |
2 - 115 |
47 - 1 K |
1.5 |
|
DRA |
RSL |
||||||
DLA |
LVDT/RVDT |
||||||
DSB |
SYN |
2 |
2 - 28 |
2 - 115 |
1 K - 5 K |
1.5 |
|
DRB |
RSL |
||||||
DLB |
LVDT/RVDT |
||||||
DSC |
SYN |
2 |
2 - 28 |
2 - 115 |
5 K - 10 K |
1.5 |
|
DRC |
RSL |
||||||
DLC |
LVDT/RVDT |
||||||
DSD |
SYN |
2 |
2 - 28 |
2 - 115 |
10 K - 20 K |
1.5 |
|
DRD |
RSL |
||||||
DLD |
LVDT/RVDT |
||||||
DSE |
SYN |
2 |
28 - 90 |
2 - 115 |
47 - 1 K |
2.2 |
|
DRE |
RSL |
||||||
DLE |
LVDT/RVDT |
||||||
DSY |
SYN |
2 |
Y |
Y |
Y |
Y |
Y = TBD; special configuration, requires special part number code designation, contact factory |
DRY |
RSL |
||||||
DLY |
LVDT/RVDT |
||||||
DSJ |
SYN |
3 |
2 - 28 |
2 - 115 |
47 - 1 K |
0.5 |
|
DRJ |
RSL |
||||||
DLJ |
LVDT/RVDT |
||||||
DSK |
SYN |
3 |
2 - 28 |
2 - 115 |
1 K - 5 K |
0.5 |
|
DRK |
RSL |
||||||
DLK |
LVDT/RVDT |
||||||
DSL |
SYN |
3 |
2 - 28 |
2 - 115 |
5 K - 10 K |
0.5 |
|
DRL |
RSL |
||||||
DLL |
LVDT/RVDT |
||||||
DSM |
SYN |
3 |
2 - 28 |
2 - 115 |
10 K - 20 K |
0.5 |
|
DRM |
RSL |
||||||
DLM |
LVDT/RVDT |
||||||
DSN |
SYN |
3 |
28 - 90 |
2 - 115 |
47 - 1 K |
0.5 |
|
DRN |
RSL |
||||||
DLN |
LVDT/RVDT |
||||||
DSZ |
SYN |
3 |
Z |
Z |
Z |
Z |
Z = TBD; special configuration, requires special part number code designation, contact factory |
DRZ |
RSL |
||||||
DLZ |
LVDT/RVDT |
SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES
SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL)
Select the Synchro/Resolver-to-Digital (SDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.
Frequency/voltage band tolerances +/- 10%.
Module ID |
Input Voltage V (Vrms) |
Reference Voltage (Vrms) |
Frequency Range (Hz) |
Notes |
SD1 |
2 - 28 |
2 - 115 |
47 - 1 K |
|
SD2 |
2 - 28 |
2 - 115 |
1K - 5 K |
|
SD3 |
2 - 28 |
2 - 115 |
5K - 10 K |
|
SD4* |
2 - 28 |
2 - 115 |
10K - 20 K |
|
SD5 |
28 - 90 |
2 - 115 |
47 - 1 K |
|
SDX* |
X |
X |
X |
X = TBD; special configuration, requires special part number code designation, contact factory |
*Consult factory for availability
LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)
Select the LVDT/RVDT-to-Digital (LDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Excitation voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.
Frequency/voltage band tolerances +/- 10%.
Module ID |
Input Signal Voltage V (Vrms) |
Excitation Voltage (Vrms) |
Frequency Range (Hz) |
Notes |
LD1 |
2 - 28 |
2 - 115 |
47 - 1 K |
|
LD2 |
2 - 28 |
2 - 115 |
1K - 5 K |
|
LD3 |
2 - 28 |
2 - 115 |
5K - 10 K |
|
LD4* |
2 - 28 |
2 - 115 |
10K - 20 K |
|
LD5 |
28 - 90 |
2 - 115 |
47 - 1 K |
|
LDX* |
X |
X |
X |
X = TBD; special configuration, requires special part number code designation, contact factory |
*Consult factory for availability
Revision History
Motherboard Manual - 67PPC2 Revision History
Revision |
Revision Date |
Description |
C |
2024-03-05 |
ECO C11199, transition to docbuilder format. Pg.7 & 9, updated from 'over 70' to 'over 100'. Pg.7, updated product image. Pg.7, updated processor clock speed from '1.5 GHz' to '1.8 GHz'. Pg.7, updated block diagram for revised processor clock speed. Pg.7, changed SATA II function slot example to '480 GB'. Pg.7, added Deos to OS support feature bullet. Pg.8-9, updated available module functions table. Pg.10, updated Introduction; added product overview section. Pg.12/17, updated +5VDC power spec. Pg.12, added +3.3V_Aux to 'Power (Motherboard)'. Pg.12, changed 'E' to 'H' in "Temperature, Operating". Pg.12, removed 'E' from "Temperature Cycling". Pg.15, updated OS support; removed BSP statement. Pg.22, updated TTL register names in table. Pg.25, changed TTL I/O Select to TTL Direction; corrected init value & data bits. Pg.25, updated TTL Data function & op settings. Pg.26, updated Loopback op settings. Pg.26, changed TTL Enable Interrupts to TTL IRQ Enable; updated function. Pg.26, changed TTL Set Edge/Level to TTL IRQ Polarity; updated function & op settings. Pg.27, changed TTL Interrupt Status to TTL IRQ Status. Pg.37, added Module Slot Addressing Ready. Pg.58, added Module Slot Addressing Ready offset. Pg.67-71, revised P0/P1/P2-P6 pinout tables to meet VPX Standard format. Pg.76-78, removed Module pinouts from manual. Pg.82, updated processor clock speed from 1.5 GHz to 1.8 GHz. Pg.82, removed Note 2 (N/A) from 'Notes' table. Pg.83, added Single Channel note. Pg.83, changed DSE/DRE/DLE Power/CH maximum (VA) value from '1.5' to '2.2'. |
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