The 68G5P 3U OpenVPX Multifunction I/O Board with External PCIe and SATA II I/F offers a variety of features designed to meet the needs of complex and time-critical sense and response requirements for I/O-intensive, mission-critical applications. Key features of the 68G5P include:

3U Profiles supported: This board is compatible with both VPX and OpenVPX standards, with module and slot profiles specified as MOD3-PAY-2U2U-16.2.16-2 and SLT3-PAY-2U2U-14.2.17, respectively. This allows for interoperability with a wide range of systems.

Connections via front panel, rear panel, or both: The board provides flexibility in connectivity options, with the ability to connect to devices via the front panel, rear panel, or both. This is particularly useful in different mounting or space-constrained scenarios.

PCIe (x1): The board features PCIe (x1) connectivity for fast and efficient data transfer.

Control via Gig-E or PCIe interface: The 68G5P provides easy integration into a system by way of Gig-E or PCIe interface control capability. Gig-E interface is ideal for systems requiring high-speed communication, while PCIe interface is an excellent option for data intensive applications.

Support for three independent, smart function modules: The board can support up to three independent, smart function modules based on the COSA® architecture. With over one hundred modules to choose from, this allows for a wide range of input and output capabilities, including analog and digital I/O, signal generation and acquisition, and communication interfaces. Each function module slot also has an independent x1 SerDes interface.

2x 10/100/1000 Base-T or 1000Base-KX Ethernet: The board has two 10/100/1000 Base-T Ethernet or 1000Base-KX Ethernet ports, with the option to have one to the rear, one to the front I/O, or both to the rear. These ports provide enhanced data communication capabilities and faster network connectivity for advanced control and data acquisition applications.

Intelligent I/O library support included: The 68G5P comes with intelligent I/O library support to help manage and control the I/O capabilities of the board.

Background Built-In-Test (BIT): The board’s BIT continually checks and reports on the health of each channel, allowing for preventative maintenance and reducing the likelihood of downtime.

Software Support Kits (SSKs) and drivers available: SSKs and drivers are available to make the board easier to integrate into a system and develop software.

VICTORY Interface Services: NAI offers VICTORY Interface Services as an option, providing an open, industry-standard approach for integrating different components in a system.

Commercial and rugged models: The 68G5P is available in both commercial and rugged models, making it suitable for a wide range of applications.

Designed to meet ANSI / VITA 47 environmental requirements: By meeting ANSI / VITA 47 environmental requirements, the 68G5P provides reliability and durability in harsh operating conditions.

Operating temperature: The board has a wide operating temperature range, with a commercial model operating from 0° C to 70° C, and a rugged model operating from -40° C to +85° C. This makes it suitable for use in a wide range of environments.

Overall, the 68G5P 3U OpenVPX Multifunction I/O Board with External PCIe and SATA II I/F is a reliable and versatile solution for demanding computing environments that require high-performance and flexible I/O capabilities.

Specifications are subject to change without notice.

Unless otherwise specified, the following table outlines the general Environmental Specifications design guidelines for board level products of North Atlantic Industries. All our cPCI, VME and OpenVPX boards are designed for either air or conduction cooling. All boards also incorporate appropriate stiffening to ensure performance during shock and vibration but also to assure reliable operation (lower fatigue stresses) over the service life of the product.

Notes:

Specifications subject to change without notice

The table below lists the BAR used for access to the motherboard and module registers. The second BAR is used internally for motherboard and module firmware updates. The other cPCI/PCIe BARs not listed are not used.

The memory map for the modules are dependent on the types of modules on the board and the order in which the modules are installed on the board as well as the firmware installed on the motherboard. The function modules are enumerated allowing for dynamic memory space allocation and therefore the “start” address of the module function register area is factory pre-defined (and read from) the Module Address register. Refer to Figure 1 for an example.

Figure 1. Register Memory Map Addressing for Motherboards with ESx and 1 Module

Motherboard Registers

Read/Write access to the motherboard registers starts with the base address for the board and then the motherboard base offset address.

For example, to address Module Slot 1 Start Address register (i.e. register address = 0x0400):

Module Registers:

Read/Write access to the Function module’s registers start with the base address of the board. Add the “content” for the Module Start Address and then, add the specific module function register offset.

For example, to address an appropriate/specific function module with a register offset:

The Module Slot Address, Module Slot Size and Module Slot ID provide information about the modules detected on the board.

The registers identified in this section provide information about the board’s hardware.

The registers in this section provide information on the revision of the firmware installed on the motherboard.

The registers in this provide motherboard temperature measurement information.

The registers in this section provide a summary of motherboard temperature sensors and their corresponding bits. Additionally, this section provides an overview of the registers allocated to those sensors, which are used to monitor current/minimum/maximum temperature readings, upper & lower critical/warning temperature thresholds, and whether or not a programmed temperature threshold has been exceeded.

These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).

The registers in this section provide information about the Ethernet Configuration for the two ports on the board.

Important: Regardless if the board is configured for one or two Ethernet ports, the second IP address cannot be on the same Subnet as the First IP Address. The table below provides examples of valid and invalid IP Addresses and Subnet Mask Addresses.

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Function: Provides the ability to command individual Modules to Reset, Power-down, or Power-up.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Operational Settings: The Module Control Commands registers provide the ability to request individual Modules to perform one of the following functions – Reset, Power-down, Power-up. Only one command can be requested at a time per Module. For example, one can’t request a Reset and a Power-down at the same time for the same Module. Once the command is recognized and handled, the bit will be cleared.

There is one Control Command Request register per Module. Each register is Bit-mapped as shown in the table below:

Function: Registers reserved as scratch pad for customer use.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Operational Settings: This area in memory is reserved for customer use.

Motherboard Core Information

Motherboard FPGA Information

Module Communications Status

Module BIT Status

The interface uses a specific message framework for all commands and responses. All messages begin with a Preamble code and end with a Postamble code. The message framework is shown below.

Notes

The interface provides two main addressing areas: Onboard and Off-board.

Onboard addressing refers to accessing resources located on the board that is implementing the operation interface (including its modules).

Off-board addressing refers to accessing resources located on another board reachable via VME, PCI, or other bus. Off-board addressing requires a Master/Slave configuration.

The user must always specify if a particular address is Onboard or Off-board. See the command descriptions for the onboard and off-board flags.

Within a particular board (Onboard or Off-board), the address space is broken up into two areas: Motherboard Common Address Space and Module Address Space. All addresses are 32-bit.

Motherboard Common Address Space starts at 0x00000000 and ends at 0x00004000. This is a 4Kx32-bit address space (16 kbytes).

Module Address Space starts at 0x00004000. Module addressing is dynamically configured at startup. NAI boards support between 1 and 6 modules. The minimum module address space size is 4Kx32 (16 kbytes) and module sizes are always a multiple of 4Kx32.

Module addressing is dynamic and cumulative. The first detected module (starting with Slot 1) is given an address of 0x00004000. The 2nd detected Module is given an address of:

First_Detected_Module_Address + First_Detected_Module_Size

If no module is detected in a module slot, that slot is not given an address. Therefore, if the first detected Module is in Slot 2, then that module address will be 0x00004000. If the next detected module is in Slot 4, then the address of that Module will be:

Second_Detected_Module_Address = First_Detected_Module_Address + First_Detected_Module_Size

If a 3rd Module is detected in Slot 6, then the address of that Module will be:

Third_Detected_Module_Address = Second_Detected_Module_Address + Second_Detected_Module_Size

Users can always retrieve the Module Addresses, Module Sizes and Module IDs from the fixed Motherboard Common address area. This data is set upon each board startup. While the Module Addressing is dynamic, the address where these addresses are stored is fixed. For example, to find the startup address of the module location in Slot 3, refer to the MB Common Address 0x00000408 from the Motherboard Common Addresses table that follows.

The 68G5P 3U OpenVPX Multifunction I/O board is available in two configurations: convection-cooled and conduction-cooled. The 68G5P follows the OpenVPX “Payload Slot Profile” configured as:

Slot profile: SLT3-PAY-2U2U-14.2.17

Module profile: MOD3-PAY-2U2U-16.2.16-2

User I/O is available through the (J3, J4) front panel connectors when card is configured with front panel I/O and through the OpenVPX user defined rear I/O connectors P1, P2 (see part number and pin-out information).

50-pin male connectors, 2 mm, Harwin P/N M80-5S25022M3.

Mate kit: Harwin M80-486 product family (mating connector kit is available from Harwin as P/N M80-9415005). This mating connector may be purchased separately under NAI P/N 05-0118 (contact factory).

Industry standard mini-HDMI type (type-C receptacle).

Front Panel LEDs indications (only available on air-cooled units).

Front Panel: No dedicated chassis GND pins available. Jack screw sockets are chassis GND. Rear connector key guides are chassis ground.

Front Panel: J3 pins 1, 26; J4 pins 25, 50 (connected to card power/system ground).

The 68G5P utilizes a Mini-HDMI type card edge connector J5, available on either convection or conduction-cooled configurations that provides the following signals:

NAI also provides an optional “breakout” adapter board (NAI P/N 75SBC4-BB) with a mini-HDMI to mini-HDMI type cable. The “breakout” adapter board and a Micro-HDMI cable (NAI P/N 75SBC4-BB) allow for standard I/O connections to Ethernet and asynchronous serial (DB9). Consult the factory for availability.

The 68G5P 3U OpenVPX multifunction I/O board provides interface via the rear VPX connectors.

The following provides connector/pinout data for Front Panel connectors J3 and J4. Each connector provides 50 pins of I/O.

Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Module Operational Manuals

Notes

Select the Synchro/Resolver-to-Digital (SDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.

Frequency/voltage band tolerances +/- 10%.