Function: The value represents voltage, current or engineering units depending on mode.

Type: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: Values are dependent on Polarity and Range settings for the channel

Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x0000 FFFF Bipolar (2’s complement. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: NA

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: Sets input format for polarity and range for each channel. Note, if the Enable Floating Point Mode register is set to 1, the Floating Point Scale register must be set to the Range.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R/W

Initialized Value: 0x0000 0010 (ADE: ± 10 V, ADF: ± 100 V)

Operational Settings: For bipolar/unipolar selection, program D4 bit as 0 for unipolar and 1 for bipolar as shown in table below. Polarity and Range

Range

Function: Sets the desired sample rate for all channels.

Type: unsigned binary word (32-bit)

Data Range: 1000 – 200000 (0x0000 03E8 to 0x0003 0D40)

Read/Write: R/W

Initialized Value: 200000 (0x0003 0D40)

Operational Settings: LSB is 1Hz. Sample rate applies to all channels.

Function: The break frequency is the 3 dB point of a digital, second-order, IIR low-pass filter.

Type: unsigned binary word (32-bit)

Data Range: 0 Hz to 90 kHz (0x0000 0000 to 0x0001 5F90)

Read/Write: R/W

Initialized Value: 20 kHz (0x0000 4E20)

Operational Settings: LSB is 1 Hz. The break frequency must not be less than 1% of the clock rate frequency. (Example: For a clock rate frequency of 2 kHz, the Filter Break Frequency should be no less than 20 Hz). Set to 0 to disables filter.

Acquisition & Conversion Time: Total time required to obtain digital result. It consists of acquisition, decimator group delay when engaged, and IIR filter. image::ADE-ADF/ADE-ADF_img2.png[] Acquisition & Conversion time will vary depending on the programmed sample rates. Expect a total delay of 5.5μs when sampling at 200kHz (max). Refer to the following chart for lower sample rates: image::ADE-ADF/ADE-ADF_img3.png[]

Function: Latches all A/D channels.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Set 1 to latch all A/D channels and 0 to unlatch all A/D channels.

Notes: The channel’s A/D Reading register will maintain the same reading while the Latch A/D bit is set to 1. Sampling for the channel will resume for that channel only when the bit is set to 0. Latch A/D Channel

Function: Resets over loaded channels (i.e., channels where an overcurrent condition has been detected).

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: W

Initialized Value: 0

Operational Settings: Set to 1 to reset over loaded channels. Writing a 1 to this register will re-enable channels in which an overcurrent condition was detected.

Function: Sets bit to enable the associated Built-In Self-Test (BIST): IBIT, CBIT and UBIT.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R/W

Initialized Value: 0x4 (CBIT Test Enabled)

Operational Settings: BIT tests include an on-line (CBIT) test and two off-line (UBIT, IBIT) tests. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggers when the BIT testing detects failures.

Test Enabled

Function: Specifies voltage to be applied for the A/D UBIT off-line test. Type: signed binary word (32-bit) Data Range: Voltage and Current values are dependent on Polarity and Range settings for the channel. Unipolar: 0x0000 to 0x0000 FFFF Bipolar (2’s complement. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF Read/Write: R/W Initialized Value: 0 Operational Settings: LSB is dependent on the Range setting. Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples. == FIFO Registers The FIFO registers are configurable for each channel.

Function: Available data in the FIFO buffer can be retrieved, one word at a time. (LSB for 16-bit word resolution is dependent on the Polarity and Range setting). Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x0000 FFFF Bipolar (2’s complement. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754) Read/Write: R Initialized Value: N/A Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples. === FIFO Word Count

Function: This is a counter that reports the number of 16-bit words stored in the FIFO buffer. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x000F FFFF Read/Write: R Initialized Value: 0 Operational Settings: Every time a read operation is made from the A/D Data memory address, its corresponding Words in FIFO counter will be decremented by one. The maximum number of words that can be stored in the FIFO is 1 mega words. === FIFO Thresholds The FIFO Almost Empty, FIFO Low Watermark, FIFO High Watermark, FIFO Almost Full and FIFO Buffer Size sets the threshold limits that are used to set the bits in the FIFO Status register. FIFO Almost Empty Function: The FIFO Almost Empty is used to set the limits for the “almost empty” status. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x000F FFFF Read/Write: R/W Initialized Value: Not set Operational Settings: When the Words in FIFO counter is greater than or equal to the value stored in the FIFO Almost Empty register, the “almost empty” bit (D1) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the register, the “almost empty” bit (D1) of the FIFO Status register will be reset. === FIFO Low Watermark

Function: The FIFO Low Watermark (low-threshold level) is used to set the limits for the “low watermark” status. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x000F FFFF Read/Write: R/W Initialized Value: Not set Operational Settings: When the Words in FIFO counter is less than or equal to the value stored in the FIFO Low Watermark register, the “low watermark” bit (D2) of the FIFO Status register will be set. When the Words in FIFO counter is greater than the value stored in the register, the “low watermark” bit (D2) of the FIFO Status register will be reset. === FIFO High Watermark

Function: The FIFO High Watermark (high-threshold level) is used to set the limits for the “high watermark” status. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x000F FFFF Read/Write: R/W Initialized Value: Not set Operational Settings: When the Words in FIFO counter is greater than or equal to the value stored in the FIFO High Watermark register, the “high watermark” bit (D3) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the high- threshold, the “high watermark” bit (D3) of the FIFO Status register will be reset. === FIFO Almost Full

Function: The FIFO Almost Full is used to set the limits for the “almost full” status. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x000F FFFF Read/Write: R/W Initialized Value: Not set Operational Settings: When the Words in FIFO counter is greater than or equal to the value stored in the FIFO Almost Full register, the “almost full” bit (D4) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the register, the “almost full” bit (D4) of the FIFO Status register will be reset. === FIFO Buffer Size

Function: Sets the number of samples to be taken and placed into the FIFO when a trigger occurs. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x000F FFFF Read/Write: R/W Initialized Value: 0x000F FFFF Operational Settings: The size of each sample (number of words written to the FIFO per sample) is determined by the sample format described by the FIFO Buffer Control register. When the Words in FIFO counter reaches the FIFO Buffer Size, the “sample done” bit (D6) is set and no additional samples will be placed in the FIFO. When Words in FIFO counter is less than FIFO Buffer Size, the “sample done” bit (D6) will be reset. === Data Control

Function: Sets the format of the samples to be stored in the FIFO buffer which is determined by the bitmapped table. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 0014 Read/Write: R/W Initialized Value: 0 Operational Settings: The Time Stamp data format (D4) requires one word of storage space from the FIFO buffer. For example, if (D4) is set to 0 and the FIFO Buffer Size register is set to 1, a FIFO write will put one word of data in the FIFO memory space per sample and discard the timestamp (sample counter). Since the maximum physical size of FIFO is 1M words for each channel, the value in the FIFO Buffer Size and Data Control registers could cause an overflow to the FIFO buffer. When an overflow condition occurs, any data that is not placed in the FIFO will be lost.

Function: Sets the number of delay samples before the actual FIFO data collection begins. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R/W Initialized Value: not set Operational Settings: The data collected during the delay period will be discarded. === FIFO Skip Count

Function: Sets how many samples to skip over when storing data in FIFO. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R/W Initialized Value: 0 (No Skip Count (FIFO stores every sample)) Operational Settings: If the sample rate for a channel is 10 kHz, there would be a new sample every 100μs. By setting the FIFO skip count to 1, the FIFO will store a new sample every 200 μs, or at a 5 kHz rate. === Clear FIFO

Function: Clears FIFO by resetting the Words in FIFO count. Type: unsigned binary word (32-bit) Data Range: 0 or 1 Read/Write: W Initialized Value: N/A Operational Settings: This resets the Words in FIFO to zero; Clear FIFO register does not clear data in the buffer. A read to the buffer data will give “aged” data. Write a 1 to reset the Words in FIFO for the channel.

Clear FIFO

Function: Starts/triggers FIFO. FIFO can be started/triggered by different sources. Type: unsigned binary word (32-bit) Data Range: 0x0 to 0x1FF Read/Write: R/W Initialized Value: 0 (Disable Trigger) Operational Settings: For the current implementation, triggering of FIFO is by Software Trigger only. Hardware triggering will be implemented in a future release. Hardware triggering will be platform dependent based on pin-outs and I/O availability. See the tables that follow for the current and pending settings.

FIFO Trigger Control

Function: Software trigger is used to start the FIFO buffer and the collection of data. Type: unsigned binary word (32-bit) Data Range: 0 or 1 Read/Write: W Initialized Value: 0 (Not Triggered) Operational Settings: To use this operation, the FIFO Trigger Control register must be set up as described in the FIFO Trigger Control register. Write a 1 to trigger FIFO collection for all channels.

FIFO Software Trigger

Function: This register sets the floating point offset to add to AD data. Type: Single Precision Floating Point Value (IEEE-754) Data Range: N/A Read/Write: R/W Initialized Value: 0.0 Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples. === Floating Point Scale

Function: This register sets the floating point scale to multiple to the AD data. Type: Single Precision Floating Point Value (IEEE-754) Data Range: N/A Read/Write: R/W Initialized Value: Default Voltage Range (ADE: 10 V, ADF: 100 V) Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples. === Floating Point State

Function: Indicates whether the module’s internal processing is converting the register values and internal values to the binary representation of the mode selected (Integer or Floating Point). Type: unsigned binary word (32-bit) Data Range: 0 to 1 Read/Write: R Initialized Value: 0 Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point). Floating Point State

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The BIT Status register will indicate an error when the voltage read is not within the error of the set value. BIT Dynamic Status BIT Latched Status BIT Interrupt Enable BIT Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s BIT error. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0 === BIT Diagnostic Upon detection of a BIT error, the following registers provide additional information about the error: Power-on BIT Error (Dynamic and Latched) Anti-Aliasing Filter Error (Dynamic and Latched) Voltage Reading Accuracy Error (Dynamic and Latched) The diagnostic Dynamic register indicates the current condition of the channel’s BIT error status. The diagnostic Latched Status register will maintain the last condition of the channel’s BIT error status. The diagnostic Latched Status will be cleared when the BIT Latched Status register is cleared. === Power-on BIT Error

Function: The Power-on BIT Error register is set when a failure is detected during the power-on self-test (POST) sequence. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R Initialized Value: 0 Operational Settings: 1 is read when a fault is detected. 0 indicates no fault detected. Note: Faults are detected (associated channel(s) bit set to 1) within 10 ms. Power-on BIT Error

Function: The Anti-Aliasing Filter Error register is set when the front-end amplifier fails an internal common-mode rejection ratio (CMRR) test. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R Initialized Value: 0 Operational Settings: 1 is read when a fault is detected. 0 indicates no fault detected. Note: Faults are detected (associated channel(s) bit set to 1) within 10 ms. Note: Clearing the latched BIT status will also clear this error register. Anti-Aliasing Filter Error

Function: The Voltage Reading Accuracy Error register is set when a redundant voltage measurement is inconsistent with the input voltage level detected. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R Initialized Value: 0 Operational Settings: 1 is read when a fault is detected. 0 indicates no fault detected. Note: Faults are detected (associated channel(s) bit set to 1) within 10 ms. Note: Clearing the latched BIT status will also clear this error register. Voltage Reading Accuracy Error

There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0-D6 is used to show the different conditions of the buffer. Description Configurable?

FIFO Dynamic Status FIFO Latched Status FIFO Interrupt Enable FIFO Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the FIFO status type; there is a separate register for each channel. Type: binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 007F Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0 Notes: Shown below is an example of interrupts generated for the High Watermark. As shown, the interrupt is generated as the FIFO count crosses the High Watermark. The interrupt will not be generated a second time until the count goes below the watermark and then above it again. image::ADE-ADF/ADE-ADF_img4.png[]

There are four registers associated with the Open/Over-Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. These registers are only applicable to Module ADE. Note: the channel 16 negative pin on the I/O connector MUST be tied to ground for the open detection circuitry to function properly. Failure to connect the channel 16 negative pin to ground will cause intermittent open-detect behavior on all channels. Note: both ends of any unused channels (Pos/Neg) should be tied to the channel 16 negative pin, referred to as the Common Mode Reference Point (CMRP; isolated from system power/ground). Tying only one end of a channel, while leaving the opposing end open, may cause Open Circuit Detection to deliver unwanted voltages to your channels in use. Open/Over-Voltage Dynamic Status Open/Over-Voltage Latched Status Open/Over-Voltage Interrupt Enable Open/Over-Voltage Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Open/Over-Voltage error. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0 === External Power Loss Status There are four registers associated with the External Power Loss Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0 = +12V External Power Loss D1 = -12V External Power Loss External Power Loss Dynamic Status External Power Loss Latched Status External Power Loss Interrupt Enable External Power Loss Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s External Power Loss error. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 0003 Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0 === Threshold Detect Status The Analog-to-Digital Modules provide registers that support threshold detection. Refer to “Analog-to-Digital Threshold and Saturation Programming Module Manual” for the register descriptions. === Saturation Status The Analog-to-Digital Modules provide registers that support saturation detection. Refer to “Analog-to-Digital Threshold and Saturation Programming Module Manual” for the register descriptions. === Front-End Amplifier Failure Status There are four registers associated with the Front-end Amplifier Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. These registers are only applicable to Module ADF. Front-end Amplifier Failure Dynamic Status Front-end Amplifier Failure Latched Status Front-end Amplifier Failure Interrupt Enable Front-end Amplifier Failure Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Front-end Amplifier Failure error. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0 === Inter-FPGA Failure Status Data is periodically transferred between the Lattice FPGA and the Xilinx FPGA. A CRC value is calculated and verified with each data transfer. A CRC error flag is sent from the Lattice FPGA to the Xilinx FPGA if a CRC error is detected. The Xilinx FPGA contains a counter that will increase by two when a CRC error is flagged and decremented by one when there is no CRC error. If the counter reaches ten, the Xilinx FPGA will set the Inter-FPGA Failure status bit and shut down the isolated power supply. In order to recover from an Inter-FPGA Failure, the module needs to be reset and re-initialized. There are four registers associated with the Inter-FPGA Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. 0 = Normal; 0x0FFF = Inter-FPGA Communication Failure. The status represents the status for all channels on the module. Inter-FPGA Failure Dynamic Status Inter-FPGA Failure Latched Status Inter-FPGA Failure Interrupt Enable Inter-FPGA Failure Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s Inter-FPGA Failure error. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0 === Summary Status There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Summary Status Dynamic Status Summary Status Latched Status Summary Status Interrupt Enable Summary Status Set Edge/Level Interrupt

Function: Sets the corresponding bit if any fault (BIT, Overcurrent, Open, External Power Loss, or Inter-FPGA Failure) occurs on that channel. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) Initialized Value: 0== FUNCTION REGISTER MAP

Key: Bold Italic = Configuration/Control Bold Underline = Measurement/Status

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).