Data Sheet

North Atlantic Industries (NAI) is a leading independent supplier of rugged COTS embedded computing products for industrial, commercial aerospace, and defense markets. Aligned with MOSA, SOSA and FACE standards, NAI’s Configurable Open System Architecture™ (COSA®) accelerates a customer’s time-to-mission by providing the most modular, agile, and rugged COTS portfolio of embedded smart modules, I/O boards, Single Board Computers (SBCs), Power Supplies and Ruggedized Systems of its kind. COSA products are pre-engineered to work together, enabling easy changes, reuses, or repurposing down the road. By utilizing FPGAs and SoCs, NAI has created smart modules that enable the rapid creation of configurable mission systems while reducing or eliminating SBC overhead.

NAI’s 68ARM2 3U OpenVPX Single Board Computer supports a wide range of input and output capabilities, including analog and digital I/O, signal generation and acquisition, and communication interfaces. Powered by a Xilinx Zynq® Ultrascale+™ dual- or quad-core ARM® Cortex™A53 MPCore™ @ 1.3 GHz MP SoC processor, the 68ARM2 provides a balanced performace vs. power dissipation SBC solution for harsh, SWaP-constrained environments.

The ENAIBL Software Support Kit (SSK) is supplied with all system platform based board level products. This platform’s SSK contents include html format help documentation which defines board specific library functions and their respective parameter requirements. A board specific library and its source code is provided (module level ‘C’ and header files) to facilitate function implementation independent of user operating system (O/S). Portability files are provided to identify Board Support Package (BSP) dependent functions and help port code to other common system BSPs. With the use of the provided help documentation, these libraries are easily ported to any 32-bit O/S such as RTOS or Linux.

The latest version of a board specific SSK can be downloaded from our website www.naii.com in the software downloads section. A Quick-Start Software Manual is also available for download where the SSK contents are detailed, Quick-Start Instructions provided and GUI applications are described therein. For other operating system support, contact factory.

The 68ARM2 is a 3U OpenVPX, low-power and high-performance Single Board Computer (SBC). The 68ARM2 offers on-board I/O expansion through three (3) Generation-5 (GEN5) NAI smart I/O function modules. Powered by the Xilinx Zynq® UltraScale+™ dual- or quad-core ARM® Cortex™-A53 MPCore™ @ 1.3 GHz MP SoC processor, the 68ARM2 provides a balanced performance vs. power dissipation SBC solution, for today’s demanding, space constrained and resource limited embedded systems.

The 68ARM2 SBC, supplemented with a full complement of software I/O libraries and drivers, is ideally suited for integration within a multitude of commercial and rugged, military embedded processing and I/O systems. The 68ARM2 SBC provides a PCIe bus root-complex and/or Gigabit Ethernet (GbE) capability and may be utilized with other NAI high-density multifunction I/O boards to provide a complete, expandable, low power, high performance and programmable solution for sensor and communication data acquisition, management, processing and distribution. All I/O sensor data is available on the PCIe bus or GbE.

The 68ARM2 card provides high-density rear I/O for systems requiring closed chassis operation (i.e. embedded, conduction cooled applications) and simple card replacement. Using rear I/O minimizes the effort required to remove cards from a chassis improving maintainability and reliability.

The 68ARM2 card uses OpenVPX P0, P1, and P2 rear connectors. Rear I/O connectivity, via the P2 and P1 connectors, includes Ethernet, asynchronous serial, I2C, programmable TTL, USB and access to the on-board add-on Module I/O.

The 68ARM2 utilizes the UltraScale+™ dual- or quad-core ARM® Cortex™-A53 MPCore™ processor with the following capabilities. Note: all processor capabilities may not be user accessible features at the end item level.

Four ARM® Cortex™-A53 cores

8GB of DDR4 SDRAM (plus ECC)

2 Ethernet interfaces, supporting combinations of:

Up to two 1 Gbps KX Ethernet MACs

Up to two 1 Gbps TX Ethernet MACs

Two PCIe interfaces

6x1 PCIe ports for VPX communication (default)

1x1 PCIe to Module interface 2

Two SATA 2.0 controllers

32GB onboard ROM

SATA interface for storage through Module Slot-3 (factory configured).

One high-speed USB 3.0 port

I C port to the VPX backplane

RS232 Serial debug port

On-board TTL Digital I/O

Quad SPI Flash controller

8 Kb FRAM

I/O Modules

Three I/O module slots enable integrators to mix-n-match a variety I/O and communication functions. The 68ARM2 uses a GEN5 high-speed SerDes Modbus. Some of the new modules are currently under development. Please consult the factory for updates on the availability of certain functions. Module I/O signals are available as both front and rear I/O.

Software

The 68ARM2 supports options for Power-On-Self-Test (POST) testing (memory, peripherals, etc.). The 68ARM2 also supports function modules with NAI‘s flexible, leading-edge, fully programmable and continuous background built-in-test (BIT) enabled function. BIT tests both 68ARM2 on board functions and functions contained on expansion modules, making it a useful field service tool.

The U-boot firmware provides a foundation layer to interface between the raw board hardware. U-boot has programmable device set-up, setup flexibility, and supports booting supported Operating Systems with a straight-forward user interface. U-boot also allows booting from several different devices (check part numbering options).

VxWorks utilizes the WindRiver VxWorks Boot ROM. When specified/configured with VxWorks as an OS, a VxWorks Boot ROM image (with utilities) is pre-flashed at the factory supporting VxWorks development and FLASH download (check part numbering options).

Wind River VxWorks 7.0 and HVP, Xilinx PetaLinux, DDC-I Deos Contact NAI for availability of other operating systems.

Conduction-Cooled/Rugged

Operating temperature -40 to 85° C (measured at card edge/rail)

Storage temperature -55 to 105° C

Relative humidity 5 to 95% non-condensing

MTBF TBD

(see NAI card-level Environmental Specifications for other ruggedization & application environment levels)

*The 68ARM2 without modules does not derive any power from the +12V and -12V backplane rail supplies. When calculating total power supply consumption, remember to add the +12, -12, and 5V power consumption for two optional modules.

The 68ARM2 is compatible with the OpenVPX ANSI Vita 46 Specification. Conduction cooled 68ARM2 cards comply with ANSI/VITA 30.1‐2002. The following diagram is for reference only. All dimensions are in inches.

Real-Time Clock/Calendar (RTCC) is used to provide a system time and date function or can be used as an event timer. In addition, the MCP79410 includes:

64 Bytes SRAM, Battery Backed

1 Kbits EEPROM (128x8)

Power-Fail Time-Stamp for Battery Switchover

To maintain the RTCC and SRAM functions when the 5 V power is off, the RTC_STDBY pin must be connected to an external battery or power supply. The RTC_STDBY supply voltage should be between 1.4 V to 5.0 V. A typical RTC_STDBY supply requirement is 3.0 V @ 5 µA.

5.5 V is the maximum allowable RTC_STDBY input voltage. Any voltage larger than 5.5 V on the RTC_STDBY pin will damage the RTCC.

Serial Peripheral Interface Bus or SPI is a synchronous serial data link standard. SPI operates in full duplex mode. SPI devices communicate in master/slave mode where the master device starts a frame and sources the clock. The Ultrascale+™ CPU has one SPI controller with four device select pins (SPI_CS [3:0]). SPI_CS [0] is attached to an TPM. SPI_C [1,2,3] are unconnected. Linux device drivers are available to access TPM features.

The 68ARM2 has one serial port to the front and to the rear of the card. Do not plug into the serial port from both the front and rear of the card at the same time. This will cause errors when communicating to the card through the serial port.

For U-boot, the console port is selected at compile time. The 68ARM2 is configured to use the first serial port (SER1), which is routed to the OpenVPX P0 connector at rear of the card.

For Linux, the console port is passed as a kernel parameter by U-boot when it loads Linux and so can be selected at run-time.

TTL I/O are available as a configuration options (see pin-outs/P/N configuration).

Attached to the Ultrascale+™ CPU via local bus is a portion of the FPGA. This logic provides miscellaneous “glue” functions and 8 programmable TTL I/O channels (TTL_CH [8:1]). (These TTL channels may be programmed as inputs or outputs as needed. Channels that are programmed as inputs may generate interrupts. Interrupts on input pins can be programmed to occur on (high to low) or (low to high) input pin transitions. TTL interrupts occur on the IRQ10 input of the Ultrascale+™ CPU.

The 68ARM2 utilizes level shifting single ended bus transceivers, allowing the I/O pins to be 5 V tolerant. Each I/O pin is individually pulled up on card by a 4.7 KΩ resistor to the internal 3.3 V supply rail. External pull ups are not required for open collector operation. The TTL_CH [8:1] signals are pinned out as rear I/O on connector P2. As a factory option, the TTL_CH [8:5] pins may be disconnected and their associated P2 pins used to support additional module I/O signals.

Function: TTL direction. Sets channels as inputs or outputs. Bitmapped.

Function Address Offset(s): 0x83C1 0314

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value:0xFF (all channels to Input)

Operational Settings: Write 0 for input; 1 for output: Default is configured for Input. Data bits [7:0] correspond to one of eight channels TTL_CH [8:1] respectively.

TTL Direction

Function: Reads the TTL output of a specific channel’s I/O pin. Write to this register to set the channel to drive high or low. Bitmapped.

Function Address Offset(s): 0x83C1 0318

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value:0x00

Operational Settings: TTL_DIR register must be set for input (0). Write 0 for Low output; write 1 for High output: Data bits [7:0] correspond to one of eight channels TTL_CH [8:1] respectively.

Note Reading this register returns the output to the I/O pin of a specific channel and does not return the value set to the register. Because of this, if there is impedance to the pin it may not return the proper setting. For example, if the channel is set to drive high and some impedance causes it to drive low, then this register will read low (0). To guarantee the correct setting is read, please refer to the TTL Loopback register.

TTL Data

Function: Reads back TTL output channel(s) register contents. Bitmapped.

Function Address Offset(s): 0x83C1 031C

Type: binary word (16-bit)

Read/Write: R

Initialized Value:0x00

Operational Settings: Reads the state of output register for each channel, regardless of the state of the I/O channel. Note This provides the last commanded/written output value, which may differ from the TTL Data ‘read' status (if there is a problem, can be used for BIT status).

TTL Loopback

Function: TTL_DIR register must be set for inputs (0). Selects channels to be enabled for interrupts. Bitmapped.

*Function Address Offset(s): *0x83C1 0320

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value: 0x00

Operational Settings: Write 1 to enable interrupts for selected channel. Write 0 for interrupts not enabled, is default.

TTL IRQ Enable

Function: When the TTL IRQ Enable register is enabled, this register determines whether the interrupt will be generated for either “rising edge” or “falling edge” event detection.

Function Address Offset(s): 0x83C1 0324

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value:0x00

Operational Settings: Write a 1 to sense on a rising edge and a 0 to sense on a falling edge.

TTL IRQ Polarit

Function: When an interrupt for a channel or channels occurs, the corresponding bit for that channel will be set High in this register. Bitmapped.

Function Address Offset(s): 0x83C1 0328

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value:0x00

Operational Settings: When a TTL input channel generates an interrupt, the corresponding bit in the TTL_IRQ_STAT is set High (1). Once a bit is set by a transition on the input pin, the bit remains set until cleared by a register write. Writing a (1) to the corresponding bit resets the interrupt status to (0).

TTL IRQ Status

Function: Sets the bit to be either writable or write protected. Bitmapped.

Function Address Offset(s): 0x83C1 0094

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value:0x00

Operational Settings: Write a 1 to set the bit to Write Protected, and a 0 to set the bit to Writable.

Note There are other bits in this register such as Quick erase and Dataflush, so read/modify writes must be used.

SATA Register

NAI is developing an optional Tamper Detect Interface and Action Circuit for improved Security/Cybersecurity requirements. This circuit will offer FIPS 140-2 Level 3 Design Support, Crypto-Key Storage (with Battery-Backed RAM), Secure Boot and Anti-Tamper/Tamper Detect & Sanitize functions. For further information, please contact NAI.

68ARM2 BSP Processor Module Library

The 68ARM2 Processor library package provides function interfaces to the on-module functionality as well as the OpenVPX interface. This package contains Help documentation (in html format) that explains all the functions available in the library. The package also contains the source code (*.h, *.c) files as well as the files needed to build the library using Wind River Linux or other supported operating systems similar. Example programs are also provided to demonstrate the usage of the libraries in typical applications of the module.

Associated Documents

Check the NAI website or contact factory for the latest downloads and documentation.

The register map address consists of the following:

Function: Specifies the ARM Platform Type and Maximum Module Slot Count.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Operational Settings:

ARM Platform Type – UltraScale+ = 3

ARM Platform Type/Maximum Module Slot Count

Key: Bold Underline = Measurement/Status/Board Information Bold Italic = Configuration/Control

(For detailed supplement, please visit the NAI web-site specific product page and refer to: Ethernet Interface for Generation 5 SBC and Embedded IO Boards Specification)

The Ethernet Interface Option allows communications and control access to all function modules either via the system BUS or Ethernet ports 1 or 2.

The NAI interface supports IPv4 and IPv6 and both the TCP and UDP protocols. The Ethernet Operation Mode Command Listener application running on the motherboard host processor implements the operation interface. The listener is operational on startup through the nai_MBStartup process and listen on specific ports for commands to process. The default ports are listed below:

While the listener is active, note that interrupts from the motherboard do not trigger. The listener can be disabled by turning off the nai_MBStartup process through the Motherboard EEPROM. To turn off nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 1 in the console, either by serial port or telnet to the motherboard, and then reboot the system. To turn on the nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 0 in the console, either by serial port or telnet to the motherboard, and then reboot the system.

The 68ARM2 3U OpenVPX SBCand Multifunction I/O board is available in a conduction-cooled configuration. The 68ARM2 follows the OpenVPX “Payload Slot Profile” configured as:

Slot profile: SLT3-PAY-1F2U-14.2.12

Module profile: MOD3-PAY-1F2U-16.2.11-2

User I/O is available through the OpenVPX user defined rear I/O connectors P1, P2 (see part number and pin-out information).

Rear connector key guides are chassis ground.

The 68ARM2 utilizes a Mini-HDMI type card edge connector J5, available on either convection or conduction-cooled configurations that provides the following signals:

NAI also provides an optional “breakout” adapter board (NAI P/N 75SBC4-BB) with a mini-HDMI to mini-HDMI type cable. The “breakout” adapter board and a Micro-HDMI cable (NAI P/N 75SBC4-BB) allow for standard I/O connections to Ethernet and asynchronous serial (DB9). Consult the factory for availability.

Signal Descriptions J5

The 68ARM2 3U OpenVPX SBC and Multifunction I/O board provides interface via the rear VPX connectors.

Rear I/O Summary

Signals defined as N/C currently have no functionality associated and are not required for general operation.

P0 - Utility plane. Contains the following signal definitions:

P1 - Defined as Data/Control Planes (User defined I/O secondary)

P2 - User defined I/O (primary)

The P0 (Utility) Plane contains the primary power, bus and utility signals for the OpenVPX board. Additionally, several of the user defined pins can be utilized for Geographical Addressing, NVMRO, and a parallel SYSRST# signal. Signals defined as N/C currently have no functionality associated and is not required for general operation.