The 68ARM2 supports options for Power-On-Self-Test (POST) testing (memory, peripherals, etc.). The 68ARM2 also supports function modules with NAI‘s flexible, leading-edge, fully programmable and continuous background built-in-test (BIT) enabled function. BIT tests both 68ARM2 on board functions and functions contained on expansion modules, making it a useful field service tool.

The U-boot firmware provides a foundation layer to interface between the raw board hardware. U-boot has programmable device set-up, setup flexibility, and supports booting supported Operating Systems with a straight-forward user interface. U-boot also allows booting from several different devices (check part numbering options).

VxWorks utilizes the WindRiver VxWorks Boot ROM. When specified/configured with VxWorks as an OS, a VxWorks Boot ROM image (with utilities) is pre-flashed at the factory supporting VxWorks development and FLASH download (check part numbering options).

Wind River VxWorks 7.0 and HVP, Xilinx PetaLinux, DDC-I Deos

Contact NAI for availability of other operating systems.

The 68ARM2 conduction cooled version has four I/O connectors P0, P1, P2 and J5. Connectors P1, and P2 at the rear of the module, are used for the OpenVPX interface and for user I/O. Connector J5 is utilized for GbE Ethernet interface option & RS-232 Serial debug/console access. J5 uses a Mini-HDMI connector for USB port1, asynchronous serial (debug port) and optionally Ethernet port 1. A J5 connector adapter cable/breakout board P/N 75SBC4-BB optional accessory kit is available for quick connect (contact factory).

While only available in a conduction cooled option, the 68ARM2 may also be installed in a commercial air-cooled system chassis via a CC-to-AC chassis rail conversion kit. Please refer to part numbering options and contact factory for additional details.

The 68ARM2 provides a total of 8 GB of ECC DDR4 memory. This memory is organized as 4 1Gb x 16 MT40A1G16 devices (parts may vary), with a fifth device providing storage for ECC data. The Ultrascale+™ has an on chip 64-bit DDR4 memory controller. The controller has full ECC error-correction support, with the ability to detect multi-bit errors and correct single-bit errors within a nibble. Please consult the Micron data sheet for DDR4 device specific details.

The 68ARM2 supports one Micron MT25QL02GCBB8E12-0SIT 2Gb, Quad-SPI (QSPI) flash device. This device is used for nonvolatile storage of the ARM boot code, user data, and program. The device connects to the APU dedicated interface. The device interface may contain a secondary boot code. The device supports the Common Flash Interface (CFI). This 4-bit data memory interface can sustain burst read operations.

The FM24CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. The ferroelectric random-access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years. The 68ARM2 FRAM 64K bits are organized as 8,192 x 8 bits random access memory, connected to the Ultrascale+™ CPU through the I2C.

The Ultrascale+™ CPU has two available on-chip SATA 2 type controllers. SATA port 1 is supported with SerDes12, and SATA port 2 is supported with SerDes13. The 68ARM2 SATA port 2 is connected to an on-board SATA 2 Solid State Drive. SATA2 is connected to Module Slot 3 (supports direct SATA 2 solid-state FLASH module, if fitted) or to an external storage device via a programmable switch.

SATA Port 1

The SATA port 1 controller interface on the Ultrascale+™ CPU is directly connected to an on-board, solid-state drive. The SSD contains a single level cell NAND Flash together with a controller in a single multi-chip package. This multi-chip packaged device is soldered directly to the printed circuit board, for reliable electrical and mechanical connection.

The SSD has an internal write protect signal SATA-WP. This signal is pinned out as rear I/O on connector P2. The SATA-WP signal must be switched to ground to enable any write to the SSD. The SATA-WP signal is pulled up on card by a 4.7 KΩ resistor to the internal 3.3 V supply.

The onboard SATA drive conforms to the follow specifications:

The standard ordering code for the 68ARM2 includes a 32GB SSD drive. Larger devices are available; please consult the factory for availability.

SATA Port 2

The SATA port 2 interface on the Ultrascale+™ CPU is connected directly to a high-speed connector for Module Slot 3. An optional SATA Flash drive is available for the 68ARM2; please consult the Factory for availability.

The Ultrascale+™ supports two 10/100/1000Base-TX or two 1000Base-KX Ethernet ports.

The 68ARM2 Ethernet ports support:

Ethernet Port 1 can be routed as 10/100/1000Base-TX to the front, 10/100/1000Base-TX to the rear, or KX-Ethernet to the rear as build options.

Ethernet Port 2 can be routed as 10/100/1000Base-Tx to the rear or KX-Ethernet to the rear as build options.

I/O pin outs can be found in the Pinout Details section of this document.

The 68ARM2 supports one USB 3.0 port on the backplane and one USB 2.0 port on the front. Do not populate both interfaces at the same time. Contact factory for availability.

USB port 0 is available at the front of 68ARM2, on connector J5. The USB port can operate as a standalone host.

I²C is a two-wire, bidirectional single ended serial bus that provides efficient method of exchanging data between a master and slave device. The 68ARM2 has one device for communicating with onboard devices, as shown in the table below.

Real-Time Clock

Real-Time Clock/Calendar (RTCC) is used to provide a system time and date function or can be used as an event timer. In addition, the MCP79410 includes:

To maintain the RTCC and SRAM functions when the 5 V power is off, the RTC_STDBY pin must be connected to an external battery or power supply. The RTC_STDBY supply voltage should be between 1.4 V to 5.0 V. A typical RTC_STDBY supply requirement is 3.0 V @ 5 µA.

Serial Peripheral Interface Bus or SPI is a synchronous serial data link standard. SPI operates in full duplex mode. SPI devices communicate in master/slave mode where the master device starts a frame and sources the clock. The Ultrascale+™ CPU has one SPI controller with four device select pins (SPI_CS [3:0]). SPI_CS [0] is attached to an TPM. SPI_C [1,2,3] are unconnected.

Linux device drivers are available to access TPM features.

The 68ARM2 has one serial port to the front and to the rear of the card. Do not plug into the serial port from both the front and rear of the card at the same time. This will cause errors when communicating to the card through the serial port.

For U-boot, the console port is selected at compile time. The 68ARM2 is configured to use the first serial port (SER1), which is routed to the OpenVPX P0 connector at rear of the card.

For Linux, the console port is passed as a kernel parameter by U-boot when it loads Linux and so can be selected at run-time.

TTL Input

Input levels: TTL and CMOS compatible, single ended inputs

Input levels:

Vin L (min): 0 V

Vin L (max): 0.8 V

Vin H (min): 2.0 V

Vin H (max): 5.0 V

Attached to the Ultrascale+™ CPU via local bus is a portion of the FPGA. This logic provides miscellaneous “glue” functions and 8 programmable TTL I/O channels (TTL_CH [8:1]). (These TTL channels may be programmed as inputs or outputs as needed. Channels that are programmed as inputs may generate interrupts. Interrupts on input pins can be programmed to occur on (high to low) or (low to high) input pin transitions. TTL interrupts occur on the IRQ10 input of the Ultrascale+™ CPU.

The 68ARM2 utilizes level shifting single ended bus transceivers, allowing the I/O pins to be 5 V tolerant. Each I/O pin is individually pulled up on card by a 4.7 KΩ resistor to the internal 3.3 V supply rail. External pull ups are not required for open collector operation. The TTL_CH [8:1] signals are pinned out as rear I/O on connector P2. As a factory option, the TTL_CH [8:5] pins may be disconnected and their associated P2 pins used to support additional module I/O signals.

Function: Indicates that the module slots are ready to be addressed.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: 0xA5A5A5A5

Operational Settings: This register will contain the value of 0xA5A5A5A5 when the module addresses have been determined.

Function: Specifies the Base Address for the module in the specific slot position.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Based on board’s module configuration.

Operational Settings: 0x0000 0000 indicates no Module found.

Function: Specifies the Memory Size (in bytes) allocated for the module in the specific slot position.

Type: unsigned binary word (32-bit)

Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Assigned by factory for the module.

Operational Settings: 0x0000 0000 indicates no Module found.

Function: Specifies the Model ID for the module in the specified slot position.

Type: 4-character ASCII string

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Assigned by factory for the module.

Operational Settings: The Module ID is formatted as four ASCII bytes: three characters followed by a space. Module IDs are in little-endian order with a single space following the first three characters. For example, 'TL1' is '1LT', 'SC1' is '1CS' and so forth. Example below is for “TL1” (MSB justified). All value of 0000 0000 indicates no Module found.

Function: Specifies the Board Serial Number.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Serial number assigned by factory for the board.

Operational Settings: N/A

Function: Specifies the Board Platform Identifier. Values are for the ASCII characters for the NAI valid platforms (Identifiers).

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Initialized Value: ASCII code is for the Platform Identifier of the board

Operational Settings: Valid NAI platform and the associated value for the platform is shown below:

Function: Specifies the Board Model Identifier. Value is for the ASCII characters for the NAI valid model.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Initialized Value: ASCII code is for the Model Identifier of the board

Operational Settings: Example of NAI model and the associated value for the model is shown below:

Function: Specifies the Board Generation. Identifier values are for the ASCII characters for the NAI valid generation identifiers.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Initialized Value: ASCII code is for the Generation Identifier of the board

Operational Settings: Example of NAI generation and the associated value for the generation is shown below:

Function: Specifies the Processor Count and Ethernet Count

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Operational Settings:

     Processor Count - Integer: indicates the number of unique processor types on the motherboard.

     Ethernet Interface Count - Indicates the number of Ethernet interfaces on the product motherboard. For example, Single Ethernet = 1; Dual Ethernet = 2.

Function: Specifies the Maximum Module Slot Count and ARM Platform Type.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Operational Settings:

     Maximum Module Slot Count - Indicates the number of modules that can be installed on the product.

     ARM Platform - Altera = 1; Xilinx X1 = 2; Xilinx X2 = 3; UltraScale = 4

The registers in this section provide information about the Operating System that is running on the host processor on the motherboard. For boards that have more than one processor (ex. 75PPC1, 75INT2, 68PPC2, etc), the host processor would be the Power-PC or Intel processor.

Function: Specifies the ARM Processor on the motherboard. Values are for the ASCII characters for the NAI host processor platforms specified by the Operating System.

Type: 8-character ASCII string - Two (2) unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: ASCII code is for the Host Platform Identifier of the board.

Operational Settings: Valid NAI platforms based on Operating System loaded to host processor.

Function: Specifies the Operating System installed for the host processor. Values are for the ASCII characters for the NAI supported operating systems.

Type: 12-character ASCII string - Three (3) unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Operational Settings: ASCII, 12 characters; ('Linux', 'VxWorks', 'RTOS', …​)

Function: Specifies the Version of Operating System installed for the host processor.

Type: 8-character ASCII string - Two (2) unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Operational Settings: ASCII, 8 characters

Function: Specifies the Version of the NAI factory provided Motherboard Core Application installed on the board.

Type: Two (2) unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Operational Settings: The motherboard firmware version consists of four components: Major, Minor, Minor 2 and Minor 3.

Function: Specifies the Build Date/Time of the NAI factory provided Motherboard Core Application installed on the board.

Type: Two (2) unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Operational Settings: The motherboard firmware time consists of the Build Date and Build Time.

Function: Specifies the Version of the NAI factory provided Motherboard FPGA installed on the board.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Operational Settings: The motherboard FPGA firmware version consists of two components: Major, Minor.

Function: Specifies the Compile Date/Time of the NAI factory provided Motherboard FPGA installed on the board.

Type: unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Operational Settings: The motherboard firmware time consists of the Build Date and Time in the following format:

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) for the processor and PCB for UltraScale processor.

These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).

Function: Specifies the Measured Temperatures on Motherboard.

Type: signed byte (8-bits) for each temperature reading - Six (6) 32-bit words

Data Range: 0x0000 0000 to 0xFFFF 0000

Read/Write: R

Initialized Value: Value corresponding to the measured temperatures based on the table below.

Operational Settings: The 8-bit temperature readings are signed bytes. For example, if the following register contains the value 0x2B2B 0000:

Example:

The values would represent the following temperatures:

These registers provide higher precision readings of the current UltraScale and PCB temperatures.

Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds.

Type: unsigned binary word (32-bits)

Data Range: See table below

Read/Write: R

Initialized Value: 0

Operational Settings: This register provides a summary for motherboard sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.

The registers listed in this section apply to each module sensor listed for the Motherboard Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring motherboard temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Zynq Core Temperature sensor as an example.

Function: Specifies the Ethernet MAC Address and Ethernet Settings for the Ethernet port.

Type: Two (2) unsigned binary word (32-bit)

Data Range: See table.

Read/Write: R

Operational Settings: The Ethernet MAC Address consists of six octets. The Ethernet Settings are defined in table.

Function: Specifies the Ethernet Interface Name for the Ethernet port.

Type: 8-character ASCII string

Data Range: See table.

Read/Write: R

Operational Settings: The Ethernet Interface Name (eth0, eth1, etc) for the Ethernet port.

Function: Specifies the Ethernet IPv4 Address for the Ethernet port.

Type: Three (3) unsigned binary word (32-bit)

Data Range: See table.

Read/Write: R

Operational Settings: The Ethernet IPv4 Address consists of three parts: IPv4 Address, IPv4 Subnet Mask and IPv4 Gateway.

Function: Specifies the Ethernet IPv6 Address for the Ethernet port.

Type: Five (5) unsigned binary word (32-bit)

Data Range: See table.

Read/Write: R

Operational Settings: The IPv6 Prefix length indicates the network portion of an IPv6 address using the following format:

The following is an illustration of IPv6 addressing with IPv6 Prefix length of 64.

Function: Set an identifier for the interrupt.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Function: Sets where to direct the interrupt.

Type: unsigned binary word (32-bit)

Data Range: See table Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, the interrupt is sent as specified:

Function: Provides the ability to monitor the individual Module BIT Status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Operational Settings: The Module BIT Status registers provide the ability to monitor individual Module BIT results as Latched and current value. A 1 is any bit field indicates BIT failure for the Module in that slot.