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AC Reference Voltage Module

1 Introduction
2 Features
3 Specifications
Specifications
4 Principle of Operation
4.1 Built-In Test (BIT)/Diagnostic Capability
4.1.1 Auto Gain Control and Voltage Out-of-Spec Detection
4.1.2 Frequency Out-of-Spec Detection
4.1.3 Overcurrent Detection
4.2 Background BIT Threshold Programming
4.3 Status and Interrupts
4.4 Unit Conversions
4.5 User Watchdog Timer Capability
Register Descriptions
5 Register Descriptions
5.1 Reference Command Registers
- 5.1.1 Reference Frequency
- 5.1.2 Reference Voltage
5.2 Reference Reading Registers
5.3 Reference Control Registers
5.4 Background BIT Threshold Programming Registers
- 5.4.1 Background BIT Threshold
- 5.4.2 Reset BIT
5.5 Unit Conversion Programming Registers
- 5.5.1 Enable Floating Point Mode
- 5.5.2 Floating Point State
5.6 User Watchdog Timer Registers
5.7 Status and Interrupt Registers
6. Function Register Map
Reference Command Registers
Reference Reading Registers
Reference Control Registers
Unit Conversion Programming Registers
User Watchdog Timer Registers
Status Registers
Background BIT Threshold Programming Registers
Status Registers
Interrupt Registers
7 AC Reference Module Hardware Block Diagram
8 AC Reference Module Processing Block Diagram
9 Appendix A – Register Name Changes From Previous Releases
10 Firmware Revision Notes
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
Status Registers
Interrupt Registers
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

12-Channel Sigma-Delta ADC

AD1-AD3 DATA SHEET
INTRODUCTION
PRINCIPLE OF OPERATION
Engineering Scaling Conversions
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
Saturation Programming Registers
Status Registers
- Interrupt Registers
APPENDIX A: INTEGER/FLOATING POINT MODE PROGRAMMING
- Integer Mode Programming
- Floating Point Mode Voltage/Current Programming
Floating Point Mode Engineering Units Programming
APPENDIX B: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
APPENDIX C: PIN-OUT DETAILS
FIRMWARE REVISION NOTES
STATUS AND INTERRUPTS
THRESHOLD AND SATURATION CAPABILITY
PRINCIPLE OF OPERATION
- Threshold Detect
- Saturation Programming
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
- Threshold Detect Programming Registers
Saturation Programming Registers
- Status Registers
- Interrupt Registers
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

16-Channel Multiplexed A/D Modules

16-Channel 10V A/D Converters

ADE-ADF DATA SHEET
INTRODUCTION
- ADE-ADF Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
- A/D Measurement Registers
- A/D Control Registers
A/D Test Registers
Engineering Scaling Conversions Registers
Interrupt Registers
APPENDIX A: INTEGER/FLOATING POINT MODE PROGRAMMING
APPENDIX B: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
APPENDIX C: PIN-OUT DETAILS
Notes
A/D HARDWARE BLOCK DIAGRAM
FIRMWARE REVISION NOTES
STATUS AND INTERRUPTS
THRESHOLD AND SATURATION CAPABILITY
PRINCIPLE OF OPERATION
- Threshold Detect
- Saturation Programming
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
- Threshold Detect Programming Registers
Saturation Programming Registers
- Status Registers
- Interrupt Registers
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

ARINC 429/575 Communications Module

Dual ARINC Communication

Introduction
Features
Specifications
Principle of Operation – ARINC568
Principle of Operation – ARINC579
Principle of Operation – ARINC579
Register Descriptions
Status and Interrupt Registers
Status Registers
Interrupt Registers
N/A
Status Registers
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

CANBus Communication Function Modules

DATA SHEET
INTRODUCTION
- CB1-CB3 Overview
PRINCIPLE OF OPERATION
- Host Module Processing
- CAN Controller: Hardware with a Synchronous Clock
Transceiver
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
Receive Registers
- Receive FIFO Threshold Registers
Transmit Registers
Transmit FIFO Threshold Registers
Control Registers
Message Status/Monitor Registers
CANBus Filtering Registers
- Module Common Registers
- Status Registers
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Chip Detector Module

CD1 DATA SHEET
INTRODUCTION
FEATURES
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
Status Registers
Interrupt Registers
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP

MIL-STD-1553 and ARINC 429 Combination

Dual-redundant MIL-STD-1553 I/O

Introduction
MIL-STD-1553B Features
Discrete I/O Features
Discrete I/O
INPUT CHARACTERISTICS
Output Characteristics
General
MIL-STD-1553B
Principle of Operation - MIL-STD-1553B
Table 1 - Summary of MIL-STD-1553 Characteristics
Table 2 - Summary of MIL-STD-1553 Transmission Media Characteristics
Bus Controller
Remote Terminal
Bus Monitor
MIL-STD-1553 Protocol
Message Formats
Message Components
Command Word
Data Word
Status Word
External RT Address and Auto Start-up Modes
External RT Address
Start-up Modes
Assisted Mode (AM)
Register Descriptions – MIL-STD-1553B
AM Commands Registers
AM 1553 Message FIFO Registers
Auxiliary Registers
Status and Interrupt Registers
BIT Status
Discrete Input/Output Threshold Programming Registers
Discrete Input/Output Measurement Registers
VCC Bank Registers
6.2.5 Discrete Input/Output Control Registers
- Debounce Time
- Overcurrent Reset
Unit Conversion Programming Registers
- Enable Floating Point Mode
- Floating Point State
Background BIT Threshold Programming Registers
- Background BIT Threshold
- Reset BIT
User Watchdog Timer Programming Registers
Status and Interrupt Registers
Unit Conversions
User Watchdog Timer Capability
Enhanced Functionality
Register Descriptions – Discrete I/O
Discrete Input/Output Registers
Input/Output Format
Write Outputs
Write Outputs
Input/Output State
Input/Output State
Discrete Input/Output Threshold Programming Registers
Max High Threshold (Enable Floating Point Mode: Floating Point Mode)
Upper Threshold (Enable Floating Point Mode: Floating Point Mode)
Lower Threshold (Enable Floating Point Mode: Floating Point Mode)
Min Low Threshold (Enable Floating Point Mode: Floating Point Mode)
Max High Threshold
Data Range:
Upper Threshold
Data Range:
Lower Threshold
Min Low Threshold
Data Range:
Discrete Input/Output Measurement Registers
Voltage Reading
Data Range:
Voltage Reading (Enable Floating Point Mode: Floating Point Mode)
Current Reading
Data Range:
Current Reading (Enable Floating Point Mode: Floating Point Mode)
VCC Bank Registers
Select Pullup or Pulldown
Select Pullup or Pulldown
Current for Source/Sink
Data Range:
Current for Source/Sink (Enable Floating Point Mode: Integer Mode)
Current for Source/Sink (Enable Floating Point Mode: Floating Point Mode)
VCC Bank Reading
Data Range:
VCC Bank Reading (Enable Floating Point Mode: Integer Mode)
VCC Bank Reading (Enable Floating Point Mode: Floating Point Mode)
6.2.5 Discrete Input/Output Control Registers
Debounce Time
Overcurrent Reset
Overcurrent Reset
Unit Conversion Programming Registers
Enable Floating Point Mode
Enable Floating Point Mode
Floating Point State
Floating Point State
Background BIT Threshold Programming Registers
Background BIT Threshold
Reset BIT
Reset BIT
User Watchdog Timer Programming Registers
Status and Interrupt Registers
Channel Status Enabled
Channel Status Enabled
BIT Status
BIT Dynamic Status
BIT Latched Status
BIT Interrupt Enable
BIT Set Edge/Level Interrupt
Voltage Reading Error
Voltage Reading Error
Driver Error
Driver Error
Low-to-High Transition Status
Low-to-High Dynamic Status
Low-to-High Latched Status
Low-to-High Interrupt Enable
Low-to-High Set Edge/Level Interrupt
High-to-Low Transition Status
High-to-Low Dynamic Status
High-to-Low Latched Status
High-to-Low Interrupt Enable
High-to-Low Set Edge/Level Interrupt
Overcurrent Status
Overcurrent Dynamic Status
Overcurrent Latched Status
Overcurrent Interrupt Enable
Overcurrent Set Edge/Level Interrupt
Above Max High Threshold Status
Above Max High Threshold Dynamic Status
Above Max High Threshold Latched Status
Above Max High Threshold Interrupt Enable
Above Max High Threshold Set Edge/Level Interrupt
Below Min Low Threshold Status
Below Min Low Threshold Dynamic Status
Below Min Low Threshold Latched Status
Below Min Low Threshold Interrupt Enable
Below Min Low Threshold Set Edge/Level Interrupt
6.2.9.8 Mid-Range Status
Mid-Range Dynamic Status
Mid-Range Latched Status
Mid-Range Interrupt Enable
Mid-Range Set Edge/Level Interrupt
User Watchdog Timer Fault Status
Summary Status
Summary Status Dynamic Status
Summary Status Latched Status
Summary Status Interrupt Enable
Summary Status Set Edge/Level Interrupt
- Interrupt Vector and Steering
Enhanced Functionality Registers
Function Register Map – Discrete I/O
Discrete I/O
BIT Status
Discrete Input/Output Threshold Programming Registers
Discrete Input/Output Measurement Registers
VCC Bank Registers
Discrete Input/Output Control Registers
Unit Conversion Programming Registers
User Watchdog Timer Programming Registers
Background BIT Threshold Programming Registers
Status Registers
Enhanced Functionality Registers
Interrupt Registers
NAI Cares
FAQ
Application Notes
Calibration and Repairs
Call Us
Revision History
STATUS AND INTERRUPTS
Revision History
USER WATCHDOG TIMER MODULE MANUAL
NAI Cares
FAQ
Application Notes
Calibration and Repairs
Call Us
Revision History
Enhanced Input/Output Functionality Capability
Principle of Operation
Input Modes
Pulse Measurements
High Time Pulse Measurements
Time
Low Time Pulse Measurements
Transition Timestamps
Transition Timestamp of All Rising Edges
Transition Timestamp of All Falling Edges
Transition Timestamp of All Edges
Transition Counter
Rising Edges Transition Counter
Falling Edges Transition Counter
Period Measurement
Frequency Measurement
Output Modes
2.2.1 PWM Output
PWM Continuous
PWM Burst
Pattern Generator
Register Descriptions
Enhanced Functionality Registers
Input Modes Registers
- Reset Timer/Counter
FIFO Registers
Transition Count Registers
- Transition Count
Frequency Measurement Registers
- Frequency Measurement Period
Output Modes Registers
PWM Registers
Pattern Generator Registers
Pattern RAM
Pattern RAM Start Address
Pattern RAM Start Address
Pattern RAM End Address
Pattern RAM End Address
Pattern RAM Period
Pattern RAM Control
Pattern RAM Control
Pattern RAM Number of Cycles
Function Register Map
Enhanced I/O Functionality Registers
Input Modes Registers
FIFO Registers
Transition Count Registers
Frequency Measurement Registers
Output Mode Registers
PWM Registers
Pattern Generator Registers
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Combined Analog-Digital Function Module

CME, CMF
Analog-to-Digital & Digital-to-Analog Combination Function Module
CME-CMF Combination Modules Analog-to-Digital Function Modules Combination Module: 8-Ch. A/D (CME = ±10 V, CMF = ±100 V) and 8-Ch. D/A (±10.0 V @ 10 mA)
Specifications
Architected for Versatility
Board Support Package and Software Support
Background Built-In-Test (BIT)
One-Source Efficiencies
Product Lifecycle Management
INTRODUCTION
Analog-to-Digital (ADE/ADF Module-Type) Features
Digital-to-Analog (DA2 Module-Type) Features
Built-In Test (BIT)/Diagnostic Capability
Power-On Self-Test (POST)/Power-On BIT (PBIT)/Start-Up (SBIT)
Continuous Background Built-In Test
Initiated Built-In Test
A/D FIFO Buffering
Threshold and Saturation Programming
Status and Interrupts
Module Common Registers
Engineering Scaling Conversions
Register Descriptions
A/D Measurement Registers
- A/D Reading
A/D Control Registers
A/D Test Registers
- Test Enabled
- UBIT Test Data
FIFO Registers
Threshold Detect Programming Registers
Saturation Programming Registers
Engineering Scaling Conversions Registers
Background BIT Threshold Programming Registers
- Background BIT Threshold
- BIT Count Clear
Module Common Registers
Status and Interrupt Registers
Function Register Map
A/D Measurement Registers
A/D Control Registers
FIFO Registers
Threshold Detect Programming Registers
Saturation Programming Registers
Engineering Scaling Conversions Registers
Module Common Registers
A/D Status Registers
A/D Interrupt Registers
D/A Output Registers
- DAC Value
D/A Control Registers
D/A Measurement Registers
D/A Test Registers
FIFO Registers
Interrupt Registers
Appendix A: Integer/Floating Point Mode Programming
Integer Mode Programming
A/D Reading and FIFO Buffer Data
ADF Modules:
UBIT Test Programming
ADE Modules:
ADF Modules:
Threshold Programming
ADE Modules:
Saturation Programming
ADF Modules:
Floating Point Mode Voltage/Current Programming
A/D Reading and FIFO Buffer Data
ADE Modules:
ADF Modules:
UBIT Test Programming
ADE Modules:
= ADF Modules:
Threshold Programming
Saturation Programming
Floating Point Mode Engineering Units Programming
A/D Reading
Threshold Programming
Saturation Programming
DIGITAL-TO-ANALOG FUNCTION
Principle of Operation
Built-In Test (BIT)/Diagnostic Capability
Power-On Self-Test (POST)/Power-On BIT (PBIT)/Start-Up BIT (SBIT)
Continuous Background Built-In Test (CBIT)
Initiated Built-In Test (IBIT)
D/A FIFO Buffering
Status and Interrupts
Module Common Registers
Engineering Scaling Conversion
Register Description
D/A Control Registers
Voltage Range
Output Enable
Update Rate
Overcurrent Reset
D/A Measurement Registers
Wrap Voltage
Wrap Current
Internal Voltage
D/A Test Registers
FIFO Registers
Data Mode
FIFO Buffer Data
FIFO Word Count
FIFO Thresholds
FIFO Almost Empty
FIFO Low Watermark
FIFO High Watermark
FIFO Almost Full
Clear FIFO
Pattern Control
Software Trigger
Engineering Scaling Conversion Registers
Enable Floating Point Mode
Floating Point Offset
Floating Point Scale
Floating Point State
Background BIT Threshold Programming Registers
Background BIT Threshold
BIT Count Clear
Status and Interrupt Registers
Channel Status Enable
Overcurrent Status
External Power Under Voltage Status
Inter-FPGA Failure Status
FIFO Status
Interrupt Steering and Vector
Interrupt Vector
Interrupt Steering
Function Register Map
FIFO Thresholds
Module Common Registers
D/A Status Registers
BIT Registers
External Power Under Voltage
Inter-FPGA Failure
D/A Interrupt Registers
Threshold Detect Programming Registers
Status Registers
Saturation
Interrupt Registers
Integer Mode Programming
Floating Point Mode Voltage Programming
Floating Point Mode Engineering Units Programming
PIN-OUT DETAILS
STATUS AND INTERRUPTS
Analog-to-Digital
Threshold and Saturation Programming
THRESHOLD AND SATURATION CAPABILITY
PRINCIPLE OF OPERATION
Threshold Detect
Saturation Programming
REGISTER DESCRIPTIONS
Engineering Scaling Conversion Registers
Background BIT Threshold Programming Registers
- Background BIT Threshold
- BIT Count Clear
Status and Interrupt Registers
Threshold Detect Programming Registers
Saturation Programming Registers
FUNCTION REGISTER MAP
Threshold Detect Programming Registers
Status Registers
Saturation
Interrupt Registers
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
FUNCTION REGISTER MAP
Module Information Registers
Module Measurement Registers
Module Health Monitoring Registers
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

12-Channel Digital-to-Analog Converter

Introduction
Features
Specifications
Principle of Operation
Built-In Test (BIT)/Diagnostic Capability
Register Descriptions
Status and Interrupt Registers
Function Register Map
Status Registers
FIFO Dynamic Status, FIFO Latched Status, FIFO Interrupt Enable, FIFO Set Edge/Level Interrupt
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

16-Channel D/A Output Module

INTRODUCTION
PRINCIPLE OF OPERATION
Power-On Self-Test (POST)/Power-On BIT (PBIT)/Start-Up BIT (SBIT)
Continuous Background Built-In Test (CBIT)
Initiated Built-In Test (IBIT)
REGISTER DESCRIPTIONS
D/A Output Registers
- DAC Value
D/A Control Registers
D/A Measurement Registers
D/A Test Registers
- Test Enabled
FIFO Registers
Engineering Scaling Conversion Registers
Background BIT Threshold Programming Registers
- Background BIT Threshold
- Reset BIT
Watchdog Timer Registers
Module Common Registers
Status and Interrupt Registers
FUNCTION REGISTER MAP
D/A Output Registers
- DAC Value
D/A Control Registers
D/A Measurement Registers
D/A Test Registers
- Test Enabled
FIFO Registers
Engineering Scaling Conversion Registers
Background BIT Threshold Programming Registers
- Background BIT Threshold
- Reset BIT
Watchdog Timer Registers
Module Common Registers
Status and Interrupt Registers
APPENDIX A: INTEGER/FLOATING POING MODE PROGRAMMING
APPENDIX B: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
APPENDIX C: PIN-OUT DETAILS
FIRMWARE REVISION NOTES
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

4-Channel D/A Output Module

INTRODUCTION
DA3 Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
D/A Output Registers
- DAC Value
D/A Control Registers
D/A Measurement Registers
- Wrap Voltage
- Wrap Current
D/A Test Registers
- Test Enabled
FIFO/RAM Registers
- Data Mode
- Buffer Mode
FIFO Registers
- FIFO Buffer Data
- FIFO Word Count
FIFO Thresholds
Pattern Registers
Engineering Scaling Conversion Registers
Background BIT Threshold Registers
- Background BIT Threshold
- Reset BIT
Watchdog Timer Registers
Module Common Registers
Status and Interrupt Registers
FUNCTION REGISTER MAP
D/A Output Registers
D/A Control Registers
D/A Measurement Registers
FIFO/RAM Controls
FIFO Registers
FIFO Thresholds
Pattern Registers
Engineering Scaling Conversion Registers
Watchdog Timer Registers
Module Common Registers
Status Registers
D/A Test Registers
Background BIT Threshold Registers
Status Registers
Interrupt Registers
User Watchdog Timer Registers
Status Registers
Interrupt Register
Module Information Registers
Module Measurement Registers
Module Health Monitoring Registers
APPENDIX A: INTEGER/FLOATING POINT MODE PROGRAMMING
APPENDIX B: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
APPENDIX C: PIN-OUT DETAILS
FIRMWARE REVISION NOTES
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

High-Voltage D/A Module

INTRODUCTION
FEATURES
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
D/A Output Registers
- DAC Value
D/A Control Registers
D/A Measurement Registers
- Wrap Voltage
- Wrap Current
D/A Test Registers
- Test Enabled
FIFO/RAM Registers
- Data Mode
- Buffer Mode
FIFO Registers
- FIFO Buffer Data
- FIFO Word Count
FIFO Thresholds
Pattern Registers
Engineering Scaling Conversion Registers
Background BIT Threshold Registers
- Background BIT Threshold
- Reset BIT
Watchdog Timer Registers
Status and Interrupt Registers
FUNCTION REGISTER MAP
D/A Output Registers
D/A Control Registers
D/A Measurement Registers
FIFO/RAM Registers
FIFO Registers
FIFO Thresholds
Pattern Registers
Engineering Scaling Conversion Registers
Watchdog Timer Registers
Status Registers
D/A Test Registers
Background BIT Threshold Registers
Status Registers
Interrupt Registers
User Watchdog Timer Registers
Status Registers
Interrupt Register
APPENDIX A: INTEGER/FLOATING POINT MODE PROGRAMMING
- Floating Point Mode Voltage Programming
APPENDIX B: PIN-OUT DETAILS
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

High-Voltage Current D/A Module

DA5 DATA SHEET
INTRODUCTION
- DA5 Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
- D/A Output Registers
D/A Control Registers
APPENDIX A: INTEGER/FLOATING POINT MODE PROGRAMMING
Floating Point Mode Engineering Units Programming
APPENDIX B: PIN-OUT DETAILS
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Programmable Differential I/O Module

INTRODUCTION
FEATURES
SPECIFICATIONS
- Input Characteristics
- Output Characteristics
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Enhanced Differential I/O Module

Introduction
Specifications
- INPUT CHARACTERISTICS
- OUTPUT CHARACTERISTICS
Principle of Operation
- Automatic Background Built-In Test (BIT)/Diagnostic Capability
Register Descriptions
Status and Interrupt Registers
General Purpose Status Functions
- BIT Error Interrupt Interval
- BIT Count Error Clear
Enhanced Functionality
FIFO Operations/Functions
PWM Operations/Functions
Pattern Generator Operations/Functions
Enhanced Functionality
- Pattern RAM Control
- Output Polarity
Enhanced I/O Functionality Registers
- Mode Select
- 3.1.2 Enable Measurements/Outputs
3.1.3 Input Modes Registers
- 3.1.3.1 Reset Timer/Counter
3.1.3.2 FIFO Registers
3.1.3.3 Transition Count Registers
- 3.1.3.3.1 Transition Count
3.1.3.4 Frequency Measurement Registers
- 3.1.3.4.1 Frequency Measurement Period
3.1.4 Output Modes Registers
3.1.4.1 PWM Registers
3.1.4.2 Pattern Generator Registers
Function Register Map
Status Registers
Enhanced I/O Functionality Registers
Input Modes Registers
FIFO Registers
Transition Count Registers
Frequency Measurement Registers
PWM Registers
Pattern Generator Registers
User Watchdog Timer Registers
Interrupt Register s
Enhanced
1 Enhanced Input/Output Functionality Capability
2.1 Input Modes
2.1.1 Pulse Measurements
2.1.1.1 High Time Pulse Measurements
2.1.1.2 Low Time Pulse Measurements
2.1.2 Transition Timestamps
2.1.2.1 Transition Timestamp of All Rising Edges
2.1.2.2 Transition Timestamp of All Falling Edges
2.1.2.3 Transition Timestamp of All Edges
2.1.3 Transition Counter
2.1.3.1 Rising Edges Transition Counter
2.1.3.2 Falling Edges Transition Counter
2.1.3.3 All Edges Transition Counter
2.1.4 Period Measurement
2.1.5 Frequency Measurement
2.2 Output Modes
2.2.1 PWM Output
2.2.1.1 PWM Continuous
2.2.1.2 PWM Burst
2.2.2 Pattern Generator
Function Register Map
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Three-Channel LVDT Simulation

DLx DATA SHEET
INTRODUCTION
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

High-Density Synchro Simulator

DSx DATA SHEET
INTRODUCTION
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
Control Registers
Measurement Registers
Threshold Programming Registers
- Module Common Registers
- Status and Interrupt Registers
Test Registers
Status Registers
Interrupt Registers
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Programmable 24-Channel Discrete I/O

DT1 DATA SHEET
INTRODUCTION
- DT1 Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
- Discrete Input/Output Registers
Discrete Input/Output Measurement Registers
VCC Bank Registers
Discrete Input/Output Control Registers
Unit Conversion Programming Registers
User Watchdog Timer Programming Registers
Module Common Registers
Status Registers
Background BIT Threshold Programming Registers
Status Registers
Interrupt Registers
APPENDIX A: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
APPENDIX B: PIN-OUT DETAILS
DISCRETE INPUT/OUTPUT HARDWARE BLOCK DIAGRAM
DISCRETE INPUT/OUTPUT PROCESSING BLOCK DIAGRAM
FIRMWARE REVISION NOTES
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
Function Register Map
Bold Underline = Status
User Watchdog Timer Registers
Status Registers
Interrupt Register
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
FUNCTION REGISTER MAP
Module Information Registers
Module Measurement Registers
Module Health Monitoring Registers
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

16-Channel Programmable I/O

INTRODUCTION
- DT2 Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
Discrete Input/Switch Registers
Discrete Input/Output Threshold Programming Registers
Discrete Measurement Registers
Discrete Input/Output Control Registers
FUNCTION REGISTER MAP
Bold Underline = State/Measurement/Status
Discrete Input/Switch Registers
Discrete Input/Output Threshold Programming Registers
Discrete Input/Output Measurement Registers
Discrete Input/Output Control Registers
User Watchdog Timer Programming Registers
Module Common Registers
Status Registers
Interrupt Registers
User Watchdog Timer Registers
Status Registers
Interrupt Register
Module Information Registers
Module Health Monitoring Registers
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
Function Register Map
Bold Underline = Status
User Watchdog Timer Registers
Status Registers
Interrupt Register
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
FUNCTION REGISTER MAP
Bold Italic = Configuration/Control
Module Information Registers
Module Health Monitoring Registers
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

High-Current Discrete Output

24-Channel Programmable Discrete Module

*DT4* I/O Modules Discrete IO - Multichannel, Programmable Function Modules Enhanced 24 Discrete I/O Channels (0 to 60 VDC, 500 mA/Ch.)
Specifications
Architected for Versatility
Board Support Package and Software Support
Background Built-In-Test (BIT)
One-Source Efficiencies
Product Lifecycle Management
INTRODUCTION
DT4 Overview
Current Sharing:
Inrush Current Handling:
Dual Turn-On Application Support:
Debounce Circuitry:
Background Built-In-Test (BIT):
Input Diagnostics:
Voltage and Current Readings:
Enhanced Functionality Features:
PRINCIPLE OF OPERATION
Operational requirements/assumptions:
Input/Output Interface
Output
Input
Discrete I/O Threshold Programming
Automatic Background Built-In Test (BIT)/Diagnostic Capability
Status and Interrupts
Module Common Registers
Unit Conversions
User Watchdog Timer Capability
Enhanced Functionality
REGISTER DESCRIPTIONS
Discrete Input/Output Registers
Discrete Input/Output Voltage Threshold Programming Registers
Discrete Input/Output Measurement Registers
- Voltage Reading
- Current Reading
VCC Bank Registers
Discrete Input/Output Control Registers
- Debounce Time
- Overcurrent Reset
Unit Conversion Programming Registers
- Enable Floating Point Mode
- Floating Point State
Background BIT Threshold Programming Registers
- Background BIT Threshold
- BIT Count Clear
User Watchdog Timer Programming Registers
Module Common Registers
Status and Interrupt Registers
FUNCTION REGISTER MAP
Discrete Input/Output Registers
Discrete Input/Output Voltage Threshold Programming Registers
Discrete Input/Output Measurement Registers
VCC Bank Registers
Discrete Input/Output Control Registers
Unit Conversion Programming Registers
User Watchdog Timer Programming Registers
Module Common Registers
Status Registers
Background BIT Threshold Programming Registers
Status Registers
Enhanced Functionality Registers
Interrupt Registers
Status Registers
Interrupt Register
APPENDIX A: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
Discrete Input/Output Registers
Discrete I/O Threshold Programming Registers
Discrete I/O Input/Output Measurement Registers
VCC Bank Registers
Discrete Input/Output Control Registers
Unit Conversion Registers
Background BIT Threshold Programming Registers
User Watchdog Timer Programming Registers
Status and Interrupt Registers
Status and Interrupt Registers
APPENDIX B: PIN-OUT DETAILS
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
Function Register Map
Status Registers
Interrupt Register
PRINCIPLE OF OPERATION
Input Modes
Pulse Measurements
High Time Pulse Measurements
Low Time Pulse Measurements
Transition Timestamps
Transition Timestamp of All Rising Edges
Transition Timestamp of All Edges
Transition Counter
Rising Edges Transition Counter
Falling Edges Transition Counter
All Edges Transition Counter
Period Measurement
Frequency Measurement
Output Modes
PWM Output
PWM Continuous
PWM Burst
Pattern Generator
REGISTER DESCRIPTIONS
Enhanced I/O Functionality Registers
Input Modes Registers
FIFO Registers
Transition Count Registers
Frequency Measurement Registers
PWM Registers
Pattern Generator Registers
FUNCTION REGISTER MAP
Module Information Registers
Module Measurement Registers
Module Health Monitoring Registers
Module Manual - DT4 Revision History
Module Manual - Status and Interrupts Revision History
Module Manual - User Watchdog Timer Revision History
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Documentation
FAQ
Application Notes
Calibration and Repairs
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32-Channel Discrete I/O

Introduction
Features
INPUT CHARACTERISTICS
BIDIRECTIONAL SWITCH
Principle of Operation
Input/Switch Interface
Open Circuit Detection
Register Descriptions
Threshold Programming
Status and Interrupt Registers
Enhanced Functionality
FIFO Operations/Functions
PWM Operations/Functions
Pattern Generator Operations/Functions
Function Register Map
NAI Cares
FAQ
Application Notes
Calibration and Repairs
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Revision History
1 Enhanced Input/Output Functionality Capability
2 Principle of Operation
2.1 Input Modes
2.1.1 Pulse Measurements
2.1.1.1 High Time Pulse Measurements
2.1.1.2 Low Time Pulse Measurements
2.1.2 Transition Timestamps
2.1.2.1 Transition Timestamp of All Rising Edges
2.1.2.2 Transition Timestamp of All Falling Edges
2.1.2.3 Transition Timestamp of All Edges
2.1.3 Transition Counter
2.1.3.1 Rising Edges Transition Counter
2.1.3.2 Falling Edges Transition Counter
2.1.3.3 All Edges Transition Counter
2.1.4 Period Measurement
2.1.5 Frequency Measurement
2.2 Output Modes
2.2.1 PWM Output
2.2.1.1 PWM Continuous
2.2.1.2 PWM Burst
2.2.2 Pattern Generator
3 Register Descriptions
3.1 Enhanced I/O Functionality Registers
3.1.1 Mode Select
- 3.1.2 Enable Measurements/Outputs
3.1.3 Input Modes Registers
- 3.1.3.1 Reset Timer/Counter
3.1.3.2 FIFO Registers
3.1.3.3 Transition Count Registers
- 3.1.3.3.1 Transition Count
3.1.3.4 Frequency Measurement Registers
- 3.1.3.4.1 Frequency Measurement Period
3.1.4 Output Modes Registers
3.1.4.1 PWM Registers
3.1.4.2 Pattern Generator Registers
4 Function Register Map
Enhanced I/O Functionality Registers
4.1.1 Input Modes Registers
4.1.1.1 FIFO Registers
4.1.1.2 Transition Count Registers
4.1.1.3 Frequency Measurement Registers
4.1.2 Output Mode Registers
4.1.2.1 PWM Registers
4.1.2.2 Pattern Generator Registers
NAI Cares
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Application Notes
Calibration and Repairs
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Revision History
STATUS AND INTERRUPTS
Revision History
USER WATCHDOG TIMER MODULE MANUAL
1.3.3 Function Register Map
1.3.3.1 User Watchdog Timer Registers
1.3.3.2 Status Registers
1.3.3.3 Interrupt Register
Revision History
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FAQ
Application Notes
Calibration and Repairs
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Dual-Port Gigabit Ethernet Network Interface Card

INTRODUCTION
EM1 Overview
APPENDIX: PINOUT DETAILS
Module Manual - EM1 Revision Histor
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Managed Ethernet Switch

ES2 DATA SHEET
ES2 SWITCH CONFIGURATIONS & UTILITIES
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Assisted Mode 1553 Module

DATA SHEET
INTRODUCTION
- FTA-FTF Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
APPENDIX A: 1553 RECEIVE MESSAGE FIFO FORMAT
APPENDIX B: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
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Documentation
FAQ
Application Notes
Calibration and Repairs
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Dual-Channel MIL-STD-1760 Interface

DATA SHEET
INTRODUCTION
- FTJ-FTK Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
Reset Registers
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Versatile LVDT/RVDT Transformer

LDx Measurement & Simulation Modules LVDT RVDT Measurement and
Features
Specifications
Architected for Versatility
Board Support Package and Software Support
Background Built-In-Test (BIT)
One-Source Efficiencies
Product Lifecycle Management
INTRODUCTION
FEATURES
PRINCIPLE OF OPERATION
2-Wire System
Operational Note:
3-Wire or 4-Wire System
Position Measurement
Velocity Measurement
Bandwidth Setting
Signal/Reference Measurements
Built-In Test (BIT)/Diagnostic Capability
Power-On Self-Test (POST)/Power-on BIT (PBIT)/Start-up BIT (SBIT)
Continuous Background Built-In Test
Initiate Built-In Test
LVDT/RVDT Threshold Programming
LVDT/RVDT FIFO Buffering
Status and Interrupts
Engineering Scaling Conversions
REGISTER DESCRIPTIONS
LVDT/RVDT Measurement Registers
3- or 4-Wire Specific Register
- Measured Signal (RMS)
- Va+Vb RMS
LVDT/RVDT Control Registers
Threshold Programming Registers
3-Wire/4-Wire Signal Fault Register
- Signal Fault Low Threshold
- Signal Fault High Threshold
2-Wire Signal Fault Register
- Va Fault High Threshold
- Vb Fault High Threshold
LVDT/RVDT Test Registers
Floating Point Mode:
- BIT Error Limit
FIFO Registers
- FIFO Buffer Data
- FIFO Word Count
FIFO Thresholds
Engineering Scaling Conversion Registers
Status and Interrupt Registers
- Channel Status Enable
- BIT Status
3-Wire/4-Wire Fault Status
- Signal Fault Low Status
- Signal Fault High Status
2-Wire Fault Status
FUNCTION REGISTER MAP
Bold Underline = Measurement/Status
LVDT/RVDT Measurement Registers
LVDT/RVDT Control Registers
Threshold Programming Registers
3-Wire/4-Wire Signal Fault Register
2-Wire Signal Fault Register
FIFO Registers
FIFO Thresholds
Engineering Scaling Conversion Registers
Status Registers
LVDT/RVDT Test Registers
Floating Point Mode
3-Wire/4-Wire Signal Fault Status
2-Wire Fault Status
Interrupt Registers
APPENDIX A: INTEGER/FLOATING POINT MODE PROGRAMMING
Integer Mode Programming
Position, Velocity, and FIFO Buffering Data Programming
Position Data Calculation:
Velocity: The value read in the Velocity or FIFO Buffer Data (velocity data) register, while in Integer Mode, has an LSB weight of 0.1%
Velocity Data Calculation:
FIFO Buffer Data:
Timestamp value from FIFO Data Buffer:
UBIT Testing Programming
Test Position:
Threshold and Delta Position Programming
Delta Position:
Open and Short Detect Thresholds:
RMS Voltage Reading
Frequency Reading
LVDT/RVDT Scale Programming
Floating Point Mode Position/Velocity Programming
Test Position:
Threshold and Delta Position Programming
Delta Position:
Open and Short Detect Thresholds:
RMS Voltage Reading
Frequency Reading
Floating Point Mode Engineering Units Programming
APPENDIX B: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
APPENDIX C: PIN-OUT DETAILS
STATUS AND INTERRUPTS
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Rugged Dual-Function I/O Ethernet Subsystem

Introduction
NIU2A Rugged COTS Systems
Features
Select up to 2 independent functions for your application
I/O Modules
Measurement & Simulation Modules
Communication Modules
Storage
Combination Modules
Architected for Versatility
Board Support Package and Software Support
Background Built-In-Test (BIT)
One-Source Efficiencies
Product Lifecycle Management
INTRODUCTION
SOFTWARE SUPPORT
CONVENTIONS USED IN THIS MANUAL
GENERAL SAFETY NOTICES
Repair
High Voltage
Input Power Always On
SYSTEM SPECIFICATIONS & DETAILS
Introduction
Objectives
Scope
SPECIFICATIONS
General
Environmental
Ingress Protection IEC 60529
EMC/EMI
Notes:
MTBF
UNPACKING & INSPECTION
Unpacking
System/Chassis Identification
Inspection
MECHANICAL INTERFACE
Mechanical Description
Mounting Requirements
Chassis (Earth) GND
Note
CONNECTOR DESIGNATION & DESCRIPTION
Connector Details and Pinout
J1, Primary Power Connector
Parts Identification
Pinout
J2, I/O, Module 1
Parts Identification
Pinout
J3, Ethernet Communications & Debug
Parts Identification
1. SYSRSTn : An active “low” or GND logic level (as referenced to System GND of the NIU2A) assertion of the SYSRST# signal (internally pulled ‘high') on the NIU2A
J4, I/O, Module 2
Parts Identification
Pinout
Notes
J5, Fiber Optic, Option
Parts Identification
Pinout
POWER-UP & OPERATIONAL DESCRIPTION
Panel LEDs & Functions
Basic Operations
Additional operational windows will be dependent on the function modules installed. The ESP program, once communication has been
REGISTER MEMORY MAP ADDRESSING
Board Base Address
Module Slot and Function Address
Address Calculation
Motherboard Registers:
Module Registers:
REGISTER DESCRIPTIONS
Module Information Registers
Module Slot Address
Module Slot Size
Module Slot ID
Hardware Information Registers
Product Serial Number
Platform
Model
Generation
Processor Count/Ethernet Interface Count
Ethernet Interface Count - Indicates the number of Ethernet interfaces on the product motherboard. For example, Single Ethernet = 1; Dual
Maximum Module Slot Count/ARM Platform Type
Motherboard Firmware Information Registers
Motherboard Core Firmware Version
Motherboard Firmware Build Date/Time
Motherboard Monitoring Registers
Zynq Core Voltage
Zynq Aux Voltage
Zynq DDR Voltage
Temperature Readings Register
Temperature Readings
Higher Precision Temperature Readings Registers
Higher Precision Motherboard PCB Temperature
Ethernet Configuration Registers
Ethernet MAC Address and Ethernet Settings
Ethernet Interface Name
Ethernet IPv4 Address
Ethernet IPv6 Address
- Interrupt Vector and Steering
Motherboard Health Monitoring Registers
Motherboard Sensor Registers
Sensor Current Reading
Sensor Minimum Reading
Sensor Maximum Reading
Sensor Lower Warning Threshold
Sensor Lower Critical Threshold
Sensor Upper Warning Threshold
Sensor Upper Critical Threshold
Module Control Command Requests
Modules Health Monitoring Registers
Module Communication Status
Module Powered-down:
Module Not Detected:
Module LinkInit Not Done:
Module Firmware Not Ready:
Module Communications Error Detected:
Module BIT Status
Scratchpad Area
MOTHERBOARD FUNCTION REGISTER MAP
Bold Italic = Configuration/Control
Module Information Registers
Hardware Information Registers
Motherboard Firmware Information Registers
Motherboard Measurements Registers
Temperature Readings
Higher Precision Temperature Readings
Ethernet Configuration Registers
Interrupt Vector and Steering
Motherboard Health Monitoring Registers
Module Control Command Requests
Modules Health Monitoring Registers
Module Communication Status
Module BIT Status
Scratchpad Registers
ETHERNET
Ethernet Interface to Generation 5 SBC and Embedded IO Boards Specification
While the listener is active, note that interrupts from the motherboard do not trigger. The listener can be disabled by turning off the
Ethernet Message Framework
Message Elements
Notes
Board Addressing
Onboard addressing refers to accessing resources located on the board that is implementing the operation interface (including its modules).
Off-board addressing refers to accessing resources located on another board reachable via VME, PCI, or other bus. Off-board addressing
Motherboard Common Address Space starts at 0x00000000 and ends at 0x00004000. This is a 4Kx32-bit address space (16 kbytes).
Module Address Space starts at 0x00004000. Module addressing is dynamically configured at startup. NAI boards support between 1 and 6
Ethernet Wiring Convention
NIU2A I/O MAPPING
PART NUMBER DESIGNATION
SYN/RSL & LVDT/RVDT SIMULATION MODULE CODE TABLES
SYNCHRO/RESOLVER & LVDT/RVT MEASUREMENT MODULE CODE TABLES
SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL
LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)
Revision History
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Documentation
FAQ
Application Notes
Calibration and Repairs
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Rugged Xilinx Zynq System Board

Introduction
NIU3A Rugged COTS Systems
Select up to 3 independent functions for your application
Architected for Versatility
Board Support Package and Software Support
Background Built-In-Test (BIT)
One-Source Efficiencies
Product Lifecycle Management
NIU3A DATA SHEET
INTRODUCTION
SOFTWARE SUPPORT
CONVENTIONS USED IN THIS MANUAL
GENERAL SAFETY NOTICES
SYSTEM SPECIFICATIONS & DETAILS
- Introduction
ON BOARD RESOURCES
SPECIFICATIONS
UNPACKING & INSPECTION
MECHANICAL INTERFACE
- Mechanical Description
- Chassis (Earth) GND
CONNECTOR DESIGNATION & DESCRIPTION
- Connector Details and Pinout
POWER-UP & OPERATIONAL DESCRIPTION
- Panel LEDs & Functions
- Basic Operations
REGISTER MEMORY MAP ADDRESSING
REGISTER DESCRIPTIONS
MOTHERBOARD FUNCTION REGISTER MAP
Motherboard Health Monitoring Registers
- Modules Health Monitoring Registers
- Scratchpad Registers
ETHERNET
NIU3A I/O MAPPING
NIU3A PART NUMBER DESIGNATION
SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES
SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES
- SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL)
- LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)
APPENDIX A: ONBOARD MODULE FUNCTION
APPENDIX B: ONBOARD MODULE STATUS AND INTERRUPTS
APPENDIX C: ONBOARD DISCRETE I/O USER WATCHDOG TIMER FUNCTIONALITY
APPENDIX D: ONBOARD DISCRETE I/O ENHANCED INPUT/OUTPUT FUNCTIONALITY
Hardware Manual - NIU3E Revision History
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FAQ
Application Notes
Calibration and Repairs
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Rugged Ethernet Switch System Board

Pulse Timer Receiver Generator

DATA SHEET
INTRODUCTION
- PT1 Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
APPENDIX: PINOUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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IRIG Timecode Receiver Generator

RG1 DATA SHEET
INTRODUCTION
FEATURES
PRINCIPLE OF OPERATION
Built-In Test (BIT)/Diagnostic Capability
Status and Interrupts
Module Common Registers
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
Real Time Clock (RTC) Registers
- Status Registers
- Interrupt Registers
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

8-Channel RTD Measurement

RT1 Measurement & Simulation Modules Thermocouple and RTD Measurement
Features
Specifications
Architected for Versatility
Board Support Package and Software Support
Background Built-In-Test (BIT)
One-Source Efficiencies
Product Lifecycle Management
INTRODUCTION
- RT1 Overview
PRINCIPLE OF OPERATION
- Built-In-Test (BIT)/Diagnostic Capability
Temperature Threshold Detect Programming
- Status and Interrupts
- Module Common Registers
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Latching and Non-Latching Relays

DATA SHEET
INTRODUCTION
- RY1/RY2 Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Serial Module

Introduction
Features
Specifications
Module SC1/SC7 - Serial Communications with Programmable Interface Levels
Module SC2 – Isolated Serial Communications with Programmable Interface Levels
Register Descriptions
Status and Interrupt Registers
Function Register Map
Status
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Programmable Serial and GPIO Module

SC3 DATA SHEET
INTRODUCTION
- SC3 Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
APPENDIX A: REGISTER NAME CHANGE
APPENDIX B: PIN-OUT DETAILS
SC3 HARDWARE BLOCK DIAGRAM
SC3 PROCESSING BLOCK DIAGRAM
FIRMWARE REVISION NOTES
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Isolated Serial Communication Channels

SC5 DATA SHEET
INTRODUCTION
FEATURES
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
Status Registers
- Interrupt Registers
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Programmable Serial Communication Channels

SC6 DATA SHEET
INTRODUCTION
FEATURES
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Synchro Resolver Measurement Modules

SD1-SD5 DATA SHEET
INTRODUCTION
SD1-SD5 Overview
PRINCIPLE OF OPERATION
Multi-Speed Operation
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
- SD/RD Measurement Registers
- SD/RD Control Registers
Threshold Programming Registers
FIFO Registers
FIFO Thresholds
Engineering Scaling Conversion Registers
APPENDIX A: INTEGER/FLOATING POINT MODE PROGRAMMING
- Integer Mode Programming
- Floating Point Mode Angle/Velocity Programming
APPENDIX B: REGISTER NAME CHANGES FROM PREVIOUS REVISIONS
APPENDIX C: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Module Manual - SD1-SD5 Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Strain Gauge Measurement Module

DATA SHEET
INTRODUCTION
FEATURES
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTIONAL REGISTER MAP
BIT Registers
Status Registers
High Strain Alert 1
High Strain Alert 2
Low Strain Alert 1
Low Strain Alert 2
Error Summary
- Interrupt Registers
APPENDIX: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Rugged VPX Sensor Interface Unit

SIU34 DATA SHEET
INTRODUCTION
OBJECTIVES
SCOPE
CONVENTIONS USED IN THIS MANUAL
GENERAL SAFETY NOTICES
SYSTEM SPECIFICATIONS AND DETAILS
Introduction
General
UNPACKING AND INSPECTION
MECHANICAL INTERFACE
- Mechanical Description
- Finish
CONNECTOR DESIGNATIONS, LOCATIONS & DESCRIPTIONS
CONNECTOR DETAILS AND PINOUTS
- J5, Primary Power Connector
- I/O Connectors (J1 to J4) and SLOT Designations
POWER-UP AND BASIC OPERATIONS
QUALIFICATION
- EMI/EMC Specifications
HEAT DISSIPATION
RELIABILITY
- MTBF
SIGNAL PIN-OUTS
- Pin-Out / General / I/O Connector (Slot 2-4)
- General System Functions
PART NUMBER DESIGNATION
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Compact Rugged Mission Control System

SIU36 DATA SHEET
INTRODUCTION
OBJECTIVES
SCOPE
CONVENTIONS USED IN THIS MANUAL
GENERAL SAFETY NOTICES
SYSTEM SPECIFICATIONS AND DETAILS
- Introduction
- Specifications
General
UNPACKING AND INSPECTION
- Unpacking
- System/Chassis Identification
Label information provided:
- Inspection
MECHANICAL INTERFACE
- Mechanical Description
- Finish
CONNECTOR DESIGNATIONS, LOCATIONS & DESCRIPTIONS
CONNECTOR DETAILS AND PINOUTS
- J7, Primary Power Connector
CONNECTOR DETAILS AND PINOUTS
- I/O Connectors (J1 to J6) and SLOT Designations
POWER-UP AND BASIC OPERATIONS
QUALIFICATION
- EMI/EMC Specifications
HEAT DISSIPATION
RELIABILITY
- MTBF
SIGNAL PIN-OUTS
- Pin-Out / General / I/O Connector (Slot 1)
Pin-Out / General / I/O Connector (Slot 2-6)
- General System Functions
PART NUMBER DESIGNATION
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Versatile Thermocouple Measurement Module

TC1 DATA SHEET
INTRODUCTION
- TC1 Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
APPENDIX A: OPTIONAL EXTERNAL COLD JUNCTION COMPENSATION (CJC) BLOCK ACCESSORY
APPENDIX B: THERMOCOUPLE TYPE TEMPERATURE TOLERANCES
APPENDIX C: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Tri-Redundant Ethernet Interface

INTRODUCTION
FEATURES
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
APPENDIX A: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
APPENDIX B: PIN-OUT DETAILS
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

24-Channel TTL/CMOS I/O

TL1 and Variants
Function Module
Introduction
Features
Specifications
TTL INPUT
TTL OUTPUT
Principle of Operation
Automatic Background Built-In Test (BIT)/Diagnostic Capability
Register Descriptions
Status and Interrupt Registers
General Purpose Status Functions
- BIT Error Interrupt Interval
- BIT Count Error Clear
Function Register Map
Status Registers
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
1.3.3 Function Register Map
1.3.3.1 User Watchdog Timer Registers
1.3.3.2 Status Registers
1.3.3.3 Interrupt Register
NAI Cares
FAQ
Application Notes
Calibration and Repairs
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Enhanced TTL/CMOS I/O Module

TL2 and Variants
Function Module
Introduction
Features
Specifications
Principle of Operation
Automatic Background Built-In Test (BIT)/Diagnostic Capability
Register Descriptions
Status and Interrupt Registers
General Purpose Status Functions
- BIT Error Interrupt Interval
- BIT Count Error Clear
Enhanced Functionality
FIFO Operations/Functions
Function Register Map
BIT
Transition
Enhanced I/O Functionality Registers
- Mode Select
- Enable Measurements/Outputs
Input Modes Registers
- Reset Timer/Counter
FIFO Registers
Transition Count Registers
- Transition Count
Frequency Measurement Registers
- Frequency Measurement Period
Output Modes Registers
PWM Registers
Pattern Generator Registers
Status Registers
NAI Cares
FAQ
Application Notes
Calibration and Repairs
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Enhanced
Discrete I/O, Digital I/O Functionality
1 Enhanced Input/Output Functionality Capability
- 2 Principle of Operation
2.1 Input Modes
2.1.1 Pulse Measurements
2.1.1.1 High Time Pulse Measurements
2.1.1.2 Low Time Pulse Measurements
2.1.2 Transition Timestamps
2.1.2.1 Transition Timestamp of All Rising Edges
2.1.2.2 Transition Timestamp of All Falling Edges
2.1.2.3 Transition Timestamp of All Edges
2.1.3 Transition Counter
2.1.3.1 Rising Edges Transition Counter
2.1.3.2 Falling Edges Transition Counter
2.1.3.3 All Edges Transition Counter
2.1.4 Period Measurement
2.1.5 Frequency Measurement
2.2 Output Modes
2.2.1 PWM Output
2.2.1.1 PWM Continuous
2.2.1.2 PWM Burst
2.2.2 Pattern Generator
3 Register Descriptions
3.1 Enhanced I/O Functionality Registers
3.1.1 Mode Select
3.1.2 Enable Measurements/Outputs
3.1.3 Input Modes Registers
3.1.3.1 Reset Timer/Counter
3.1.3.2 FIFO Registers
3.1.3.2.1 FIFO Buffer Data
3.1.3.2.2 FIFO Word Count
3.1.3.2.3 Clear FIFO
3.1.3.2.4 FIFO Status
3.1.3.3 Transition Count Registers
3.1.3.3.1 Transition Count
3.1.3.4 Frequency Measurement Registers
3.1.3.4.1 Frequency Measurement Period
3.1.4 Output Modes Registers
3.1.4.1 PWM Registers
3.1.4.1.1 PWM Period
3.1.4.1.2 PWM Pulse Width
3.1.4.1.3 PWM Output Polarity
3.1.4.1.4 PWM Number of Cycles
3.1.4.2 Pattern Generator Registers
3.1.4.2.1 Pattern RAM
3.1.4.2.2 Pattern RAM Start Address
3.1.4.2.3 Pattern RAM End Address
3.1.4.2.4 Pattern RAM Period
3.1.4.2.5 Pattern RAM Control
3.1.4.2.6 Pattern RAM Number of Cycles
4 Function Register Map
4.1 Enhanced I/O Functionality Registers
4.1.1 Input Modes Registers
4.1.1.1 FIFO Registers
4.1.1.3 Frequency Measurement Registers
4.1.2 Output Mode Registers
4.1.2.1 PWM Registers
4.1.2.2 Pattern Generator Registers
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
1.3.3 Function Register Map
1.3.3.1 User Watchdog Timer Registers
1.3.3.2 Status Registers
1.3.3.3 Interrupt Register
NAI Cares
FAQ
Application Notes
Calibration and Repairs
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Thermocouple/RTD Module

Thermocouple/RTD Function Module
TR1 Measurement & Simulation Modules Thermocouple and RTD Measurement
Features
Thermocouple Measurement
RTD Measurement
Independently Programmable
Independent Mode Select
Programmable Sample Rate
Offset Temperature
Specifications
Thermocouple
Architected for Versatility
Board Support Package and Software Support
Background Built-In-Test (BIT)
One-Source Efficiencies
Product Lifecycle Management
INTRODUCTION
TR1 Overview
Thermocouple Features
RTD Features
General Features
PRINCIPLE OF OPERATION
Thermocouple Capability
RTD Capability
Low Voltage A/D Measurement Capability
Automatic Background Built-In Test (BIT)/Diagnostic Capability
Temperature Threshold Detect Programming
Status and Interrupts
Module Common Registers
REGISTER DESCRIPTIONS
TR1 Measurement Registers
- Temperature (°C)
- Temperature (°F)
Thermocouple - Specific Measurement Registers
- Voltage
RTD - Specific Measurement Registers
- Resistance
TR1 Control Registers
Thermocouple - Specific Control
Suspend Background Maintenance Operations Register
RTD - Specific Control
Temperature Threshold Detect Programming
Temperature Threshold Detect 1
- Temperature Threshold Low 1
- Temperature Threshold High 1
Temperature Threshold Detect 2
FUNCTION REGISTER MAP
TR1 Measurement Registers
Thermocouple-Specific Measurement Registers
RTD-Specific Measurement Registers
TR1 Control Registers
Thermocouple-Specific Control Registers
Thermocouple-Specific Suspend Maintenance Operations Registers
RTD-Specific Control Registers
Temperature Threshold Detect Programming Registers
Module Common Registers
Status Registers
Interrupt Registers
APPENDIX A: OPTIONAL EXTERNAL COLD JUNCTION COMPENSATION (CJC) BLOCK ACCESSORY
APPENDIX B: THERMOCOUPLE TYPE TEMPERATURE TOLERANCES
APPENDIX C: PIN-OUT DETAILS
FIRMWARE REVISION NOTES
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
FUNCTION REGISTER MAP
Module Information Registers
Module Measurement Registers
Module Health Monitoring Registers
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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8-Channel VR Pulse Counter

VR1 DATA SHEET
INTRODUCTION
- VR1 Overview
PRINCIPLE OF OPERATION
REGISTER DESCRIPTIONS
FUNCTION REGISTER MAP
Interrupt Registers
APPENDIX A: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
APPENDIX B: INTEGER/FLOATING POINT MODE PROGRAMMING
- Integer/Floating Point Mode Supported Registers
APPENDIX C: HARDWARE BLOCK DIAGRAM
APPENDIX D: GETTING STARTED
APPENDIX E: PIN-OUT DETAILS
STATUS AND INTERRUPTS
MODULE COMMON REGISTERS
FUNCTION REGISTER MAP
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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3U OpenVPX Intel SBC

DATA SHEET
INTRODUCTION
- 68INT6 Overview
SPECIFICATIONS
- General for the Motherboard
- Environmental
SOFTWARE
Built-In Test
BIOS
Operating System Support
- Software Support
INITIAL SETUP
68INT6 ON BOARD RESOURCES
- Memory
- Peripheral I/O
- I2C
- Onboard TTL
TTL Output
- PRC Register Descriptions
- Tamper Detect Interface and Action Circuit
68INT6 SOFTWARE LIBRARIES/ASSOCIATED DOCUMENTS
- 68INT6 BSP Processor Module Library
68INT6 CONNECTOR/PIN-OUT INFORMATION
MECHANICAL
- General Outline
68INT6 PART NUMBER DESIGNATION
APPENDIX: NAI-XMC CONFIGURATION OPTION
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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SOSA-Aligned Intel Xeon SBC

DATA SHEET
- INTRODUCTION
- 68INT6H Overview
SPECIFICATIONS
- General for the Motherboard
- Environmental
SOFTWARE
INITIAL SETUP
68INT6H ON BOARD RESOURCES
68INT6H SOFTWARE LIBRARIES/ASSOCIATED DOCUMENTS
- 68INT6H BSP Processor Module Library
68INT6H CONNECTOR/PIN-OUT INFORMATION
- Rear Panel Connectors
Panel LEDs
- Chassis Ground
- Rear I/O VPX Connectors P0-P2 (Conduction-Cooled)
XMC/Built-In I/O - Defined Area (P2)
68INT6H Standard VITA 61/VITA 42 XMC Site PCIe Pinouts
Rear User I/O Mapping (NAI-XMC Configuration Option Only)
MECHANICAL
- General Outline
68INT6H PART NUMBER DESIGNATION
APPENDIX: NAI-XMC CONFIGURATION OPTION
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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Phase Angle Voltmeter

VME ARM Cortex-A9 SBC

64ARM1 DATA SHEET
INTRODUCTION
- 64ARM1 Overview
SOFTWARE SUPPORT
SPECIFICATIONS
- General for the Motherboard
- Environmental
REGISTER MEMORY MAP ADDRESSING
REGISTER DESCRIPTIONS
MOTHERBOARD REGISTER FUNCTION MAP
ADDRESS CONFIGURATION
ETHERNET
CONNECTOR/PIN-OUT INFORMATION
MECHANICAL DETAILS
- General - Outline
64ARM1 PART NUMBER DESIGNATION
SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES
SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES
- SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL)
- LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)
APPENDIX: EMBEDDED ARM (XILINX® XC7Z015 SOC) OPTION DETAILS
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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6U OpenVPX Multifunction I/O

Data Sheet
INTRODUCtION
- *67G6 Overview*
SOFTWARE SUPPORT
SPECIFICATIONS
- General for the Motherboard
- Environmental
REGISTER MEMORY MAP ADDRESSING
REGISTER DESCRIPTIONS
MOTHERBOARD FUNCTION REGISTER MAP
ETHERNET
67G6 CONNECTOR/PIN-OUT INFORMATION
J1-J6 Front Panel Connector Pinout Mapping Summary (Convection-Cooled)
- Front and Rear User I/O Mapping
- Connector Signal/Pinout Notes
Additional Pinout Notes
MECHANICAL DETAILS
- PART NUMBER DESIGNATION
SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES
SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES
Onboard Discrete Input/Output Option Function Register Map
User Watchdog Timer Programming Registers
STATUS AND INTERRUPTS
USER WATCHDOG TIMER MODULE MANUAL
Appendix C: Enhanced Input/Output Functionality
Enhanced Input/Output Functional Register Map
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Rugged Mil-Aero SBC

67PPC2 DATA SHEET
INTRODUCTION
- 67PPC2 Overview
SOFTWARE SUPPORT
SPECIFICATIONS
- General for the Motherboard
- Environmental
67PPC2 OVERVIEW
67PPC2 ENVIRONMENTAL/POWER SPECIFICATIONS
- Conduction-Cooled/Rugged
- Power Requirements
67PPC2 OUTLINE DIMENSIONS
67PPC2 ON BOARD RESOURCES
REGISTER DESCRIPTIONS
67PPC2 SOFTWARE LIBRARIES/ASSOCIATED DOCUMENTS
- 67PPC2 BSP processor Module Library
- Associated Documents
REGISTER MEMORY MAP ADDRESSING
MOTHERBOARD COMMON REGISTER DESCRIPTIONS
MOTHERBOARD FUNCTION REGISTER MAP
Interrupt Vector and Steering
- Module Health Monitoring Registers
- Scratchpad Area
ETHERNET
67PPC2 CONNECTOR/PIN-OUT INFORMATION
MECHANICAL DETAILS
- General - Outline
PART NUMBER DESIGNATION
SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES
SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES
- SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL)
- LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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3U OpenVPX ARM Computer

INTRODUCTION
68ARM1 Overview
3U Profiles supported:
Connection Flexibility:
2x 10/100/1000 Base-T and 2x 1000Base-KX Ethernet:
ARM® Cortex®-A9 Dual Core 800 MHz Processor:
512 MB DDR3 SDRAM:
32 GB SATA II NAND Flash:
Less than 10 Watts Motherboard Power Dissipation:
Support for three independent, smart function:
Peripheral I/O:
Continuous Background Built-In-Test (BIT):
Software Support Kits (SSKs):
VICTORY Interface Services:
Commercial and rugged mechanical options:
SOFTWARE SUPPORT
Specifications
- General for the Motherboard
- Environmental
REGISTER MEMORY MAP ADDRESSING
- Board Base Address
- Module Slot and Function Addresses
REGISTER DESCRIPTIONS
MOTHERBOARD FUNCTION REGISTER MAP
Module Information Registers
Hardware Information Registers
Motherboard Firmware Information Registers
Motherboard Measurement Registers
Boards with additional Slave Zynq Processor
Temperature Readings
Ethernet Configuration Registers
Interrupt Vector and Steering
Motherboard Health Monitoring Registers
Module Control Command Requests
Modules Health Monitoring Registers
Module Communications Status
Module BIT Status
Scratchpad Area
ETHERNET
68ARM1 CONNECTOR/PIN-OUT INFORMATION
Front I/O Utility Connector J5 (Convection and Conduction-Cooled)
Rear I/O VPX Connectors P0-P2 (Conduction-Cooled)
Rear I/O Summary
- Rear I/O Utility Plane (P0)
- Rear I/O Data/Control Planes (P1)
USER I/O - Defined Area (User Defined I/O) (P2)
MECHANICAL DETAILS
- Conduction Cooled
- Convection Cooled
PART NUMBER DESIGNATION
SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES
SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES
- SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL)
- LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)
APPENDIX: EMBEDDED ARM (XILINX® XC7Z015 SOC) OPTION DETAILS
Linux Application Developer
Reference Manuals
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
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3U OpenVPX ARM SBC

INTRODUCTION
SOFTWARE SUPPORT
Specifications
- General for the Motherboard
- Environmental
68ARM2 OVERVIEW
Built-In Test
U-Boot Firmware (Boot Utility/Linux®)
Boot ROM (VxWorks®)
Operating System Support
Mechanicals
- Heat Sink
- 68ARM2 Connector Interfaces
68ARM2 ENVIRONMENTAL/POWER SPECIFICATIONS
Power Requirements
68ARM2 OUTLINE DIMENSIONS
68ARM2 ON BOARD RESOURCES
- *Memory*
- *Peripheral I/O*
Real-Time Clock
CAUTION
SPI
Serial Ports
Onboard TTL
TTL I/O Specifications
- TTL Input
- TTL Output
TTL Register Descriptions
TTL Direction
TTL Data
TTL Loopback
TTL IRQ Enable
TTL IRQ Polarity
TTL IRQ Status
SATA Register
68ARM2 TAMPER DETECT INTERFACE AND ACTION CIRCUIT
68ARM2 SOFTWARE LIBRARIES/ASSOCIATED DOCUMENTS
REGISTER MEMORY MAP ADDRESSING
ARM Platform Type/Maximum Module Slot Count
MOTHERBOARD FUNCTION REGISTER MAP
- Module Information Registers
Hardware Information Registers
Motherboard Firmware Information Registers
Motherboard Core Information
Motherboard FPGA Information
Motherboard Measurement Registers
Temperature Readings
Higher Precision Temperature Readings
Ethernet Configuration Registers
Interrupt Vector and Steering
Motherboard Health Monitoring Registers
Modules Health Monitoring Registers
Scratchpad Registers
ETHERNET
68ARM2 CONNECTOR/PIN-OUT INFORMATION
Front and Rear Panel Connectors
- Front Panel Connector
Chassis Ground
*Front I/O Utility Connector J5 (Convection and Conduction-Cooled)*
Rear I/O VPX Connectors P0-P2 (Conduction-Cooled)
Rear I/O Utility Plane (P0)
Rear I/O Data/Control Planes (P1)
USER I/O - Defined Area (User Defined I/O) (P2)
Rear User I/O Mapping
High Speed I/O Modules
- Ethernet (Rear I/O)
Connector Signal/Pin outs Notes
- NAI Synchro/Resolver Naming Convention
- Additional Pinout Notes
Part Number
Notes
SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES
SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES
- SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL)
- LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

Rugged OpenVPX I/O Board

68G5 DATA SHEET
INTRODUCTION
- 68G5 Overview
SOFTWARE SUPPORT
SPECIFICATIONS
- General for the Motherboard
- Environmental
REGISTER MEMORY MAP ADDRESSING
REGISTER DESCRIPTIONS
MOTHERBOARD FUNCTION REGISTER MAP
ETHERNET
68G5 CONNECTOR/PIN-OUT INFORMATION
MECHANICAL DETAILS
- General - Outline
68G5 PART NUMBER DESIGNATION
SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES
SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES
- SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL)
- LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)
Revision History
NAI Cares
Documentation
FAQ
Application Notes
Calibration and Repairs
Call Us

3U Multi-channel Discrete I/O Board

Introduction
Manual
68DT1 3U OpenVPX High Density I/O Boards
Architected for Versatility
Board Support Package and Software Support
Background Built-In-Test (BIT)
One-Source Efficiencies
Product Lifecycle Management
INTRODUCTION
68DT1 Overview
SOFTWARE SUPPORT
Specifications
- General for the Motherboard
- Environmental
REGISTER MEMORY MAP ADDRESSING
- Board Base Address
- Module Slot and Function Addresses
MOTHERBOARD REGISTER DESCRIPTIONS
MOTHERBOARD FUNCTION REGISTER MAP
Module Information Registers
Hardware Information Registers
Temperature Readings
Ethernet Configuration Registers
Interrupt Vector and Steering
Motherboard Health Monitoring Registers
Modules Health Monitoring
Module Communications Status
Module BIT Status
SPECIFIC FUNCTION OVERVIEW
DISCRETE INPUT/OUTPUT REGISTER DESCRIPTIONS
Discrete Input/Output Registers
Input/Output Format Low (DT-I/O Ch 1-24, 25-48 only)
Input/Output Format High (DT-I/O Ch 1-24, 25-48 only)
Write Outputs (DT-I/O Ch 1-24, 25-48 only)
Input/Output State
Discrete Input/Output Threshold Programming Registers
Max High Threshold
Upper Threshold
Lower Threshold
Min Low Threshold
Discrete Input/Output Measurement Registers
Voltage Reading
Current Reading
VCC Bank Registers
Select Pullup or Pulldown
Current for Source/Sink
VCC Bank Reading
Discrete Input/Output Control Registers
Debounce Time
Overcurrent Reset
Unit Conversion Programming Registers
Enable Floating Point Mode
Floating Point State
Background BIT Threshold Programming Registers
Background BIT Threshold
Reset BIT
User Watchdog Timer Programming Registers
Module Common Registers
Status and Interrupt Registers
BIT Status
Function: Sets the corresponding bit associated with the channel's BIT error.
Voltage Reading Error
Driver Error
Low-to-High Transition Status
High-to-Low Transition Status
Overcurrent Status (DT-I/O Ch 1-24, 25-48 only)
Above Max High Threshold Status
Below Min Low Threshold Status
Mid-Range Status
User Watchdog Timer Fault
Summary Status
DISCRETE INPUT (DT-IN CH 1-24, 25-48) FUNCTION REGISTER MAP
Discrete Input Registers
Discrete Input Threshold Programming Registers
VCC Bank Registers
Discrete Input Control Registers
Unit Conversion Programming Registers
User Watchdog Timer Programming Registers<