The 75ARM1 3U cPCI Single Board Computer (SBC) offers a variety of features designed to meet the needs of complex requirements for integrated multifunction I/O-intensive, mission-critical applications. Some of the key features include:

3U cPCI Form Factor: The 75ARM1 is housed in a 3U cPCI form factor, ensuring compatibility with existing CompactPCI systems while providing a compact yet power solution for your application.

Connection Flexibility: The SBC provides flexibility in connectivity options, with the ability to connect to devices via the front panel, rear panel, or both. This feature is particularly useful in different mounting or space-constrained scenarios.

2x 10/100/1000 Base-T Ethernet: The 75ARM1 has two 10/100/1000 Base-T Ethernet ports, with the option to have one to the rear, one to the front I/O, or both to the rear.

ARM® Cortex®-A9 Dual Core 800 MHz Processor: he 75ARM1 offers a significant advantage by providing enhanced processing power and efficiency. With its dual-core configuration and 800 MHz clock speed, it enables advanced computational tasks and real-time processing capabilities, making it an ideal choice for applications requiring high performance computing within a compact form factor.

512 MB DDR3 SDRAM: The SBC features a 512 MB DDR3 SDRAM, which offers users a dependable memory solution for demanding military, industrial, and aerospace environments:

32 GB SATA II NAND Flash: The 75ARM1 utilizes a SATA II NAND Flash memory capable of providing up to 32 GB of storage, offering high-capacity, durable, reliable, and rugged data storage. It is well suited for applications where data must be securely stored and accessed in challenging environmental conditions while providing a cost-effective storage solution.

Less than 5 Watts Motherboard Power Dissipation: With a power dissipation of less than 5 watts, the 75ARM1 proves a highly efficient solution, offering superior energy conservation, effective thermal management, extended mission endurance, and heightened reliability for demanding military, industrial, and aerospace applications.

Support for three independent, smart function: The SBC can support up to three independent, smart function modules based on the COSA® architecture. With over 100 modules to choose from, this allows for a wide range of input and output capabilities, including analog and digital I/O, signal generation and acquisition, and communication interfaces. Each function module slot has an independent x1 SerDes interface for motherboard-to-smart module interface, to offload the host processor from I/O management.

Peripheral I/O: The 75ARM1 board features several sophisticated on-board (on motherboard) peripheral I/O interfaces, all of which are rear accessed. Designed to meet the diverse requirements of complex projects, this comprehensive I/O suite includes:

Continuous Background Built-In-Test (BIT): Continuously monitoring the board’s health and functionality during operation, this feature allows for proactive maintenance, minimizing downtime and facilitating early issue resolution for uninterrupted performance in demanding operational environments.

Software Support Kits (SSKs): SSKs are provided ‘free of charge' and include base motherboard and function module API libraries and documentation. Sample and source code are also available, as well as support for real-time operating systems (RTOS) such as Wind River® VxWorks®, Xilinx® PetaLinux, and DDC-I Deos™, providing developers with flexibility and customization options for their specific application needs.

VICTORY Interface Services: NAI offers VICTORY Interface Services as an option, providing an open industry-standard approach for integrating different components in a system.

Commercial and rugged mechanical options: The 75ARM1 is available in both commercial and rugged models, making it suitable for a wide range of applications.

Specifications are subject to change without notice.

Unless otherwise specified, the following table outlines the general Environmental Specifications design guidelines for board level products of North Atlantic Industries. All our cPCI, VME and OpenVPX boards are designed for either air or conduction cooling. All boards also incorporate appropriate stiffening to ensure performance during shock and vibration but also to assure reliable operation (lower fatigue stresses) over the service life of the product.

Notes:

Specifications subject to change without notice

The table below lists the BAR used for access to the motherboard and module registers. The second BAR is used internally for motherboard and module firmware updates. The other cPCI/PCIe BARs not listed are not used.

The memory map for the modules are dependent on the types of modules on the board and the order in which the modules are installed on the board as well as the firmware installed on the motherboard. The function modules are enumerated allowing for dynamic memory space allocation and therefore the “start” address of the module function register area is factory pre-defined (and read from) the Module Address register. Refer to Figure 1 for an example.

Motherboard Registers

Read/Write access to the motherboard registers starts with the base address for the board and then the motherboard base offset address.

For example, to address Module Slot 1 Start Address register (i.e. register address = 0x0400):

Module Registers:

Read/Write access to the Function module’s registers start with the base address of the board. Add the “content” for the Module Start Address and then, add the specific module function register offset.

For example, to address an appropriate/specific function module with a register offset:

The Module Slot Addressing Ready, Module Slot Address, Module Slot Size and Module Slot ID registers provide information about the modules detected on the board.

The registers identified in this section provide information about the board’s hardware.

The registers in this section provide information on the revision of the firmware installed on the motherboard.

The registers in this provide motherboard temperature measurement information, and where applicable the slave processor measurements.

The registers in this section provide a summary of motherboard temperature sensors and their corresponding bits. Additionally, this section provides an overview of the registers allocated to those sensors, which are used to monitor current/minimum/maximum temperature readings, upper & lower critical/warning temperature thresholds, and whether or not a programmed temperature threshold has been exceeded.

These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).

The registers in this section provide information about the Ethernet Configuration for the two ports on the board.

Important: Regardless if the board is configured for one or two Ethernet ports, the second IP address cannot be on the same Subnet as the First IP Address. The table below provides examples of valid and invalid IP Addresses and Subnet Mask Addresses.

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Function: Provides the ability to command individual Modules to Reset, Power-down, or Power-up.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Operational Settings: The Module Control Commands registers provide the ability to request individual Modules to perform one of the following functions – Reset, Power-down, Power-up. Only one command can be requested at a time per Module. For example, one can’t request a Reset and a Power-down at the same time for the same Module. Once the command is recognized and handled, the bit will be cleared.

There is one Control Command Request register per Module. Each register is Bit-mapped as shown in the table below:

Function: Registers reserved as scratch pad for customer use.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Operational Settings: This area in memory is reserved for customer use.

Temperature Readings

Higher Precision Temperature Readings

Module Communications Status

Module BIT Status

The interface uses a specific message framework for all commands and responses. All messages begin with a Preamble code and end with a Postamble code. The message framework is shown below.

Notes

The interface provides two main addressing areas: Onboard and Off-board.

Onboard addressing refers to accessing resources located on the board that is implementing the operation interface (including its modules).

Off-board addressing refers to accessing resources located on another board reachable via VME, PCI, or other bus. Off-board addressing requires a Master/Slave configuration.

The user must always specify if a particular address is Onboard or Off-board. See the command descriptions for the onboard and off-board flags.

Within a particular board (Onboard or Off-board), the address space is broken up into two areas: Motherboard Common Address Space and Module Address Space. All addresses are 32-bit.

Motherboard Common Address Space starts at 0x00000000 and ends at 0x00004000. This is a 4Kx32-bit address space (16 kbytes).

Module Address Space starts at 0x00004000. Module addressing is dynamically configured at startup. NAI boards support between 1 and 6 modules. The minimum module address space size is 4Kx32 (16 kbytes) and module sizes are always a multiple of 4Kx32.

Module addressing is dynamic and cumulative. The first detected module (starting with Slot 1) is given an address of 0x00004000. The 2nd detected Module is given an address of:

First_Detected_Module_Address + First_Detected_Module_Size

If no module is detected in a module slot, that slot is not given an address. Therefore, if the first detected Module is in Slot 2, then that module address will be 0x00004000. If the next detected module is in Slot 4, then the address of that Module will be:

Second_Detected_Module_Address = First_Detected_Module_Address + First_Detected_Module_Size

If a 3rd Module is detected in Slot 6, then the address of that Module will be:

Third_Detected_Module_Address = Second_Detected_Module_Address + Second_Detected_Module_Size

Users can always retrieve the Module Addresses, Module Sizes and Module IDs from the fixed Motherboard Common address area. This data is set upon each board startup. While the Module Addressing is dynamic, the address where these addresses are stored is fixed. For example, to find the startup address of the module location in Slot 3, refer to the MB Common Address 0x00000408 from the Motherboard Common Addresses table that follows.

Front Panel LEDs indications (only available on air-cooled units).

Front Panel: J3 pins 1, 26; J4 pins 25, 50 (Connected to cPCI system ground).

Front Panel: No dedicated pins - screw insert only.

The 75ARM1 utilizes a Mini-HDMI card edge connector J5, available on either convection or conduction cooled configurations, which provides the following signals:

NAI also provides an optional “breakout” adapter board (NAI P/N 75SBC4-BB) with an HDMI cable. The “breakout” adapter board and a MicroHDMI cable (NAI P/N 75SBC4-BB) allow for standard I/O connections to Ethernet, mini-USB-B, and asynchronous serial (DB9). Consult the factory for availability.

The 75ARM1 implements a 32-bit Compact PCI interface, conforming to the PICMG 2.0 R3.0 specification, and running at 33MHz. Hot Swap is NOT currently implemented on this card. The 75ARM1 card use 3.3 V signaling voltage, and is 5 V tolerant.

CAUTION: The 75ARM1 is specifically designed for use with 32-bit Compact PCI backplanes and is not compatible with 64-bit backplanes. Plugging this card into a 64-bit backplane may cause permanent component damage.

The following provides connector pin-out information for Rear Connector J2. Note that while there are several options for user input/output, there are also system dedicated pins that are reserved for specific motherboard functions. This provides 32 pins of available I/O. Dual Ethernet or Single Rear Ethernet with Rear USB option for Module Slot 2 reduces available I/O to 24 pins.

The following provides connector/pinout data for Front Panel connectors J3 and J4. Each connector provides 50 pins of I/O.

Front/Rear User I/O Mapping (for reference) is shown in the following table, with respect to DATAIO. Additional information on pin-outs can be found in the Module Operational Manuals or by contacting the factory.

Notes

Optional - see part number for specific configuration.

Select the Synchro/Resolver-to-Digital (SDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.

Frequency/voltage band tolerances +/- 10%.

*Consult factory for availability

Select the LVDT/RVDT-to-Digital (LDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Excitation voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.

Frequency/voltage band tolerances +/- 10%.