Specifications are subject to change without notice.

The module contains automatic background BIT testing that verifies channel processing (data read or write logic), tests for overcurrent conditions and provides status for threshold signal transitioning.

Any failure triggers an Interrupt (if enabled) with the results available in status registers. The testing is totally transparent to the user, requires no external programming and has no effect on the operation of this card. It can be enabled or disabled via the bus (see further details in register description), and continually checks that each channel is functional. This capability is accomplished by an additional test comparator that is incorporated into each module. The test comparator checks each channel and is compared against the operational channel. Depending upon the configuration, the Input data read or Output logic written of the operational channel and test comparator must agree or a fault is indicated with the results available in the associated status register. Low-toHigh and High-to-Low logic transitions are indicated.

There is no independent overcurrent detection. Instead, the BIT detection circuitry is used to infer an overcurrent condition if the output state setting doesn’t match the readback value seen by the input circuitry. For example, a shorted output, causing the read state to be opposite from the expected value would trigger this. If the fault persists beyond the BIT interval stabilization time, the overcurrent protection will kick in and reset the drive output by returning the transceiver to input mode. To reset this condition, a reset command needs to be issued to the Overcurrent Reset register, which will restore drive output and allow the latched status to be reset. This is separate from the reset for the Overcurrent Interrupt Enable register on this module. It is recommended that a reset command is done whenever status is cleared to avoid a non-apparent output reset condition.

Function: Sets channels as inputs or outputs.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0x 0000 0000

Operational Settings: Write 0 for input (default), 1 for output: Power-on default or reset is configured for input. Bit-mapped per channel.

I/O Format

Function: Reads High (1) or Low (0) inputs or outputs as defined by internal channel threshold values.

Type: binary word (32-bit)

Read/Write: R

Initialized Value: NA

Operational Settings: NA

Read I/O

Function: Sets data outputs High (1) or Low (0).

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write 1 for High output; write 0 for Low.

Notes: • Each bit corresponds to one of 16 channels.

Write Outputs

Function: When the Input/Output Format register is programmed for Input mode, the input signal will have the debounce filtering applied based on this programmed value. This is selectable for each channel.

Type: binary word (32-bit)

Data Range: 0x0000 0002 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: The Debounce register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Enter required debounce time into appropriate channel registers. LSB weight is 8 ns/bit (register may be programmed from 0 (debounce filter inactive) through a maximum of 32.36s (full scale w/ 8 ns resolution). Once a signal level is a logic voltage level period longer than the debounce time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed debounce time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state. Enter a value of 0 to disable debounce filtering. Debounce defaults to 0000h upon reset.

Function: Enables user selection of Normal Mode or a reduced (Slow Mode) slew rate to soften the driver output edges to control high-frequency EMI emissions.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write 1 for Normal Mode or 0 for Slow Mode.

Default: Normal Mode (1)

Slew Rate

Function: Enables 120 Ω termination.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write 1 for 120 Ω termination.

Notes: • With Slow Mode selected, the data rate is limited to about 250 kbps.

Termination

Function: Channels set for Inputs – BIT Dynamic Interrupt Status is set when a redundant measurement is inconsistent with the input measurement level detected. Channels set for Outputs – BIT Dynamic Interrupt Status is set when a dedicated measurement circuit compares the commanded level with the actual output level and the measurement is inconsistent with the commanded level.

Type: binary word (32-bit)

Read/Write: R

Initialized Value: 0

Operational Settings: 1 is read when a fault is detected. 0 indicates no fault detected.

Notes: Considered “momentary” during the actual event when detected.

Associated channel(s) bit set to 1) within 10 ms (pending characterization).

Bit Dynamic Status

Function: Channels set for Inputs – BIT Latched Status is set when a redundant measurement is inconsistent with the input measurement level detected. Channels set for Outputs – BIT Latched Status is set when a dedicated measurement circuit compares the commanded level with the actual output level and the measurement is inconsistent with the commanded level.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: 1 is written when a fault is detected. 0 indicates no fault detected.

Notes: • Faults are detected (associated channel(s) bit set to 1) within 10 ms (pending characterization).

BIT Latched Status

Function: When enabled, interrupts are generated for each channel when the BIT Interrupt Enable register indicates a fault. (See BIT Error Interrupt Interval register.)

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to enable interrupts. Write a 0 to disable interrupts.

Notes • A programmed valid Interrupt Vector should be assigned for typical ISR handling.

BIT Interrupt Enable

Function: When the BIT Interrupt Enable register is enabled, this register determines whether the interrupt will be generated for either “sense on edge” or “sense on level” event detection. Sense on “edge” requires a change from “no-go” to “go” state to trigger the status detection, while sense on “level” is independent of the previous state.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge.

BIT Set Edge/Level Interrupt

Function: Outputs only – senses an overcurrent or overload condition for each channel and provides real-time status. The output channel is also immediately disabled at time of overcurrent sensed condition.

Type: binary word (32-bit)

Read/Write: R

Initialized Value: 0

Operational Settings: 1 is read when overcurrent or overload condition transition is sensed. 0 indicates normal status.

Notes: • Status is indicated (associated channel(s) bit set to 1, based on BIT status), within 80 ms (pending characterization).

Overcurrent Dynamic Status

Function: Outputs only – senses an overcurrent or overload condition for each channel and provides status. The output channel is also immediately disabled at time of overcurrent sensed condition.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: 1 is written when overcurrent or overload condition transition is sensed. 0 indicates no status.

Notes: • Status is indicated (associated channel(s) bit set to 1, based on BIT status), within 80 ms (pending characterization).

Overcurrent Latched Status

Function: When enabled, interrupts are generated for each channel when the Overcurrent Latched Interrupt Status register senses an overcurrent or overload condition for any channel.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to enable interrupts. Write a 0 to disable interrupts.

Notes: • A programmed valid Interrupt Vector should be assigned for typical ISR handling.

Overcurrent Interrupt Enable

Function: Resets disabled channels in Overcurrent Latched Interrupt Status register following an overcurrent condition. Bit-mapped per channel.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: 1 is written to reset disabled channels. Processor will write a 0 back to the Overcurrent Reset register when reset process is complete.

Function: Inputs only – senses High to Low transitions for each channel and provides real-time status.

Type: binary word (32-bit)

Read/Write: R

Initialized Value: 0

Operational Settings: 1 is read when a rising edge transition is sensed. 0 indicates no status.

Notes: • Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 40 ns (pending characterization).

Hi-Lo Transition Dynamic Status

Function: Inputs only – senses High to Low transitions for each channel and provides status.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: 1 is written when a falling edge transition is sensed. 0 indicates no status.

Notes: • Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 40 ns (pending characterization).

Hi-Lo Transition Latched Status

Function: When enabled, interrupts are generated for each channel when the Hi-Lo Transition Latched Interrupt Status register senses a High to Low transition for any channel.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to enable interrupts. Write a 0 to disable interrupts.

Notes: • A programmed valid Interrupt Vector should be assigned for typical ISR handling.

Hi-Lo Transition Interrupt Enable

Function: This register controls whether the Lo-Hi Transition Latched Interrupt Status register will trigger on an edge or a level.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge.

Lo-Hi Transition Set Edge/Level Interrupt

Function: Sets up a threshold requirement of “successive” events to accumulate before a BIT error is generated. Accumulated successive fault detections add a +2 to the count and no-fault detections subtract 1 from the count to filter BIT errors prior to an actual interrupt generation. Once the count exceeds this registers value, a BIT error is generated.

Type: binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0x 0000 0003

Operational Settings: Write a threshold to filter BIT errors prior to generating a BIT Error.

Notes: Advantageous in “noisy”/unstable application environments or for general filtering purposes.

BIT Error Interrupt Interval

Function: Clears the BIT error.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to clear BIT errors.

BIT Count Error Clear

There are 10 Input modes. All input modes may be configured with debounce capability. Debounce capability allows configurable filtering of noisy signals and transients. Each channel may be set to an individual debounce time value. When a debounce time is set to a non-zero value, the signal reading after a transition must remain at the same level for the debounce interval before it is propagated through, otherwise it is rejected. All Input Modes (1-10) FIFO buffers are 1024 words deep.

Mode 0 – No Enhancement Mode: Behaves the same as a standard functionality only module.

Mode 1 – High Time Pulse Measurement (FIFO Buffer): Timing measurements record the time interval (in 8 ns ticks) from a pair of transitions.

Mode 2 – Low Time Pulse Measurement (FIFO Buffer): Timing measurements record the time interval (in 8 ns ticks) from a pair of transitions.

Mode 3 – Transition Timestamp of All Rising Edges (FIFO Buffer): Rising Edge time stamps from 125 MHz, 32-bit counter will be sequentially available and stored in the FIFO buffer.

Note: In this example, four counter values at the rising edge transitions are recorded to the FIFO: 0x344321, 0x344999, 0x345011, 0x345689, etc. Delta of 0x678 = 1656 counts, or 13.248 µs interval between pulses.

Mode 4 – Transition Timestamp of All Falling Edges (FIFO Buffer): Falling Edge time stamps from 125 MHz, 32-bit counter will be sequentially available and stored in the FIFO buffer.

Mode 5 – Transition Timestamp of All Edges (FIFO Buffer): Rising and Falling Edge time stamps from 125 MHz, 32-bit counter will be sequentially available and stored in the FIFO buffer.

Note: In this example, all edges time stamp. Four counter values at the transitions are recorded to the FIFO: 0x344321, 0x344999, 0x345011, 0x345689, etc. Delta of 0x33C = 828 counts, or 6.624 µs interval between pulses.

Mode 6 – Rising Edge Transition Counter: When selected, the rising edge count will be available from the count register at the FIFO read address. The counter is reset via user command.32-bit count range to 232.

Mode 7 – Falling Edge Transition Counter: When selected, falling edge count will be available from the count register at the FIFO read address. The counter is reset via user command. 32-bit count range to 232.

Mode 8 – Rising and Falling Edge Transition Counter: When selected, cumulative edge counts will be available from the count register at the FIFO read address. The counter is reset via user command. 32-bit count range to 232.

Mode 9 - Period Measurement: Timing measurements record the intervals from pulse-to-pulse in 8 ns ticks (delta timestamp).

Note: In Period Measurement mode, the same three pulse-to-pulse interval values as calculated in the timestamp measurement would be directly recorded to the FIFO.

Mode 10 - Frequency Measurement: Enables frequency measurement, which will be available and stored in the FIFO buffer. Frequency measurement correlates to/utilizes a programmable time interval, which is programmed in the Period register. Direct readout of frequency is available when the interval is set to one second.

There are three Output modes, which include a standard output mode, two PWM outputs and a Pattern Generator Output mode.

Mode 32 (0x20) – PWM Continuous Output Mode: In the sample shown below, each of the 24 channels has been set up with incrementing periods and pulse widths, running in continuous mode. Timing is asynchronous to each channel, but is very precise and with low jitter. In this mode, the configured PWM output is enabled and disabled with the Start Output/Measure Enable register.

Mode 33 (0x21) - PWM Burst: Repeats the pulse based on programmed Period and Pulse Width “n” times as programmed in the Number of Cycles register.

Mode 34 (0x22) – Pattern Generator Output: Outputs all mode selected channels based on the pattern programmed in the Pattern RAM register. The output rate is set in the Pattern RAM Period register. The output is a cyclic transmission of a 216 deep X 24 bit pattern array at configurable pattern intervals with 8 ns resolution. Pattern output may be stopped and resumed at the same point in the cycle. The following shows an arbitrary output of patterns as displayed on 24 channels of a logic analyzer. Each vertical column represents one 24-bit pattern of the 216 pattern array.

Function: This register provides selection of 13 different modes (0-10; 32,33,34). See the table that follows for a brief description of each mode.

Type: binary word (32-bit)

Data Range: 0 to 10, 32 to 34

Read/Write: R/W

Initialized Value: 0

Operational Settings: Modes 0 through 10; 32 through 34 are selectable for each channel. Writing a 0 will reset the Modes to their initialized state.

Notes:

Function:

Output Modes: When the Mode Select register is programmed for PWM output modes (Modes 32 & 33), the Start Output/Measure Enable register is used to start the channel outputs.

Input Modes: When the Mode Select register is programmed for PWM input modes (Modes 1-10), the Start Output/Measure Enable register is used to start measurement.

Type: binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: The channel(s) output is based on the pattern preset in the programmed pulse characteristic registers: Period, Pulse Width and Output Polarity. If the Mode Select register is set to Mode 33, the number of pulses is controlled by the Number of Cycles register.

Function: Resets Timer to default value.

Type: binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: W

Initialized Value: 0

Operational Settings: Writing any value to this register resets the Timer to default value.

Notes: • Resetting timers will also retrigger the FIFO store mechanism to trigger or restart the FIFO on the next valid low-to-high transition detected.

Function: Depends upon Mode Select register setting.

Read FIFO: Provides stored data dependent on the input channel(s) mode selected. Applicable to Modes 1 through 5, 9 and 10. See Mode Select register.

Read Count: Applicable to Modes 6, 7 and 8. See Mode Select register.

Type: binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: 0

Operational Settings: The available data in the FIFO buffer can be retrieved, one word at a time (32-bits), from the identified memory/register address.

Note: The Read FIFO and Read Count functions share a register. They are mutually exclusive in that depending upon the setting of the Mode Select register, either one or the other will become active.

Function: Reads the number of 32-bit words stored in FIFO for each channel.

Type: binary word (32-bit)

Data Range: Any value

Read/Write: R/W

Initialized Value: 0

Operational Settings: Mode Select register set for Modes 1-10.

Function: Provides a real-time status of the following conditions: FIFO empty, FIFO full, Almost Empty, Almost Full

Type: binary word (32-bit)

Data Range: 0x0000 0000 to 0x4

Read/Write: R

Initialized Value: 0

Operational Settings: See table below.

Read FIFO Status

D0 – Full

D1 – Almost Full

D2 – Almost Empty

D3 - Empty

Function: Resets measurement FIFO (only) to zero. Applicable to Modes 1 through 5, 9 and 10. See Mode Select register.

Type: binary word (32-bit)

Read/Write: W

Initialized Value: 0

Operational Settings: The act of writing any value to this register will apply the reset.

The Period register works in conjunction with the Pulse Width, Output Select, Number of Cycles and Start Output/Measure Enable registers to configure PWM output. See Configuring PWM Output figure below. It is also used for Period and Frequency measurement.

Configuring PWM Output

Function: When the Mode Select register is programmed for PWM output modes (Modes 32 & 33), the PWM Period is based on the programmed value set in this register.

Type: binary word (32-bit)

Data Range: 0x0000 0002 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Mode Select register is set to Mode 32 or 33, the Period register is used to program the desired channel PWM output pulse period. Enter the desired PWM pulse period (LSB=@ 8 ns; valid entries are: 16 ns to 34.36 sec.).

Note: Programmed PWM Period must be greater than the value set in the Pulse Width register.

Function: When the Mode Select register is programmed for PWM output modes (Modes 32 & 33), the Pulse Width register is used to program the desired channel(s) PWM Pulse Width “ON” time. See Configuring PWM Output figure. When the Mode Select register is programmed for frequency measurement (Mode 10), the Pulse Width register is used to program the Timebase for the desired channel(s).

Type: binary word (32-bit)

Data Range: 0x0000 0001 to 0xFFFF FFFE

Read/Write: R/W

Initialized Value: 0

Operational Settings:

Applied to Mode(s) 32 & 33: Enter the desired PWM Pulse Width (LSB=@ 8 ns; valid entries from 8 ns to 34.36 s). Used in conjunction with the Period register.

Note: Programmed PWM Pulse Width must be less than the value set in the Period register.

Applied to Mode 10: For channel(s) with functions that rely on frequency measurement, the Pulse Width register is used to program the desired channel “Timebase” for the frequency measurement transition count period of time.

Note: There may be an initial “low” level output delay based on the Period time before the initial pulse is output.

Function: When Mode Select register is programmed for Mode 33, the Number of Cycles register is used to program the number of times to repeat the pulse.

Type: binary word (32-bit)

Data Range: 0x0000 0001 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Pulse is determined and used in conjunction with the Period and Pulse Width registers. Enter the desired Number of Cycles.

Note: If continuous pulse generation is desired, select Mode 32.

Pattern RAM Start Address

Function: Programs the desired channel output pattern rate.

Register Offset(s): 0x201C

Type: binary word (32-bit)

Data Range: 0x0000 0001 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Enter the desired Pattern Generator RAM period (LSB=@ 8 ns).

Default: 0

Function: Programs the starting address for the Pattern Generator.

Register Offset(s): 0x2014

Type: binary word (32-bit)

Data Range: 0x40000 to 0x7FFFC

Read/Write: R/W

Initialized Value: 0

Operational Settings: Output rate is determined by the rate programmed in the Pattern RAM Period register. Write a 1 to start the RAM pattern output; write a 0 to stop the RAM pattern output.

Default: 0

Pattern RAM Start Address

Function: Programs the ending address for the Pattern Generator. There are 32K address locations from 0x40000 to 0x7FFFC.

Register Offset(s): 0x2018

Type: binary word (32-bit)

Data Range: 0x40000 to 0x7FFFC

Read/Write: R/W

Initialized Value: 0

Operational Settings: NA

Default: 0

Pattern RAM End Address

Function: Program the number of times to repeat the pattern.

Register Offset(s): 0x2020

Type: binary word (32-bit)

Data Range: 0x0000 0001 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Programmable from 1 to 232 cycles.

Default: 0

Function: Control the RAM data pattern.

Type: binary word (32-bit)

Data Range: N/A

Read/Write: W

Initialized Value: 0

Operational Settings: The Pattern RAM Start Address register determines where the pattern RAM output will begin when enabled. The Pattern RAM End Address register determines where the pattern RAM output will end when enabled. After the pattern at the pattern end address is outputted, it will loop back to the start address.

Pattern RAM Control

Notes: Write the following values to the register to perform each function.

Function: When the Mode Select register is programmed for PWM output modes (Modes 32 & 33), the Output Polarity programs the PWM Pulse Period to start either High (0) or Low (1).

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Applies to Modes 32 and 33. The Output Polarity register is used to program the start “level” (or state) of the PWM Pulse Period. The default is ON (High), which is set when the PWM Polarity bit is 0. The PWM start level channel(s) output will be High for the initial start of the period. See Configuring PWM Output figure. The time is defined by the Period and Pulse Width registers. The remainder of the PWM Period time will be “low” defined by the [PWM Period - PWM Pulse Width]. If the PWM Polarity bit is set to 1, the PWM start level will be “low” for the programmed PWM Pulse Width and the remainder of the PWM Period time will be “high” defined by the [PWM Period – PWM Pulse Width]. Bit mapped per channel.

Note: There may be an initial “low” level output delay based on the Period time before the initial pulse is output.

Output Polarity

Function: Configures the Enhanced Functionality Modes to apply to the channel.

Type: unsigned binary word (32-bit)

Data Range: See table

Read/Write: R/W

Initialized Value: 0

Operational Settings: It is important that the channel is correctly configured to either input or output in the Input/Output Format registers to correspond to the Enhanced Functionality Mode selected. Setting a 0 to this register will configure that channel to normal operation.

Function: Enables/starts the measurements or outputs based on the Mode Select for the channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x00FF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Setting the bit for the associated channel to a “1” will start the measurement or output depending on the Mode Select configuration for that channel. Setting the bit for the associated channel to “0” will stop the measurements/outputs.

Enable Measurements/Outputs

Function: Resets the measurement timestamp and counter for the channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x00FF FFFF

Read/Write: W

Initialized Value: 0

Operational Settings: Setting the bit for the associated channel to a “1” will:

Reset Timer/Counter

Function: The data stored in the FIFO Buffer Data is dependent on the input mode.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: N/A

Operational Settings: Refer to examples in section 2.1.

Function: This is a counter that reports the number of 32-bit words stored in the FIFO buffer.

Type: unsigned binary word (32-bit)

Data Range: 0 – 255 (0x0000 0000 to 0x0000 00FF)

Read/Write: R

Initialized Value: 0

Operational Settings: Every time a read operation is made from the FIFO Buffer Data register, the value in the FIFO Word Count register will be decremented by one. The maximum number of words that can be stored in the FIFO is 255.

FIFO Word Count

Function: Clears FIFO by resetting the FIFO Word Count register.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: W

Initialized Value: N/A

Operational Settings: Write a 1 to resets the Words in FIFO to zero; Clear FIFO register does not clear data in the buffer. A read to the buffer data will give “aged” data.

Clear FIFO

Function: Sets the corresponding bit associated with the FIFO status type; there is a separate register for each channel.

Type: unsigned binary word (32-bit)

Data Range: See table

Read/Write: R

Initialized Value: 0

Description

FIFO Status

Function: Contains the count of the transitions depending on the configuration in the Mode Select register – Rising Edges, Falling Edges or All Edges.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: 0

Operational Settings: Refer to examples in section 2.1.3 Transition Counter.

Function: When the Mode Select register is programmed for Frequency Measurement mode (10), the value in the Frequency Measurement Period is used as the time interval for counting the number of rising edge transitions within that interval.

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Set the Frequency Measurement Period (LSB = 10 µs). Refer to examples in section 2.1.5 Frequency Measurement.

Function: When the Mode Select register is programmed for PWM Continuous or PWM Burst mode (32-33), the value in the PWM Period is used as the time interval for outputting the PWM signal.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0001 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Set the PWM Period (LSB = 10 µs). The PWM Period must be greater than the value set in the PWM Pulse Width register. Refer to examples in section 2.2.1.

Function: When the Mode Select register is programmed for PWM Continuous or PWM Burst mode (32-33), the value in the PWM Pulse Width is used as the time interval of the “ON” state for outputting the PWM signal.

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Set the PWM Pulse Width (LSB = 10 µs). The PWM Pulse Width must be less than the value set in the PWM Pulse Width register. Refer to examples in section 2.2.1.

Function: When the Mode Select register is programmed for PWM Continuous or PWM Burst mode (32-33), the value in the PWM Output Polarity is used to specify whether the PWM output signal starts with a rising edge (Positive (0)), or a falling edge (Negative (1)).

Type: unsigned binary word (32-bit)