Specifications are subject to change without notice.

Unless otherwise specified, the following table outlines the general Environmental Specifications design guidelines for board level products of North Atlantic Industries. All our cPCI, VME and OpenVPX boards are designed for either air or conduction cooling. All boards also incorporate appropriate stiffening to ensure performance during shock and vibration but also to assure reliable operation (lower fatigue stresses) over the service life of the product.

Notes:

Specifications subject to change without notice

The table below lists the BAR used for access to the motherboard and module registers. The second BAR is used internally for motherboard and module firmware updates. The other cPCI/PCIe BARs not listed are not used.

The memory map for the modules are dependent on the types of modules on the board and the order in which the modules are installed on the board as well as the firmware installed on the motherboard. The function modules are enumerated allowing for dynamic memory space allocation and therefore the “start” address of the module function register area is factory pre-defined (and read from) the Module Address register. Refer to Figure 1 for an example.

Figure 1. Register Memory Map Addressing for Motherboards with ESx and 1 Module

Motherboard Registers

Read/Write access to the motherboard registers starts with the base address for the board and then the motherboard base offset address.

For example, to address Module Slot 1 Start Address register (i.e. register address = 0x0400):

Module Registers:

Read/Write access to the Function module’s registers start with the base address of the board. Add the “content” for the Module Start Address and then, add the specific module function register offset.

For example, to address an appropriate/specific function module with a register offset:

The Module Slot Addressing Ready, Module Slot Address, Module Slot Size and Module Slot ID provide information about the modules detected on the board.

The registers identified in this section provide information about the board’s hardware.

The registers in this section provide information on the revision of the firmware installed on the motherboard.

The registers in this provide motherboard temperature measurement information.

The registers in this section provide a summary of motherboard temperature sensors and their corresponding bits. Additionally, this section provides an overview of the registers allocated to those sensors, which are used to monitor current/minimum/maximum temperature readings, upper & lower critical/warning temperature thresholds, and whether or not a programmed temperature threshold has been exceeded.

These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).

The registers in this section provide information about the Ethernet Configuration for the two ports on the board.

Important: Regardless if the board is configured for one or two Ethernet ports, the second IP address cannot be on the same Subnet as the First IP Address. The table below provides examples of valid and invalid IP Addresses and Subnet Mask Addresses.

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Function: Provides the ability to command individual Modules to Reset, Power-down, or Power-up.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Operational Settings: The Module Control Commands registers provide the ability to request individual Modules to perform one of the following functions – Reset, Power-down, Power-up. Only one command can be requested at a time per Module. For example, one can’t request a Reset and a Power-down at the same time for the same Module. Once the command is recognized and handled, the bit will be cleared.

There is one Control Command Request register per Module. Each register is Bit-mapped as shown in the table below:

Function: Registers reserved as scratch pad for customer use.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Operational Settings: This area in memory is reserved for customer use.

Temperature Readings

Higher Precision Temperature Readings

Module Communications Status

Module BIT Status

The interface uses a specific message framework for all commands and responses. All messages begin with a Preamble code and end with a Postamble code. The message framework is shown below.

Notes

The interface provides two main addressing areas: Onboard and Off-board.

Onboard addressing refers to accessing resources located on the board that is implementing the operation interface (including its modules).

Off-board addressing refers to accessing resources located on another board reachable via VME, PCI, or other bus. Off-board addressing requires a Master/Slave configuration.

The user must always specify if a particular address is Onboard or Off-board. See the command descriptions for the onboard and off-board flags.

Within a particular board (Onboard or Off-board), the address space is broken up into two areas: Motherboard Common Address Space and Module Address Space. All addresses are 32-bit.

Motherboard Common Address Space starts at 0x00000000 and ends at 0x00004000. This is a 4Kx32-bit address space (16 kbytes).

Module Address Space starts at 0x00004000. Module addressing is dynamically configured at startup. NAI boards support between 1 and 6 modules. The minimum module address space size is 4Kx32 (16 kbytes) and module sizes are always a multiple of 4Kx32.

Module addressing is dynamic and cumulative. The first detected module (starting with Slot 1) is given an address of 0x00004000. The 2nd detected Module is given an address of:

First_Detected_Module_Address + First_Detected_Module_Size

If no module is detected in a module slot, that slot is not given an address. Therefore, if the first detected Module is in Slot 2, then that module address will be 0x00004000. If the next detected module is in Slot 4, then the address of that Module will be:

Second_Detected_Module_Address = First_Detected_Module_Address + First_Detected_Module_Size

If a 3rd Module is detected in Slot 6, then the address of that Module will be:

Third_Detected_Module_Address = Second_Detected_Module_Address + Second_Detected_Module_Size

Users can always retrieve the Module Addresses, Module Sizes and Module IDs from the fixed Motherboard Common address area. This data is set upon each board startup. While the Module Addressing is dynamic, the address where these addresses are stored is fixed. For example, to find the startup address of the module location in Slot 3, refer to the MB Common Address 0x00000408 from the Motherboard Common Addresses table that follows.

The 68G5E 3U OpenVPX Multifunction I/O board is available in two configurations: convection-cooled and conduction-cooled. The 68G5E follows the OpenVPX “Payload Slot Profile” configured as:

Slot profile: SLT3-SWH-16T-14.4.6 (GbE Switch Only Configuration)

                      SLT3-PER-1U-14.3.3 (GbE Switch w/1-MFIO Function)

Module profile: MOD3-PER-1U-16.3.3-2

User I/O is available through the OpenVPX user defined rear I/O connectors P1, P2 (see part number and pin-out information).

Front Panel LEDs indications (only available on air-cooled units).

Rear connector key guides are chassis ground.

The 68G5E utilizes a Mini-HDMI type card edge connector J5, available on either convection or conduction-cooled configurations that provides the following signals:

NAI also provides an optional “breakout” adapter board (NAI P/N 75SBC4-BB) with a mini-HDMI to mini-HDMI type cable. The “breakout” adapter board and a Micro-HDMI cable (NAI P/N 75SBC4-BB) allow for standard I/O connections to Ethernet and asynchronous serial (DB9). Consult the factory for availability.

The 68G5E 3U OpenVPX Ethernet Switch and Multifunction I/O board provides interface via the rear VPX connectors.

Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Module Operational Manuals.

*See Part Number Designator for availability

Select the Synchro/Resolver-to-Digital (SDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.

Frequency/voltage band tolerances +/- 10%.

*Consult factory for availability

Select the LVDT/RVDT-to-Digital (LDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Excitation voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.

Frequency/voltage band tolerances +/- 10%.

*Consult factory for availability

To allow each of the above-mentioned Ethernet configuration utilities to access the ES2, the PC’s Ethernet port must be configured properly. For example, if the ES2 default IP address was set to 12.0.0.1 with a subnet mask of 255.0.0.0, the management PC must be configured to operate within the same IP subnet.

Continuing with this example, the PC must now be configured to operate within this same IP subnet.

Set the IP address of the Network Interface Card on the PC to be within the same subnet. For example, set the PC’s IP address to be 12.0.0.20.

The various configuration utilities supported by ES2 allow the user to configure, manage, and monitor the ES2 switch. Overviews of the CLI, Telnet, SSH, HTTP, and SNMP methods of connecting to the Management Port are provided in this section of the manual.

Once the ES2 has been configured, it is possible to save the final configuration, and upon each subsequent reboot or power cycle the ES2 will initialize to this configuration.

These configuration settings may be saved though the Management Port interface and may be saved as many times as you choose.

The CLI (Command Line Interface) is used to configure the ISS from a console attached to the serial port of the switch or from a remote terminal using TELNET or SSH.

The following table lists the generic CLI command modes.

At the ISS login prompt that is displayed, use the user name root and password admin123 to access the CLI shell.

The basic configuration of the switch involves configuring IP address, VLAN, and so on. All commands and parameters can be abbreviated to their shortest unambiguous length. On the command line, the TAB key may be used to display available command options and autocomplete commands. The 'help' command displays a list of commands.

The ES2 comes up with a VLAN configured, by default. This VLAN is called the default VLAN (VLAN ID = 1). All ports in the switch are members of the default VLAN. Port 1 (g 0/3) is enabled by default.

The ports are configured and referenced as <interface-type>[space]<slot number>/<port number>

<interface-type> is either “gigabitethernet” or “extreme-ethernet” and can be abbreviated as “g” or “e”.

<slot number> is 0.

<port number> is 3 to 18 for 1 Gb ports and 1 to 4 for 10Gb ports.

The configuration made by the user can be saved in the Flash and can be restored when the switch is started.

The configurations saved using write startup config command will not update the configurations in issnvram.txt (that is, it will not change the factory default settings). If the factory default settings need to be changed, administrator should explicitly modify it through default ip address command.

Configuring the Default IP Address is a three-step procedure that will result in the IP address to be written to the NVRAM and configuration and this will be used as the IP address of the default interface when the switch is restarted.

Detailed Steps:

1) Execute the following commands to configure the Default IP Address. Enter the Global Configuration mode.

Configure the default IP address and subnet mask as 12.0.0.100 and 255.255.0.0, respectively.

Exit from the Global Configuration mode.

2) View the default IP address and subnet mask by executing the following command

Proceed to section “Configuring IP address for an Interface” and set the same IP address and subnet mask for VLAN 1 (default VLAN). The switch will have this IP address and subnet mask after the switch restart only if the allocation method is manual.

Setting the default IP allocation mode for the Switch configures the mode by which the default interface acquires its IP address. The default IP allocation mode for a switch can be manual or dynamic. The default value is manual.

1) Execute the following commands to change the default IP allocation mode of the default VLAN.

Enter the Global Configuration mode.

Configure the default mode to dynamic.

Exit from the Global Configuration mode.

2) View the default mode by executing the following command.

ISS uses the dynamic address allocation protocols - BOOTP or DHCP or RARP - to acquire the IP for management VLAN during switch restart.

Configuring the default IP address allocation protocol configures the protocol by which the default interface dynamically acquires its IP address.

1) Execute the following commands to configure the default dynamic address allocation protocol.

Enter the Global Configuration mode.

Configure the default allocation protocol.

Exit from the Global Configuration mode.

2) View the default IP Address Allocation Protocol by executing the following command

Configuring IP address for an Interface configures the IP address which will be used for sending and receiving the packets.

1) Execute the following commands to configure an IP address for a VLAN interface. Enter the Global Configuration mode.

Enter the Interface Configuration mode.

Shut down the VLAN interface.

Configure the IP address and subnet mask.

Bring up the VLAN interface.

Exit from the Interface Configuration mode.

Configuring the IP address for an Interface requires the interface to be shutdown prior to the configuration.

2) View the configured interface IP address by executing the following show command.

3) Save the configuration

An interface can be configured to acquire the dynamic IP address either from DHCP or from RARP. The default value is DHCP.

1) Execute the following commands to acquire dynamic IP for VLAN 1 through DHCP.

Enter the Global Configuration mode.

Enter the Interface Configuration mode.

Configure the VLAN interface to dynamically acquire an IP address through the Dynamic Host Configuration Protocol

Exit from configuration mode.

2) View the configured IP address by executing the following show command.

A DHCP server must exist in the network to allocate dynamic IP through DHCP mechanism.

CLI commands are focused on performing specific operations. In order to provide a consistent, composable user experience, the CLI commands of the ES2 protocols and IP implementation solutions adhere to the Industry Standard CLI syntax.

The following table provide a listing and identification of which CLI commands are supported.