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CD1 Manual

INTRODUCTION

As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurement and simulation, communications, Ethernet switch, and SBC functions. The CD1 is compatible with all NAI Generation 5 motherboards. When bearings and gears start to fail in a machine, they shed metallic wear debris into the lubricant. The presence of a significant number of metal chips in the transmission fluid usually indicates mechanical problems. A chip detector is used to monitor the health of the engine or gear box. The chip detector is partially immersed in the transmission fluid so that it is exposed to the metal chips circulating inside of the fluid. The chip detector has a magnet to attract and retain metal chips of all sizes. Much of the metallic chips are referred to as “fuzz” which is produced by normal wear of components and represent no danger. New transmission and engines, for instance, produce relatively large amounts of fuzz during their break-in periods. This fuzz builds up in the chip detector, causing a short across the contacts of the chip detect. The problem is how to distinguish between relatively harmless fuzz from that of larger size chips which indicate that the piece of equipment being monitored has internal components that are failing. If the failure of internal components goes undetected, a catastrophic equipment failure is possibly imminent. Thus, there is a real need to be able to, during flight, determine if the chip detector has detected large chips or just nuisance fuzz. Too many false alarms caused by nuisance fuzz degrades the effectiveness of the chip detector system as a pilot is more likely to attribute a chip indication to just another false alarm. The Chip Detector Module CD1 provides 6 chip detection and burn channels. Each channel has a programmable energy setting and can be configured for either manual or automatic burn.

For a brief summary of the features and complete list of specifications, click here for the CD1 data sheet.

CD1 Overview

Six (6) chip detection and burn channels: The CD1 function module provides six independent channels for chip detection and burn operations. This allows the module to monitor and control multiple devices or circuits at the same time, giving the system greater flexibility for applications that require parallel channel support.
Programmable energy setting of 0.25 to 2.30 Joules: The module allows the user to program the burn energy level from 0.25 to 2.30 Joules to match specific application requirements. This adjustability helps optimize burn performance while reducing the risk of applying too little or too much energy to the connected device.
Programmable Auto-Burn feature: The programmable Auto-Burn feature gives users control over when the burn function is triggered by allowing a detection threshold to be defined. It also lets the user set a maximum burn count, which helps limit repeated burn attempts and supports safer, more controlled operation.
Built-in Test: Built-in Test enhances system reliability by providing diagnostic capability within the module. This feature helps identify faults or operational issues, supporting maintenance efforts and improving confidence in module performance.

PRINCIPLE OF OPERATION

The CD1 module provides both Chip Detection and Fuzz Burn capability. Programming capabilities for chip detection thresholds, fuzz burn energy levels and retries allows for this module to be used on many different types of engines/gearboxes. In addition, the CD1 module includes internal built-in tests that provide monitoring of the Chip Detection and Fuzz Burn circuitry.

Chip Detection

The CD1 provides programmable resistance thresholds (warning and fault) for each channel independently. The module will read and store each channel’s resistance. A warning status bit will be set if the resistance is below the warning resistance threshold set by the user. A fault status bit will be set if the resistance is below the fault resistance threshold. Programming capability allows for common circuit use on many different types of gearbox/transmissions.

Fuzz Burn

The CD1 provides programmable energy level controls for each channel independently for the Fuzz Burn charge and release. A programmable energy level control provides adjustable parameters for the Fuzz Burn that may be tailored for different gearbox/transmission characteristics.

The Fuzz Burn feature can be configured in Auto-Burn or Manual-Burn mode. In Auto-Burn mode, the user will load a warning resistance threshold, fault resistance threshold and maximum count. After this setup, the user will enable the Auto-Burn bit in the configuration register to arm the system. The system will automatically initiate a burn when the channel resistance is at or below the fault resistance threshold. The auto-burn will continue until the measured resistance goes above the warning resistance threshold or the maximum Auto-Burn count is met. In Manual-Burn, the user can monitor the channel resistance to decide when to initiate a burn.

The burn count will automatically reset to zero and rearm for continued operation without further intervention if the burn operation is successful and the detected resistance rises above the warning threshold.

Built-in Test

The CD1 module supports three types of built-in tests: Initiated, Power-On, and Background. The results of these tests are logically ORed together and stored in the BIT Dynamic Status and BIT Latched Status registers. Test coverage is module-wide, for circuitry common to all channels.

Initiated Built-In Test

The user Initiated Built-In-Test (IBIT) is a charge and discharge test on the BIT channel. After the test completes, the user can read the results stored in the BIT Dynamic Status register, a 0 indicates that the channel has passed and a 0x3F indicates that it failed.

Power-On Built-In Test

The Power-On Built-In-Test (PBIT) is performed on the module automatically when power is applied. The Power- On BIT runs the same test as Initiated BIT, and automatically performed on boot-up. Results of the test are stored in the BIT Dynamic Status register.

Background Built-In Test

The background Built-In-Test or Continuous BIT (CBIT) runs in the background for the module. It charges up the capacitor bank to a different voltage each iteration and discharges it to an on-board load. If the circuitry detects an incorrect voltage or discharge profile, a BIT error will be set. Channels that are enabled and discharged will also be checked for an acceptable discharge profile. The results of this background test are stored in the BIT Dynamic Status register. Test intervals of 150 seconds minimize impact on normal operation.

Status and Interrupts

The Chip Detection/Fuzz Burn Function Module provides registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

Module Common Registers

The Chip Detection/Fuzz Burn Function Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

REGISTER DESCRIPTIONS

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and where applicable, a data table.

Chip Detection Registers

The registers associated with the Chip Detection feature allow configuration of individual channels. Settings include channel enable/disable, burn modes, and the thresholds for the Chip Detect Warning and Fault status.

Channel resistance registers allow reading of the detected resistance on each channel.

Channel Enabled

Function:

Enables the chip detection for the channel.

Type:

unsigned binary word (32-bits)

Data Range:

0x0000 0000 to 0x0000 003F

Read/Write:

R/W

Initialized Value:

0x00000000

Operational Settings:

Set to 1 to enable the chip detection, 0 to disable chip detection for the channel. Disabled channels will not trigger burn events or report status. When a channel is reenabled from a disabled state, the burn counter will automatically reset to 0 to allow for a full burn count sequence.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

Channel Resistance

Function:

Measured resistance for the channel.

Type:

unsigned binary word (32-bits)

Data Range:

0 to 100000 (0x0000 0000 to 0x0001 86A0)

Read/Write:

Initialized Value:

N/A

Operational Settings:

Measures resistance in ohms. This reading is used to determine if Fuzz Burn is needed when the mode is configured for Auto-Burn. Readings to 100kΩ, with optimal measurement accuracy with resistance values below 8kΩ.

All burn triggers observe a burn threshold of 2kΩ. Burn triggering for each channel is suppressed for all threshold settings and burn modes when the measured resistance is above 2kΩ.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Warning Resistance Threshold

Function:

Sets the resistance threshold associated with the Warning Resistance Level Status.

Type:

unsigned binary word (32-bits)

Data Range:

0 to 100000 (0x0000 0000 to 0x0001 86A0)

Read/Write:

R/W

Initialized Value:

100000

Operational Settings:

When the measured resistance is below this threshold, the Warning Resistance Level Status is set for this channel. After a burn event, a detected resistance above the warning threshold will automatically reset the burn count to allow for continued operation.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Fault Resistance Threshold

Function:

Sets the resistance threshold associated with the Fault Resistance Level Status.

Type:

unsigned binary word (32-bits)

Data Range:

0 to 100000 (0x0000 0000 to 0x0001 86A0)

Read/Write:

R/W

Initialized Value:

Operational Settings:

When the measured resistance is at or below this threshold, the Fault Resistance Level Status is set for this channel. This threshold is the primary criteria for triggering auto-burn pulses.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Open Resistance Threshold

Function:

Sets the resistance threshold associated with the Open Resistance Level Status.

Type:

unsigned binary word (32-bits)

Data Range:

1000 to 400000

Read/Write:

R/W

Initialized Value:

Operational Settings:

When the measured resistance is above this threshold, the Open Resistance Level Status is set for this channel. Recommended configuration with a monitor resistance connected in parallel to the operating channels, with this threshold set to allow detection of an open wire harness connection.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Fuzz Burn Registers

The registers associated with the Fuzz Burn are used for individual channel configuration of the energy setting, burn mode, and burn count limit.

Energy Setting

Function:

Sets the channel’s energy level in Joules

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

0.25 to 2.30

Read/Write:

R/W

Initialized Value:

0.25

Operational Settings:

This sets the pulse energy to be delivered when a burn is triggered. Typical requirement for burn of a 0.003 wire standard is approximately 0.6J.

Auto-Burn Mode Select

Function:

Configures for auto-burn or manual-burn mode for channel.

Type:

unsigned binary word (32-bits)

Data Range:

0x0000 0000 to 0x0000 003F

Read/Write:

R/W

Initialized Value:

0x00000000

Operational Settings:

Set bit associated with the channel to 1 for auto-burn mode or 0 for manual-burn mode. Auto-burn mode will fire the burn automatically when the monitored resistance threshold requirements are met. Manual burn mode allows the user to trigger a burn pulse manually, provided the detected resistance is below a 2kΩ threshold.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

Auto-Burn Maximum Count

Function:

When Auto-Burn Select Mode is set, this register specifies the maximum number of burns before the module stops the fuzz burn.

Type:

unsigned binary word (32-bits)

Data Range:

0 to 20 (0x0000 0000 to 0x0000 0014)

Read/Write:

R/W

Initialized Value:

Operational Settings:

When Auto-Burn Select Mode is set, this register specifies the maximum number of burns before the module stops and sets “Auto Burn Complete” bit in the Auto-Burn Count register.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	D	D	D	D	D	D

Auto-Burn Count

Function:

When Auto-Burn Select Mode is set, this register specifies the number of Auto-Burn attempts since enabled.

Type:

unsigned binary word (32-bits)

Data Range:

See table

Read/Write:

Initialized Value:

Operational Settings:

When Auto-Burn Select Mode is set, this register specifies the maximum number of burns attempts. After each burn attempt, the resistance value is read. If the value is above the value for the Warning Resistance Threshold, the module stops the burn attempt. If the resistance read is below value specified for the Fault Resistance Threshold, the module will continue to attempt to burn the fuzz until the number of attempts reach the Auto-Burn Maximum Count value or the resistance is above the threshold value after the burn.

Bit(s)

Interface

Description

D31:D16

Reserved

Set Reserved bits to 0

D5:D0

Auto Burn Count of Channel

Count

Manual-Burn Initiate

Function:

When Auto-Burn Select Mode for the channel is set to Manual-Burn, writing to the bit associated with the channel will initiate a manual burn. Bit will be cleared after burn completed.

Type:

unsigned binary word (32-bits)

Data Range:

Read/Write:

R/W

Initialized Value:

0x00000000

Operational Settings:

Set channel bit to 1 to initiate a manual burn.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

Test Registers

The chip detect module provides the ability to run an initiated test (IBIT).

Test Enabled

Function:

Set bit IBIT to enable the associated Initiated Built-In-Test.

Type:

unsigned binary word (32-bit)

Data Range:

0 to 0x0000 0008

Read/Write:

R/W

Initialized Value:

0x0

Operational Settings:

BIT tests include an Initiated BIT test. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects failures.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	IBIT	0	0	0

Background BIT Threshold Programming Registers

The technique used by the automatic background BIT test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged. This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state.

For example, the Background BIT Threshold is set to 6 (Initialized Value). During normal operation, the automatic background BIT sequence is operating. In each of three separate (but consecutive) 150-second BIT sequences, an internal BIT fault is detected. This will cause the fault bit within the BIT Status register of that specific channel to be set. The reason for this is as each BIT sequence was internally identified as “failed”, the internal BIT counter added two counts (+2) per fault. Three consecutive BIT faults (x3) results in an internal count of 6, which meets the programmed Background BIT Threshold of 6. Therefore:

BIT Status (channel) = 1 (set) when (+2 counts when failed) x (3 BIT sequences) ≥ 6 (Threshold).

Background BIT Threshold

Function:

Sets background BIT Threshold value to use for all channels for BIT failure indication.

Data Range:

1 to 65,535

Read/Write:

R/W

Initialized Value:

Operational Settings:

Using the automatic background BIT test counting scheme described in Background BIT Threshold Programming Registers, the Background BIT Threshold is specified as an internal “count” compare number. This “count” number is associated and compared to a count of faulted internal BIT sequences. The BIT sequence execution time is approximately 150 sec. (the time is typical; it may vary and is dependent on module board platform configuration). A specific channel’s BIT fault status will be set in the BIT Status register once the internal BIT counter has met or exceeded the programmed Background BIT Threshold value (refer to Background BIT Threshold section for detailed description of this function).

Reset BIT

Function:

Resets the PBIT, CBIT and IBIT internal circuitry and count mechanism.

Type:

unsigned binary word (32-bit)

Data Range:

0 to 0x0000 FFFF

Read/Write:

Initialized Value:

Operational Settings:

Set bit to 1 to reset the PBIT, CBIT and IBIT mechanisms. Bit is self-clearing.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	All

Module Common Registers

Refer to “Module Common Registers Module Manual” for the register descriptions.

Status and Interrupt Registers

The CD1 Module provides status registers for BIT, Warning Resistance and Fault Resistance Thresholds as well as Channel Status.

BIT Status

There are four registers associated with the BIT Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.

BIT Status

Function:

Indicates the corresponding channels associated with the channel’s BIT status or configuration

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0001

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

BIT Dynamic Status

BIT Latched Status

BIT Interrupt Enable

BIT Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Fault Resistance Status

There are four registers associated with the Fault Resistance Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.

Fault Resistance Status

Function:

Status for fault resistance level. If measured resistance is below the Fault Resistance Threshold setting, the bit associated with that channel will be set to a 1.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 003F

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Fault Resistance Dynamic Status

Fault Resistance Latched Status

Fault Resistance Interrupt Enable

Fault Resistance Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Warning Resistance Status

There are four registers associated with the Warning Resistance Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.

Warning Resistance Status

Function:

Status for warning resistance level. If measured resistance is below the Warning Resistance Threshold setting, the bit associated with that channel will be set to a 1.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 003F

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Warning Resistance Dynamic Status

Warning Resistance Latched Status

Warning Resistance Interrupt Enable

Warning Resistance Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Open Resistance Status

There are four registers associated with the Fault Resistance Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.

Open Resistance Status

Function:

Status for an open resistance level. If measured resistance is above the Open Resistance Threshold setting, the bit associated with that channel will be set to a 1.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 003F

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

Open Resistance Dynamic Status

Open Resistance Latched Status

Open Resistance Interrupt Enable

Open Resistance Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Summary Status

There are four registers associated with the Summary Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.

Summary Status

Function:

Sets the corresponding bit associated with the channel that has an error condition. Allows monitoring of a single register to detect multiple types of errors. The summary status is an OR of the following individual status register components: Fault, Warning, Open, and BIT. Bit mapped for per-channel indication.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 003F

Read/Write:

R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value:

N/A

Summary Dynamic Status

Summary Latched Status

Summary Interrupt Enable

Summary Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.

In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note	The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector

Function:

Set an identifier for the interrupt.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

R/W

Initialized Value:

Operational Settings:

When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering

Function:

Sets where to direct the interrupt.

Type:

unsigned binary word (32-bit)

Data Range:

See table

Read/Write:

R/W

Initialized Value:

Operational Settings:

When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME	1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)	2
Direct Interrupt to PCIe Bus	5
Direct Interrupt to cPCI Bus	6

FUNCTION REGISTER MAP

KEY

Configuration/Control

Measurement/Status

MEASUREMENT REGISTERS
NOTE: Base Address - 0x4000 0000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1000	Channel Enabled	R/W

0x1104	Channel Resistance Ch 1	R	0x110C	Warning Resistance Threshold Ch 1	R/W
0x1204	Channel Resistance Ch 2	R	0x120C	Warning Resistance Threshold Ch 2	R/W
0x1304	Channel Resistance Ch 3	R	0x130C	Warning Resistance Threshold Ch 3	R/W
0x1404	Channel Resistance Ch 4	R	0x140C	Warning Resistance Threshold Ch 4	R/W
0x1504	Channel Resistance Ch 5	R	0x150C	Warning Resistance Threshold Ch 5	R/W
0x1604	Channel Resistance Ch 6	R	0x160C	Warning Resistance Threshold Ch 6	R/W

0x1108	Fault Resistance Ch 1	R/W	0x1110	Open Resistance Threshold Ch 1	R/W
0x1208	Fault Resistance Ch 2	R/W	0x1210	Open Resistance Threshold Ch 2	R/W
0x1308	Fault Resistance Ch 3	R/W	0x1310	Open Resistance Threshold Ch 3	R/W
0x1408	Fault Resistance Ch 4	R/W	0x1410	Open Resistance Threshold Ch 4	R/W
0x1508	Fault Resistance Ch 5	R/W	0x1510	Open Resistance Threshold Ch 5	R/W
0x1608	Fault Resistance Ch 6	R/W	0x1610	Open Resistance Threshold Ch 6	R/W

MEASUREMENT REGISTERS

NOTE: Base Address - 0x4000 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x1000

Channel Enabled

R/W

0x1104

Channel Resistance Ch 1

0x110C

Warning Resistance Threshold Ch 1

R/W

0x1204

Channel Resistance Ch 2

0x120C

Warning Resistance Threshold Ch 2

R/W

0x1304

Channel Resistance Ch 3

0x130C

Warning Resistance Threshold Ch 3

R/W

0x1404

Channel Resistance Ch 4

0x140C

Warning Resistance Threshold Ch 4

R/W

0x1504

Channel Resistance Ch 5

0x150C

Warning Resistance Threshold Ch 5

R/W

0x1604

Channel Resistance Ch 6

0x160C

Warning Resistance Threshold Ch 6

R/W

0x1108

Fault Resistance Ch 1

R/W

0x1110

Open Resistance Threshold Ch 1

R/W

0x1208

Fault Resistance Ch 2

R/W

0x1210

Open Resistance Threshold Ch 2

R/W

0x1308

Fault Resistance Ch 3

R/W

0x1310

Open Resistance Threshold Ch 3

R/W

0x1408

Fault Resistance Ch 4

R/W

0x1410

Open Resistance Threshold Ch 4

R/W

0x1508

Fault Resistance Ch 5

R/W

0x1510

Open Resistance Threshold Ch 5

R/W

0x1608

Fault Resistance Ch 6

R/W

0x1610

Open Resistance Threshold Ch 6

R/W

CONTROL REGISTERS
NOTE: Base Address - 0x4000 0000
NOTE: ~ Data is always in Floating Point.
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1100	Energy Setting Ch 1~	R/W	0x1008	Auto-Burn Mode Select	R/W
0x1200	Energy Setting Ch 2~	R/W	0x1004	Manual-Burn Initiate	R/W
0x1300	Energy Setting Ch 3~	R/W
0x1400	Energy Setting Ch 4~	R/W
0x1500	Energy Setting Ch 5~	R/W
0x1600	Energy Setting Ch 6~	R/W

0x1114	Auto-Burn Maximum Count Ch 1	R/W	0x111C	Auto-Burn Count Ch 1	R
0x1214	Auto-Burn Maximum Count Ch 2	R/W	0x121C	Auto-Burn Count Ch 2	R
0x1314	Auto-Burn Maximum Count Ch 3	R/W	0x131C	Auto-Burn Count Ch 3	R
0x1414	Auto-Burn Maximum Count Ch 4	R/W	0x141C	Auto-Burn Count Ch 4	R
0x1514	Auto-Burn Maximum Count Ch 5	R/W	0x151C	Auto-Burn Count Ch 5	R
0x1614	Auto-Burn Maximum Count Ch 6	R/W	0x161C	Auto-Burn Count Ch 6	R

CONTROL REGISTERS

NOTE: Base Address - 0x4000 0000

NOTE: ~ Data is always in Floating Point.

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x1100

Energy Setting Ch 1~

R/W

0x1008

Auto-Burn Mode Select

R/W

0x1200

Energy Setting Ch 2~

R/W

0x1004

Manual-Burn Initiate

R/W

0x1300

Energy Setting Ch 3~

R/W

0x1400

Energy Setting Ch 4~

R/W

0x1500

Energy Setting Ch 5~

R/W

0x1600

Energy Setting Ch 6~

R/W

0x1114

Auto-Burn Maximum Count Ch 1

R/W

0x111C

Auto-Burn Count Ch 1

0x1214

Auto-Burn Maximum Count Ch 2

R/W

0x121C

Auto-Burn Count Ch 2

0x1314

Auto-Burn Maximum Count Ch 3

R/W

0x131C

Auto-Burn Count Ch 3

0x1414

Auto-Burn Maximum Count Ch 4

R/W

0x141C

Auto-Burn Count Ch 4

0x1514

Auto-Burn Maximum Count Ch 5

R/W

0x151C

Auto-Burn Count Ch 5

0x1614

Auto-Burn Maximum Count Ch 6

R/W

0x161C

Auto-Burn Count Ch 6

TEST REGISTERS
NOTE: Base Address - 0x4000 0000
0x0248	Test Enabled	R/W

TEST REGISTERS

NOTE: Base Address - 0x4000 0000

0x0248

Test Enabled

R/W

BACKGROUND BIT THRESHOLD REGISTERS
NOTE: Base Address - 0x4000 0000
0x02B8	Background BIT Threshold	R/W	0x02BC	Clear Background BIT Counter	W

BACKGROUND BIT THRESHOLD REGISTERS

NOTE: Base Address - 0x4000 0000

0x02B8

Background BIT Threshold

R/W

0x02BC

Clear Background BIT Counter

MODULE COMMON REGISTERS
Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.

MODULE COMMON REGISTERS

Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.

STATUS REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x4000 0000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0800	BIT Dynamic Status	R
0x0804	BIT Latched Status*	R/W
0x0808	BIT Interrupt Enable	R/W
0x080C	BIT Set Edge/Level Interrupt	R/W

0x02AC	Power-on BIT Complete⁺⁺	R/W
NOTE: ⁺⁺After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.

Fault Resistance Status	Warning Resistance Status
0x0810	Dynamic Status	R	0x0820	Dynamic Status	R
0x0814	Latched Status*	R/W	0x0824	Latched Status*	R/W
0x0818	Interrupt Enable	R/W	0x0828	Interrupt Enable	R/W
0x081C	Set Edge/Level Interrupt	R/W	0x082C	Set Edge/Level Interrupt	R/W

Open Resistance Status	Summary Status
0x0830	Dynamic Status	R	0x09A0	Dynamic Status	R
0x0834	Latched Status*	R/W	0x09A4	Latched Status*	R/W
0x0838	Interrupt Enable	R/W	0x09A8	Interrupt Enable	R/W
0x083C	Set Edge/Level Interrupt	R/W	0x09AC	Set Edge/Level Interrupt	R/W

STATUS REGISTERS

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).

NOTE: Base Address - 0x4000 0000

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0800

BIT Dynamic Status

0x0804

BIT Latched Status*

R/W

0x0808

BIT Interrupt Enable

R/W

0x080C

BIT Set Edge/Level Interrupt

R/W

0x02AC

Power-on BIT Complete⁺⁺

R/W

NOTE: ⁺⁺After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.

Fault Resistance Status

Warning Resistance Status

0x0810

Dynamic Status

0x0820

Dynamic Status

0x0814

Latched Status*

R/W

0x0824

Latched Status*

R/W

0x0818

Interrupt Enable

R/W

0x0828

Interrupt Enable

R/W

0x081C

Set Edge/Level Interrupt

R/W

0x082C

Set Edge/Level Interrupt

R/W

Open Resistance Status

Summary Status

0x0830

Dynamic Status

0x09A0

Dynamic Status

0x0834

Latched Status*

R/W

0x09A4

Latched Status*

R/W

0x0838

Interrupt Enable

R/W

0x09A8

Interrupt Enable

R/W

0x083C

Set Edge/Level Interrupt

R/W

0x09AC

Set Edge/Level Interrupt

R/W

INTERRUPT REGISTERS
The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0500	Module 1 Interrupt Vector 1 - BIT	R/W	0x0600	Module 1 Interrupt Steering 1 - BIT	R/W
0x0504	Module 1 Interrupt Vector 2 - Fault Resistance Status	R/W	0x0604	Module 1 Interrupt Steering 2 - Fault Resistance Status	R/W
0x0508	Module 1 Interrupt Vector 3 - Warning Resistance Status	R/W	0x0608	Module 1 Interrupt Steering 3 - Warning Resistance Status	R/W
0x050C	Module 1 Interrupt Vector 4 - Open Resistance Status	R/W	0x060C	Module 1 Interrupt Steering 4 - Open Resistance Status	R/W
0x0510 to 0x0564	Module 1 Interrupt Vector 5 to 26 - Reserved	R/W	0x0610 to 0x0664	Module 1 Interrupt Steering 5 to 26 - Reserved	R/W
0x0568	Module 1 Interrupt Vector 27 - Summary	R/W	0x0668	Module 1 Interrupt Steering 27 - Summary	R/W
0x056C to 0x057C	Module 1 Interrupt Vector 28 to 32 - Reserved	R/W	0x066C to 0x067C	Module 1 Interrupt Steering 28 to 32 - Reserved	R/W

0x0700	Module 2 Interrupt Vector 1 - BIT	R/W	0x0800	Module 2 Interrupt Steering 1 - BIT	R/W
0x0704	Module 2 Interrupt Vector 2 - Fault Resistance Status	R/W	0x0804	Module 2 Interrupt Steering 2 - Fault Resistance Status	R/W
0x0708	Module 2 Interrupt Vector 3 - Warning Resistance Status	R/W	0x0808	Module 2 Interrupt Steering 3 - Warning Resistance Status	R/W
0x070C	Module 2 Interrupt Vector 4 - Open Resistance Status	R/W	0x080C	Module 2 Interrupt Steering 4 - Open Resistance Status	R/W
0x0710 to 0x0764	Module 2 Interrupt Vector 5 to 26 - Reserved	R/W	0x0810 to 0x0864	Module 2 Interrupt Steering 5 to 26 - Reserved	R/W
0x0768	Module 2 Interrupt Vector 27 - Summary	R/W	0x0868	Module 2 Interrupt Steering 27 - Summary	R/W
0x076C to 0x077C	Module 2 Interrupt Vector 28 to 32 - Reserved	R/W	0x086C to 0x087C	Module 2 Interrupt Steering 28 to 32 - Reserved	R/W

0x0900	Module 3 Interrupt Vector 1 - BIT	R/W	0x0A00	Module 3 Interrupt Steering 1 - BIT	R/W
0x0904	Module 3 Interrupt Vector 2 - Fault Resistance Status	R/W	0x0A04	Module 3 Interrupt Steering 2 - Fault Resistance Status	R/W
0x0908	Module 3 Interrupt Vector 3 - Warning Resistance Status	R/W	0x0A08	Module 3 Interrupt Steering 3 - Warning Resistance Status	R/W
0x090C	Module 3 Interrupt Vector 4 - Open Resistance Status	R/W	0x0A0C	Module 3 Interrupt Steering 4 - Open Resistance Status	R/W
0x0910 to 0x0964	Module 3 Interrupt Vector 5 to 26 - Reserved	R/W	0x0A10 to 0x0A64	Module 3 Interrupt Steering 5 to 26 - Reserved	R/W
0x0968	Module 3 Interrupt Vector 27 - Summary	R/W	0x0A68	Module 3 Interrupt Steering 27 - Summary	R/W
0x096C to 0x097C	Module 3 Interrupt Vector 28 to 32 - Reserved	R/W	0x0A6C to 0x0A7C	Module 3 Interrupt Steering 28 to 32 - Reserved	R/W

0x0B00	Module 4 Interrupt Vector 1 - BIT	R/W	0x0C00	Module 4 Interrupt Steering 1 - BIT	R/W
0x0B04	Module 4 Interrupt Vector 2 - Fault Resistance Status	R/W	0x0C04	Module 4 Interrupt Steering 2 - Fault Resistance Status	R/W
0x0B08	Module 4 Interrupt Vector 3 - Warning Resistance Status	R/W	0x0C08	Module 4 Interrupt Steering 3 - Warning Resistance Status	R/W
0x0B0C	Module 4 Interrupt Vector 4 - Open Resistance Status	R/W	0x0C0C	Module 4 Interrupt Steering 4 - Open Resistance Status	R/W
0x0B10 to 0x0B64	Module 4 Interrupt Vector 5 to 26 - Reserved	R/W	0x0C10 to 0x0C64	Module 4 Interrupt Steering 5 to 26 - Reserved	R/W
0x0B68	Module 4 Interrupt Vector 27 - Summary	R/W	0x0C68	Module 4 Interrupt Steering 27 - Summary	R/W
0x0B6C to 0x0B7C	Module 4 Interrupt Vector 28 to 32 - Reserved	R/W	0x0C6C to 0x0C7C	Module 4 Interrupt Steering 28 to 32 - Reserved	R/W

0x0D00	Module 5 Interrupt Vector 1 - BIT	R/W	0x0E00	Module 5 Interrupt Steering 1 - BIT	R/W
0x0D04	Module 5 Interrupt Vector 2 - Fault Resistance Status	R/W	0x0E04	Module 5 Interrupt Steering 2 - Fault Resistance Status	R/W
0x0D08	Module 5 Interrupt Vector 3 - Warning Resistance Status	R/W	0x0E08	Module 5 Interrupt Steering 3 - Warning Resistance Status	R/W
0x0D0C	Module 5 Interrupt Vector 4 - Open Resistance Status	R/W	0x0E0C	Module 5 Interrupt Steering 4 - Open Resistance Status	R/W
0x0D10 to 0x0D64	Module 5 Interrupt Vector 5 to 26 - Reserved	R/W	0x0E10 to 0x0E64	Module 5 Interrupt Steering 5 to 26 - Reserved	R/W
0x0D68	Module 5 Interrupt Vector 27 - Summary	R/W	0x0E68	Module 5 Interrupt Steering 27 - Summary	R/W
0x0D6C to 0x0D7C	Module 5 Interrupt Vector 28 to 32 - Reserved	R/W	0x0E6C to 0x0E7C	Module 5 Interrupt Steering 28 to 32 - Reserved	R/W

0x0F00	Module 6 Interrupt Vector 1 - BIT	R/W	0x1000	Module 6 Interrupt Steering 1 - BIT	R/W
0x0F04	Module 6 Interrupt Vector 2 - Fault Resistance Status	R/W	0x1004	Module 6 Interrupt Steering 2 - Fault Resistance Status	R/W
0x0F08	Module 6 Interrupt Vector 3 - Warning Resistance Status	R/W	0x1008	Module 6 Interrupt Steering 3 - Warning Resistance Status	R/W
0x0F0C	Module 6 Interrupt Vector 4 - Open Resistance Status	R/W	0x100C	Module 6 Interrupt Steering 4 - Open Resistance Status	R/W
0x0F10 to 0x0F64	Module 6 Interrupt Vector 5 to 26 - Reserved	R/W	0x1010 to 0x1064	Module 6 Interrupt Steering 5 to 26 - Reserved	R/W
0x0F68	Module 6 Interrupt Vector 27 - Summary	R/W	0x1068	Module 6 Interrupt Steering 27 - Summary	R/W
0x0F6C to 0x0F7C	Module 6 Interrupt Vector 28 to 32 - Reserved	R/W	0x106C to 0x107C	Module 6 Interrupt Steering 28 to 32 - Reserved	R/W

INTERRUPT REGISTERS

The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0500

Module 1 Interrupt Vector 1 - BIT

R/W

0x0600

Module 1 Interrupt Steering 1 - BIT

R/W

0x0504

Module 1 Interrupt Vector 2 - Fault Resistance Status

R/W

0x0604

Module 1 Interrupt Steering 2 - Fault Resistance Status

R/W

0x0508

Module 1 Interrupt Vector 3 - Warning Resistance Status

R/W

0x0608

Module 1 Interrupt Steering 3 - Warning Resistance Status

R/W

0x050C

Module 1 Interrupt Vector 4 - Open Resistance Status

R/W

0x060C

Module 1 Interrupt Steering 4 - Open Resistance Status

R/W

0x0510 to 0x0564

Module 1 Interrupt Vector 5 to 26 - Reserved

R/W

0x0610 to 0x0664

Module 1 Interrupt Steering 5 to 26 - Reserved

R/W

0x0568

Module 1 Interrupt Vector 27 - Summary

R/W

0x0668

Module 1 Interrupt Steering 27 - Summary

R/W

0x056C to 0x057C

Module 1 Interrupt Vector 28 to 32 - Reserved

R/W

0x066C to 0x067C

Module 1 Interrupt Steering 28 to 32 - Reserved

R/W

0x0700

Module 2 Interrupt Vector 1 - BIT

R/W

0x0800

Module 2 Interrupt Steering 1 - BIT

R/W

0x0704

Module 2 Interrupt Vector 2 - Fault Resistance Status

R/W

0x0804

Module 2 Interrupt Steering 2 - Fault Resistance Status

R/W

0x0708

Module 2 Interrupt Vector 3 - Warning Resistance Status

R/W

0x0808

Module 2 Interrupt Steering 3 - Warning Resistance Status

R/W

0x070C

Module 2 Interrupt Vector 4 - Open Resistance Status

R/W

0x080C

Module 2 Interrupt Steering 4 - Open Resistance Status

R/W

0x0710 to 0x0764

Module 2 Interrupt Vector 5 to 26 - Reserved

R/W

0x0810 to 0x0864

Module 2 Interrupt Steering 5 to 26 - Reserved

R/W

0x0768

Module 2 Interrupt Vector 27 - Summary

R/W

0x0868

Module 2 Interrupt Steering 27 - Summary

R/W

0x076C to 0x077C

Module 2 Interrupt Vector 28 to 32 - Reserved

R/W

0x086C to 0x087C

Module 2 Interrupt Steering 28 to 32 - Reserved

R/W

0x0900

Module 3 Interrupt Vector 1 - BIT

R/W

0x0A00

Module 3 Interrupt Steering 1 - BIT

R/W

0x0904

Module 3 Interrupt Vector 2 - Fault Resistance Status

R/W

0x0A04

Module 3 Interrupt Steering 2 - Fault Resistance Status

R/W

0x0908

Module 3 Interrupt Vector 3 - Warning Resistance Status

R/W

0x0A08

Module 3 Interrupt Steering 3 - Warning Resistance Status

R/W

0x090C

Module 3 Interrupt Vector 4 - Open Resistance Status

R/W

0x0A0C

Module 3 Interrupt Steering 4 - Open Resistance Status

R/W

0x0910 to 0x0964

Module 3 Interrupt Vector 5 to 26 - Reserved

R/W

0x0A10 to 0x0A64

Module 3 Interrupt Steering 5 to 26 - Reserved

R/W

0x0968

Module 3 Interrupt Vector 27 - Summary

R/W

0x0A68

Module 3 Interrupt Steering 27 - Summary

R/W

0x096C to 0x097C

Module 3 Interrupt Vector 28 to 32 - Reserved

R/W

0x0A6C to 0x0A7C

Module 3 Interrupt Steering 28 to 32 - Reserved

R/W

0x0B00

Module 4 Interrupt Vector 1 - BIT

R/W

0x0C00

Module 4 Interrupt Steering 1 - BIT

R/W

0x0B04

Module 4 Interrupt Vector 2 - Fault Resistance Status

R/W

0x0C04

Module 4 Interrupt Steering 2 - Fault Resistance Status

R/W

0x0B08

Module 4 Interrupt Vector 3 - Warning Resistance Status

R/W

0x0C08

Module 4 Interrupt Steering 3 - Warning Resistance Status

R/W

0x0B0C

Module 4 Interrupt Vector 4 - Open Resistance Status

R/W

0x0C0C

Module 4 Interrupt Steering 4 - Open Resistance Status

R/W

0x0B10 to 0x0B64

Module 4 Interrupt Vector 5 to 26 - Reserved

R/W

0x0C10 to 0x0C64

Module 4 Interrupt Steering 5 to 26 - Reserved

R/W

0x0B68

Module 4 Interrupt Vector 27 - Summary

R/W

0x0C68

Module 4 Interrupt Steering 27 - Summary

R/W

0x0B6C to 0x0B7C

Module 4 Interrupt Vector 28 to 32 - Reserved

R/W

0x0C6C to 0x0C7C

Module 4 Interrupt Steering 28 to 32 - Reserved

R/W

0x0D00

Module 5 Interrupt Vector 1 - BIT

R/W

0x0E00

Module 5 Interrupt Steering 1 - BIT

R/W

0x0D04

Module 5 Interrupt Vector 2 - Fault Resistance Status

R/W

0x0E04

Module 5 Interrupt Steering 2 - Fault Resistance Status

R/W

0x0D08

Module 5 Interrupt Vector 3 - Warning Resistance Status

R/W

0x0E08

Module 5 Interrupt Steering 3 - Warning Resistance Status

R/W

0x0D0C

Module 5 Interrupt Vector 4 - Open Resistance Status

R/W

0x0E0C

Module 5 Interrupt Steering 4 - Open Resistance Status

R/W

0x0D10 to 0x0D64

Module 5 Interrupt Vector 5 to 26 - Reserved

R/W

0x0E10 to 0x0E64

Module 5 Interrupt Steering 5 to 26 - Reserved

R/W

0x0D68

Module 5 Interrupt Vector 27 - Summary

R/W

0x0E68

Module 5 Interrupt Steering 27 - Summary

R/W

0x0D6C to 0x0D7C

Module 5 Interrupt Vector 28 to 32 - Reserved

R/W

0x0E6C to 0x0E7C

Module 5 Interrupt Steering 28 to 32 - Reserved

R/W

0x0F00

Module 6 Interrupt Vector 1 - BIT

R/W

0x1000

Module 6 Interrupt Steering 1 - BIT

R/W

0x0F04

Module 6 Interrupt Vector 2 - Fault Resistance Status

R/W

0x1004

Module 6 Interrupt Steering 2 - Fault Resistance Status

R/W

0x0F08

Module 6 Interrupt Vector 3 - Warning Resistance Status

R/W

0x1008

Module 6 Interrupt Steering 3 - Warning Resistance Status

R/W

0x0F0C

Module 6 Interrupt Vector 4 - Open Resistance Status

R/W

0x100C

Module 6 Interrupt Steering 4 - Open Resistance Status

R/W

0x0F10 to 0x0F64

Module 6 Interrupt Vector 5 to 26 - Reserved

R/W

0x1010 to 0x1064

Module 6 Interrupt Steering 5 to 26 - Reserved

R/W

0x0F68

Module 6 Interrupt Vector 27 - Summary

R/W

0x1068

Module 6 Interrupt Steering 27 - Summary

R/W

0x0F6C to 0x0F7C

Module 6 Interrupt Vector 28 to 32 - Reserved

R/W

0x106C to 0x107C

Module 6 Interrupt Steering 28 to 32 - Reserved

R/W

APPENDIX: PIN-OUT DETAILS

Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals.

Module Signal (Ref Only)	44-Pin I/O	50-Pin I/O (Mod Slot 1-J3)	50-Pin I/O (Mod Slot 2-J4)	50-Pin I/O (Mod Slot 3-J3)	50-Pin I/O (Mod Slot 3-J4)	Chip Detect (CD1)
DATIO1	2	10	1	2		CH1-RET
DATIO2	24	35	26	27		CH2-RET
DATIO3	3	11	2	3		CH1-RET
DATIO4	25	36	27	28		CH2-RET
DATIO5	5	13	4	5		CH1-VOUT
DATIO6	27	38	29	30		CH2-VOUT
DATIO7	7	14	5	6		CH1-RET
DATIO8	29	39	30	31		CH2-RET
DATIO9	8	15	6	7		CH3-RET
DATIO10	30	40	31	32		CH4-RET
DATIO11	10	17	8	9		CH3-VOUT
DATIO12	32	42	33	34		CH4-VOUT
DATIO13	12	18	9		17	CH3-RET
DATIO14	34	43	34		42	CH4-RET
DATIO15	13	19	10		18	CH3-RET
DATIO16	35	44	35		43	CH4-RET
DATIO17	15	21	12		20	CH5-VOUT
DATIO18	37	46	37		45	CH6-VOUT
DATIO19	17	22	13		21	CH5-RET
DATIO20	39	47	38		46	CH6-RET
DATIO21	18	23	14		22	CH5-RET
DATIO22	40	48	39		47	CH6-RET
DATIO23	20	25	16		24	(+)28VIN
DATIO24	42	50	41		49	28VIN-RTN
DATIO25	4	12	3	4		CH1-RET
DATIO26	26	37	28	29		CH2-RET
DATIO27	9	16	7	8		CH3-RET
DATIO28	31	41	32	33		CH4-RET
DATIO29	14	20	11		19	CH5-RET
DATIO30	36	45	36		44	CH6-RET
DATIO31	19	24	15		23	CH5-RET
DATIO32	41	49	40		48	CH6-RET
DATIO33	6
DATIO34	28
DATIO35	11
DATIO36	33
DATIO37	16
DATIO38	38
DATIO39	21
DATIO40	43
N/A

REVISION HISTORY

DOCS.NAII REVISIONS

Revision Date

Description

2025-03-06

Updated module pinout table to add module I/O pinouts for 44- & 50-pin connectors.

2026-04-16

Formatting updates throughout manual (non-technical changes); added data sheet link.

STATUS AND INTERRUPTS

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Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.

For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.

Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.

Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).

Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.

Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).

Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edge-triggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Interrupt Trigger Types

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

Dynamic and Latched Status Registers Examples

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

		No Clearing of Latched Status	Clearing of Latched Status (Edge-Triggered)	Clearing of Latched Status(Level-Triggered)
Time	Dynamic Status	Latched Status	Action	Latched Status	Action	Latched
T0	0x0	0x0	Read Latched Register	0x0	Read Latched Register	0x0
T1	0x1	0x1	Read Latched Register	0x1		0x1
T1	0x1	0x1	Write 0x1 to Latched Register		Write 0x1 to Latched Register
T1	0x1	0x1		*0x0*		*0x1*
T2	0x0	0x1	Read Latched Register	0x0	Read Latched Register	0x1
T2	0x0	0x1	Read Latched Register	0x0	Write 0x1 to Latched Register
T2	0x0	0x1	Read Latched Register	0x0		*0x0*
T3	0x2	0x3	Read Latched Register	0x2	Read Latched Register	0x2
T3	0x2	0x3	Write 0x2 to Latched Register		Write 0x2 to Latched Register
T3	0x2	0x3		*0x0*		*0x2*
T4	0x2	0x3	Read Latched Register	0x1	Read Latched Register	0x3
T4	0x2	0x3	Write 0x1 to Latched Register		Write 0x3 to Latched Register
T4	0x2	0x3		*0x0*		*0x2*
T5	0xC	0xF	Read Latched Register	0xC	Read Latched Register	0xE
T5	0xC	0xF	Write 0xC to Latched Register		Write 0xE to Latched Register
T5	0xC	0xF		*0x0*		*0xC*
T6	0xC	0xF	Read Latched Register	0x0	Read Latched	0xC
T6	0xC	0xF	Read Latched Register	0x0	Write 0xC to Latched Register
T6	0xC	0xF	Read Latched Register	0x0		*0xC*
T7	0x4	0xF	Read Latched Register	0x0	Read Latched Register	0xC
T7	0x4	0xF	Read Latched Register	0x0	Write 0xC to Latched Register
T7	0x4	0xF	Read Latched Register	0x0		*0x4*
T8	0x4	0xF	Read Latched Register	0x0	Read Latched Register	0x4

No Clearing of Latched Status

Clearing of Latched Status (Edge-Triggered)

Clearing of Latched Status(Level-Triggered)

Time

Dynamic Status

Latched Status

Action

Latched Status

Action

Latched

0x0

Read Latched Register

0x0

Read Latched Register

0x0

0x1

Read Latched Register

0x1

Write 0x1 to Latched Register

0x1

0x0

0x1

0x0

0x1

Read Latched Register

0x0

Read Latched Register

0x1

0x0

0x1

Read Latched Register

0x0

Write 0x1 to Latched Register

0x0

0x1

Read Latched Register

0x0

0x0

0x2

0x3

Read Latched Register

0x2

Read Latched Register

0x2

0x3

Write 0x2 to Latched Register

0x2

0x3

0x0

0x2

0x2

0x3

Read Latched Register

0x1

Read Latched Register

0x3

0x2

0x3

Write 0x1 to Latched Register

Write 0x3 to Latched Register

0x2

0x3

0x0

0x2

0xC

0xF

Read Latched Register

0xC

Read Latched Register

0xE

0xC

0xF

Write 0xC to Latched Register

Write 0xE to Latched Register

0xC

0xF

0x0

0xC

0xC

0xF

Read Latched Register

0x0

Read Latched

0xC

0xF

Read Latched Register

0x0

Write 0xC to Latched Register

0xC

0xF

Read Latched Register

0x0

0xC

0x4

0xF

Read Latched Register

0x0

Read Latched Register

0xC

0x4

0xF

Read Latched Register

0x0

Write 0xC to Latched Register

0x4

0xF

Read Latched Register

0x0

0x4

0x4

0xF

Read Latched Register

0x0

Read Latched Register

0x4

Interrupt Examples

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

Time

Latched Status (Edge-Triggered - Clear Multi-Channel)

Latched Status (Edge-Triggered - Clear Single Channel)

Latched Status (Level-Triggered - Clear Multi-Channel)

Action

Latched

Action

Latched

Action

Latched

T1 (Int 1)

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

T1 (Int 1)

Write 0x1 to Latched Register

T1 (Int 1)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T2.

0x1

T3 (Int 2)

Interrupt Generated Read Latched Registers

0x2

Interrupt Generated Read Latched Registers

0x2

Interrupt Generated Read Latched Registers

0x2

T3 (Int 2)

Write 0x2 to Latched Register

T3 (Int 2)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.

0x2

T4 (Int 3)

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x3

T4 (Int 3)

Write 0x1 to Latched Register

Write 0x3 to Latched Register

T4 (Int 3)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.

0x3

T4 (Int 3)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.

0x2

T6 (Int 4)

Interrupt Generated Read Latched Registers

0xC

Interrupt Generated Read Latched Registers

0xC

Interrupt Generated Read Latched Registers

0xE

T6 (Int 4)

Write 0xC to Latched Register

Write 0x4 to Latched Register

Write 0xE to Latched Register

T6 (Int 4)

0x0

Interrupt re-triggers Write 0x8 to Latched Register

0x8

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.

0xE

T6 (Int 4)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.

0xC

T6 (Int 4)

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.

0x4

REVISION HISTORY

Motherboard Manual - Status and Interrupts Revision History

Revision

Revision Date

Description

2021-11-30

C08896; Transition manual to docbuilder format - no technical info change.

DOCS.NAII REVISIONS

Revision Date

Description

2026-03-02

Formatting updates to document; no technical changes.

MODULE COMMON REGISTERS

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The registers described in this document are common to all NAI Generation 5 modules.

Module Information Registers

The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.

FPGA Version Registers

The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.

FPGA Revision

Function:

FPGA firmware revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the revision of the board’s FPGA

Operational Settings:

The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

FPGA Compile Timestamp

Function:

Compile Timestamp for the FPGA firmware.

Type:

unsigned binary word (32-bit)

Data Range:

N/A

Read/Write:

Initialized Value:

Value corresponding to the compile timestamp of the board’s FPGA

Operational Settings:

The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

day (5-bits)

month (4-bits)

year (6-bits)

D15

D14

D13

D12

D11

D10

hour (5-bits)

minutes (6-bits)

seconds (6-bits)

FPGA SerDes Revision

Function:

FPGA SerDes revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the SerDes revision of the board’s FPGA

Operational Settings:

The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

FPGA Template Revision

Function:

FPGA Template revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the template revision of the board’s FPGA

Operational Settings:

The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

FPGA Zynq Block Revision

Function:

FPGA Zynq Block revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the Zynq block revision of the board’s FPGA

Operational Settings:

The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

Bare Metal Version Registers

The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.

Bare Metal Revision

Function:

Bare Metal firmware revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the revision of the board’s Bare Metal

Operational Settings:

The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

Bare Metal Compile Time

Function:

Provides an ASCII representation of the Date/Time for the Bare Metal compile time.

Type:

24-character ASCII string - Six (6) unsigned binary word (32-bit)

Data Range:

N/A

Read/Write:

Initialized Value:

Value corresponding to the ASCII representation of the compile time of the board’s Bare Metal

Operational Settings:

The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Note	little-endian order of ASCII values

Word 1 (Ex. 0x2079614D)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Month ('y' - 0x79)

D15

D14

D13

D12

D11

D10

Month ('a' - 0x61)

Month ('M' - 0x4D)

Word 2 (Ex. 0x32203731)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Year ('2' - 0x32)

Space (0x20)

D15

D14

D13

D12

D11

D10

Day ('7' - 0x37)

Day ('1' - 0x31)

Word 3 (Ex. 0x20393130)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Year ('9' - 0x39)

D15

D14

D13

D12

D11

D10

Year ('1' - 0x31)

Year ('0' - 0x30)

Word 4 (Ex. 0x31207461)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Hour ('1' - 0x31)

Space (0x20)

D15

D14

D13

D12

D11

D10

'a' (0x74)

't' (0x61)

Word 5 (Ex. 0x38333A35)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Minute ('8' - 0x38)

Minute ('3' - 0x33)

D15

D14

D13

D12

D11

D10

':' (0x3A)

Hour ('5' - 0x35)

Word 6 (Ex. 0x0032333A)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

NULL (0x00)

Seconds ('2' - 0x32)

D15

D14

D13

D12

D11

D10

Seconds ('3' - 0x33)

':' (0x3A)

FSBL Version Registers

The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).

FSBL Revision

Function:

FSBL firmware revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the revision of the board’s FSBL

Operational Settings:

The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

FSBL Compile Time

Function:

Provides an ASCII representation of the Date/Time for the FSBL compile time.

Type:

24-character ASCII string - Six (6) unsigned binary word (32-bit)

Data Range:

N/A

Read/Write:

Initialized Value:

Value corresponding to the ASCII representation of the Compile Time of the board’s FSBL

Operational Settings:

The six 32-bit words provide an ASCII representation of the Date/Time.

The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Note	little-endian order of ASCII values

Word 1 (Ex. 0x2079614D)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Month ('y' - 0x79)

D15

D14

D13

D12

D11

D10

Month ('a' - 0x61)

Month ('M' - 0x4D)

Word 2 (Ex. 0x32203731)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Year ('2' - 0x32)

Space (0x20)

D15

D14

D13

D12

D11

D10

Day ('7' - 0x37)

Day ('1' - 0x31)

Word 3 (Ex. 0x20393130)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Year ('9' - 0x39)

D15

D14

D13

D12

D11

D10

Year ('1' - 0x31)

Year ('0' - 0x30)

Word 4 (Ex. 0x31207461)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Hour ('1' - 0x31)

Space (0x20)

D15

D14

D13

D12

D11

D10

'a' (0x74)

't' (0x61)

Word 5 (Ex. 0x38333A35)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Minute ('8' - 0x38)

Minute ('3' - 0x33)

D15

D14

D13

D12

D11

D10

':' (0x3A)

Hour ('5' - 0x35)

Word 6 (Ex. 0x0032333A)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

NULL (0x00)

Seconds ('2' - 0x32)

D15

D14

D13

D12

D11

D10

Seconds ('3' - 0x33)

':' (0x3A)

Module Serial Number Registers

The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.

Interface Board Serial Number

Function:

Unique 128-bit identifier used to identify the interface board.

Type:

16-character ASCII string - Four (4) unsigned binary words (32-bit)

Data Range:

N/A

Read/Write:

Initialized Value:

Serial number of the interface board

Operational Settings:

This register is for information purposes only.

Functional Board Serial Number

Function:

Unique 128-bit identifier used to identify the functional board.

Type:

16-character ASCII string - Four (4) unsigned binary words (32-bit)

Data Range:

N/A

Read/Write:

Initialized Value:

Serial number of the functional board

Operational Settings:

This register is for information purposes only.

Module Capability

Function:

Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0x0000 0107

Read/Write:

Initialized Value:

0x0000 0107

Operational Settings:

A “1” in the bit associated with the capability indicates that it is supported.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	Flt-Pt	0	0	0	0	0	Pack	FIFO Blk	Blk

Module Memory Map Revision

Function:

Module Memory Map revision

Type:

unsigned binary word (32-bit)

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Value corresponding to the Module Memory Map Revision

Operational Settings:

The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

Minor Revision Number

Module Measurement Registers

The registers in this section provide module temperature measurement information.

Temperature Readings Registers

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.

Interface Board Current Temperature

Function:

Measured PCB and Zynq Core temperatures on Interface Board.

Type:

signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range:

0x0000 0000 to 0x0000 FFFF

Read/Write:

Initialized Value:

Value corresponding to the measured PCB and Zynq core temperatures based on the table below

Operational Settings:

The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

PCB Temperature

Zynq Core Temperature

Functional Board Current Temperature

Function:

Measured PCB temperature on Functional Board.

Type:

signed byte (8-bits) for PCB

Data Range:

0x0000 0000 to 0x0000 00FF

Read/Write:

Initialized Value:

Value corresponding to the measured PCB on the table below

Operational Settings:

The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Interface Board Maximum Temperature

Function:

Maximum PCB and Zynq Core temperatures on Interface Board since power-on.

Type:

signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range:

0x0000 0000 to 0x0000 FFFF

Read/Write:

Initialized Value:

Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below

Operational Settings:

The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

PCB Temperature

Zynq Core Temperature

Interface Board Minimum Temperature

Function:

Minimum PCB and Zynq Core temperatures on Interface Board since power-on.

Type:

signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range:

0x0000 0000 to 0x0000 FFFF

Read/Write:

Initialized Value:

Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below

Operational Settings:

The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

PCB Temperature

Zynq Core Temperature

Functional Board Maximum Temperature

Function:

Maximum PCB temperature on Functional Board since power-on.

Type:

signed byte (8-bits) for PCB

Data Range:

0x0000 0000 to 0x0000 00FF

Read/Write:

Initialized Value:

Value corresponding to the measured PCB on the table below

Operational Settings:

The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Functional Board Minimum Temperature

Function:

Minimum PCB temperature on Functional Board since power-on.

Type:

signed byte (8-bits) for PCB

Data Range:

0x0000 0000 to 0x0000 00FF

Read/Write:

Initialized Value:

Value corresponding to the measured PCB on the table below

Operational Settings:

The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Higher Precision Temperature Readings Registers

These registers provide higher precision readings of the current Zynq and PCB temperatures.

Higher Precision Zynq Core Temperature

Function:

Higher precision measured Zynq Core temperature on Interface Board.

Type:

signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Measured Zynq Core temperature on Interface Board

Operational Settings:

The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

Fractional Part of Temperature

Higher Precision Interface PCB Temperature

Function:

Higher precision measured Interface PCB temperature.

Type:

signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Measured Interface PCB temperature

Operational Settings:

The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

Fractional Part of Temperature

Higher Precision Functional PCB Temperature

Function:

Higher precision measured Functional PCB temperature.

Type:

signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range:

0x0000 0000 to 0xFFFF FFFF

Read/Write:

Initialized Value:

Measured Functional PCB temperature

Operational Settings:

The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

Fractional Part of Temperature

Module Health Monitoring Registers

The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.

Module Sensor Summary Status

Function:

The corresponding sensor bit is set if the sensor has crossed any of its thresholds.

Type:

unsigned binary word (32-bits)

Data Range:

See table below

Read/Write:

Initialized Value:

Operational Settings:

This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.

Bit(s)

Sensor

D31:D6

Reserved

Functional Board PCB Temperature

Interface Board PCB Temperature

D3:D0

Reserved

Module Sensor Registers

The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.

Sensor Threshold Status

Function:

Reflects which threshold has been crossed

Type:

unsigned binary word (32-bits)

Data Range:

See table below

Read/Write:

Initialized Value:

Operational Settings:

The associated bit is set when the sensor reading exceed the corresponding threshold settings.

Bit(s)

Description

D31:D4

Reserved

Exceeded Upper Critical Threshold

Exceeded Upper Warning Threshold

Exceeded Lower Critical Threshold

Exceeded Lower Warning Threshold

Sensor Current Reading

Function:

Reflects current reading of temperature sensor

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

Initialized Value:

N/A

Operational Settings:

The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Minimum Reading

Function:

Reflects minimum value of temperature sensor since power up

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

Initialized Value:

N/A

Operational Settings:

The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Maximum Reading

Function:

Reflects maximum value of temperature sensor since power up

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

Initialized Value:

N/A

Operational Settings:

The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Lower Warning Threshold

Function:

Reflects lower warning threshold of temperature sensor

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

Default lower warning threshold (value dependent on specific sensor)

Operational Settings:

The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.

Sensor Lower Critical Threshold

Function:

Reflects lower critical threshold of temperature sensor

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

Default lower critical threshold (value dependent on specific sensor)

Operational Settings:

The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.

Sensor Upper Warning Threshold

Function:

Reflects upper warning threshold of temperature sensor

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

Default upper warning threshold (value dependent on specific sensor)

Operational Settings:

The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.

Sensor Upper Critical Threshold

Function:

Reflects upper critical threshold of temperature sensor

Type:

Single Precision Floating Point Value (IEEE-754)

Data Range:

Single Precision Floating Point Value (IEEE-754)

Read/Write:

R/W

Initialized Value:

Default upper critical threshold (value dependent on specific sensor)

Operational Settings:

The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.

FUNCTION REGISTER MAP

KEY

Configuration/Control

Measurement/Status/Board Information

MODULE INFORMATION REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x003C

FPGA Revision

0x0074

Bare Metal Revision

0x0030

FPGA Compile Timestamp

0x0080

Bare Metal Compile Time (Bit 0-31)

0x0034

FPGA SerDes Revision

0x0084

Bare Metal Compile Time (Bit 32-63)

0x0038

FPGA Template Revision

0x0088

Bare Metal Compile Time (Bit 64-95)

0x0040

FPGA Zynq Block Revision

0x008C

Bare Metal Compile Time (Bit 96-127)

0x0090

Bare Metal Compile Time (Bit 128-159)

0x0094

Bare Metal Compile Time (Bit 160-191)

0x007C

FSBL Revision

0x00B0

FSBL Compile Time (Bit 0-31)

0x00B4

FSBL Compile Time (Bit 32-63)

0x00B8

FSBL Compile Time (Bit 64-95)

0x00BC

FSBL Compile Time (Bit 96-127)

0x00C0

FSBL Compile Time (Bit 128-159)

0x00C4

FSBL Compile Time (Bit 160-191)

0x0000

Interface Board Serial Number (Bit 0-31)

0x0010

Functional Board Serial Number (Bit 0-31)

0x0034

Interface Board Serial Number (Bit 32-63)

0x0014

Functional Board Serial Number (Bit 32-63)

0x0008

Interface Board Serial Number (Bit 64-95)

0x0018

Functional Board Serial Number (Bit 64-95)

0x000C

Interface Board Serial Number (Bit 96-127)

0x001C

Functional Board Serial Number (Bit 96-127)

0x0070

Module Capability

0x01FC

Module Memory Map Revision

MODULE MEASUREMENTS REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x0200

Interface Board PCB/Zynq Current Temp

0x0208

Functional Board PCB Current Temp

0x0218

Interface Board PCB/Zynq Max Temp

0x0228

Functional Board PCB Max Temp

0x0220

Interface Board PCB/Zynq Min Temp

0x0230

Functional Board PCB Min Temp

0x02C0

Higher Precision Zynq Core Temperature

0x02C4

Higher Precision Interface PCB Temperature

0x02E0

Higher Precision Functional PCB Temperature

MODULE HEALTH MONITORING REGISTERS

OFFSET

REGISTER NAME

ACCESS

OFFSET

REGISTER NAME

ACCESS

0x07F8

Module Sensor Summary Status

Module Sensor Registers Memory Map

REVISION HISTORY

Motherboard Manual - Module Common Registers Revision History

Revision

Revision Date

Description

2023-08-11

ECO C10649, initial release of module common registers manual.

2024-05-15

ECO C11522, removed Zynq Core/Aux/DDR Voltage register descriptions from Module Measurement Registers. Pg.16, updated Module Sensor Summary Status register to add PS references; updated Bit Table to change voltage/current bits to 'reserved'. Pg.16, updated Module/Power Supply Sensor Registers description to better describe register functionality and to add figure. Pg.17, added 'Exceeded' to threshold bit descriptions. Pg.17-18, removed voltage/current references from sensor descriptions. Pg.20, removed Zynq Core/Aux/DDR Voltage register offsets from Module Measurement Registers. Pg.20, updated Module Health Monitoring Registers offset tables.

2024-07-10

ECO C11701, pg.16, updated Module Sensor Summary Status register to remove PS references;updated Bit Table to change PS temperature bits to 'reserved'. Pg.16, updated Module SensorRegisters description to remove PS references. Pg.20, updated Module Health MonitoringRegisters offset tables to remove PS temperature register offsets.

DOCS.NAII REVISIONS

Revision Date

Description

2025-11-05

Corrected register offsets for Interface Board Min Temp and Function Board Min & Max Temps.

2026-03-02

Formatting updates to document; no technical changes.

NAI Cares

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D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	All

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	All

CD1 Manual

Table of Contents

Integrator Resources

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	All