Function: Programs reference frequency for each channel.

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: AC1:47 to 10kHz, AC2: 47 to 20kHz, AC3: 47 to 2.5kHz

Enable Floating Point Mode: 0 (Integer Mode) AC1: 0x0000 125C to 0x000F 4240, AC2: 0x0000 125C to 0x001E 8480, AC3: 0x0000 125C to 0x0003 D090

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: 47 Hz

Operational Settings:

Integer Mode: LSB is 0.01 Hz. For example: to program 400 Hz, 400 / 0.01 = 40000. (binary equivalent for 40000 is 0x0000 9C40).

Floating Point Mode: Set value as Single Precision Floating Point Value (IEEE-754). For example, to program 400 Hz, enter 400 as Single Precision Floating Point Value (IEEE-754) (binary equivalent 400 is 0x43C8 0000).

Reference Frequency (Enable Floating Point Mode: Integer Mode)

Reference Frequency (Enable Floating Point Mode: Floating Point Mode)

Function: Program Reference Voltage for each channel.

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: AC1: 2.0 to 115Vrms, AC2: 2.0 to 28.0Vrms, AC3: 28.0 to 115Vrms

Enable Floating Point Mode: 0 (Integer Mode) AC1: 0x0000 00C8 to 0x0000 2CEC, AC2: 0x0000 00C8 to 0x0000 0AF0, AC3: 0x0000 0AF0 to 0x0000 2CEC

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: 2 V

Operational Settings:

Integer Mode: LSB is 0.01 VRMS. For example: to program 26.1 VRMS, 26.1 / 0.01 = 2610 (binary equivalent for 2610 is 0x0000 0A32).

Floating Point Mode: Set Single Precision Floating Point Value (IEEE-754) for reference frequency. For example, to program 26.1 V, enter 26.1 as Single Precision Floating Point Value (IEEE-754) (binary equivalent for 26.1 is 0x41D0 CCCD).

Reference Voltage (Enable Integer Mode: Integer Mode)

Reference Voltage (Enable Floating Point Mode: Floating Point Mode)

Function: Read Voltage for each channel.

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: N/A Enable Floating Point Mode: 0 (Integer Mode) 0x0000 0000 to 0x0000 0AF0

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings:

Integer Mode: LSB is 0.01 VRMS. If the register value is 2610 (binary equivalent for this value is 0x0000 0A32), conversion to the voltage value is 2610 * 0.01 = 26.1 V.

Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754). For example, the binary equivalent for 0x41D0 CCCD is 26.1 which represent 26.1 V.

Voltage Reading (Enable Floating Point Mode: Integer Mode)

Voltage Reading (Enable Floating Point Mode: Floating Point Mode)

Function: Read Current for each channel

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

Enable Floating Point Mode: 0 (Integer Mode) (Actual current * 100)

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings:

Integer Mode: LSB is .01 mA. If the register value is 10 (binary equivalent for this value is 0x0000 000A), conversion to the current value is 10 * .01 = .10 mA.

Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754). For example, the binary equivalent for 0x4120 0000 is 10.0 which represent 10 mA.

Current Reading (Enable Floating Point Mode: Integer Mode)

Current Reading (Enable Floating Point Mode: Floating Point Mode)

Function: Read Frequency for each channel

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

Enable Floating Point Mode: 0 (Integer Mode) (Actual Frequency * 100)

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings:

Integer Mode: LSB is 0.01 Hz. If the register value is 40000 (binary equivalent for this value is 0x0000 9C40), conversion to the hertz value is 40000 * 0.01 = 400 Hz.

Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754). For example, the binary equivalent for 0x43C8 0000 is 400 which represent 400 Hz.

Frequency Reading (Enable Floating Point Mode: Integer Mode)

Frequency Reading (Enable Floating Point Mode: Floating Point Mode)

Function: Set the Current Limit for each channel

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

Enable Floating Point Mode: 0 (Integer Mode) (Current limit to the nearest milliamp)

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: N/A

Operational Settings: Set the current limit for the channel in mA

Integer Mode: LSB is 1.0 mA. For example: to program 100 mA, 100 x 1.0= 100 (binary equivalent for this value is 0x0000 0064).

Floating Point Mode: Set as Single Precision Floating Point Value (IEEE-754) for reference frequency. For example, to program 100 mA, enter 100.0 as Single Precision Floating Point Value (IEEE-754) (binary equivalent for 100.0 is 0x42C8 0000).

Current Limit (Enable Floating Point Mode: Integer Mode)

Current Limit (Enable Floating Point Mode: Floating Point Mode)

Function: Enable for each channel

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: R/W

Initialized Value: 0

Operational Settings: Writing a 1 to this register turns on the channel. Writing a 0 to this register turns off the channel.

Channel Enable

Function: Reset overcurrent for each channel

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: R/W

Initialized Value: 0

Operational Settings: The Reset Overcurrent register will be set to 0. To re-enable the overcurrent protection circuit, write a 1 to the Reset Overcurrent register. The firmware will write a 0 when the overcurrent reset is complete

Reset Overcurrent

Function: Sets BIT Threshold value (in milliseconds) to use for all channels for BIT failure indication.

Type: unsigned binary word (32-bit)

Data Range: 1 ms to TBD

Read/Write: R/W

Initialized Value: TBD

Operational Settings: The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module.

Function: Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0003

Read/Write: W

Initialized Value: 0

Operational Settings: Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.

Reset BIT

Function: Sets all channels for floating point mode or integer module.

Type: unsigned binary word (32-bit)

Data Range: 0 to 1

Read/Write: R/W

Initialized Value: 0

Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode. Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

Enable Floating Point Mode

Function: Indicates whether the module’s internal processing is converting the register values and internal values to the binary representation of the mode selected (Integer or Floating Point).

Type: unsigned binary word (32-bit)

Data Range: 0 to 1

Read/Write: R

Initialized Value: 0

Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

Floating Point State

Function: Determines whether to update the status for the channels. This feature can be used to “mask” status bits of unused channels in status registers that are bitmapped by channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0FFF (Channel Status)

Read/Write: R/W

Initialized Value: 0x0000 0FFF

Operational Settings: When the bit corresponding to a given channel in the Channel Status Enabled register is not enabled (0) the status will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status and Summary Status). Note, Background BIT will continue to run even if the Channel Status Enabled is set to ‘0'.

Channel Status Enabled

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The BIT Status register will indicate an error when the voltage read is not within the error of the set value.

BIT Dynamic Status BIT Latched Status BIT Interrupt Enable BIT Set Edge/Level Interrupt

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0003

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the Reference Channel Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The Reference Channel Status register will indicate an error for the conditions shown in the table below:

Description

Reference Channel Dynamic Status Reference Channel Latched Status Reference Channel Interrupt Enable Reference Channel Edge/Level Interrupt

Function: Sets the corresponding bits associated with a channel’s Overcurrent, Voltage or Frequency out-ofspecification error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0007

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status and Interrupt Descriptions.

There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Summary Status Dynamic Status Summary Status Latched Status Summary Status Interrupt Enable Summary Status Set Edge/Level Interrupt

Function: Sets the corresponding bit when a fault is detected for BIT or any error condition that is set in the Reference Channel Status (Overcurrent, Voltage out-of-spec, and Frequency out-of-spec) on that channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0003

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

The User Watchdog Timer (UWDT) Capability is available on the following modules:

The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.

The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:

A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.

The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.

The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.

Figure 1. User Watchdog Timer Overview

Figure 2. User Watchdog Timer Example

Figure 3. User Watchdog Timer Failures

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

Key

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.