Rugged Xilinx Zynq System Board

NIU3A DATA SHEET

INTRODUCTION

This manual provides information about the North Atlantic Industries, Inc. (NAI) NIU3A System. The NIU3A is a “Nano Interface Unit”; self-contained Multifunction I/O System preconfigured with 24-CH programmable Discrete I/O, 8-CH ARINC 429/575, 4-CH CANBus and 2-CH MIL-STD-1553 functions. The NIU3A can also be configured with up to three additional smart Configurable Open Systems Architecture™ (COSA®) function modules. The NIU3A boasts a dual ARM ®Cortex®-A53 processor for customer application and I/O and communications management.

SOFTWARE SUPPORT

The ENAIBL Software Support Kit (SSK) is supplied with all system platform based board level products. This platform’s SSK contents include html format help documentation which defines board specific library functions and their respective parameter requirements. A board specific library and its source code is provided (module level ‘C' and header files) to facilitate function implementation independent of user operating system (O/S). Portability files are provided to identify Board Support Package (BSP) dependent functions and help port code to other common system BSPs. With the use of the provided help documentation, these libraries are easily ported to any 32-bit O/S such as RTOS or Linux.

The latest version of a board specific SSK can be downloaded from our website www.naii.com in the software downloads section. A Quick-Start Software Manual is also available for download where the SSK contents are detailed, Quick-Start Instructions provided and GUI applications are described therein. For other operating system support, contact factory.

CONVENTIONS USED IN THIS MANUAL

Note	An operating procedure, practice, or condition, etc., that is essential to emphasize.

All numbers are expressed in decimal format unless otherwise noted.

Website

http://www.naii.com/

GENERAL SAFETY NOTICES

The following general safety notices supplement the specific warnings and cautions appearing elsewhere in the manual. They are recommended precautions that must be understood and applied during operation and maintenance of the instrument covered herein.

Death or serious injury may result if personnel fail to observe safety precautions. Dependent on configuration, some modules (e.g. Synchro / Resolver or AC signal sources) can generate output signals with high voltages. Be careful not to contact high-voltage connections when installing, operating or maintaining this instrument.

The NIU3A is delivered as a standalone system with no accessible or serviceable parts.

Repair

DO NOT ATTEMPT REPAIR. Under no circumstances should repair of this instrument be attempted. All repairs to this chassis must be accomplished at the factory.

High Voltage

HIGH VOLTAGE may be used in the operation of this equipment.

Input Power Always On

Note	The design of the model NIU3A is such that DC input power is continuously supplied to internal circuits when connected to a main power source. To disconnect the NIU3A from external power, the external power source should first be de-energized. The power input cable can then be disconnected.

SYSTEM SPECIFICATIONS & DETAILS

Introduction

The Nano Interface Unit (NIU3A) is a second-generation, integrated, compact, “nano-sized” subsystem with unprecedented I/O capability configurations. The NIU3A connects to existing platform Ethernet networks, making data available to any system on the network. Additionally, the NIU3A is delivered with ARM® Cortex®-A53 access support for standalone or other processor related capability. The NIU3A easily adds sensor data acquisition and distribution and communication interfaces to mission computers without expensive chassis and backplane redesign. It has been designed with rugged embedded industrial, military and aerospace applications in mind. Leveraging NAI’s field-proven, unique modular architecture, the NIU3A supports a wide selection of different Intelligent I/O, motion simulation/measurement and communications functions such as:

A/D Converter

D/A Converter

I/O TTL/CMOS

RTD

I/O Discrete

I/O Differential Transceiver

Synchro/Resolver LVDT/RVDT Measurement

Synchro/Resolver LVDT/RVDT Simulation

Strain Gage

Encoder

Dual-Channel Dual Redundant BC/RT/MT MIL-STD-1553

High-Speed Sync/Async RS232/422/423/485

ARINC 429/575

CANBus

I/O Relay

AC Reference

Ethernet Switch

SSD/Flash

This approach provides unprecedented flexibility for supporting existing or new applications where there are specific interfacing requirements.

Significant application benefits include:

Independent (pre-processed) I/O functionality targeted to specific data acquisition/control areas
Additional capabilities, technology insertion and sensor interfacing to existing fielded applications
Minimal integration risk based on current field-proven, deployed technologies
Only ~ 7.2” x 5.5” x 3.2” @ ~5.4 lbs. (2.45 kg) conduction/convection cooled
2x Ethernet
- 10/100/1000Base-T (GbE) (default)

Objectives

This manual provides the user with basic hardware implementation and information regarding the operation and interface of the NIU3A. Each NIU3A is fitted with one, two or three function modules, four embedded module functions, dual-core processor and an integrated motherboard, power supply unit (PSU) and interface connectors.

Scope

This manual covers the basic operation of the NIU3A as a standalone I/O subsystem with pertinent/specific details relating to the operation/communications from/to the NIU3A with the available function module(s) fitted within the NIU3A.

ON BOARD RESOURCES

Memory

DDR4 SDRAM

The NIU3A provides a total of 8 GB of ECC DDR4 memory. This memory is organized as 4 1Gb x 16 MT40A1G16RC devices (parts may vary), with a fifth device providing storage for ECC data. The Ultrascale+™ has an on chip 64-bit DDR4 memory controller. The controller has full ECC error-correction support, with the ability to detect multi-bit errors and correct single-bit errors within a nibble. Please consult the Micron data sheet for DDR4 device specific details.

NOR Flash

Connected through the local bus, the NIU3A supports 2 x 2 gigabytes of flash. The Flash consists of a stacked (four 512Mb die) Micron® Flash MT25QL02GCBB8E12-0SIT device. Flash features a high-speed SPI-compatible bus interface that utilizes dual QSPI via a two-input logic gate to increase I/O throughput rates four times for each device. The NOR Flash has an erase capacity of 100,000 cycles per sector and typical data retention of 20 years.

FRAM

The FM24CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. The ferroelectric random-access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years. The NIU3A FRAM 64K bits are organized as 8,192 x 8 bits random access memory, connected to the Ultrascale+™ CPU through the I2C controller.

SATA

The Ultrascale+™ CPU is directly connected to an onboard Solid-State Drive (SSD). The SSD contains a single level cell NAND Flash together with a controller in a single Multi-Chip package. The Multi-Chip packaged device is soldered directly to the printed circuit board for reliable electrical and mechanical connection.

The SSD has an internal write protect signal SATA_WP. The SATA_WP signal must be connected or switched to ground to enable any write to the SSD. The SATA_WP signal is pulled up on card by a 4.7 KΩ resistor to the internal 3.3 V supply.

The onboard SATA drive conforms to the follow specifications:

Complies with Serial ATA 2.5 Specification
Supports speeds: 1.5 Gbps (first-generation SATA), 3 Gbps (second-generation SATA and eSATA)
Supports advanced technology attachment packet interface (ATAPI) devices
Contains high-speed descriptor-based DMA controller
Supports native command queuing (NCQ) commands

The standard ordering code for the NIU3A includes a 32GB SSD drive. Larger devices are available; please consult the factory for availability.

Peripheral I/O

Ethernet

The NIU3A supports two 10/100/1000Base-TX Ethernet connections using two Marvell Alaska 88E1512 Ethernet PHY devices and the Xilinx Gigabit Ethernet MACs. The PHY-to-MAC interface employs a Reduced Gigabit Media Independent Interface (RGIII) connection using four data lines at 250 Mbps each for a connection speed of 1 Gbps. The NIU3A contains internal magnetics and can directly drive copper CAT5e or CAT6 twisted pairs.

The NIU3A Ethernet ports support:

Detection and correction of pair swaps (MDI crossover), and pair polarity
MAC-side and line-side loopback
Auto-negotiation

Ethernet Port 1 can be routed as 10/100/1000Base-TX Ethernet as a build option.

Ethernet Port 2 can be routed as 10/100/1000Base-TX Ethernet as a build option.

I/O pin outs can be found in the Pinout Details section of this document.

USB

The NIU3A supports one USB 2.0 port. Contact factory for availability.

USB0 is available on the NIU3A, on connector J2. The USB port can operate as a standalone host.

Compatible with USB specification, Rev. 2.0
Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
Supports operation as a standalone USB host controller
Supports USB root hub with one downstream-facing port
Enhanced host controller interface (EHCI)-compatible
One controller supports operation as a standalone USB device
Supports one upstream-facing port
Supports six programmable USB endpoints

I²C

I²C is a two-wire, bidirectional single ended serial bus that provides an efficient method of exchanging data between a master and slave device. The NIU3A has one I²C device for communicating with onboard devices, as shown in the table below.

Assignment

I²C addresses

Device

Onboard Devices

0x50

Security Manager

Onboard Devices

0x56

EEPROM

Onboard Devices

0x53

FRAM

Serial Port

The NIU3A has a single, asynchronous serial port. The interface uses a two-wire, TXD, RXD interface (system/power GND referenced). The SER-TXD and SER-RXD RS-232 signals are routed to J2 on the NIU3A.

Tamper Detect Interface and Action Circuit

NAI is developing an optional Tamper Detect Interface and Action Circuit for improved Security/Cybersecurity requirements. This circuit will offer FIPS 140-3 Level 3 Design Support, Crypto-Key Storage (with Battery-Backed RAM), Secure Boot and Anti-Tamper/Tamper Detect & Sanitize functions. For further information, please contact NAI.

Software Libraries/Associated Documents

NIU3A BSP Processor Module Library

The NIU3A Processor library package provides function interfaces to the on-module functionality. This package contains Help documentation (in html format) that explains all the functions available in the library. The package also contains the source code (*.h, *.c) files as well as the files needed to build the library using any of the supported operating systems. Example programs are also provided to demonstrate the usage of the libraries in typical applications of the module.

Associated Documents

Check the NAI website or contact factory for the latest downloads and documentation.

SPECIFICATIONS

The NIU3A is designed to meet the following general specifications.

General

Ethernet Data Transfer:

Data transfers within 1 ms (typical)

Input Voltage

18 to 36 VDC (28 VDC nominal)

Power (Base unit):

0.930 A (~26 W) @ 28 VDC nominal plus module(s) power (see specific module(s) specifications)

I/O Signal GND reference is isolated from main power source return and chassis.

Power/Heat Dissipation:

~30 watts (maximum) when properly mounted, with the thermal transfer mounting surface maintained at a temperature not to exceed 71°C.

Note: The total NIU3A power dissipation is dependent on the configuration of the modules fitted in the NIU3A.

Temperature, Operating:

-40°C to 71°C (conduction cooled - measured at primary thermal interface)

Temperature, Storage:

-55°C to 105°C

Size:

Depth: ~5.5" (139.7 mm)

Height: ~3.2" (81.3 mm)

Width: ~7.2” (182.9 mm)

Weight:

The weight of an NIU3A system is dependent on the configuration. The approximate weight of the NIU3A is based on the selection of the functional module(s). The approximate weight of a typical fully configured NIU3A (model #) is ~5.4 lbs. (2.45 kg).

Environmental

Environmental MIL-STD-810(F-H) (*1)

No.

Description

Procedure (for ref.)

Cycles (for ref.)

Table (for ref.)

Fig. (for ref.)

Comments

514

Random Vibe

Method 514.6, 0.1g2/Hz from 100 to 1K Hz., -3dB octave 5-100 Hz and -6dB 1K-2K Hz,(Operational)

514

Sinusoidal Vibe

TBD

501

Temp (High)

3 periods (@ 4 hrs. ea.) within 24 hrs. cycle at 71 ºC baseplate

502

Temp (Low)

3 periods (@ 4 hrs. ea.) within 24 hrs. cycle at -40 ºC baseplate

503

Temp (Shock)

3 x 1 hr. each hot & cold cycles (non-operational)

507

Humidity

507.5-7

507.5-IX

Cyclic high humidity (Cycle B2)

500

Altitude (50K)

n/a

10m/s to 50,000ft for 1 hr.

500

Altitude (70K)

n/a

10m/s to 70,000ft for 1 hr.

513

Acceleration

513.6-II

n/a

Carrier-based Aircraft (18g’s max)

516

Shock - Operating

516.6-I

n/a

40g’s, 3 pulses each ± X, Y, Z axis (total of 18 shock pulses)

516

Shock - Crash

516.6-I

n/a

75g’s, 3 pulses each ± X, Y, Z axis (total of 18 shock pulses)

Ingress Protection IEC 60529 (*1)

No.

Description

Procedure

Cycles

Table

Figure

Comments

IP54

Dust Protection

IP54

Water Splashing

IP65

Dust Tight

IP65

Water Jets

EMC/EMI

EMC / MIL-STD-461 (*1, * 2)

MIL-STD-461(G)

Method/Curve/Procedure

Comments

CE102

Conducted emissions, power leads, 30 Hz to 10 kHz.

CS101

Conducted emissions, power leads, 10 kHz to 10 MHz

CS106

Conducted susceptibility, power leads, 30 Hz to 150 kHz.

CS114

Conducted susceptibility, transients, power leads

CS115

Conducted susceptibility, bulk cable injection, 10 kHz to 200 MHz

CS116

Conducted susceptibility, bulk cable injection, impulse excitation

RE101

Conducted susceptibility, damped sinusoidal transients, cables and power leads, 10 kHz to 100 MHz

RE102

Radiated emissions, magnetic field, 30 Hz to 100 kHz.

RS101

Radiated emissions, electric field, 10 kHz to 18 GHz.

RS103

Radiated, susceptibility, magnetic field, 30 Hz – 100 kHz

Notes:

*1 – Designed to meet / Generic Test Reports (contact factory for availability).

*2 – Utilizing proper shielded cables and system practices.

Note	Specifications are subject to change without notice.

UNPACKING & INSPECTION

Figure 1. NIU3A

Unpacking

The NIU3A packing materials were designed specifically for transport protection of the NIU3A. When receiving the shipment container, inspect packaging for any evidence of physical damage. If damage is evident, it is recommended that the carrier agent is present when opening the shipping container. It is further recommended that all packing material is retained in the event the NIU3A needs to be shipped elsewhere.

System/Chassis Identification

An identification label, indicating part number, unique serial number, and Ethernet PHY MACs / default IP address(es) is affixed to the back of the system chassis.

Figure 2. Unit Identification

Inspection

Inspect the chassis and connectors to ensure that they were not damaged during transit.

MECHANICAL INTERFACE

Mechanical Description

The NIU3A is a rugged, aluminum, conduction-cooled system. It must be mounted to a cold plate. The system thermal management design considerations should ensure that the chassis thermal interface (NIU3A bottom surface) does not exceed 71°C. Mounting holes are provided on the chassis bottom housing flanges (as depicted). See the outline drawing below.

Mounting Requirements

The NIU3A is conduction cooled and must be mounted in accordance with the drawing. The OID provides recommended hardware, torque, cold-plate flatness and surface finish specifications, and thermal conductivity requirements.

Figure 3. NIU3A Outline Dimensions/Cold Plate Mounting Pattern (Reference Only)

Notes:

Unless otherwise specified, dimensions are in inches (mm); tolerances are:
- 2 PL DEC ±0.01; 3 PL DEC ±0.005
- FRACT ±1/64 (0.4); ANGLES ±1/2 (12.7)

Chassis (Earth) GND

Chassis ground point threaded insert location is on the connector side of the NIU3A as shown.

Figure 4. NIU3A Outline Dimensions/Chassis GND Location

Note	Chassis GND braid or equivalent to be secured by #6-32 screw/studs (with a depth of 0.3 inches) as end application requires. The NIU3A chassis is provided with #6-32 threaded insert only. The recommended torque for the NIU3A Chassis GND screw is 11 in-lbs. (125 N·cm)

CONNECTOR DESIGNATION & DESCRIPTION

The Power, I/O Interface and Ethernet connectors are located on the NIU3A front panel housing.

Figure 5. NIU3A (Front Panel Connector Placement)

Table 1. NIU3A Connector Designation and Description
Connector Designation	Description
J1	I/O Connector 1, Smart Module I/O Slot-1 & Slot-2
J2	2x GbE, Maintenance, Debug (RS-232, System Reset) & extended processor option signals (RS-232, Hardware SATA Write Protect)
J3	I/O Connector 2, Smart Module I/O Slot-3 & Onboard Discrete I/O
J4	I/O Connector 3, Onboard ARINC-429, MIL-SDT-1553 & CANBus
J5	Primary Power Connector, VDC

Connector Details and Pinout

Generic pinout. See module I/O section or contact factory regarding any special module I/O configuration.