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Latching and Non-Latching Relays

DATA SHEET

INTRODUCTION

As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurements and simulation, communications, Ethernet switch, and SBC functions. Our RY1 and RY2 smart function modules provide multichannel, signal switching capabilities up to 220 VDC / 250 VAC at 2 A maximum (cumulative maximum switching power 60 W / 62.5 VA per channel). These two mechanical relay-interface modules feature four individual, user single-pole, DPDT Form C (changeover/break-before-make type) relays (channels). Each channel has a common input terminal ©, a normally closed output terminal (N/C), and a normally open (N/O) output terminal. The channel either energizes or de-energizes the relays (close or open) so that the signal provided on © may be switched/directed to either the (N/C) or (N/O) terminals. This user manual is designed to help you get the most out of our Relay smart function modules.

RY1/RY2 Overview

NAI’s Relay Modules offer several features designed to suit a variety of system requirements, including:

Four Independent Relay Channels:

The Relay Modules come equipped with four independently controlled mechanical contact relay channels. This allows for flexibility in managing multiple electrical circuits simultaneously.

Non-Latching or Latching Options:

NAI’s Relay Modules provide both non-latching (RY1) and latching (RY2) options, which can be selected based on your specific requirements. Non-latching relays remain de-energized (or in the 'reset' position) until commanded to the 'set' position; if power is removed, they will return to the 'reset' position. Latching relays use magnetic latching to ensure that relays remain in the 'set' or 'reset' position even when power is removed.

Continuous Background Built-In-Test (BIT):

All channels have continuous background Built-In-Test (BIT), which provides real-time channel health to ensure reliable operation in mission-critical systems. This feature runs in the background and is transparent in normal operations.

Form-C, DPDT contacts:

Each channel on the module is equipped with Form-C, DPDT (Double Pole Double Throw) contacts. These contacts offer versatile switching capabilities, making them suitable for a wide range of applications. While physically 'double-pole' the module utilizes a single pole for relay functionality (the second set of Form-C contacts is dedicated to BIT functionality, ensuring that the relay channels maintain uninterrupted operation even during diagnostic checks).

PRINCIPLE OF OPERATION

This module provides four, individual, single-pole, Form C, DPDT (changeover/break-before-make type) relay I/O channels. The second set of pole contacts is used for Built-In-Test (BIT). Each channel has a common input terminal ©, a normally closed output terminal (N/C) and a normally open (N/O) output terminal. The channel is commanded to energize or de-energize the relays (close or open) so that the signal provided may be switched/directed to either the (N/C) or (N/O) terminals. Interrupts can be enabled/configured for each channel to indicate if a BIT fault (state of secondary set of contacts does not match command) occurs. Internal de-bounce circuits for each channel provide the required time delay to eliminate false signals resulting from contact bounce commonly experienced with mechanical relays and switches. The RY1 implements non-latching type relays. The relays utilized on the RY1 module power-on default remain de-energized or in the “reset position” until commanded to the “set” position. The contacts will then remain in the “set” position until commanded to the “reset” position or if power is removed from the card/module. The RY2 implements “latching” type relays. The relays on the RY2 module utilize magnetic latching to assure that once a relay channel is 'set' or 'reset' (even if power is removed from the card/module), the channel will remain at the last commanded position. Data is double buffered for immediate availability.

Automatic Background Built-In Test (BIT)/Diagnostic Capability

The module contains automatic background BIT testing that verifies channel processing from a secondary set of contacts (data read compared to write logic), and tests for relay state. Any discrepancy (or fault) triggers an Interrupt (if enabled) with the results available in status registers. The testing is totally transparent to the user, requires no external programming and has no effect on the operation of this card.

Status and Interrupts

The Relay Function Module provides registers that indicate faults or events. Refer to ”Status and Interrupts Module Manual” for the Principle of Operation description.

Module Common Registers

The Relay Function Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

REGISTER DESCRIPTIONS

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Control Registers

Set Position

Function: Sets relay as either normally closed ro normally open. Type: unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a logic level High (1) (set/closed) or Low (0) (reset/open) to associated channel bit, in 32-bit binary word, to toggle/command between the "set" or "reset" of the channel respectively.

Set Position
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
	0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2

BIT Induce

Function: Forces BIT to fail.

Type: unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a logic level High (1) to force BIT to fail by outputting a (0) to a Normally Open Contact. Write a logic level High (0) to force BIT to fail by outputting a (1) to a Normally Closed Contact.

BIT Induce
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Measurement Registers

Relay Type

Function: Indicates if relay is latching or not-latching type.

Type: unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: 0

Operational Settings: A non-latching relay is indicated in bit (D0) by a 0. A latching relay is indicated by a (1).

Relay Type
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Read Relay Position

Function: Indicates relay position, either closed or open.

Type: unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: N/A

Operational Settings: Reads the logic state of the relay channel. A 0 indicates Open and a (1) indicates Closed.

Read Relay Position
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Module Common Registers

Refer to “Module Common Registers Module Manual” for the register descriptions.

Status and Interrupt Registers

The Relay Module provides status registers for BIT.

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

BIT Dynamic Status
BIT Latched Status
BIT Interrupt Enable
BIT Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.

In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note	the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector

Function: Set an identifier for the interrupt.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering

Function: Sets where to direct the interrupt.

Type: unsigned binary word (32-bit)

Data Range: See table

Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME	1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)	2
Direct Interrupt to PCIe Bus	5
Direct Interrupt to cPCI Bus	6

FUNCTION REGISTER MAP

Key: Bold Italic = Configuration/Control

Bold Underline = Measurement/Status

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a '1' to a bit set to '1' will set the bit to '0').

Control Registers

0x1000

Set Position

R/W

0x1004

BIT Induce

R/W

Measurement Registers

0x1008

Relay Type

0x1018

Read Relay Type

Module Common Registers

Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map

Status Registers

BIT Status

0x0800

Dynamic Status

0x0804

Latched Status*

R/W

0x0808

Interrupt Enable

R/W

0x080C

Set Edge/Level Interrupt

R/W

Interrupt Registers

The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.

0x0500

Module 1 Interrupt Vector 1 - BIT

R/W

0x0504 to 0x057C

Module 1 Interrupt Vector 2-32 - Reserved

R/W

0x0600

Module 1 Interrupt Steering 1 - BIT

R/W

0x0604 to 0x067C

Module 1 Interrupt Steering 2-32 - Reserved

R/W

0x0700

Module 2 Interrupt Vector 1 - BIT

R/W

0x0704 to 0x077C

Module 2 Interrupt Vector 2-32 - Reserved

R/W

0x0800

Module 2 Interrupt Steering 1 - BIT

R/W

0x0804 to 0x087C

Module 2 Interrupt Steering 2-32 - Reserved

R/W

0x0900

*_Module 3 Interrupt Vector 1 - BIT

R/W

0x0904 to 0x097C

Module 3 Interrupt Vector 2-32 - Reserved

R/W

0x0A00

*_Module 3 Interrupt Steering 1 - BIT

R/W

0x0A04 to 0x0A7C

Module 3 Interrupt Steering 2-32 - Reserved

R/W

0x0B00

*_Module 4 Interrupt Vector 1 - BIT

R/W

0x0B04 to 0x0B7C

Module 4 Interrupt Vector 2-32 - Reserved

R/W

0x0C00

*_Module 4 Interrupt Steering 1 - BIT

R/W

0x0C04 to 0x0C7C

Module 4 Interrupt Steering 2-32 - Reserved

R/W

0x0D00

*_Module 5 Interrupt Vector 1 - BIT

R/W

0x0D04 to 0x0D7C

Module 6 Interrupt Vector 2-32 - Reserved

R/W

0x0E00

*_Module 5 Interrupt Steering 1 - BIT

R/W

0x0E04 to 0x0E7C

Module 5 Interrupt Steering 2-32 - Reserved

R/W

0x1000

*_Module 6 Interrupt Steering 1 - BIT

R/W

0x1004 to 0x107C

Module 6 Interrupt Steering 2-32 - Reserved

R/W

APPENDIX: PIN-OUT DETAILS

Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals.

Module Signal

(Ref Only)

4-Channel Relay

(RY1/RY2)

DATIO1

COM-CH1

DATIO2

COM-CH1

DATIO3

COM-CH1

DATIO4

COM-CH1

DATIO5

NO-CH1

DATIO6

NC-CH1

DATIO7

COM-CH2

DATIO8

COM-CH2

DATIO9

COM-CH2

DATIO10

COM-CH2

DATIO11

NO-CH2

DATIO12

NC-CH2

DATIO13

COM-CH3

DATIO14

COM-CH3

DATIO15

COM-CH3

DATIO16

COM-CH3

DATIO17

NO-CH3

DATIO18

NC-CH3

DATIO19

COM-CH4

DATIO20

COM-CH4

DATIO21

COM-CH4

DATIO22

COM-CH4

DATIO23

NO-CH4

DATIO24

NC-CH4

DATIO25

DATIO26

DATIO27

DATIO28

DATIO29

DATIO30

DATIO31

DATIO32

DATIO33

DATIO34

DATIO35

DATIO36

DATIO37

DATIO38

DATIO39

DATIO40

STATUS AND INTERRUPTS

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Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.

For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.

Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.

Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).

Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.

Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).

Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edgetriggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Interrupt Trigger Types

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

Dynamic and Latched Status Registers Examples

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

No Clearing of Latched Status

Clearing of Latched Status (Edge-Triggered)

Clearing of Latched Status (Level-Triggered)

Time

Dynamic Status

Latched Status

Action

Latched Status

Action

Latched

0x0

Read Latched Register

0x0

Read Latched Register

0x0

0x1

Read Latched Register

0x1

Write 0x1 to Latched Register

0x0

0x1

0x0

0x1

Read Latched Register

0x0

Read Latched Register

0x1

Write 0x1 to Latched Register

0x0

0x2

0x3

Read Latched Register

0x2

Read Latched Register

0x2

Write 0x2 to Latched Register

0x0

0x2

0x2

0x3

Read Latched Register

0x1

Read Latched Register

0x3

Write 0x1 to Latched Register

Write 0x3 to Latched Register

0x0

0x2

0xC

0xF

Read Latched Register

0xC

Read Latched Register

0xE

Write 0xC to Latched Register

Write 0xE to Latched Register

0x0

0xC

0xC

0xF

Read Latched Register

0x0

Read Latched

0xC

Write 0xC to Latched Register

0xC

0x4

0xF

Read Latched Register

0x0

Read Latched Register

0xC

Write 0xC to Latched Register

0x4

0x4

0xF

Read Latched Register

0x0

Read Latched Register

0x4

Interrupt Examples

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

Time

Latched Status (Edge-Triggered – Clear Multi-Channel)

Latched Status (Edge-Triggered – Clear Single Channel)

Latched Status (Level-Triggered – Clear Multi-Channel)

Action

Latched

Action

Latched

Action

Latched

T1 (Int 1)

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Write 0x1 to Latched Register

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T2.

0x1

T3 (Int 2)

Interrupt Generated Read Latched Registers

0x2

Interrupt Generated Read Latched Registers

0x2

Interrupt Generated Read Latched Registers

0x2

Write 0x2 to Latched Register

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.

0x2

T4 (Int 3)

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x1

Interrupt Generated Read Latched Registers

0x3

Write 0x1 to Latched Register

Write 0x3 to Latched Register

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.

0x3

Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.

0x2

T6 (Int 4)

Interrupt Generated Read Latched Registers

0xC

Interrupt Generated Read Latched Registers

0xC

Interrupt Generated Read Latched Registers

0xE

Write 0xC to Latched Register

Write 0x4 to Latched Register

Write 0xE to Latched Register

0x0

Interrupt re-triggers Write 0x8 to Latched Register

0x8

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.

0xE

0x0

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.

0xC

Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.

0x4

MODULE COMMON REGISTERS

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The registers described in this document are common to all NAI Generation 5 modules.

Module Information Registers

The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.

FPGA Version Registers

The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.

FPGA Revision

Function: FPGA firmware revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the revision of the board’s FPGA

Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

Table 1. FPGA Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

FPGA Compile Timestamp

Function: Compile Timestamp for the FPGA firmware.

Type: unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: Value corresponding to the compile timestamp of the board’s FPGA

Operational Settings: The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:

Table 2. FPGA Compile Timestamp
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
day (5-bits)					month (4-bits)				year (6-bits)						hr
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
hour (5-bits)				minutes (6-bits)						seconds (6-bits)

FPGA SerDes Revision

Function: FPGA SerDes revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the SerDes revision of the board’s FPGA

Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

Table 3. FPGA SerDes Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

FPGA Template Revision

Function: FPGA Template revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the template revision of the board’s FPGA

Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

Table 4. FPGA Template Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

FPGA Zynq Block Revision

Function: FPGA Zynq Block revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the Zynq block revision of the board’s FPGA

Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

Table 5. FPGA Zynq Block Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

Bare Metal Version Registers

The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.

Bare Metal Revision

Function: Bare Metal firmware revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the revision of the board’s Bare Metal

Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

Table 6. Bare Metal Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

Bare Metal Compile Time

Function: Provides an ASCII representation of the Date/Time for the Bare Metal compile time.

Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: Value corresponding to the ASCII representation of the compile time of the board’s Bare Metal

Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Table 7. Bare Metal Compile Time (Note: little-endian order of ASCII values)
Word 1 (Ex. 0x2079614D)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Space (0x20)								Month ('y' - 0x79)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Month ('a' - 0x61)								Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Year ('2' - 0x32)								Space (0x20)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Day ('7' - 0x37)								Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Space (0x20)								Year ('9' - 0x39)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Year ('1' - 0x31)								Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Hour ('1' - 0x31)								Space (0x20)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
'a' (0x74)								't' (0x61)
Word 5 (Ex. 0x38333A35)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Minute ('8' - 0x38)								Minute ('3' - 0x33)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
':' (0x3A)								Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
NULL (0x00)								Seconds ('2' - 0x32)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Seconds ('3' - 0x33)								':' (0x3A)

FSBL Version Registers

The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).

FSBL Revision

Function: FSBL firmware revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the revision of the board’s FSBL

Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

Table 8. FSBL Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

FSBL Compile Time

Function: Provides an ASCII representation of the Date/Time for the FSBL compile time.

Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: Value corresponding to the ASCII representation of the Compile Time of the board’s FSBL

Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time.

The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Table 9. FSBL Compile Time (Note: little-endian order of ASCII values)
Word 1 (Ex. 0x2079614D)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Space (0x20)								Month ('y' - 0x79)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Month ('a' - 0x61)								Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Year ('2' - 0x32)								Space (0x20)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Day ('7' - 0x37)								Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Space (0x20)								Year ('9' - 0x39)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Year ('1' - 0x31)								Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Hour ('1' - 0x31)								Space (0x20)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
'a' (0x74)								't' (0x61)
Word 5 (Ex. 0x38333A35)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Minute ('8' - 0x38)								Minute ('3' - 0x33)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
':' (0x3A)								Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
NULL (0x00)								Seconds ('2' - 0x32)
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Seconds ('3' - 0x33)								':' (0x3A)

Module Serial Number Registers

The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.

Interface Board Serial Number

Function: Unique 128-bit identifier used to identify the interface board.

Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: Serial number of the interface board

Operational Settings: This register is for information purposes only.

Functional Board Serial Number

Function: Unique 128-bit identifier used to identify the functional board.

Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit)

Data Range: N/A

Read/Write: R

Initialized Value: Serial number of the functional board

Operational Settings: This register is for information purposes only.

Module Capability

Function: Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0107

Read/Write: R

Initialized Value: 0x0000 0103

Operational Settings: A “1” in the bit associated with the capability indicates that it is supported.

Table 10. Module Capability
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	Flt-Pt	0	0	0	0	0	Pack	FIFO Blk	Blk

Module Memory Map Revision

Function: Module Memory Map revision

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Value corresponding to the Module Memory Map Revision

Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

Table 11. Module Memory Map Revision
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Major Revision Number
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Minor Revision Number

Module Measurement Registers

The registers in this section provide module temperature measurement information.

Temperature Readings Registers

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.

Interface Board Current Temperature

Function: Measured PCB and Zynq Core temperatures on Interface Board.

Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R

Initialized Value: Value corresponding to the measured PCB and Zynq core temperatures based on the table below

Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.

Table 12. Interface Board Current Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
PCB Temperature								Zynq Core Temperature

Functional Board Current Temperature

Function: Measured PCB temperature on Functional Board.

Type: signed byte (8-bits) for PCB

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R

Initialized Value: Value corresponding to the measured PCB on the table below

Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.

Table 13. Functional Board Current Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Interface Board Maximum Temperature

Function: Maximum PCB and Zynq Core temperatures on Interface Board since power-on.

Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R

Initialized Value: Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below

Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.

Table 14. Interface Board Maximum Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
PCB Temperature								Zynq Core Temperature

Interface Board Minimum Temperature

Function: Minimum PCB and Zynq Core temperatures on Interface Board since power-on.

Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R

Initialized Value: Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below

Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.

Table 15. Interface Board Minimum Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
PCB Temperature								Zynq Core Temperature

Functional Board Maximum Temperature

Function: Maximum PCB temperature on Functional Board since power-on.

Type: signed byte (8-bits) for PCB

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R

Initialized Value: Value corresponding to the measured PCB on the table below

Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.

Table 16. Functional Board Maximum Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Functional Board Minimum Temperature

Function: Minimum PCB temperature on Functional Board since power-on.

Type: signed byte (8-bits) for PCB

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R

Initialized Value: Value corresponding to the measured PCB on the table below

Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.

Table 17. Functional Board Minimum Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Higher Precision Temperature Readings Registers

These registers provide higher precision readings of the current Zynq and PCB temperatures.

Higher Precision Zynq Core Temperature

Function: Higher precision measured Zynq Core temperature on Interface Board.

Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Measured Zynq Core temperature on Interface Board

Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.

Table 18. Higher Precision Zynq Core Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Signed Integer Part of Temperature
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Fractional Part of Temperature

Higher Precision Interface PCB Temperature

Function: Higher precision measured Interface PCB temperature.

Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Measured Interface PCB temperature

Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.

Table 19. Higher Precision Interface PCB Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Signed Integer Part of Temperature
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Fractional Part of Temperature

Higher Precision Functional PCB Temperature

Function: Higher precision measured Functional PCB temperature.

Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Measured Functional PCB temperature

Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.

Table 20. Higher Precision Functional PCB Temperature
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
Signed Integer Part of Temperature
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Fractional Part of Temperature

Module Health Monitoring Registers

The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.

Module Sensor Summary Status

Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds.

Type: unsigned binary word (32-bits)

Data Range: See table below

Read/Write: R

Initialized Value: 0

Operational Settings: This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.

Table 21. Module Sensor Summary Status
Bit(s)	Sensor
D31:D6	Reserved
D5	Functional Board PCB Temperature
D4	Interface Board PCB Temperature
D3:D0	Reserved

Module Sensor Registers

The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.

Sensor Threshold Status

Function: Reflects which threshold has been crossed

Type: unsigned binary word (32-bits)

Data Range: See table below

Read/Write: R

Initialized Value: 0

Operational Settings: The associated bit is set when the sensor reading exceed the corresponding threshold settings.

Table 22. Sensor Threshold Status
Bit(s)	Description
D31:D4	Reserved
D3	Exceeded Upper Critical Threshold
D2	Exceeded Upper Warning Threshold
D1	Exceeded Lower Critical Threshold
D0	Exceeded Lower Warning Threshold

Sensor Current Reading

Function: Reflects current reading of temperature sensor

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings: The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Minimum Reading

Function: Reflects minimum value of temperature sensor since power up

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings: The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Maximum Reading

Function: Reflects maximum value of temperature sensor since power up

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings: The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Lower Warning Threshold

Function: Reflects lower warning threshold of temperature sensor

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: Default lower warning threshold (value dependent on specific sensor)

Operational Settings: The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.

Sensor Lower Critical Threshold

Function: Reflects lower critical threshold of temperature sensor

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: Default lower critical threshold (value dependent on specific sensor)

Operational Settings: The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.

Sensor Upper Warning Threshold

Function: Reflects upper warning threshold of temperature sensor

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: Default upper warning threshold (value dependent on specific sensor)

Operational Settings: The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.

Sensor Upper Critical Threshold

Function: Reflects upper critical threshold of temperature sensor

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: Default upper critical threshold (value dependent on specific sensor)

Operational Settings: The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.

FUNCTION REGISTER MAP

Key

Bold Underline

= Measurement/Status/Board Information

Bold Italic

= Configuration/Control

Module Information Registers

0x003C

FPGA Revision

0x0030

FPGA Compile Timestamp

0x0034

FPGA SerDes Revision

0x0038

FPGA Template Revision

0x0040

FPGA Zynq Block Revision

0x0074

Bare Metal Revision

0x0080

Bare Metal Compile Time (Bit 0-31)

0x0084

Bare Metal Compile Time (Bit 32-63)

0x0088

Bare Metal Compile Time (Bit 64-95)

0x008C

Bare Metal Compile Time (Bit 96-127)

0x0090

Bare Metal Compile Time (Bit 128-159)

0x0094

Bare Metal Compile Time (Bit 160-191)

0x007C

FSBL Revision

0x00B0

FSBL Compile Time (Bit 0-31)

0x00B4

FSBL Compile Time (Bit 32-63)

0x00B8

FSBL Compile Time (Bit 64-95)

0x00BC

FSBL Compile Time (Bit 96-127)

0x00C0

FSBL Compile Time (Bit 128-159)

0x00C4

FSBL Compile Time (Bit 160-191)

0x0000

Interface Board Serial Number (Bit 0-31)

0x0004

Interface Board Serial Number (Bit 32-63)

0x0008

Interface Board Serial Number (Bit 64-95)

0x000C

Interface Board Serial Number (Bit 96-127)

0x0010

Functional Board Serial Number (Bit 0-31)

0x0014

Functional Board Serial Number (Bit 32-63)

0x0018

Functional Board Serial Number (Bit 64-95)

0x001C

Functional Board Serial Number (Bit 96-127)

0x0070

Module Capability

0x01FC

Module Memory Map Revision

Module Measurement Registers

0x0200

Interface Board PCB/Zynq Current Temperature

0x0208

Functional Board PCB Current Temperature

0x0218

Interface Board PCB/Zynq Max Temperature

0x0228

Interface Board PCB/Zynq Min Temperature

0x0218

Functional Board PCB Max Temperature

0x0228

Functional Board PCB Min Temperature

0x02C0

Higher Precision Zynq Core Temperature

0x02C4

Higher Precision Interface PCB Temperature

0x02E0

Higher Precision Functional PCB Temperature

Module Health Monitoring Registers

0x07F8

Module Sensor Summary Status

NAI Cares

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North Atlantic Industries (NAI) is a leading independent supplier of Embedded I/O Boards, Single Board Computers, Rugged Power Supplies, Embedded Systems and Motion Simulation and Measurement Instruments for the Military, Aerospace and Industrial Industries. We accelerate our clients’ time-to-mission with a unique approach based on a Configurable Open Systems Architecture™ (COSA®) that delivers the best of both worlds: custom solutions from standard COTS components.

We have built a reputation by listening to our customers, understanding their needs, and designing, testing and delivering board and system-level products for their most demanding air, land and sea requirements. If you have any applications or questions regarding the use of our products, please contact us for an expedient solution.

Please visit us at: www.naii.com or select one of the following for immediate assistance:

Documentation

https://www.docs.naii.com

FAQ

http://www.naii.com/faq/

Application Notes

http://www.naii.com/appNotes/

Calibration and Repairs

http://www.naii.com/calibration/

Call Us

(631) 567-1100

Integrator Resources

Latching and Non-Latching Relays

DATA SHEET

INTRODUCTION

RY1/RY2 Overview

PRINCIPLE OF OPERATION

Automatic Background Built-In Test (BIT)/Diagnostic Capability