24-Channel Programmable Discrete Module
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DT4 I/O Modules Discrete IO - Multichannel, Programmable Function Modules Enhanced 24 Discrete I/O Channels (0 to 60 VDC, 500 mA/Ch.)
The DT4 module (the enhanced version) features 24 programmable channels for either input (voltage or contact sensing with programmable, onmodule pull-up/pull down current sources), or output (current source, sink, or push-pull) up to 500 mA per channel from an applied, external 3 – 60 VCC source. These modules can sense broken input connections and whether an input is shorted to +VCC or to ground. Additional features of the DT4 (Enhanced Version) are listed below.
Features
•24 channels available as inputs or outputs
•Ability to handle high inrush current loads (for example, two #327 incandescent lamps in parallel)
•Built-In-Test runs in background constantly monitoring system health for each channel
•Programmable for Input (voltage or contact sensing) or Output (current source, sink or push-pull) per channel/bank
•Supports 'dual turn-on' (series channel output) applications (for example, dual series 'key' missile launch control)
•Ability to sense broken input connection and if input is shorted to +V or to ground
•Ability to current share, by connecting multiple outputs in parallel, to sink/source up to 2 A per bank*
•Programmable debounce circuitry with selectable time delay eliminates false signals resulting from relay contact bounce
•Ability to read I/O voltage and output current for improved diagnostics (indicates if load is connected)
•Enhanced DT4 Functionality Features:
Additional Enhanced Input Mode
Operation: Pulse Measurements,
Transition Timestamps, Transition
Counters, Period Measurement and
Frequency Measurement
Additional Enhanced Output Mode
Operation: PWM Output and Pattern
Generator Output
Specifications
Input Range |
0 to 60 VDC. Programmable for either voltage or switch closure sensing. |
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Overvoltage Surge Protection |
80 VDC max. (< 50 ms); 100 VDC max. (< 1 μs) |
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Voltage/Content Sensing |
Software selectable per bank. When the input channel is utilized for direct voltage sense, Vcc is not required. When input is used to detect switch closures, Vcc is required to provide a current source (pull-up). Vcc per channel bank must be between 5 VDC min. and 60 VDC max. A module has 4 Vcc banks, each with 6 channels for a total of 24 channels/module. |
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Input Pulse Detection |
A pulse of > 20 μs minimum width will be sensed and reported by the appropriate High–Low or Low-High transition status/interrupt. |
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Input Impedance |
1 MΩ (with or without power applied to module) |
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Switching Threshold |
Four levels (Upper, Lower, Max High, Max Low ) are programmable from 0 to 60 VDC with 10-bit resolution. |
Voltage Measurement |
|
User can read input voltage of each channel. From: LSB=100 mV; Accuracy: ±3 LSB’s (300 mV) over temp. To: 1% FSR. |
HIGH/LOW Differential (Hysteresis) |
300 mV min. recommended. Programmable by using Upper & Lower thresholds. |
|
Debounce |
Programmable per channel from 0x00000000 (deactivated) to 0xFFFFFFFF (2^32 * 10µs) (LSB= 10 μs; 32-bit resolution). |
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Update Rate |
Each channel is updated every 10 μs. |
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Additional Enhanced Input Mode Operation |
Pulse Measurements, Transition Timestamps, Transition Counters, Period Measurement and Frequency Measurement. |
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Output Formats |
Low-Side (I sink), High-Side (I source) or Push-Pull (I source-sink); programmable per channel. |
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Output Voltage Range |
0 to 60 VDC. (Output voltage is defined by the user provided Vcc applied to channel bank) Low-side drive does not require Vcc. High-side and push-pull drive requires Vcc. |
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Overvoltage Surge Protection |
80 VDC max. (< 50 ms); 100 VDC max. (< 1 μs) |
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Output Current |
0.5 A maximum (28 V Vcc typical) per channel. 2 A total per Vcc bank (total Module capacity 8 A). Measurement accuracy: ±10% ± 25 mA. |
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Output Impedance |
< 1 Ω (0.5 Ω typical) |
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Current Share Applications |
0.5 A maximum (28 V Vcc typical) per channel. 2 A total per Vcc bank (total Module capacity 8 A). Each channel can be programmed to generate frequency, pulse or arbitrary pulse width with 10 microsecond minimum resolution. Short circuit protected. |
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Overcurrent Protection |
Low current (average): > 625 mA average over 3 ms. High current (pulse): > 6 amps for less than or equal to 30 µs. |
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Additional Enhanced Output Mode Operation |
PWM Output and Pattern Generator Output. |
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Power |
600 mA @ 5 V (typical, non-inclusive of any external VCC related current). |
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Weight |
1.5 oz. (42 g) |
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Architected for Versatility
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NAI’s Custom-On-Standard Architecture™ (COSA®) offers a choice of over 40 Intelligent I/O, communications, or Ethernet switch functions, providing the highest packaging density and greatest flexibility of any 3U SBC in the industry. Preexisting, fully-tested functions can be combined in an unlimited number of ways quickly and easily.
Board Support Package and Software Support
The 75PPC1 includes BSP and SDK support for Wind River® VxWorks®. In addition, software support kits are supplied, with source code and board-specific library I/O APIs, to facilitate system integration. Each I/O function has dedicated processing, unburdening the SBC from unnecessary data management overhead.
Background Built-In-Test (BIT)
BIT continuously monitors the status of all I/O during normal operations and is totally transparent to the user. SBC resources are not consumed while executing BIT routines. This simplifies maintenance, assures operational readiness, reduces life-cycle costs and— keeps your systems mission ready.
One-Source Efficiencies
Eliminate man-months of integration with a configured, field-proven system from NAI. Specification to deployment is a seamless experience as all design, state-of-the-art manufacturing, assembly and test are performed— by one trusted source. All facilities are in the U.S. and optimized for high-mix/low volume production runs and extended lifecycle support.
Product Lifecycle Management
From design-in to production, and beyond, NAI’s product lifecycle management strategy ensures the long-term availability of COTS products through configuration management, technology refresh, and obsolescence component purchase and storage.
INTRODUCTION
As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurements and simulation, communications, Ethernet switch, and SBC functions. Our enhanced function (EF) discrete I/O multichannel smart function modules provide the same interfacing solutions for almost embedded or test application (unparalleled programming flexibility, wide range of operating characteristics, unique design that eliminates the need for pull-up resistors or mechanical jumpers) as the standard function (SF) version. Additionally, the EF module adds built-in functionality to provide Pulse/Frequency Period Measurements of the incoming signal (input) and/or Pulse/Frequency arbitrary signal generation (output). This user manual is designed to help you get the most out of our discrete I/O smart function modules.
DT4 Overview
NAI’s DT4 module offers a range of features designed to suit a variety of system requirements, including:
•24 Channels of Programmable Discrete Input/Output:
The DT4 module features 24 channels programmable for either discrete input or output that provide the following: •Input – voltage or contact sensing with programmable, pull-up/pull-down current sources, eliminating the need for external resistors or mechanical jumpers. •Output – programmable current source (high-side), sink (low-side) or push-pull switching up to 500 mA per channel from an applied 3- 60V external VCC source (or sink to ISO-GND).
Current Sharing:
The module enables current sharing* by connecting multiple outputs in parallel, capable of sinking or sourcing up to 2A per bank, enhancing your system’s capacity and reliability. (*) Current Share: The maximum output load per-channel is ±0.5A. Channels can be connected and operated in parallel to provide > 0.5A to act as a single channel. The load current between paralleled channels cannot be effectively characterized and is not expected to be equal due to factors including: Channel/bank position, module position, motherboard/system platform configuration, operating temperature range including external application/configuration influences (e.g., external cabling). Therefore, when operating in shared current (parallel channel) configuration, it is recommended to de-rate the per-channel maximum current output to at least 66% (or 333 mA/channel) to ensure that no single channel is overburdened by handling most of the load current. For example: If the maximum continuous load current is expected to be 1A: 1/0.33 ≅ 3 channels (minimum).
Inrush Current Handling:
The DT4 module can efficiently handle high inrush current loads, such as connecting two #327 incandescent lamps in parallel, without compromising performance.
Dual Turn-On Application Support:
The module supports ‘dual turn-on' applications, such as dual series ‘key' missile launch control, providing seamless control in critical operations.
Debounce Circuitry:
Programmable debounce circuitry with selectable time delay eliminates false signals caused by relay contact bounce, ensuring accurate data acquisition.
Background Built-In-Test (BIT):
All channels have continuous background Built-In-Test (BIT), which provides real-time channel health to ensure reliable operation in mission-critical systems. This feature runs in the background and is transparent in normal operations.
Input Diagnostics:
The DT4 module can sense broken input connections and detect if inputs are shorted to +V or ground, allowing for early detection and troubleshooting.
Voltage and Current Readings:
The module offers the ability to read I/O voltage and output current, facilitating improved diagnostics and load status identification (indicates if load is connected).
Enhanced Functionality Features:
In addition to offering the same functionality as the DT1 standard function (SF) module, the DT4 includes the following enhanced features: •Enhanced Input Mode – Pulse Measurements, Transition Timestamps, Transition Counters, Period Measurement, and Frequency Measurement. •Enhanced Output Mode – PWM Output and Pattern Generator Output.
PRINCIPLE OF OPERATION
DT4 provides up to 24 individual digital I/O channels with BIT fault detection, which enables flagging of non-compliant outputs or inconsistent input readings between dual input measurements
When channels are programmed as inputs, they can be used for either voltage or contact sensing. Channels set for contact sensing (e.g., sensing a relay contact position; OPEN-CLOSED) can be configured with a programmable “pull-up” or “pull-down” (current source or sink) which effectively provides the proper voltage level change to sense the open state of the contact. This unique design eliminates the need for external resistors or mechanical jumpers. Instead, this design offers a current source/sink (in banks of 6 channels) that the user programs to a desired current (0-5 mA) level.
When programmed as outputs, each channel can be set for high-side (current-source), low-side (current-sink) or push-pull (current-source-sink) operation. The load impedance determines the delivered switched output current drive – up to 500 mA per channel. Diode clamping is provided (useful for inductive loads, such as relays) and thermal protection.
Overcurrent protection is implemented using current sensing technology. When the current exceeds a programmed threshold of 650 mA steadystate, or a higher short duration, the overcurrent/short-circuit protection is triggered, shutting down the output drivers for safety. The overcurrent fault status will be indicated for the affected channels and will require a reset operation to restore output. To reset this condition, a reset command needs to be issued to the Overcurrent Reset register, which will restore drive output and allow the latched status to be reset. This is separate from the reset for the Overcurrent Interrupt Enable register on this module. It is recommended that a reset command is done whenever status is cleared to avoid a non-apparent output reset condition.
The 24 channels are configured as 4 banks of 6 channels. Each bank is provided with a separate external input VCC and a ground return (GND) pin. The GND pins are common within the module but are isolated from system (power) GND.
Operational requirements/assumptions:
•An external source VCC supply must be wired for proper: •Output operation as a current source •Input operation when requiring a programmed pull-up current (i.e., programmed “pull-up” for input contact sense; OPEN/GND detect/state change). •An external source Ground/Return must be wired for all I/O configurations. The Ground/Return must be the input signal or the load current sink ground/reference.
Output
When configured as an output, the interface can act as a “High-Side”, “Low-Side” or “Push-Pull” drive, providing up to 500 mA per channel or 1 A when two channels are connected in parallel. The total output per module is 8 A (2 A per bank).
Note: Maximum source current ‘rules' for rear I/O connectors still apply – see specifications.
Input
When configured as an input, output drivers are disabled. The I/O interface can act as a constant current source, current sink or voltage sensing circuit. For contact sensing, each channel may be set for pull-up or pull-down using the Select Pull-Up or Pull-Down register and by entering the appropriate current level in the Pull-Up/Down Current register. Contact closure and hysteresis may be defined using the Upper Voltage and Lower Voltage Threshold registers. No additional resistors or hardware are required to provide for current flow. A current value of zero disables the current source/sink circuits and configures the module for voltage sensing. Default is voltage sensing. Level or contact sensing can be mixed within a channel bank, if the contact sensing channels are externally pulled up or pulled down.
Note: If this module supplies the current for the contact sensing, then level and contact sensing cannot be mixed within a channel bank.
All four threshold levels must be programmed in monotonic, increasing order of: Minimum Low, Lower, Upper and Maximum High. For input and output, threshold levels define logic state. For output, threshold levels are used in BIT test (wrap-around) signal monitoring. A pair of drive FETs and current circuits are provided at each I/O pin. See the functional representation of the drivers in the I/O Circuits interface diagram below.
Discrete I/O Threshold Programming
Four threshold levels: Max High Voltage Threshold, Upper Voltage Threshold, Lower Voltage Threshold, and Min Low Voltage Threshold offer maximum user flexibility. All four threshold levels must be programmed. For input or output, the threshold levels will define the logic states. For proper operation, the threshold values should be programmed such that:
Max High Voltage Threshold > Upper Voltage Threshold > Lower Voltage Threshold > Min Low Voltage Threshold
Program Upper and Lower Voltage Thresholds, keeping the 0.25 V min. differential in mind, and then add debounce time as required. When the input signal exceeds the Upper Voltage Threshold, a logic high 1 is maintained until the input signal falls below the Lower Voltage Threshold. Conversely, when the input signal falls below the Lower Voltage Threshold, a logic low 0 is maintained until the input signal rises above the Upper Voltage Threshold.
=Debounce Programming The Debounce register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Once a signal level is a logic voltage level period longer than the Debounce Time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed Debounce Time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state.
Automatic Background Built-In Test (BIT)/Diagnostic Capability
The Discrete module supports automatic background BIT testing that verifies channel processing. The testing is totally transparent to the user, requires no external programming and has no effect on the operation of the module. This capability is accomplished by an additional test comparator that is incorporated into each module. The test comparator checks each channel and is compared against the operational channel. Depending upon the configuration, the Input data read, or Output logic written of the operational channel and test comparator must agree or a fault is indicated with the results available in the associated status register. The results of the tests are stored in the BIT Dynamic Status and BIT Latched Status registers.
The technique used by the continuous background BIT (CBIT) test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. Note, the interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g., BIT faults would register when sustained; i.e., at a ten second interval, not a 10-millisecond interval). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state.
In addition to BIT, the Discrete module tests for overcurrent conditions and provides Above Max High Voltage, Below Min Low Voltage, and MidRange Voltage statuses for threshold signal transitioning.
Status and Interrupts
The DT Discrete I/O Function Module provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.
Module Common Registers
The Discrete I/O Function Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.
Unit Conversions
The Discrete Module Threshold and Measurement registers can be programmed to be utilized as a single precision floating point value (IEEE-754) or as a 32-bit integer value. The purpose for providing this feature is to offload the processing that is normally performed by the mission processor to convert the integer values to floating-point values.
When the Enable Floating Point Mode register is set to 1 (Floating Point Mode) the following registers are formatted as Single Precision Floating Point Value (IEEE-754): •Voltage Reading (Volts) •Current Reading (mA) •VCC Voltage Reading (Volts)
•Max High Voltage Threshold (Volts)
•Upper Voltage Threshold (Volts)
•Lower Voltage Threshold (Volts)
•Min Low Voltage Threshold (Volts)
•Pull-Up/Down Current (mA)
*When the Enable Floating Point Mode register is set to 1, it is important that these registers are updated with the Single Precision Floating Point (IEEE-754) representation of the value for proper operation of the channel. Conversely, when the Enable Floating Point Mode register is set to 0, these registers must be updated with the Integer 32-bit representation of the value.
Note: when changing the Enable Floating Point Mode from Integer Mode to Floating Point Mode or vice versa, the following steps are followed to avoid faults from falsely being generated: 1. Set the Enable Floating Point Mode register to the desired mode (Integer or Floating Point). 2. The application waits for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete. Data registers will be converted to the units specified and can be read in that specified format.
User Watchdog Timer Capability
The Discrete Modules provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the Principle of Operation description.
Enhanced Functionality
The DT4 Module provides enhanced input and output mode functionality. For incoming signals (inputs), the DT4 enhanced modes include Pulse Measurements, Transition Timestamps, Transition Counters, Period Measurement and Frequency Measurement. For outputs, the DT4 enhanced modes include PWM (Pulse Width Modulation) Outputs and Pattern Generator Outputs.
Refer to “Enhanced Discrete I/O, Digital I/O Functionality – Module Manual” for the Principle of Operation description.
REGISTER DESCRIPTIONS
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.
Discrete Input/Output Registers
Each channel can be configured as an input or one of three types of outputs. The I/O Format (Ch1-16 and Ch17-24) registers are used to set each channel input/output configuration. The Write Outputs register controls the output channels to either a High (1) or Low (0) state, and the Read I/O register contains the discrete channel’s state (High (1) or Low (0)) as specified by the channel’s threshold configurationss.
I/O Format Ch1-16
Function: Sets channels 1-16 as inputs or outputs. See I/O Format Ch17-24 register for channels 17-24.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: Write integer 0 for input; 1, 2 or 3 for specific output format.
Integer |
DH |
DL |
(2 bits per channel) |
0 |
0 |
0 |
Input |
1 |
0 |
1 |
Output, Low-side switched, with/without current pull up |
2 |
1 |
0 |
Output, High-side switched, with/without current pull down |
3 |
1 |
1 |
Output, push-pull |
I/O Format Ch1-16
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
Ch16 |
Ch16 |
Ch15 |
Ch15 |
Ch14 |
Ch14 |
Ch13 |
Ch13 |
Ch12 |
Ch12 |
Ch11 |
Ch11 |
Ch10 |
Ch10 |
Ch9 |
Ch9 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch8 |
Ch8 |
Ch7 |
Ch7 |
Ch6 |
Ch6 |
Ch5 |
Ch5 |
Ch4 |
Ch4 |
Ch3 |
Ch3 |
Ch2 |
Ch2 |
Ch1 |
Ch1 |
I/O Format Ch17-24
Function: Sets channels 17-24 as inputs or outputs. See I/O Format Ch1-16 for channels 1-16.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: Write integer 0 for input; 1, 2 or 3 for specific output format.
Integer |
DH |
DL |
(2 bits per channel) |
0 |
0 |
0 |
Input |
1 |
0 |
1 |
Output, Low-side switched, with/without current pull up |
2 |
1 |
0 |
Output, High-side switched, with/without current pull down |
3 |
1 |
1 |
Output, push-pull |
I/O Format Ch17-24
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch24 |
Ch24 |
Ch23 |
Ch23 |
Ch22 |
Ch22 |
Ch21 |
Ch21 |
Ch20 |
Ch20 |
Ch19 |
Ch19 |
Ch18 |
Ch18 |
Ch17 |
Ch17 |
Write Outputs
Function: Drives output channels High 1 or Low 0
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: Write 1 to drive output high. Write 0 to drive output low.
Write Outputs
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Input/Output State
Function: Reads High 1 or Low 0 inputs or outputs as defined by internal channel threshold values.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R
Initialized Value: N/A
Operational Settings: Bit-mapped per channel.
Input/Output State
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Discrete Input/Output Voltage Threshold Programming Registers
Four threshold levels: Max High Voltage Threshold, Upper Voltage Threshold, Lower Voltage Threshold, and Min Low Voltage Threshold are programmable for each Discrete channel in the module.
Max High Voltage Threshold (Enable Floating Point Mode: Integer Mode) Upper Voltage Threshold (Enable Floating Point Mode: Integer Mode) Lower Voltage Threshold (Enable Floating Point Mode: Integer Mode) Min Low Voltage Threshold (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Max High Voltage Threshold (Enable Floating Point Mode: Floating Point Mode) Upper Voltage Threshold (Enable Floating Point Mode: Floating Point Mode) Lower Voltage Threshold (Enable Floating Point Mode: Floating Point Mode) Min Low Voltage Threshold (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Max High Voltage Threshold
Function: Sets the maximum high voltage threshold value. Programmable per channel from 0 VDC to 60 VDC.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) 0x0000 0000 to 0x0000 0258
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 0x32
Operational Settings: Assumes that the programmed level is the minimum voltage used to indicate a Max High Voltage Threshold. If a signal is greater than the Max High Voltage Threshold value, a flag is set in the Max High Voltage Threshold Status register. The Max High Voltage Threshold register may be used to monitor any type of high signal voltage condition or threshold such as a “Short to +V” as it applies to input measurement as well as contact sensing applications.
Integer Mode: LSB is 0.1 VDC. For example: to program 5.0 VDC, 5.0 / 0.1 = 50 (binary equivalent for 50 is 0x0000 0032).
Floating Point Mode: Set Max High Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 5.0V, enter 5.0 as a single precision floating point value (IEEE-754) (binary equivalent 5.0 is 0x40A0 0000).
Upper Voltage Threshold
Function: Sets the upper voltage threshold value. Programmable per channel from 0 VDC to 60 VDC.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) 0x0000 0000 to 0x0000 0258
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 0x28
Operational Settings: A signal is considered logic High 1 when its value exceeds the Upper Voltage Threshold and does not consequently fall below the Upper Voltage Threshold in less than the programmed Debounce Time
Integer Mode: LSB is 0.1 VDC. For example: to program 3.5 VDC, 3.5 / 0.1 = 35 (binary equivalent for 35 is 0x0000 0023).
Floating Point Mode: Set Upper Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 3.5 V, enter 3.5 as a single precision floating point value (IEEE-754) (binary equivalent 3.5 is 0x4060 0000).
Lower Voltage Threshold
Function: Sets the lower voltage threshold value. Programmable per channel from 0 VDC to 60 VDC.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) 0x0000 0000 to 0x0000 0258
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 0x10
Operational Settings: A signal is considered logic Low 0 when its value falls below the Lower Voltage Threshold and does not consequently rise above the Lower Voltage Threshold in less than the programmed Debounce Time.
Integer Mode: LSB is 0.1 VDC. For example: to program 1.5 VDC, 1.5 / 0.1 = 15 (binary equivalent for 15 is 0x0000 000F).
Floating Point Mode: Set Lower Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 1.5 V, enter 1.5 as a single precision floating point value (IEEE-754) (binary equivalent 1.5 is 0x3FC0 0000).
Min Low Voltage Threshold
Function: Sets the minimum low voltage threshold. Programmable per channel 0 VDC to 60 VDC.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) 0x0000 0000 to 0x0000 0258
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 0xA
Operational Settings: Assumes that the programmed level is the voltage used to indicate a Minimum Low Voltage Threshold. If a signal is less than the Min Low Voltage Threshold value, a flag is set in the Min Low Voltage Threshold Status register. The Min Low Voltage Threshold register may be used to monitor any type of low signal voltage condition or threshold such as a “Short to Ground” as it applies to input measurement as well as contact sensing applications.
Integer Mode: LSB is 0.1 VDC. For example: to program 0.5 VDC, 0.5 / 0.1 = 5 (binary equivalent for 5 is 0x0000 0005).
Floating Point Mode: Set Min Low Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 0.5 V, enter 0.5 as a single precision floating point value (IEEE-754) (binary equivalent 0.5 is 0x3F00 0000).
Discrete Input/Output Measurement Registers
The measured voltage and current at the I/O pin for each channel can be read from the Voltage Reading and Current Reading registers.
Voltage Reading
Function: Reads actual voltage at I/O pin per individual channel.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) 0x0000 0000 to 0x0000 0258
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings:
Integer Mode: LSB is 0.1 VDC. If the register value is 261 (binary equivalent for 261 is 0x0000 0105), conversion to the voltage value is 261 * 0.1 = 26.1 V.
Floating Point Mode: Read as a Single Precision Floating Point Value (IEEE-754). For example, if the register value is 0x41D0 CCCD, this is equivalent to is 26.1, which represent 26.1 V.
Voltage Reading (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Voltage Reading (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Current Reading
Function: Reads actual output current through I/O pin per channel.
Type: signed binary word (32-bit (only lower 16-bit is used)) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) (2’s compliment. 16-bit value sign extended to 32 bits) 0x0000 0000 to 0x0000 00D0 (positive) or 0x0000 FF30 (negative)
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings:
Integer Mode: LSB is 3.0 mA. Value is signed binary 16-bit word. Read as 2’s complement value for positive and negative current readings. For example, if the register value is 50 (binary equivalent for 50 is 0x0000 0032), the conversion to the current value is 50 * 3.0 = 150 mA. If register value is -50 (binary equivalent for -150 is 0x0000 FFCE), the conversion to the current value is -50 * 3.0 = -150 mA.
Floating Point Mode: Read as a Single Precision Floating Point Value (IEEE-754). The value will represent a positive or negative current reading. For example, if the register value is 0x4316 0000, this is equivalent to 150, which represent 150 mA. If the register value is 0xC316 0000, this is equivalent to -150, which represents -150 mA.
Current Reading (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Current Reading (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
VCC Bank Registers
There are four VCC banks where each bank controls 6 discrete channels. Configuration for each bank involves specifying if the bank is configured for pull-up or pull-down and the current for source/sink. The measured voltage for each VCC bank can be read from the VCC Voltage Reading register.
Select Pull-Up or Pull-Down
Function: Configures Pull-up or Pull-down configuration per 6-channel bank
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0000 000F
Read/Write: R/W
Initialized Value: 0
Operational Settings: Set bit to 1 to configure channel bank to Pull-up. Set bit to 0 to configure channel bank to Pull-down. Each data bit configures entire bank of 6 channels.
Note: For contact (switch closure) applications, a current supply (Vcc) is required for internal pull-up.
Select Pull-Up or Pull-Down
Bit(s) |
Name |
Description |
D31:D4 |
Reserved |
Set Reserved bits to 0. |
D3 |
Configure Bank 4 (Ch 19-24) |
1=Pull-Up, 0=Pull-Down |
D2 |
Configure Bank 3 (Ch 13-18) |
1=Pull-Up, 0=Pull-Down |
D1 |
Configure Bank 2 (Ch 07-12) |
1=Pull-Up, 0=Pull-Down |
D0 |
Configure Bank 1 (Ch 01-06) |
1=Pull-Up, 0=Pull-Down |
Pull-Up/Down Current
Function: Sets current for pull-up/down per 6-channel bank. Programmable from 0 to 5 mA.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) 0x0000 0000 to 0x0000 0032
Enable Floating Point Mode: 1 (Floating Point Mode) Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 0
Operational Settings: A current of zero disables the current pull-down circuits and configures for voltage sensing.
Integer Mode: LSB is 0.1 mA. For example: to program 5 mA, 5 / 0.1 = 50 (binary equivalent for 50 is 0x0000 0032).
Floating Point Mode: Set the current for pull-up/down as a Single Precision Floating Point Value (IEEE-754). For example, to program 5 mA, enter 5.0 as a Single Precision Floating Point Value (IEEE-754) (binary equivalent for 5.0 is 0x40A0 0000).
Pull-Up/Down Current (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
D |
D |
D |
D |
D |
Pull-Up/Down Current (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
VCC Voltage Reading
Function: Read the VCC bank voltage.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Enable Floating Point Mode: 0 (Integer Mode) 0x0000 0000 to 0x0000 0258
Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings:
Integer Mode: LSB is 0.1 VDC. If the register value is 260 (binary equivalent for this value is 0x0000 0104), conversion to the voltage value is 260 * 0.1 = 26.0 V.
Floating Point Mode: Read as a Single Precision Floating Point Value (IEEE-754). For example, the binary equivalent for 0x41D0 0000 is 26.0 which represent 26.0 V.
VCC Voltage Reading (Enable Floating Point Mode: Integer Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
D |
0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
VCC Voltage Reading (Enable Floating Point Mode: Floating Point Mode)
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
D |
Discrete Input/Output Control Registers
Control of the Discrete I/O channels include specifying the Debounce time for each input channel and resetting the I/O channel on an overcurrent condition.
Debounce Time
Function: When set for inputs, the input signal will have the debounce filtering applied based on this programmed value. This is selectable for each channel.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: The Debounce Time register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Enter required Debounce Time into appropriate channel registers. LSB weight is 10 µs/bit (register may be programmed from 0x0000 0000 (debounce filter inactive) through a maximum of 0xFFFF FFFF (2^32 * 10µs). (full scale w/ 10 µs resolution). Once a signal l vel is a logic voltage level period longer than the debounce time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed Debounce Time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state. Enter a value of 0 to disable debounce filtering.
Overcurrent Reset
Function: Resets disabled channels in Overcurrent Latched Status register following an overcurrent condition as measured by the Current Reading register.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: 1 is written to reset disabled channels. Processor will write a 0 back to the Overcurrent Reset register when reset process is complete.
Overcurrent Reset
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Unit Conversion Programming Registers
The Enable Floating Point register provides the ability to set the Threshold values as floating-point values and read the Voltage Reading and Current Reading registers as floating-point values. The purpose for this feature is to offload the processing that is normally performed by the mission processor to convert the integer values to floating-point values.
Enable Floating Point Mode
Function: Sets all channels for floating point mode or integer module.
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: R/W
Initialized Value: 0
Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode. Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).
Enable Floating Point Mode
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Floating Point State
Function: Indicates the state of the mode selected (Integer or Floating Point).
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: R
Initialized Value: 0
Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).
Floating Point State
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
D |
Background BIT Threshold Programming Registers
The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The BIT Count Clear register provides the ability to reset the BIT counter used in CBIT.
Background BIT Threshold
Function: Sets BIT Threshold value (in milliseconds) to use for all channels for BIT failure indication.
Type: unsigned binary word (32-bit)
Data Range: 1 ms to 2^32 ms
Read/Write: R/W
Initialized Value: 5 ms
Operational Settings: The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module.
BIT Count Clear
Function: Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: W
Initialized Value: 0
Operational Settings: Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.
BIT Count Clear
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
User Watchdog Timer Programming Registers
Refer to “User Watchdog Timer Module Manual” for the Register descriptions.
Module Common Registers
Refer to “Module Common Registers Module Manual” for the register descriptions.
Status and Interrupt Registers
The Discrete Module provides status registers for BIT, Low-to-High Transition, High-to-Low Transition, Overcurrent, Above Max High Voltage,Below Min Low Voltage, and Mid-Range Voltage
Channel Status Enable
Function: Determines whether to update the status for the channels. This feature can be used to “mask” status bits of unused channels in status registers that are bitmapped by channel.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF (Channel Status)
Read/Write: R/W
Initialized Value: 0x00FF FFFF
Operational Settings: When the bit corresponding to a given channel in the Channel Status Enable register is not enabled (0) the status will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status, Low-to-High Transition Status, Highto-Low Transition Status, Overcurrent Status, Above Max High Voltage Status, Below Min Low Voltage Status, Mid-Range Voltage and Summary Status). NOTE: Background BIT will continue to run even if the Channel Status Enable is set to ‘0'.
Channel Status Enable
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
BIT Status
There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Note, when a BIT fault is detected, reading the Voltage Reading Error and the Driver Error register will provide additional diagnostics on the cause of the BIT fault.
BIT Dynamic Status BIT Latched Status BIT Interrupt Enable BIT Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s BIT error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Note: Faults are detected (associated channel(s) bit set to 1) within 10 ms.
Voltage Reading Error
Function: The Voltage Reading Error register is set when a redundant voltage measurement is inconsistent with the input voltage level detected.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R
Initialized Value: 0
Operational Settings: 1 is read when a fault is detected. 0 indicates no fault detected.
Note: Faults are detected (associated channel(s) bit set to 1) within 10 ms.
Note: Clearing the latched BIT status will also clear this error register.
Voltage Reading Error
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Driver Error
Function: The Driver Error register is set when the voltage reading mismatches active driver measurement and is inconsistent with the input driver level detected (Note: requires programming of thresholds).
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R
Initialized Value: 0
Operational Settings: 1 is read when a fault is detected. 0 indicates no fault detected.
Note: Faults are detected (associated channel(s) bit set to 1) within 10 ms.
Note: Clearing the latched BIT status will also clear this error register.
Driver Error
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Low-to-High Transition Status
There are four registers associated with the High-to-Low Transition Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Low-to-High Dynamic Status Low-to-High Latched Status Low-to-High Interrupt Enable Low-to-High Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Low-to-High Transition event.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Note: Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.
Note: Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.
Note: Transition status follows the value read by the Input/Output State register.
High-to-Low Transition Status
There are four registers associated with the High-to-Low Transition Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
High-to-Low Dynamic Status High-to-Low Latched Status High-to-Low Interrupt Enable High-to-Low Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s High-to-Low Transition event.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
*Initialized Value: 0
Note: Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.
Note: Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 s.
Note: Transition status follows the value read by the Input/Output State register.
Overcurrent Status
There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Overcurrent Dynamic Status Overcurrent Latched Status Overcurrent Interrupt Enable Overcurrent Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Overcurrent error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Note: Status is indicated (associated channel(s) bit set to 1), within 80 ms.
Note: Latched Status is indicated (associated channel(s) bit set to 1), within 80 ms. Channel(s) shut down by overcurrent sensed can be reset by writing to the Overcurrent Clear register.
Above Max High Voltage Status
There are four registers associated with the Above Max High Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.
Above Max High Voltage Dynamic Status Above Max High Voltage Latched Status Above Max High Voltage Interrupt Enable Above Max High Voltage Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Above Max High Voltage event.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Below Min Low Voltage Status
There are four registers associated with the Below Min Low Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.
Below Min Low Voltage Dynamic Status Below Min Low Voltage Latched Status Below Min Low Voltage Interrupt Enable Below Min Low Voltage Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Below Min Low Voltage event.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Mid-Range Voltage Status
There are four registers associated with the Mid-Range Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.
Mid-Range Voltage Dynamic Status Mid-Range Voltage Latched Status Mid-Range Voltage Interrupt Enable Mid-Range Voltage Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit associated with the channel’s Mid-Range Voltage error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Note: Voltage level needs to be between the upper and lower thresholds for the debounce time for this status to assert.
Note: In the event this status is asserted, the Input/Output state will hold its previous state.
User Watchdog Timer Fault Status
The Discrete Modules provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status Register descriptions.
Summary Status
There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Summary Status Dynamic Status Summary Status Latched Status Summary Status Interrupt Enable Summary Status Set Edge/Level Interrupt
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Ch24 |
Ch23 |
Ch22 |
Ch21 |
Ch20 |
Ch19 |
Ch18 |
Ch17 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
Ch16 |
Ch15 |
Ch14 |
Ch13 |
Ch12 |
Ch11 |
Ch10 |
Ch9 |
Ch8 |
Ch7 |
Ch6 |
Ch5 |
Ch4 |
Ch3 |
Ch2 |
Ch1 |
Function: Sets the corresponding bit if any fault (BIT and Overcurrent) occurs on that channel.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x00FF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
interruptVectorAndSteeringBoilerplate1234
FUNCTION REGISTER MAP
Key: Bold Italic = Configuration/Control
Bold Underline = State/Measurement/Status
When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0). * Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).
Discrete Input/Output Registers
0x1038 |
I/O Format (Ch1-16) |
R/W |
0x103C |
I/O Format (Ch17-24) |
R/W |
0x1000 |
I/O State |
R |
0x1024 |
Write Outputs |
R/W |
Discrete Input/Output Voltage Threshold Programming Registers
0x20C0 |
Max High Voltage Threshold Ch 1** |
R/W |
0x2140 |
Max High Voltage Threshold Ch 2** |
R/W |
0x21C0 |
Max High Voltage Threshold Ch 3** |
R/W |
0x2240 |
Max High Voltage Threshold Ch 4** |
R/W |
0x22C0 |
Max High Voltage Threshold Ch 5** |
R/W |
0x2340 |
Max High Voltage Threshold Ch 6** |
R/W |
0x23C0 |
Max High Voltage Threshold Ch 7** |
R/W |
0x2440 |
Max High Voltage Threshold Ch 8** |
R/W |
0x24C0 |
Max High Voltage Threshold Ch 9** |
R/W |
0x2540 |
Max High Voltage Threshold Ch 10** |
R/W |
0x25C0 |
Max High Voltage Threshold Ch 11** |
R/W |
0x2640 |
Max High Voltage Threshold Ch 12** |
R/W |
0x26C0 |
Max High Voltage Threshold Ch 13** |
R/W |
0x2740 |
Max High Voltage Threshold Ch 14** |
R/W |
0x27C0 |
Max High Voltage Threshold Ch 15** |
R/W |
0x2840 |
Max High Voltage Threshold Ch 16** |
R/W |
0x28C0 |
Max High Voltage Threshold Ch 17** |
R/W |
0x2940 |
Max High Voltage Threshold Ch 18** |
R/W |
0x29C0 |
Max High Voltage Threshold Ch 19** |
R/W |
0x2A40 |
Max High Voltage Threshold Ch 20** |
R/W |
0x2AC0 |
Max High Voltage Threshold Ch 21** |
R/W |
0x2B40 |
Max High Voltage Threshold Ch 22** |
R/W |
0x2BC0 |
Max High Voltage Threshold Ch 23** |
R/W |
0x2C40 |
Max High Voltage Threshold Ch 24** |
R/W |
0x20C4 |
Upper Voltage Threshold Ch 1** |
R/W |
0x2144 |
Upper Voltage Threshold Ch 2** |
R/W |
0x21C4 |
Upper Voltage Threshold Ch 3** |
R/W |
0x2244 |
Upper Voltage Threshold Ch 4** |
R/W |
0x22C4 |
Upper Voltage Threshold Ch 5** |
R/W |
0x2344 |
Upper Voltage Threshold Ch 6** |
R/W |
0x23C4 |
Upper Voltage Threshold Ch 7** |
R/W |
0x2444 |
Upper Voltage Threshold Ch 8** |
R/W |
0x24C4 |
Upper Voltage Threshold Ch 9** |
R/W |
0x2544 |
Upper Voltage Threshold Ch 10** |
R/W |
0x25C4 |
Upper Voltage Threshold Ch 11** |
R/W |
0x2644 |
Upper Voltage Threshold Ch 12** |
R/W |
0x26C4 |
Upper Voltage Threshold Ch 13** |
R/W |
0x2744 |
Upper Voltage Threshold Ch 14** |
R/W |
0x27C4 |
Upper Voltage Threshold Ch 15** |
R/W |
0x2844 |
Upper Voltage Threshold Ch 16** |
R/W |
0x28C4 |
Upper Voltage Threshold Ch 17** |
R/W |
0x2944 |
Upper Voltage Threshold Ch 18** |
R/W |
0x29C4 |
Upper Voltage Threshold Ch 19** |
R/W |
0x2A44 |
Upper Voltage Threshold Ch 20** |
R/W |
0x2AC4 |
Upper Voltage Threshold Ch 21** |
R/W |
0x2B44 |
Upper Voltage Threshold Ch 22** |
R/W |
0x2BC4 |
Upper Voltage Threshold Ch 23** |
R/W |
0x2C44 |
Upper Voltage Threshold Ch 24** |
R/W |
0x20C8 |
Lower Voltage Threshold Ch 1** |
R/W |
0x2148 |
Lower Voltage Threshold Ch 2** |
R/W |
0x21C8 |
Lower Voltage Threshold Ch 3** |
R/W |
0x2248 |
Lower Voltage Threshold Ch 4** |
R/W |
0x22C8 |
Lower Voltage Threshold Ch 5** |
R/W |
0x2348 |
Lower Voltage Threshold Ch 6** |
R/W |
0x23C8 |
Lower Voltage Threshold Ch 7** |
R/W |
0x2448 |
Lower Voltage Threshold Ch 8** |
R/W |
0x24C8 |
Lower Voltage Threshold Ch 9** |
R/W |
0x2548 |
Lower Voltage Threshold Ch 10** |
R/W |
0x25C8 |
Lower Voltage Threshold Ch 11** |
R/W |
0x2648 |
Lower Voltage Threshold Ch 12** |
R/W |
0x26C8 |
Lower Voltage Threshold Ch 13** |
R/W |
0x2748 |
Lower Voltage Threshold Ch 14** |
R/W |
0x27C8 |
Lower Voltage Threshold Ch 15** |
R/W |
0x2848 |
Lower Voltage Threshold Ch 16** |
R/W |
0x28C8 |
Lower Voltage Threshold Ch 17** |
R/W |
0x2948 |
Lower Voltage Threshold Ch 18** |
R/W |
0x29C8 |
Lower Voltage Threshold Ch 19** |
R/W |
0x2A48 |
Lower Voltage Threshold Ch 20** |
R/W |
0x2AC8 |
Lower Voltage Threshold Ch 21** |
R/W |
0x2B48 |
Lower Voltage Threshold Ch 22** |
R/W |
0x2BC8 |
Lower Voltage Threshold Ch 23** |
R/W |
0x2C48 |
Lower Voltage Threshold Ch 24** |
R/W |
0x20CC |
Min Low Voltage Threshold Ch 1** |
R/W |
0x214C |
Min Low Voltage Threshold Ch 2** |
R/W |
0x21CC |
Min Low Voltage Threshold Ch 3** |
R/W |
0x224C |
Min Low Voltage Threshold Ch 4** |
R/W |
0x22CC |
Min Low Voltage Threshold Ch 5** |
R/W |
0x234C |
Min Low Voltage Threshold Ch 6** |
R/W |
0x23CC |
Min Low Voltage Threshold Ch 7** |
R/W |
0x244C |
Min Low Voltage Threshold Ch 8** |
R/W |
0x24CC |
Min Low Voltage Threshold Ch 9** |
R/W |
0x254C |
Min Low Voltage Threshold Ch 10** |
R/W |
0x25CC |
Min Low Voltage Threshold Ch 11** |
R/W |
0x264C |
Min Low Voltage Threshold Ch 12** |
R/W |
0x26CC |
Min Low Voltage Threshold Ch 13** |
R/W |
0x274C |
Min Low Voltage Threshold Ch 14** |
R/W |
0x27CC |
Min Low Voltage Threshold Ch 15** |
R/W |
0x284C |
Min Low Voltage Threshold Ch 16** |
R/W |
0x28CC |
Min Low Voltage Threshold Ch 17** |
R/W |
0x294C |
Min Low Voltage Threshold Ch 18** |
R/W |
0x29CC |
Min Low Voltage Threshold Ch 19** |
R/W |
0x2A4C |
Min Low Voltage Threshold Ch 20** |
R/W |
0x2ACC |
Min Low Voltage Threshold Ch 21** |
R/W |
0x2B4C |
Min Low Voltage Threshold Ch 22** |
R/W |
0x2BCC |
Min Low Voltage Threshold Ch 23** |
R/W |
0x2C4C |
Min Low Voltage Threshold Ch 24** |
R/W |
Discrete Input/Output Measurement Registers
0x20E0 |
Voltage Reading Ch 1** |
R |
0x2160 |
Voltage Reading Ch 2** |
R |
0x21E0 |
Voltage Reading Ch 3** |
R |
0x2260 |
Voltage Reading Ch 4** |
R |
0x22E0 |
Voltage Reading Ch 5** |
R |
0x2360 |
Voltage Reading Ch 6** |
R |
0x23E0 |
Voltage Reading Ch 7** |
R |
0x2460 |
Voltage Reading Ch 8** |
R |
0x24E0 |
Voltage Reading Ch 9** |
R |
0x2560 |
Voltage Reading Ch 10** |
R |
0x25E0 |
Voltage Reading Ch 11** |
R |
0x2660 |
Voltage Reading Ch 12** |
R |
0x26E0 |
Voltage Reading Ch 13** |
R |
0x2760 |
Voltage Reading Ch 14** |
R |
0x27E0 |
Voltage Reading Ch 15** |
R |
0x2860 |
Voltage Reading Ch 16** |
R |
0x28E0 |
Voltage Reading Ch 17** |
R |
0x2960 |
Voltage Reading Ch 18** |
R |
0x29E0 |
Voltage Reading Ch 19** |
R |
0x2A60 |
Voltage Reading Ch 20** |
R |
0x2AE0 |
Voltage Reading Ch 21** |
R |
0x2B60 |
Voltage Reading Ch 22** |
R |
0x2BE0 |
Voltage Reading Ch 23** |
R |
0x2C60 |
Voltage Reading Ch 24** |
R |
0x20E4 |
Current Reading Ch 1** |
R |
0x2164 |
Current Reading Ch 2** |
R |
0x21E4 |
Current Reading Ch 3** |
R |
0x2264 |
Current Reading Ch 4** |
R |
0x22E4 |
Current Reading Ch 5** |
R |
0x2364 |
Current Reading Ch 6** |
R |
0x23E4 |
Current Reading Ch 7** |
R |
0x2464 |
Current Reading Ch 8** |
R |
0x24E4 |
Current Reading Ch 9** |
R |
0x2564 |
Current Reading Ch 10** |
R |
0x25E4 |
Current Reading Ch 11** |
R |
0x2664 |
Current Reading Ch 12** |
R |
0x26E4 |
Current Reading Ch 13** |
R |
0x2764 |
Current Reading Ch 14** |
R |
0x27E4 |
Current Reading Ch 15** |
R |
0x2864 |
Current Reading Ch 16** |
R |
0x28E4 |
Current Reading Ch 17** |
R |
0x2964 |
Current Reading Ch 18** |
R |
0x29E4 |
Current Reading Ch 19** |
R |
0x2A64 |
Current Reading Ch 20** |
R |
0x2AE4 |
Current Reading Ch 21** |
R |
0x2B64 |
Current Reading Ch 22** |
R |
0x2BE4 |
Current Reading Ch 23** |
R |
0x2C64 |
Current Reading Ch 24** |
R |
VCC Bank Registers
0x1104 |
Select Pull-Up or Pull-Down |
R/W |
Pull-Up/Down Current
0x20D0 |
Pull-Up/Down Current Bank 1 (Ch1-6)** |
R/W |
0x2150 |
Pull-Up/Down Current Bank 2 (Ch7-12)** |
R/W |
0x21D0 |
Pull-Up/Down Current Bank 3 (Ch13-18)** |
R/W |
0x2250 |
Pull-Up/Down Current Bank 4 (Ch19-24)** |
R/W |
VCC Voltage Reading
0x20EC |
VCC Voltage Reading Bank 1 (Ch 1-6)** |
R |
0x216C |
VCC Voltage Reading Bank 2 (Ch 7-12)** |
R |
0x21EC |
VCC Voltage Reading Bank 3 (Ch 13-18)** |
R |
0x226C |
VCC Voltage Reading Bank 4 (Ch 19-24)** |
R |
Discrete Input/Output Control Registers
0x20D4 |
Debounce Time Ch 1 |
R/W |
0x2154 |
Debounce Time Ch 2 |
R/W |
0x21D4 |
Debounce Time Ch 3 |
R/W |
0x2254 |
Debounce Time Ch 4 |
R/W |
0x22D4 |
Debounce Time Ch 5 |
R/W |
0x2354 |
Debounce Time Ch 6 |
R/W |
0x23D4 |
Debounce Time Ch 7 |
R/W |
0x2454 |
Debounce Time Ch 8 |
R/W |
0x24D4 |
Debounce Time Ch 9 |
R/W |
0x2554 |
Debounce Time Ch 10 |
R/W |
0x25D4 |
Debounce Time Ch 11 |
R/W |
0x2654 |
Debounce Time Ch 12 |
R/W |
0x26D4 |
Debounce Time Ch 13 |
R/W |
0x2754 |
Debounce Time Ch 14 |
R/W |
0x27D4 |
Debounce Time Ch 15 |
R/W |
0x2854 |
Debounce Time Ch 16 |
R/W |
0x28D4 |
Debounce Time Ch 17 |
R/W |
0x2954 |
Debounce Time Ch 18 |
R/W |
0x29D4 |
Debounce Time Ch 19 |
R/W |
0x2A54 |
Debounce Time Ch 20 |
R/W |
0x2AD4 |
Debounce Time Ch 21 |
R/W |
0x2B54 |
Debounce Time Ch 22 |
R/W |
0x2BD4 |
Debounce Time Ch 23 |
R/W |
0x2C54 |
Debounce Time Ch 24 |
R/W |
0x1100 |
Overcurrent Reset |
R/W |
Unit Conversion Programming Registers
0x02B4 |
Enable Floating Point |
R/W |
0x0264 |
Floating Point State |
R |
User Watchdog Timer Programming Registers
Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Status Function Register Map.
Module Common Registers
Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.
Status Registers
0x02B0 |
Channel Status Enabled |
R/W |
BIT Status
0x0800 |
Dynamic Status |
R |
0x0804 |
Latched Status* |
R/W |
0x0808 |
Interrupt Enable |
R/W |
0x080C |
Set Edge/Level Interrupt |
R/W |
Voltage Reading Error
0x1200 |
Voltage Reading Error Dynamic |
R |
0x1204 |
Voltage Reading Error Latched* |
R/W |
0x1208 |
Driver Error Dynamic |
R |
0x120C |
Driver Error Latched* |
R/W |
Background BIT Threshold Programming Registers
0x02B8 |
Background BIT Threshold |
R/W |
0x02BC |
BIT Count Clear |
W |
Status Registers
Low-to-High Transition Status
0x0810 |
Dynamic Status |
R |
0x0814 |
Latched Status* |
R/W |
0x0818 |
Interrupt Enable |
R/W |
0x081C |
Set Edge/Level Interrupt |
R/W |
High-to-Low Transition Status
0x0820 |
Dynamic Status |
R |
0x0824 |
Latched Status* |
R/W |
0x0828 |
Interrupt Enable |
R/W |
0x082C |
Set Edge/Level Interrupt |
R/W |
Overcurrent Status
0x0830 |
Dynamic Status |
R |
0x0834 |
Latched Status* |
R/W |
0x0838 |
Interrupt Enable |
R/W |
0x083C |
Set Edge/Level Interrupt |
R/W |
Above Max High Voltage Status
0x0840 |
Dynamic Status |
R |
0x0844 |
Latched Status* |
R/W |
0x0848 |
Interrupt Enable |
R/W |
0x084C |
Set Edge/Level Interrupt |
R/W |
Below Min High Voltage Status
0x0850 |
Dynamic Status |
R |
0x0854 |
Latched Status* |
R/W |
0x0858 |
Interrupt Enable |
R/W |
0x085C |
Set Edge/Level Interrupt |
R/W |
Mid-Range Voltage Status
0x0860 |
Dynamic Status |
R |
0x0864 |
Latched Status* |
R/W |
0x0868 |
Interrupt Enable |
R/W |
0x086C |
Set Edge/Level Interrupt |
R/W |
User Watchdog Timer Fault Status
The Discrete Modules provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status Function Register Map.
Summary Status
0x09A0 |
Dynamic Status |
R |
0x09A4 |
Latched Status* |
R/W |
0x09A8 |
Interrupt Enable |
R/W |
0x09AC |
Set Edge/Level Interrupt |
R/W |
Enhanced Functionality Registers
Refer to “Enhanced Discrete I/O, Digital I/O Functionality – Module Manual” for the Function Register Map
Interrupt Registers
The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.
0x0500 |
Module 1 Interrupt Vector 1 - BIT |
R/W |
0x0504 |
Module 1 Interrupt Vector 2 - Low-High |
R/W |
0x0508 |
Module 1 Interrupt Vector 3 - High-Low |
R/W |
0x050C |
Module 1 Interrupt Vector 4 - Overcurrent |
R/W |
0x0510 |
Module 1 Interrupt Vector 5 - Max-High |
R/W |
0x0514 |
Module 1 Interrupt Vector 6 - Min-Low |
R/W |
0x0518 |
Module 1 Interrupt Vector 7 - Mid Range |
R/W |
0x051C |
Module 1 Interrupt Vector 8 - Reserved |
R/W |
0x0520 |
Module 1 Interrupt Vector 9 - Inter-FPGA Failure |
|
0x0524 to 0x0564 |
Module 1 Interrupt Vector 10 - 26 - Reserved |
|
R/W |
0x0568 |
Module 1 Interrupt Vector 27 – Summary |
R/W |
0x056C |
Module 1 Interrupt Vector 28 – User Watchdog Timer Fault |
R/W |
0x0570 to 0x057C |
Module 1 Interrupt Vector 29-32 - Reserved |
0x0600 |
Module 1 Interrupt Steering 1 - BIT |
R/W |
0x0604 |
Module 1 Interrupt Steering 2 - Low-High |
R/W |
0x0608 |
Module 1 Interrupt Steering 3 - High-Low |
R/W |
0x060C |
Module 1 Interrupt Steering 4 - Overcurrent |
R/W |
0x0610 |
Module 1 Interrupt Steering 5 - Max-High |
R/W |
0x0614 |
Module 1 Interrupt Steering 6 - Min-Low |
R/W |
0x0618 |
Module 1 Interrupt Steering 7 - Mid Range |
R/W |
0x061C |
Module 1 Interrupt Steering 8 - Reserved |
R/W |
R/W |
0x0620 |
|
Module 1 Interrupt Steering 9 - Inter-FPGA Failure |
||
R/W |
0x0624 to 0x0664 |
|
Module 1 Interrupt Steering 10 - 26 - Reserved |
R/W |
0x0668 |
Module 1 Interrupt Steering 27 – Summary |
R/W |
0x066C |
Module 1 Interrupt Steering 28 – User Watchdog Timer Fault |
R/W |
0x0670 to 0x067C |
Module 1 Interrupt Steering 29-32 - Reserved |
0x0700 |
Module 2 Interrupt Vector 1 - BIT |
R/W |
0x0704 |
Module 2 Interrupt Vector 2 - Low-High |
R/W |
0x0708 |
Module 2 Interrupt Vector 3 - High-Low |
R/W |
0x070C |
Module 2 Interrupt Vector 4 - Overcurrent |
R/W |
0x0710 |
Module 2 Interrupt Vector 5 - Max-High |
R/W |
0x0714 |
Module 2 Interrupt Vector 6 - Min-Low |
R/W |
0x0718 |
Module 2 Interrupt Vector 7 - Mid Range |
R/W |
0x071C |
Module 2 Interrupt Vector 8 - Reserved |
R/W |
0x0720 |
Module 2 Interrupt Vector 9 - Inter-FPGA Failure |
R/W |
0x0724 to 0x0764 |
Module 2 Interrupt Vector 10 - 26 - Reserved |
R/W |
0x0768 |
Module 2 Interrupt Vector 27 – Summary |
R/W |
0x076C |
Module 2 Interrupt Vector 28 – User Watchdog Timer Fault |
R/W |
0x0770 to 0x077C |
Module 2 Interrupt Vector 29-32 - Reserved |
R/W |
0x0800 |
Module 2 Interrupt Steering 1 - BIT |
R/W |
0x0804 |
Module 2 Interrupt Steering 2 - Low-High |
R/W |
0x0808 |
Module 2 Interrupt Steering 3 - High-Low |
R/W |
0x080C |
Module 2 Interrupt Steering 4 - Overcurrent |
R/W |
0x0810 |
Module 2 Interrupt Steering 5 - Max-High |
R/W |
0x0814 |
Module 2 Interrupt Steering 6 - Min-Low |
R/W |
0x0818 |
Module 2 Interrupt Steering 7 - Mid Range |
R/W |
0x081C |
Module 2 Interrupt Steering 8 - Reserved |
R/W |
0x0820 |
Module 2 Interrupt Steering 9 - Inter-FPGA Failure |
R/W |
0x0824 to 0x0864 |
Module 2 Interrupt Steering 10 - 26 - Reserved |
R/W |
0x0868 |
Module 2 Interrupt Steering 27 – Summary |
R/W |
0x086C |
Module 2 Interrupt Steering 28 – User Watchdog Timer Fault |
R/W |
0x0870 to 0x087C |
Module 2 Interrupt Steering 29-32 - Reserved |
R/W |
0x0900 |
Module 3 Interrupt Vector 1 - BIT |
R/W |
0x0904 |
Module 3 Interrupt Vector 2 - Low-High |
R/W |
0x0908 |
Module 3 Interrupt Vector 3 - High-Low |
R/W |
0x090C |
Module 3 Interrupt Vector 4 - Overcurrent |
R/W |
0x0910 |
Module 3 Interrupt Vector 5 - Max-High |
R/W |
0x0914 |
Module 3 Interrupt Vector 6 - Min-Low |
R/W |
0x0918 |
Module 3 Interrupt Vector 7 - Mid Range |
R/W |
0x091C |
Module 3 Interrupt Vector 8 - Reserved |
R/W |
0x0920 |
Module 3 Interrupt Vector 9 - Inter-FPGA Failure |
R/W |
0x0924 to 0x0964 |
Module 3 Interrupt Vector 10 - 26 - Reserved |
R/W |
0x0968 |
Module 3 Interrupt Vector 27 – Summary |
R/W |
0x096C |
Module 3 Interrupt Vector 28 – User Watchdog Timer Fault |
R/W |
0x0970 to 0x097C |
Module 3 Interrupt Vector 29-32 - Reserved |
R/W |
0x0A00 |
Module 3 Interrupt Steering 1 - BIT |
R/W |
0x0A04 |
Module 3 Interrupt Steering 2 - Low-High |
R/W |
0x0A08 |
Module 3 Interrupt Steering 3 - High-Low |
R/W |
0x0A0C |
Module 3 Interrupt Steering 4 - Overcurrent |
R/W |
0x0A10 |
Module 3 Interrupt Steering 5 - Max-High |
R/W |
0x0A14 |
Module 3 Interrupt Steering 6 - Min-Low |
R/W |
0x0A18 |
Module 3 Interrupt Steering 7 - Mid Range |
R/W |
0x0A1C |
Module 3 Interrupt Steering 8 - Reserved |
R/W |
0x0A20 |
Module 3 Interrupt Steering 9 - Inter-FPGA Failure |
R/W |
0x0A24 to 0x0A64 |
Module 3 Interrupt Steering 10 - 26 - Reserved |
R/W |
0x0A68 |
Module 3 Interrupt Steering 27 – Summary |
R/W |
0x0A6C |
Module 3 Interrupt Steering 28 – User Watchdog Timer Fault |
R/W |
0x0A70 to 0x0A7C |
Module 3 Interrupt Steering 29-32 - Reserved |
R/W |
0x0B00 |
Module 4 Interrupt Vector 1 - BIT |
R/W |
0x0B04 |
Module 4 Interrupt Vector 2 - Low-High |
R/W |
0x0B08 |
Module 4 Interrupt Vector 3 - High-Low |
R/W |
0x0B0C |
Module 4 Interrupt Vector 4 - Overcurrent |
R/W |
0x0B10 |
Module 4 Interrupt Vector 5 - Max-High |
R/W |
0x0B14 |
Module 4 Interrupt Vector 6 - Min-Low |
R/W |
0x0B18 |
Module 4 Interrupt Vector 7 - Mid Range |
R/W |
0x0B1C |
Module 4 Interrupt Vector 8 - Reserved |
R/W |
0x0B20 |
Module 4 Interrupt Vector 9 - Inter-FPGA Failure |
R/W |
0x0B24 to 0x0B64 |
Module 4 Interrupt Vector 10 - 26 - Reserved |
R/W |
0x0B68 |
Module 4 Interrupt Vector 27 – Summary |
R/W |
0x0B6C |
Module 4 Interrupt Vector 28 – User Watchdog Timer Fault |
R/W |
0x0B70 to 0x0B7C |
Module 4 Interrupt Vector 29-32 - Reserved |
R/W |
0x0C00 |
Module 4 Interrupt Steering 1 - BIT |
R/W |
0x0C04 |
Module 4 Interrupt Steering 2 - Low-High |
R/W |
0x0C08 |
Module 4 Interrupt Steering 3 - High-Low |
R/W |
0x0C0C |
Module 4 Interrupt Steering 4 - Overcurrent |
R/W |
0x0C10 |
Module 4 Interrupt Steering 5 - Max-High |
R/W |
0x0C14 |
Module 4 Interrupt Steering 6 - Min-Low |
R/W |
0x0C18 |
Module 4 Interrupt Steering 7 - Mid Range |
R/W |
0x0C1C |
Module 4 Interrupt Steering 8 - Reserved |
R/W |
0x0C20 |
Module 4 Interrupt Steering 9 - Inter-FPGA Failure |
R/W |
0x0C24 to 0x0C64 |
Module 4 Interrupt Steering 10 - 26 - Reserved |
R/W |
0x0C68 |
Module 4 Interrupt Steering 27 – Summary |
R/W |
0x0C6C |
Module 4 Interrupt Steering 28 – User Watchdog Timer Fault |
R/W |
0x0C70 to 0x0C7C |
Module 4 Interrupt Steering 29-32 - Reserved |
R/W |
0x0D00 |
Module 5 Interrupt Vector 1 - BIT |
R/W |
0x0D04 |
Module 5 Interrupt Vector 2 - Low-High |
R/W |
0x0D08 |
Module 5 Interrupt Vector 3 - High-Low |
R/W |
0x0D0C |
Module 5 Interrupt Vector 4 - Overcurrent |
R/W |
0x0D10 |
Module 5 Interrupt Vector 5 - Max-High |
R/W |
0x0D14 |
Module 5 Interrupt Vector 6 - Min-Low |
R/W |
0x0D18 |
Module 5 Interrupt Vector 7 - Mid Range |
R/W |
0x0D1C |
Module 5 Interrupt Vector 8 - Reserved |
R/W |
0x0D20 |
Module 5 Interrupt Vector 9 - Inter-FPGA Failure |
R/W |
0x0D24 to 0x0D64 |
Module 5 Interrupt Vector 10 - 26 - Reserved |
R/W |
0x0D68 |
Module 5 Interrupt Vector 27 – Summary |
R/W |
0x0D6C |
Module 5 Interrupt Vector 28 – User Watchdog Timer Fault |
R/W |
0x0D70 to 0x0D7C |
Module 5 Interrupt Vector 29-32 - Reserved |
R/W |
0x0E00 |
Module 5 Interrupt Steering 1 - BIT |
R/W |
0x0E04 |
Module 5 Interrupt Steering 2 - Low-High |
R/W |
0x0E08 |
Module 5 Interrupt Steering 3 - High-Low |
R/W |
0x0E0C |
Module 5 Interrupt Steering 4 - Overcurrent |
R/W |
0x0E10 |
Module 5 Interrupt Steering 5 - Max-High |
R/W |
0x0E14 |
Module 5 Interrupt Steering 6 - Min-Low |
R/W |
0x0E18 |
Module 5 Interrupt Steering 7 - Mid Range |
R/W |
0x0E1C |
Module 5 Interrupt Steering 8 - Reserved |
R/W |
0x0E20 |
Module 5 Interrupt Steering 9 - Inter-FPGA Failure |
R/W |
0x0E24 to 0x0E64 |
Module 5 Interrupt Steering 10 - 26 - Reserved |
R/W |
0x0E68 |
Module 5 Interrupt Steering 27 – Summary |
R/W |
0x0E6C |
Module 5 Interrupt Steering 28 – User Watchdog Timer Fault |
R/W |
0x0E70 to 0x0E7C |
Module 5 Interrupt Steering 29-32 - Reserved |
R/W |
0x0F00 |
Module 6 Interrupt Vector 1 - BIT |
R/W |
0x0F04 |
Module 6 Interrupt Vector 2 - Low-High |
R/W |
0x0F08 |
Module 6 Interrupt Vector 3 - High-Low |
R/W |
0x0F0C |
Module 6 Interrupt Vector 4 - Overcurrent |
R/W |
0x0F10 |
Module 6 Interrupt Vector 5 - Max-High |
R/W |
0x0F14 |
Module 6 Interrupt Vector 6 - Min-Low |
R/W |
0x0F18 |
Module 6 Interrupt Vector 7 - Mid Range |
R/W |
0x0F1C |
Module 6 Interrupt Vector 8 - Reserved |
R/W |
0x0F20 |
Module 6 Interrupt Vector 9 - Inter-FPGA Failure |
R/W |
0x0F24 to 0x0F64 |
Module 6 Interrupt Vector 10 - 26 - Reserved |
R/W |
0x0F68 |
Module 6 Interrupt Vector 27 – Summary |
R/W |
0x0F6C |
Module 6 Interrupt Vector 28 – User Watchdog Timer Fault |
R/W |
0x0F70 to 0x0F7C |
Module 6 Interrupt Vector 29-32 - Reserved |
R/W |
0x1000 |
Module 6 Interrupt Steering 1 - BIT |
R/W |
0x1004 |
Module 6 Interrupt Steering 2 - Low-High |
R/W |
0x1008 |
Module 6 Interrupt Steering 3 - High-Low |
R/W |
0x100C |
Module 6 Interrupt Steering 4 - Overcurrent |
R/W |
0x1010 |
Module 6 Interrupt Steering 5 - Max-High |
R/W |
0x1014 |
Module 6 Interrupt Steering 6 - Min-Low |
R/W |
0x1018 |
Module 6 Interrupt Steering 7 - Mid Range |
R/W |
0x101C |
Module 6 Interrupt Steering 8 - Reserved |
R/W |
0x1020 |
Module 6 Interrupt Steering 9 - Inter-FPGA Failure |
R/W |
0x1024 to 0x1064 |
Module 6 Interrupt Steering 10 - 26 - Reserved |
R/W |
0x1068 |
Module 6 Interrupt Steering 27 – Summary |
R/W |
0x106C |
Module 6 Interrupt Steering 28 – User Watchdog Timer Fault |
R/W |
0x1070 to 0x107C |
Module 6 Interrupt Steering 29-32 - Reserved |
R/W |
0x1100 |
Module 7 Interrupt Vector 1 - BIT |
R/W |
0x1104 |
Module 7 Interrupt Vector 2 - Low-High |
R/W |
0x1108 |
Module 7 Interrupt Vector 3 - High-Low |
R/W |
0x110C |
Module 7 Interrupt Vector 4 - Overcurrent |
R/W |
0x1110 |
Module 7 Interrupt Vector 5 - Max-High |
R/W |
0x1114 |
Module 7 Interrupt Vector 6 - Min-Low |
R/W |
0x1118 |
Module 7 Interrupt Vector 7 - Mid Range |
R/W |
0x111C |
Module 7 Interrupt Vector 8 - Reserved |
R/W |
0x1120 |
Module 7 Interrupt Vector 9 - Inter-FPGA Failure |
R/W |
0x1124 to 0x1164 |
Module 7 Interrupt Vector 10 - 26 - Reserved |
R/W |
0x1168 |
Module 7 Interrupt Vector 27 – Summary |
R/W |
0x116C |
Module 7 Interrupt Vector 28 – User Watchdog Timer Fault |
R/W |
0x1170 to 0x117C |
Module 7 Interrupt Vector 29-32 - Reserved |
R/W |
0x1200 |
Module 7 Interrupt Steering 1 - BIT |
R/W |
0x1204 |
Module 7 Interrupt Steering 2 - Low-High |
R/W |
0x1208 |
Module 7 Interrupt Steering 3 - High-Low |
R/W |
0x120C |
Module 7 Interrupt Steering 4 - Overcurrent |
R/W |
0x1210 |
Module 7 Interrupt Steering 5 - Max-High |
R/W |
0x1214 |
Module 7 Interrupt Steering 6 - Min-Low |
R/W |
0x1218 |
Module 7 Interrupt Steering 7 - Mid Range |
R/W |
0x121C |
Module 7 Interrupt Steering 8 - Reserved |
R/W |
0x1220 |
Module 7 Interrupt Steering 9 - Inter-FPGA Failure |
R/W |
0x1224 to 0x1264 |
Module 7 Interrupt Steering 10 - 26 - Reserved |
R/W |
0x1268 |
Module 7 Interrupt Steering 27 – Summary |
R/W |
0x126C |
Module 7 Interrupt Steering 28 – User Watchdog Timer Fault |
R/W |
0x1270 to 0x127C |
Module 7 Interrupt Steering 29-32 - Reserved |
R/W |
0x01C0 |
UWDT Quiet Time |
R/W |
0x01C4 |
UWDT Window |
R/W |
0x01C8 |
UWDT Strobe |
W |
Status Registers
User Watchdog Timer Fault/Inter-FPGA Failure
0x09B0 |
Dynamic Status |
R |
0x09B4 |
Latched Status* |
R/W |
0x09B8 |
Interrupt Enable |
R/W |
0x09BC |
Set Edge/Level Interrupt |
R/W |
Interrupt Register
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.
0x056C |
Module 1 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x076C |
Module 2 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x096C |
Module 3 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0B6C |
Module 4 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0D6C |
Module 5 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0F6C |
Module 6 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x066C |
Module 1 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x086C |
Module 2 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0A6C |
Module 3 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0C6C |
Module 4 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0E6C |
Module 5 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x106C |
Module 6 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
APPENDIX A: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
This section provides a mapping of the register names used in this document against register names used in previous releases.
Rev C2 - Register Names |
Rev B - Register Names |
== Discrete Input/Output Registers |
|
I/O Format Ch1-16 |
Input/Output Format Low |
||
I/O Format Ch17-24 |
Input/Output Format High |
||
Write Outputs |
Write Outputs |
||
Input/Output State |
Input/Output State |
== Discrete I/O Threshold Programming Registers |
|
Max High Voltage Threshold |
Max High Threshold |
||
Upper Voltage Threshold |
Upper Threshold |
Lower Voltage Threshold |
|
Lower Threshold |
Min Low Voltage Threshold |
Min Low Threshold |
|
== Discrete I/O Input/Output Measurement Registers |
Voltage Reading |
Voltage Reading |
|
Current Reading |
Current Reading |
||
== VCC Bank Registers |
Select Pull-Up or Pull-Down |
Select Pullup or Pulldown |
|
Pull-Up/Down Current |
Current for Source/Sink |
||
VCC Voltage Reading |
VCC Bank Reading |
||
== Discrete Input/Output Control Registers |
Debounce Time |
Debounce Time |
|
Overcurrent Reset |
Overcurrent Reset |
||
== Unit Conversion Registers |
Enable Floating Point Mode |
Enable Floating Point Mode |
|
Floating Point State |
Floating Point State |
||
== Background BIT Threshold Programming Registers |
Background BIT Threshold |
Background BIT Threshold |
|
BIT Count Clear |
Reset BIT |
||
== User Watchdog Timer Programming Registers |
Refer to “User Watchdog Timer Module Manual” |
Refer to “User Watchdog Timer Module Manual” |
|
== Status and Interrupt Registers |
Channel Status Enable |
Channel Status Enabled |
|
BIT Dynamic Status |
BIT Dynamic Status |
||
BIT Latched Status |
BIT Latched Status |
||
BIT Interrupt Enable |
BIT Interrupt Enable |
||
BIT Set Edge/Level Interrupt |
BIT Set Edge/Level Interrupt |
||
Voltage Reading Error Dynamic |
Voltage Reading Error Dynamic |
||
Voltage Reading Error Latched |
Voltage Reading Error Latched |
Rev C2 - Register Names |
Rev B - Register Names |
== Status and Interrupt Registers |
|
Drive Error Dynamic |
Drive Error Dynamic |
||
Drive Error Latched |
Drive Error Latched |
||
Low-to-High Transition Dynamic Status |
Low-to-High Transition Dynamic Status |
||
Low-to-High Transition Latched Status |
Low-to-High Transition Latched Status |
||
Low-to-High Transition Interrupt Enable |
Low-to-High Transition Interrupt Enable |
||
Low-to-High Transition Set Edge/Level Interrupt |
Low-to-High Transition Set Edge/Level Interrupt |
||
High-to-Low Transition Dynamic Status |
High-to-Low Transition Dynamic Status |
||
High-to-Low Transition Latched Status |
High-to-Low Transition Latched Status |
||
High-to-Low Transition Interrupt Enable |
High-to-Low Transition Interrupt Enable |
||
High-to-Low Transition Set Edge/Level Interrupt |
High-to-Low Transition Set Edge/Level Interrupt |
||
Overcurrent Dynamic Status |
Overcurrent Dynamic Status |
||
Overcurrent Latched Status |
Overcurrent Latched Status |
||
Overcurrent Interrupt Enable |
Overcurrent Interrupt Enable |
||
Overcurrent Set Edge/Level Interrupt |
Overcurrent Set Edge/Level Interrupt |
||
Above Max High Voltage Dynamic Status |
Above Max High Threshold Dynamic Status |
||
Above Max High Voltage Latched Status |
Above Max High Threshold Latched Status |
||
Above Max High Voltage Interrupt Enable |
Above Max High Threshold Interrupt Enable |
||
Above Max High Voltage Set Edge/Level Interrupt |
Above Max High Threshold Set Edge/Level Interrupt |
||
Below Min Low Voltage Dynamic Status |
Below Min Low Threshold Dynamic Status |
||
Below Min Low Voltage Latched Status |
Below Min Low Threshold Latched Status |
||
Below Min Low Voltage Interrupt Enable |
Below Min Low Threshold Interrupt Enable |
||
Below Min Low Voltage Set Edge/Level Interrupt |
Below Min Low Threshold Set Edge/Level Interrupt/Level Interrupt |
||
Mid-Range Voltage Dynamic Status |
Mid-Range Dynamic Status |
||
Mid-Range Voltage Latched Status |
Mid-Range Latched Status |
||
Mid-Range Voltage Interrupt Enable |
Mid-Range Interrupt Enable |
||
Mid-Range Voltage Set Edge/Level Interrupt |
Mid-Range Set Edge/Level Interrupt |
||
User Watchdog Timer Fault Dynamic Status |
User Watchdog Timer Fault Dynamic Status |
||
User Watchdog Timer Fault Latched Status |
User Watchdog Timer Fault Latched Status |
||
User Watchdog Timer Fault Interrupt Enable |
User Watchdog Timer Fault Interrupt Enable |
||
User Watchdog Timer Fault Set Edge/Level Interrupt |
User Watchdog Timer Fault Set Edge/Level Interrupt |
||
Summary Dynamic Status |
Summary Dynamic Status |
||
Summary Latched Status |
Summary Latched Status |
||
Summary Interrupt Enable |
Summary Interrupt Enable |
||
Summary Set Edge/Level Interrupt |
Summary Set Edge/Level Interrupt |
APPENDIX B: PIN-OUT DETAILS
Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals.
Module Signal (Ref Only) |
Discrete (DT4) |
||
DATIO1 |
IO-CH01 |
||
DATIO2 |
IO-CH02 |
||
DATIO3 |
IO-CH03 |
||
DATIO4 |
IO-CH04 |
||
DATIO5 |
VCC1 (1-6) |
||
DATIO6 |
GND |
||
DATIO7 |
IO-CH07 |
||
DATIO8 |
IO-CH08 |
||
DATIO9 |
IO-CH09 |
||
DATIO10 |
IO-CH10 |
||
DATIO11 |
VCC2 (7-12) |
||
DATIO12 |
GND |
||
DATIO13 |
IO-CH13 |
||
DATIO14 |
IO-CH14 |
||
DATIO15 |
IO-CH15 |
||
DATIO16 |
IO-CH16 |
||
DATIO17 |
VCC3 (13-18) |
||
DATIO18 |
GND |
||
DATIO19 |
IO-CH19 |
||
DATIO20 |
IO-CH20 |
||
DATIO21 |
IO-CH21 |
||
DATIO22 |
IO-CH22 |
||
DATIO23 |
VCC4 (19-24) |
||
DATIO24 |
GND |
||
DATIO25 |
IO-CH05 |
||
DATIO26 |
IO-CH06 |
||
DATIO27 |
IO-CH11 |
||
DATIO28 |
IO-CH12 |
||
DATIO29 |
IO-CH17 |
||
DATIO30 |
IO-CH18 |
||
DATIO31 |
IO-CH23 |
||
DATIO32 |
IO-CH24 |
||
DATIO33 |
VCC1 (1-6) |
||
DATIO34 |
GND |
||
DATIO35 |
VCC2 (7-12) |
||
DATIO36 |
GND |
||
DATIO37 |
VCC3 (13-18) |
||
DATIO38 |
GND |
||
DATIO39 |
VCC4 (19-24) |
||
DATIO40 |
GND |
||
N/A |
STATUS AND INTERRUPTS
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Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.
For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.
Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.
Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).
Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.
Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).
-
Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edgetriggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
-
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Interrupt Trigger Types
In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.
Example 1: Fault detection
This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.
Example 2: Threshold detection
This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.
Dynamic and Latched Status Registers Examples
The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.
Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States
No Clearing of Latched Status |
Clearing of Latched Status (Edge-Triggered) |
Clearing of Latched Status (Level-Triggered) |
||||
Time |
Dynamic Status |
Latched Status |
Action |
Latched Status |
Action |
Latched |
T0 |
0x0 |
0x0 |
Read Latched Register |
0x0 |
Read Latched Register |
0x0 |
T1 |
0x1 |
0x1 |
Read Latched Register |
0x1 |
0x1 |
|
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
|||||
0x0 |
0x1 |
|||||
T2 |
0x0 |
0x1 |
Read Latched Register |
0x0 |
Read Latched Register |
0x1 |
Write 0x1 to Latched Register |
||||||
0x0 |
||||||
T3 |
0x2 |
0x3 |
Read Latched Register |
0x2 |
Read Latched Register |
0x2 |
Write 0x2 to Latched Register |
Write 0x2 to Latched Register |
|||||
0x0 |
0x2 |
|||||
T4 |
0x2 |
0x3 |
Read Latched Register |
0x1 |
Read Latched Register |
0x3 |
Write 0x1 to Latched Register |
Write 0x3 to Latched Register |
|||||
0x0 |
0x2 |
|||||
T5 |
0xC |
0xF |
Read Latched Register |
0xC |
Read Latched Register |
0xE |
Write 0xC to Latched Register |
Write 0xE to Latched Register |
|||||
0x0 |
0xC |
|||||
T6 |
0xC |
0xF |
Read Latched Register |
0x0 |
Read Latched |
0xC |
Write 0xC to Latched Register |
||||||
0xC |
||||||
T7 |
0x4 |
0xF |
Read Latched Register |
0x0 |
Read Latched Register |
0xC |
Write 0xC to Latched Register |
||||||
0x4 |
||||||
T8 |
0x4 |
0xF |
Read Latched Register |
0x0 |
Read Latched Register |
0x4 |
Interrupt Examples
The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.
Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled
Time |
Latched Status (Edge-Triggered – Clear Multi-Channel) |
Latched Status (Edge-Triggered – Clear Single Channel) |
Latched Status (Level-Triggered – Clear Multi-Channel) |
|||
Action |
Latched |
Action |
Latched |
Action |
Latched |
|
T1 (Int 1) |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x1 |
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
||||
0x0 |
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear until T2. |
0x1 |
|||
T3 (Int 2) |
Interrupt Generated Read Latched Registers |
0x2 |
Interrupt Generated Read Latched Registers |
0x2 |
Interrupt Generated Read Latched Registers |
0x2 |
Write 0x2 to Latched Register |
Write 0x2 to Latched Register |
Write 0x2 to Latched Register |
||||
0x0 |
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear until T7. |
0x2 |
|||
T4 (Int 3) |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x1 |
Interrupt Generated Read Latched Registers |
0x3 |
Write 0x1 to Latched Register |
Write 0x1 to Latched Register |
Write 0x3 to Latched Register |
||||
0x0 |
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5. |
0x3 |
|||
Interrupt re-triggers Note, interrupt re-triggers after each clear until T7. |
0x2 |
|||||
T6 (Int 4) |
Interrupt Generated Read Latched Registers |
0xC |
Interrupt Generated Read Latched Registers |
0xC |
Interrupt Generated Read Latched Registers |
0xE |
Write 0xC to Latched Register |
Write 0x4 to Latched Register |
Write 0xE to Latched Register |
||||
0x0 |
Interrupt re-triggers Write 0x8 to Latched Register |
0x8 |
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7. |
0xE |
||
0x0 |
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8. |
0xC |
||||
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always. |
0x4 |
USER WATCHDOG TIMER MODULE MANUAL
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User Watchdog Timer Capability
The User Watchdog Timer (UWDT) Capability is available on the following modules:
-
AC Reference Source Modules
-
AC1 - 1 Channel, 2-115 Vrms, 47 Hz - 20kHz
-
AC2 - 2 Channels, 2-28 Vrms, 47 Hz - 20kHz
-
AC3 - 1 Channel, 28-115 Vrms, 47 Hz - 2.5 kHz
-
-
Differential Transceiver Modules
-
DF1/DF2 - 16 Channels Differential I/O
-
-
Digital-to-Analog (D/A) Modules
-
DA1 - 12 Channels, ±10 VDC @ 25 mA, Voltage or Current Control Modes
-
DA2 - 16 Channels, ±10 VDC @ 10 mA
-
DA3 - 4 Channels, ±40 VDC @ ±100 mA, Voltage or Current Control Modes
-
DA4 - 4 Channels, ±80 VDC @ 10 mA
-
DA5 - 4 Channels, ±65 VDC or ±2 A, Voltage or Current Control Modes
-
-
Digital-to-Synchro/Resolver (D/S) or Digital-to-L( R )VDT (D/LV) Modules
-
(Not supported)
-
-
Discrete I/O Modules
-
DT1/DT4 - 24 Channels, Programmable for either input or output, output up to 500 mA per channel from an applied external 3 - 60 VCC source.
-
DT2/DT5 - 16 Channels, Programmable for either input voltage measurements (±80 V) or as a bi-directional current switch (up to 500 mA per channel).
-
DT3/DT6 - 4 Channels, Programmable for either input voltage measurements (±100 V) or as a bi-directional current switch (up to 3 A per channel).
-
-
TTL/CMOS Modules
-
TL1-TL8 - 24 Channels, Programmable for either input or output.
-
Principle of Operation
The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.
The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:
-
The application must not strobe during the Quiet time.
-
The application must strobe within the Window time.
-
The application must not strobe more than once in a single window time.
A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.
The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.
The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.
Figure 1. User Watchdog Timer Overview
Figure 2. User Watchdog Timer Example
Figure 3. User Watchdog Timer Failures
Register Descriptions
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.
User Watchdog Timer Registers
The registers associated with the User Watchdog Timer provide the ability to specify the UWDT Quiet Time and the UWDT Window that will be monitored to ensure that EXACTLY ONE User Watchdog Timer (UWDT) Strobe is written within the window.
UWDT Quiet Time
Function: Sets Quiet Time value (in microseconds) to use for the User Watchdog Timer Frame.
Type: unsigned binary word (32-bit)
Data Range: 0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write: R/W
Initialized Value: 0x0
Operational Settings: LSB = 1 µsec. The application must NOT write a strobe in the time between the previous strobe and the end of the Quiet time interval. In addition, the application must write in the UWDT Window EXACTLY ONCE.
UWDT Window
Function: Sets Window value (in microseconds) to use for the User Watchdog Timer Frame.
Type: unsigned binary word (32-bit)
Data Range: 0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write: R/W
Initialized Value: 0x0
Operational Settings: LSB = 1 µsec. The application must write the strobe once within the Window time after the end of the Quiet time interval. The application must write in the UWDT Window EXACTLY ONCE. This setting must be initialized to a non-zero value for operation and should allow sufficient tolerance for strobe timing by the application.
UWDT Strobe
Function: Writes the strobe value to be use for the User Watchdog Timer Frame.
Type: unsigned binary word (32-bit)
Data Range: 0x55AA
Read/Write: W
Initialized Value: 0x0
Operational Settings: At startup, the user watchdog is disabled. Write the value of 0x55AA to this register to start the user watchdog timer monitoring after initial power on or a reset. To prevent a disablement, the application must periodically write the strobe based on the user watchdog timer rules.
Status and Interrupt
The modules that are capable of User Watchdog Timer support provide status registers for the User Watchdog Timer.
User Watchdog Timer Status
The status register that contains the User Watchdog Timer Fault information is also used to indicate channel Inter-FPGA failures on modules that have communication between FPGA components. There are four registers associated with the User Watchdog Timer Fault/Inter-FPGA Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
User Watchdog Timer Fault/Inter-FPGA Failure Dynamic Status |
||
User Watchdog Timer Fault/Inter-FPGA Failure Latched Status |
||
User Watchdog Timer Fault/Inter-FPGA Failure Interrupt Enable |
||
User Watchdog Timer Fault/Inter-FPGA Failure Set Edge/Level Interrupt |
||
Bit(s) |
Status |
Description |
D31 |
User Watchdog Timer Fault Status |
0 = No Fault 1 = User Watchdog Timer Fault |
D30:D0 |
Reserved for Inter-FPGA Failure Status |
Channel bit-mapped indicating channel inter |
Function: Sets the corresponding bit (D31) associated with the channel’s User Watchdog Timer Fault error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value: 0
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.
In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
|
the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map). |
Interrupt Vector
Function: Set an identifier for the interrupt.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function: Sets where to direct the interrupt.
Type: unsigned binary word (32-bit)
Data Range: See table
Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME |
1 |
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) |
2 |
Direct Interrupt to PCIe Bus |
5 |
Direct Interrupt to cPCI Bus |
6 |
Function Register Map
Key
Bold Underline |
= Measurement/Status/Board Information |
Bold Italic |
= Configuration/Control |
User Watchdog Timer Registers
0x01C0 |
UWDT Quiet Time |
R/W |
0x01C4 |
UWDT Window |
R/W |
0x01C8 |
UWDT Strobe |
W |
Status Registers
User Watchdog Timer Fault/Inter-FPGA Failure
0x09B0 |
Dynamic Status |
R |
0x09B4 |
Latched Status* |
R/W |
0x09B8 |
Interrupt Enable |
R/W |
0x09BC |
Set Edge/Level Interrupt |
R/W |
Interrupt Registers
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.
0x056C |
Module 1 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x066C |
Module 1 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x076C |
Module 2 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x086C |
Module 2 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x096C |
Module 3 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0A6C |
Module 3 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0B6C |
Module 4 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0C6C |
Module 4 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0D6C |
Module 5 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0E6C |
Module 5 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x0F6C |
Module 6 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x106C |
Module 6 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
Interrupt Vector and Steering
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When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
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The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map). |
Interrupt Vector
Function: Set an identifier for the interrupt.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function: Sets where to direct the interrupt.
Type: unsigned binary word (32-bit)
Data Range: See table Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME |
1 |
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) |
2 |
Direct Interrupt to PCIe Bus |
5 |
Direct Interrupt to cPCI Bus |
6 |
Function Register Map
Key: Bold Italic = Configuration/Control
Bold Underline = Status
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a ‘1' to a bit set to ‘1' will set the bit to ‘0'). User Watchdog Timer Registers
0x01C0 |
UWDT Quiet Time |
R/W |
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0x01C4 |
UWDT Window |
R/W |
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0x01C8 |
UWDT Strobe |
W |
Status Registers
User Watchdog Timer Fault/Inter-FPGA Failure
0x09B0 |
Dynamic Status |
R |
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0x09B4 |
Latched Status* |
R/W |
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0x09B8 |
Interrupt Enable |
R/W |
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0x09BC |
Set Edge/Level Interrupt |
R/W |
Interrupt Register
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.
0x056C |
Module 1 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
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0x076C |
Module 2 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
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0x096C |
Module 3 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
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0x0B6C |
Module 4 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
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0x0D6C |
Module 5 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
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0x0F6C |
Module 6 Interrupt Vector 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
0x066C |
Module 1 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
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0x086C |
Module 2 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
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0x0A6C |
Module 3 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
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0x0C6C |
Module 4 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
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0x0E6C |
Module 5 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
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0x106C |
Module 6 Interrupt Steering 28 – User Watchdog Timer Fault/Inter-FPGA Failure |
R/W |
ENHANCED INPUT/OUTPUT FUNCTIONALITY CAPABILITY
The Enhanced Input/Output Functionality Capability is available on the following modules:
•Differential Transceiver Modules DF2 – 16 Channels Differential I/O
•Discrete I/O Modules DT4 – 24 Channels, Programmable for either input or output, output up to 500 mA per channel from an applied external 3 – 60 VCC source. DT5 – 16 Channels, Programmable for either input voltage measurements (±80 V) or as a bi-directional current switch (up to 500 mA per channel). DT6 – 4 Channels, Programmable for either input voltage measurements (±100 V) or as a bi-directional current switch (up to 3 A per channel).
•TTL/CMOS Modules TL2, TL4, TL6 and TL8 – 24 Channels, Programmable for either input or output.
PRINCIPLE OF OPERATION
The modules listed in Enhanced Input/Output Functionality Capability provide enhanced input and output mode functionality. For incoming signals (inputs), the enhanced modes include Pulse, Frequency and Period measurements. For outputs, the enhanced modes include PWM (Pulse Width Modulation) and Pattern Generation.
Input Modes
All input modes may be configured with debounce capability. Debounce capability allows configurable filtering of noisy signals and transients. Each channel may be set to an individual debounce time value. When a debounce time is set to a non-zero value, the signal reading after a transition must remain at the same level for the debounce interval before it is propagated through, otherwise it is rejected.
The waveform shown in Figure 1 will be used to illustrate the behavior for each input mode.
Pulse Measurements
There are two Pulse Measurements features available – High Time Pulse Measurements and Low Time Pulse Measurements. The Pulse Measurement data is stored in the FIFO Buffer.
High Time Pulse Measurements
In this input mode, the data in the FIFO buffer is the measurement for each rising transition to the next falling one. Timing measurements record the time interval (in 10 µs ticks) from a pair of transitions.
For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs): 1. 1500 (0x0000 05DC) 2. 2500 (0x0000 09C4) 3. 1000 (0x0000 03E8)
TimeInterval |
Calculations |
High Time Pulse Measurements |
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1 |
1500 counts * 10 µsec = 15000 µsec = 15.0 msec |
15.0 msec |
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2 |
2500 counts * 10 µsec = 25000 µsec = 25.0 msec |
25.0 msec |
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3 |
1000 counts * 10 µsec = 10000 µsec = 10.0 msec |
10.0 msec |
Low Time Pulse Measurements
In this mode, the data in the FIFO buffer is the measurement for each falling edge to the next rising edge. Timing measurements record the time interval (in 10 µs ticks) from a pair of transitions.
For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs): 1. 2000 (0x0000 07D0) 2. 500 (0x0000 01F4) 3. 1500 (0x0000 05DC)
TimeInterval |
Calculations |
High Time Pulse Measurements |
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1 |
2000 counts * 10 µsec = 2000 µsec = 20.0 msec |
20.0 msec |
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2 |
500 counts * 10 µsec = 5000 µsec = 5.0 msec |
5.0 msec |
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3 |
1500 counts * 10 µsec = 15000 µsec = 15.0 msec |
15.0 msec |
Transition Timestamps
There are three Transition Timestamp Measurements features available – Transition Timestamp for All Rising Edges, Transition Timestamp for All Falling Edges, and Transition Timestamp for All Edges. The Transition Timestamps Measurement data are store in the FIFO Buffer.
Transition Timestamp of All Rising Edges
In this mode, the data in the FIFO buffer is the Rising Edge Timestamp. The timestamp is a 32-bit counter that is incremented at the rate of 100 kHz (in other words, counter is incremented every 10 µsec). The timestamp is can be reset by the application at any time.
For this example, the FIFO Word Count register will be set to 4 and the FIFO Buffer Data register will contain the following four values (counts of 10 µs): 1. 1000 (0x0000 03E8) 2. 4500 (0x0000 1194) 3. 7500 (0x0000 1D4C) 4. 10000 (0x000 2710)
This data can be interpreted as follows:
TimeInterval |
Calculations |
High Time Pulse Measurements |
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1 to 2 |
4500 counts * 10 µsec = 35000 µsec = 35.0 msec |
35.0 msec |
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2 to 3 |
7500 counts * 10 µsec = 30000 µsec = 30.0 msec |
30.0 msec |
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3 to 4 |
10000 counts * 10 µsec = 25000 µsec = 25.0 msec |
25.0 msec |
Transition Timestamp of All Falling Edges In this mode, the data in the FIFO buffer is the Falling Edge Timestamp. The timestamp is a 32-bit counter that is incremented at the rate of 100 kHz (in other words, counter is incremented every 10 µsec). The timestamp is can be reset by the application at any time.
For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs): 1. 2500 (0x0000 09C4) 2. 7000 (0x0000 1B58) 3. 8500 (0x0000 2134)
This data can be interpreted as follows:
TimeInterval |
Calculations |
Time between falling edges |
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1 to 2 |
7000 – 2500 = 4500 counts = 4500 * 10 µsec = 45000 µsec = 45.0 msec |
45.0 msec |
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2 to 3 |
8500 – 7000 = 1500 counts = 1500 * 10 µsec = 15000 µsec = 15.0 msec |
15.0 msec |
Transition Timestamp of All Edges
In this mode, the data in the FIFO buffer is the Rising and Falling Edge Timestamp. The timestamp is a 32-bit counter that is incremented at the rate of 100 kHz (in other words, counter is incremented every 10 µsec). The timestamp is can be reset by the application at any time.
For this example, the FIFO Word Count register will be set to 7 and the FIFO Buffer Data register will contain the following seven values (counts of 10 µs): 1. 1000 (0x0000 03E8) 2. 2500 (0x0000 09C4) 3. 4500 (0x0000 1194) 4. 7000 (0x0000 1B58) 5. 7500 (0x0000 1D4C) 6. 8500 (0x0000 2134) 7. 10000 (0x000 2710)
This data can be interpreted as follows:
Interval |
Calculations |
Time between edges |
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1 to 2 |
2500 – 1000 = 1500 counts = 1500 * 10 µsec = 15000 µsec = 15.0 mse |
15.0 msec |
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2 to 3 |
4500 – 2500 = 2000 counts = 2000 * 10 µsec = 20000 µsec = 20.0 msec |
20.0 msec |
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3 to 4 |
7000 – 4500 = 2500 counts = 2500 * 10 µsec = 25000 µsec = 25.0 msec |
25.0 msec |
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4 to 5 |
7500 – 7000 = 500 counts = 500 * 10 µsec = 5000 µsec = 5.0 msec |
5.0 msec |
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5 to 6 |
8500 – 7500 = 1000 counts = 1000 * 10 µsec = 10000 µsec = 10.0 msec |
10.0 msec |
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6 to 7 |
10000 – 8500 = 1500 counts = 1500 * 10 µsec = 15000 µsec = 15.0 msec |
15.0 msec |
Transition Counter
There are three Transition Counter features available – Rising Edge Transition Counter, Falling Edge Transition Counter and All Edge Transition Counter.
Rising Edges Transition Counter
In this mode, the count of the number of Rising Edges is recorded. The counter is a 32-bit counter. The counter is can be reset by the application at any time.
For this example, the Transition Count register will be set to 4.
Falling Edges Transition Counter
In this mode, the count of the number of Falling Edges is recorded. The counter is a 32-bit counter. The counter is can be reset by the application at any time
For this example, the Transition Count register will be set to 3.
All Edges Transition Counter
In this mode, the count of the number of Rising and Falling Edges is recorded. The counter is a 32-bit counter. The counter is can be reset by the application at any time.
For this example, the Transition Count register will be set to 7.
Period Measurement
In this input mode, the data in the FIFO buffer is the measurement for each rising edge transition to the next rising edge transition. Timing measurements record the time interval (in 10 µs ticks).
For this example, the FIFO Word Count register will be set to 4 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs): 1. 2000 (0x0000 07D0) 2. 2000 (0x0000 07D0) 3. 2000 (0x0000 07D0) 4. 2000 (0x0000 07D0)
TimeInterval |
Calculations |
Period Measurements |
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1 |
2000 counts * 10 µsec = 20000 µsec = 20.0 msec |
20.0 msec |
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2 |
2000 counts * 10 µsec = 20000 µsec = 20.0 msec |
20.0 msec |
|||
3 |
2000 counts * 10 µsec = 20000 µsec = 20.0 msec |
20.0 msec |
|||
4 |
2000 counts * 10 µsec = 20000 µsec = 20.0 msec |
20.0 msec |
Frequency Measurement
In this input mode, the data in the FIFO buffer is the number of rising edge transitions for the programmable time interval programmed in the Frequency Measurement Period register.
For this example, set the Frequency Measurement Period register = 4000 (4000 * 10 µs = 40000 µs = 40 msec)
For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (numberof rising edges: 1. 2 (0x0000 0002) 2. 2 (0x0000 0002) 3. 2 (0x0000 0002)
TimeInterval |
Calculations |
FrequencyMeasurements |
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1 |
2 counts/40 msec = 2 counts/0.04 seconds = 50 Hz |
50 Hz |
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2 |
2 counts/40 msec = 2 counts/0.04 seconds = 50 Hz |
50 Hz |
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3 |
2 counts/40 msec = 2 counts/0.04 seconds = 50 Hz |
50 Hz |
Output Modes
There are three Enhanced Output Functionality modes: two PWM outputs and one Pattern Generator Output mode.
PWM Output
There are two PWM output modes, PWM Continuous and PWM Burst. The PWM timing is very precise with low jitter. In PWM Output mode, the Mode Select register is set to either “PWM Continuous or PWM Burst”. The value written to the PWM Period register specifies the period to output the PWM signal, the value written to the PWM Pulse Width register specifies the time for the “ON” state, and the value written to the PWM Output Polarity register specifies the initial edge of the output. For PWM Burst mode, the PWM Number of Cycles register specifies the number of cycles to output the signal. Note, there may be an initial “OFF” state level delay based on the Period time before the initial pulse is output.
PWM Continuous
Figure 12 and Figure 13 illustrate the PWM Continuous Output signal, one configured with PWM Output Polarity = Positive (0) and one configured with PWM Output Polarity = Negative (1). The configured PWM output is enabled and disabled with the Enable Measurements/Outputs register.
PWM Burst
Figure 14 and Figure 15 illustrate the PWM Burst Output signal with the PWM Number of Cycles = 5 pulses, one configured with PWM Output Polarity = Positive (0) and one configured with PWM Output Polarity = Negative (1). The configured PWM output is enabled with the Enable Measurements/Outputs register. Once the number of pulses that were requested is outputted, the value in the Enable Measurements/Outputs register will be reset (self-clearing) to allow for the output to be re-enabled.
Pattern Generator
For the Pattern Generator mode, there is 64K block of unsigned 32-bit words allocated to specify the data pattern for the output channels. The data in each 32-bit word is bit-mapped per channel. The Pattern RAM Start Address and Pattern RAM End Address registers specify the starting and ending address in the 64K block to use as the data to output for each channel configured for Pattern Generator mode. The Pattern RAM Period register specifies the pattern rate. The Pattern RAM Control and Pattern RAM Number of Cycles control the Pattern Generator output – Continuous, Burst with a specified number of cycles, Pause, or External Trigger from input from Channel 1. Note, when any channel is configured for External Trigger Pattern Generator mode, Channel 1 must be set as an input.
Figure 16 illustrates the output of the 24 channels for the DT4 module all configured in Pattern Generator mode
REGISTER DESCRIPTIONS
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.
Enhanced I/O Functionality Registers
0x300C |
Mode Select Ch 1 |
R/W |
0x308C |
Mode Select Ch 2 |
R/W |
0x310C |
Mode Select Ch 3 |
R/W |
0x318C |
Mode Select Ch 4 |
R/W |
0x320C |
Mode Select Ch 5 |
R/W |
0x328C |
Mode Select Ch 6 |
R/W |
0x330C |
Mode Select Ch 7 |
R/W |
0x338C |
Mode Select Ch 8 |
R/W |
0x340C |
Mode Select Ch 9 |
R/W |
0x348C |
Mode Select Ch 10 |
R/W |
0x350C |
Mode Select Ch 11 |
R/W |
0x358C |
Mode Select Ch 12 |
R/W |
0x360C |
Mode Select Ch 13 |
R/W |
0x368C |
Mode Select Ch 14 |
R/W |
0x370C |
Mode Select Ch 15 |
R/W |
0x378C |
Mode Select Ch 16 |
R/W |
0x380C |
Mode Select Ch 17 |
R/W |
0x388C |
Mode Select Ch 18 |
R/W |
0x390C |
Mode Select Ch 19 |
R/W |
0x398C |
Mode Select Ch 20 |
R/W |
0x3A0C |
Mode Select Ch 21 |
R/W |
0x3A8C |
Mode Select Ch 22 |
R/W |
0x3B0C |
Mode Select Ch 23 |
R/W |
0x3B8C |
Mode Select Ch 24 |
R/W |
0x2000 |
Enable Measurements/Outputs |
R/W |
FIFO Registers
0x3000 |
FIFO Buffer Data Ch 1 |
R |
0x3080 |
FIFO Buffer Data Ch 2 |
R |
0x3100 |
FIFO Buffer Data Ch 3 |
R |
0x3180 |
FIFO Buffer Data Ch 4 |
R |
0x3200 |
FIFO Buffer Data Ch 5 |
R |
0x3280 |
FIFO Buffer Data Ch 6 |
R |
0x3300 |
FIFO Buffer Data Ch 7 |
R |
0x3380 |
FIFO Buffer Data Ch 8 |
R |
0x3400 |
FIFO Buffer Data Ch 9 |
R |
0x3480 |
FIFO Buffer Data Ch 10 |
R |
0x3500 |
FIFO Buffer Data Ch 11 |
R |
0x3580 |
FIFO Buffer Data Ch 12 |
R |
0x3600 |
FIFO Buffer Data Ch 13 |
R |
0x3680 |
FIFO Buffer Data Ch 14 |
R |
0x3700 |
FIFO Buffer Data Ch 15 |
R |
0x3780 |
FIFO Buffer Data Ch 16 |
R |
0x3800 |
FIFO Buffer Data Ch 17 |
R |
0x3880 |
FIFO Buffer Data Ch 18 |
R |
0x3900 |
FIFO Buffer Data Ch 19 |
R |
0x3980 |
FIFO Buffer Data Ch 20 |
R |
0x3A00 |
FIFO Buffer Data Ch 21 |
R |
0x3A80 |
FIFO Buffer Data Ch 22 |
R |
0x3B00 |
FIFO Buffer Data Ch 23 |
R |
0x3B80 |
FIFO Buffer Data Ch 24 |
R |
0x3004 |
FIFO Word Count Ch 1 |
R |
0x3084 |
FIFO Word Count Ch 2 |
R |
0x3104 |
FIFO Word Count Ch 3 |
R |
0x3184 |
FIFO Word Count Ch 4 |
R |
0x3204 |
FIFO Word Count Ch 5 |
R |
0x3284 |
FIFO Word Count Ch 6 |
R |
0x3304 |
FIFO Word Count Ch 7 |
R |
0x3384 |
FIFO Word Count Ch 8 |
R |
0x3404 |
FIFO Word Count Ch 9 |
R |
0x3484 |
FIFO Word Count Ch 10 |
R |
0x3504 |
FIFO Word Count Ch 11 |
R |
0x3584 |
FIFO Word Count Ch 12 |
R |
0x3604 |
FIFO Word Count Ch 13 |
R |
0x3684 |
FIFO Word Count Ch 14 |
R |
0x3704 |
FIFO Word Count Ch 15 |
R |
0x3784 |
FIFO Word Count Ch 16 |
R |
0x3804 |
FIFO Word Count Ch 17 |
R |
0x3884 |
FIFO Word Count Ch 18 |
R |
0x3904 |
FIFO Word Count Ch 19 |
R |
0x3984 |
FIFO Word Count Ch 20 |
R |
0x3A04 |
FIFO Word Count Ch 21 |
R |
0x3A84 |
FIFO Word Count Ch 22 |
R |
0x3B04 |
FIFO Word Count Ch 23 |
R |
0x3B84 |
FIFO Word Count Ch 24 |
R |
0x3008 |
FIFO Status Ch 1 |
R |
0x3088 |
FIFO Status Ch 2 |
R |
0x3108 |
FIFO Status Ch 3 |
R |
0x3188 |
FIFO Status Ch 4 |
R |
0x3208 |
FIFO Status Ch 5 |
R |
0x3288 |
FIFO Status Ch 6 |
R |
0x3308 |
FIFO Status Ch 7 |
R |
0x3388 |
FIFO Status Ch 8 |
R |
0x3408 |
FIFO Status Ch 9 |
R |
0x3488 |
FIFO Status Ch 10 |
R |
0x3508 |
FIFO Status Ch 11 |
R |
0x3588 |
FIFO Status Ch 12 |
R |
0x3688 |
FIFO Status Ch 14 |
R |
0x3708 |
FIFO Status Ch 15 |
R |
0x3788 |
FIFO Status Ch 16 |
R |
0x3808 |
FIFO Status Ch 17 |
R |
0x3888 |
FIFO Status Ch 18 |
R |
0x3908 |
FIFO Status Ch 19 |
R |
0x3988 |
FIFO Status Ch 20 |
R |
0x3A08 |
FIFO Status Ch 21 |
R |
0x3A88 |
FIFO Status Ch 22 |
R |
0x3B08 |
FIFO Status Ch 23 |
R |
0x3B88 |
FIFO Status Ch 24 |
R |
0x2008 |
Reset FIFO |
W |
Transition Count Registers
0x3000 |
Transition Count Ch 1 |
R |
0x3080 |
Transition Count Ch 2 |
R |
0x3100 |
Transition Count Ch 3 |
R |
0x3180 |
Transition Count Ch 4 |
R |
0x3200 |
Transition Count Ch 5 |
R |
0x3280 |
Transition Count Ch 6 |
R |
0x3300 |
Transition Count Ch 7 |
R |
0x3380 |
Transition Count Ch 8 |
R |
0x3400 |
Transition Count Ch 9 |
R |
0x3480 |
Transition Count Ch 10 |
R |
0x3500 |
Transition Count Ch 11 |
R |
0x3580 |
Transition Count Ch 12 |
R |
0x3600 |
Transition Count Ch 13 |
R |
0x3680 |
Transition Count Ch 14 |
R |
0x3700 |
Transition Count Ch 15 |
R |
0x3780 |
Transition Count Ch 16 |
R |
0x3800 |
Transition Count Ch 17 |
R |
0x3880 |
Transition Count Ch 18 |
R |
0x3900 |
Transition Count Ch 19 |
R |
0x3980 |
Transition Count Ch 20 |
R |
0x3A00 |
Transition Count Ch 21 |
R |
0x3A80 |
Transition Count Ch 22 |
R |
0x3B00 |
Transition Count Ch 23 |
R |
0x3B80 |
Transition Count Ch 24 |
R |
0x3B80 |
Transition Count Ch 24 |
R |
Frequency Measurement Registers
0x3014 |
Frequency Measurement Period Ch 1 |
R/W |
0x3094 |
Frequency Measurement Period Ch 2 |
R/W |
0x3114 |
Frequency Measurement Period Ch 3 |
R/W |
0x3194 |
Frequency Measurement Period Ch 4 |
R/W |
0x3214 |
Frequency Measurement Period Ch 5 |
R/W |
0x3294 |
Frequency Measurement Period Ch 6 |
R/W |
0x3314 |
Frequency Measurement Period Ch 7 |
R/W |
0x3394 |
Frequency Measurement Period Ch 8 |
R/W |
0x3414 |
Frequency Measurement Period Ch 9 |
R/W |
0x3494 |
Frequency Measurement Period Ch 10 |
R/W |
0x3514 |
Frequency Measurement Period Ch 11 |
R/W |
0x3594 |
Frequency Measurement Period Ch 12 |
R/W |
0x3614 |
Frequency Measurement Period Ch 13 |
R/W |
0x3694 |
Frequency Measurement Period Ch 14 |
R/W |
0x3714 |
Frequency Measurement Period Ch 15 |
R/W |
0x3794 |
Frequency Measurement Period Ch 16 |
R/W |
0x3814 |
Frequency Measurement Period Ch 17 |
R/W |
0x3894 |
Frequency Measurement Period Ch 18 |
R/W |
0x3914 |
Frequency Measurement Period Ch 19 |
R/W |
0x3994 |
Frequency Measurement Period Ch 20 |
R/W |
0x3A14 |
Frequency Measurement Period Ch 21 |
R/W |
0x3A94 |
Frequency Measurement Period Ch 22 |
R/W |
0x3B14 |
Frequency Measurement Period Ch 23 |
R/W |
0x3B94 |
Frequency Measurement Period Ch 24 |
R/W |
PWM Registers
0x3014 |
PWM Period Ch 1 |
R/W |
0x3094 |
PWM Period Ch 2 |
R/W |
0x3114 |
PWM Period Ch 3 |
R/W |
0x3194 |
PWM Period Ch 4 |
R/W |
0x3214 |
PWM Period Ch 5 |
R/W |
0x3294 |
PWM Period Ch 6 |
R/W |
0x3314 |
PWM Period Ch 7 |
R/W |
0x3394 |
PWM Period Ch 8 |
R/W |
0x3414 |
PWM Period Ch 9 |
R/W |
0x3494 |
PWM Period Ch 10 |
R/W |
0x3514 |
PWM Period Ch 11 |
R/W |
0x3594 |
PWM Period Ch 12 |
R/W |
0x3614 |
PWM Period Ch 13 |
R/W |
0x3694 |
PWM Period Ch 14 |
R/W |
0x3714 |
PWM Period Ch 15 |
R/W |
0x3794 |
PWM Period Ch 16 |
R/W |
0x3814 |
PWM Period Ch 17 |
R/W |
0x3894 |
PWM Period Ch 18 |
R/W |
0x3914 |
PWM Period Ch 19 |
R/W |
0x3994 |
PWM Period Ch 20 |
R/W |
0x3A14 |
PWM Period Ch 21 |
R/W |
0x3A94 |
PWM Period Ch 22 |
R/W |
0x3B14 |
PWM Period Ch 23 |
R/W |
0x3B94 |
PWM Period Ch 24 |
R/W |
0x3010 |
PWM Pulse Width Ch 1 |
R/W |
0x3090 |
PWM Pulse Width Ch 2 |
R/W |
0x3110 |
PWM Pulse Width Ch 3 |
R/W |
0x3190 |
PWM Pulse Width Ch 4 |
R/W |
0x3210 |
PWM Pulse Width Ch 5 |
R/W |
0x3290 |
PWM Pulse Width Ch 6 |
R/W |
0x3310 |
PWM Pulse Width Ch 7 |
R/W |
0x3390 |
PWM Pulse Width Ch 8 |
R/W |
0x3410 |
PWM Pulse Width Ch 9 |
R/W |
0x3490 |
PWM Pulse Width Ch 10 |
R/W |
0x3510 |
PWM Pulse Width Ch 11 |
R/W |
0x3590 |
PWM Pulse Width Ch 12 |
R/W |
0x3610 |
PWM Pulse Width Ch 13 |
R/W |
0x3690 |
PWM Pulse Width Ch 14 |
R/W |
0x3710 |
PWM Pulse Width Ch 15 |
R/W |
0x3790 |
PWM Pulse Width Ch 16 |
R/W |
0x3810 |
PWM Pulse Width Ch 17 |
R/W |
0x3890 |
PWM Pulse Width Ch 18 |
R/W |
0x3910 |
PWM Pulse Width Ch 19 |
R/W |
0x3990 |
PWM Pulse Width Ch 20 |
R/W |
0x3A10 |
PWM Pulse Width Ch 21 |
R/W |
0x3A90 |
PWM Pulse Width Ch 22 |
R/W |
0x3B10 |
PWM Pulse Width Ch 23 |
R/W |
0x3B90 |
PWM Pulse Width Ch 24 |
R/W |
0x3018 |
PWM Number of Cycles Ch 1 |
R/W |
0x3098 |
PWM Number of Cycles Ch 2 |
R/W |
0x3118 |
PWM Number of Cycles Ch 3 |
R/W |
0x3198 |
PWM Number of Cycles Ch 4 |
R/W |
0x3218 |
PWM Number of Cycles Ch 5 |
R/W |
0x3298 |
PWM Number of Cycles Ch 6 |
R/W |
0x3318 |
PWM Number of Cycles Ch 7 |
R/W |
0x3398 |
PWM Number of Cycles Ch 8 |
R/W |
0x3418 |
PWM Number of Cycles Ch 9 |
R/W |
0x3498 |
PWM Number of Cycles Ch 10 |
R/W |
0x3518 |
PWM Number of Cycles Ch 11 |
R/W |
0x3598 |
PWM Number of Cycles Ch 12 |
R/W |
0x3618 |
PWM Number of Cycles Ch 13 |
R/W |
0x3698 |
PWM Number of Cycles Ch 14 |
R/W |
0x3718 |
PWM Number of Cycles Ch 15 |
R/W |
0x3798 |
PWM Number of Cycles Ch 16 |
R/W |
0x3818 |
PWM Number of Cycles Ch 17 |
R/W |
0x3898 |
PWM Number of Cycles Ch 18 |
R/W |
0x3918 |
PWM Number of Cycles Ch 19 |
R/W |
0x3998 |
PWM Number of Cycles Ch 20 |
R/W |
0x3A18 |
PWM Number of Cycles Ch 21 |
R/W |
0x3A98 |
PWM Number of Cycles Ch 22 |
R/W |
0x3B18 |
PWM Number of Cycles Ch 23 |
R/W |
0x3B98 |
PWM Number of Cycles Ch 24 |
R/W |
0x200C |
PWM Output Polarity |
R/W |
Pattern Generator Registers
0x0004 0000 to 0x0007 |
FFFC Pattern RAM |
R/W |
0x2010 |
Pattern RAM Period |
R/W |
0x2014 |
Pattern RAM Start Address |
|
R/W |
0x2018 |
Pattern RAM End Address |
R/W |
0x201C |
Pattern RAM Control |
R/W |
0x2020 |
Pattern RAM Number of Cycles |
moduleCommonRegistersBoilerplate
FUNCTION REGISTER MAP
Key: Bold Underline = Measurement/Status
Bold Italic = Configuration/Control
Module Information Registers
0x003C |
FPGA Revision |
R |
|||
0x0030 |
FPGA Compile Timestamp |
R |
|||
0x0034 |
FPGA SerDes Revision |
R |
|||
0x0038 |
FPGA Template Revision |
R |
|||
0x0040 |
FPGA Zynq Block Revision |
R |
0x0074 |
Bare Metal Revision |
R |
||
0x0080 |
Bare Metal Compile Time (Bit 0-31) |
R |
||
0x0084 |
Bare Metal Compile Time (Bit 32-63) |
|||
R |
0x0088 |
Bare Metal Compile Time (Bit 64-95) |
||
R |
0x008C |
|||
Bare Metal Compile Time (Bit 96-127) |
R |
0x0090 |
||
Bare Metal Compile Time (Bit 128-159) |
R |
|||
0x0094 |
Bare Metal Compile Time (Bit 160-191) |
R |
0x007C |
FSBL Revision |
R |
|||
0x00B0 |
FSBL Compile Time (Bit 0-31) |
R |
|||
0x00B4 |
FSBL Compile Time (Bit 32-63) |
R |
|||
0x00B8 |
FSBL Compile Time (Bit 64-95) |
R |
|||
0x00BC |
FSBL Compile Time (Bit 96-127) |
R |
|||
0x00C0 |
FSBL Compile Time (Bit 128-159) |
R |
|||
0x00C4 |
FSBL Compile Time (Bit 160-191) |
R |
0x0000 |
Interface Board Serial Number (Bit 0-31) |
R |
|||
0x0004 |
Interface Board Serial Number (Bit 32-63) |
R |
|||
0x0008 |
Interface Board Serial Number (Bit 64-95) |
R |
|||
0x000C |
Interface Board Serial Number (Bit 96-127) |
R |
0x0010 |
Functional Board Number (Bit 0-31) |
R |
|||
0x0014 |
Functional Serial Number (Bit 32-63) |
R |
|||
0x0018 |
Functional Serial Number (Bit 64-95) |
R |
|||
0x001C |
Functional Serial Number (Bit 96-127) |
R |
0x0070 |
Module Capability |
R |
0x01FC |
Module Memory Map Revision |
R |
Module Information Registers
0x003C |
FPGA Revision |
R |
0x0030 |
FPGA Compile Timestamp |
R |
0x0034 |
FPGA SerDes Revision |
R |
0x0038 |
FPGA Template Revision |
R |
0x0040 |
FPGA Zynq Block Revision |
R |
0x0074 |
Bare Metal Revision |
R |
0x0080 |
Bare Metal Compile Time (Bit 0-31) |
R |
0x0084 |
Bare Metal Compile Time (Bit 32-63) |
R |
0x0088 |
Bare Metal Compile Time (Bit 64-95) |
R |
0x008C |
Bare Metal Compile Time (Bit 96-127) |
R |
0x0090 |
Bare Metal Compile Time (Bit 128-159) |
R |
0x0094 |
Bare Metal Compile Time (Bit 160-191) |
R |
0x007C |
FSBL Revision |
R |
0x00B0 |
FSBL Compile Time (Bit 0-31) |
R |
0x00B4 |
FSBL Compile Time (Bit 32-63) |
R |
0x00B8 |
FSBL Compile Time (Bit 64-95) |
R |
0x00BC |
FSBL Compile Time (Bit 96-127) |
R |
0x00C0 |
FSBL Compile Time (Bit 128-159) |
R |
0x00C4 |
FSBL Compile Time (Bit 160-191) |
R |
0x0000 |
Interface Board Serial Number (Bit 0-31) |
R |
0x0004 |
Interface Board Serial Number (Bit 32-63) |
R |
0x0008 |
Interface Board Serial Number (Bit 64-95) |
R |
0x000C |
Interface Board Serial Number (Bit 96-127) |
R |
0x0010 |
Functional Board Number (Bit 0-31) |
R |
0x0014 |
Functional Serial Number (Bit 32-63) |
R |
0x0018 |
Functional Serial Number (Bit 64-95) |
R |
0x001C |
Functional Serial Number (Bit 96-127) |
R |
0x0070 |
Module Capability |
R |
0x01FC |
Module Memory Map Revision |
R |
Module Measurement Registers
0x029C |
Zynq Core Voltage |
R |
0x02A0 |
Zynq Aux Voltage |
R |
0x02A4 |
Zynq DDR Voltage |
R |
0x0200 |
Interface Board PCB/Zynq Current Temp |
R |
0x0208 |
Functional Board PCB Current Temp |
R |
0x0218 |
Interface Board PCB/Zynq Max Temp |
R |
0x0220 |
Interface Board PCB/Zynq Min Temp |
R |
0x0228 |
Functional Board PCB Max Temp |
R |
0x0230 |
Functional Board PCB Min Temp |
R |
0x02C0 |
Higher Precision Zynq Core Temperature |
R |
Module Health Monitoring Registers
0x07F8 |
Module Sensor Summary Status |
R |
Notes: 1. Available on modules with the interface board rev. C and higher 2. Available on the following modules: PB1 and TE2
Module Manual - DT4 Revision History
Revision |
Revision Date |
Description |
|||
C |
17-11-2022 |
ECO C09844, transition to docbuilder format. Replace 'Specifications' section with 'Data Sheet'. Pg.6, remove pending from debounce spec. Pgs.15/18/21, updated D12-D10 in register table to 'D' to accommodate full Integer Mode range. Pgs.15-18/21, changed VRMS to VDC. Pg.16, updated Upper Threshold operations settings to '…below the Upper…'. Pg.16, updated Lower Threshold operations settings to '…above the Lower…'. Pg.20, added 'mA' to '5' in Function. Pg.25-29, removed pendings from status registers. Pg.25, corrected # of channels/data range/initialized value in "Channel Status Enabled". Pg.26, added 2nd note to Voltage Reading and Driver Error. Pg.26, updated Driver Error function. Pg.27, changed Low-to-High/High-to-Low Transition Status function to 'event'. Pg.27, added 3rd note to Low-to-High/High-to-Low Transition status. Pg.28, changed Above Max High Threshold Status function to 'event'. Pg.29, changed Below Min Low Threshold Status function to 'event'. Pg.29, changed Mid-Range Status to 'event'; added notes to Mid-Range Status. |
|||
C1 |
2024-01-17 |
ECO C11167, pg.8, updated Introduction; replaced Features with product overview. Pg.12/25/36,added Module Common Registers. |
|||
C2 |
19-24-2024 |
ECO C11424, pg.10, updated register names in Input section. Pg.10, updated I/O circuits figure to remove diode from LS/HS drive output configs & 'open collect' from LS drive output config. Pg.11, added Voltage to threshold level names; updated threshold diagram. Pg.12, changed Threshold to Voltage in Above Max High/Below Min Low/Mid-Range. Pg.13, revised register names in Unit Conversions. Pg.13, updated Note. Pg.14, changed Input/Output Format Low to I/O Format Ch1- 16. Pg.14, changed Input/Output Format High to I/O Format Ch17-24. Pg.16, added Voltage to section heading and threshold level names in bit table. Pg.16, changed Max High Threshold to Max High Voltage Threshold. Pg.17, changed Upper Threshold to Upper Voltage Threshold. Pg.17, changed Lower Threshold to Lower Voltage Threshold. Pg.18, changed Min Low Threshold to Min Low Voltage Threshold. Pg.21, changed VCC Bank Reading to VCC Voltage Reading. Pg.21, changed Select Pullup or Pulldown to Select Pull-Up or Pull-Down. Pg.21, changed Current for Source/Sink to Pull-Up/Down Current. Pg.22, changed VCC Bank Reading to VCC Voltage Reading. Pg.25, changed Reset BIT to BIT Count Clear. Pg.26, changed Channel Status Enabled to Channel Status Enable. Pg.29, changed Above Max High Threshold to Above Max High Voltage. Pg.30, changed Below Min Low Threshold to Below Min Low Voltage. Pg.30, changed Mid-Range to Mid-Range Voltage. Pg.33-37, updated register offset names per revised register description names. Pg.41-42, updated list of revised register description names. Pg.45, updated processing diagram per revised register description names. |
Module Manual - Status and Interrupts Revision History
Revision |
Revision Date |
Description |
|||
C |
2021-11-30 |
C08896; Transition manual to docbuilder format - no technical info change. |
Module Manual - User Watchdog Timer Revision History
Revision |
Revision Date |
Description |
|||
C |
2021-11-30 |
C08896; Transition manual to docbuilder format - no technical info change. |
Module Manual - Enhanced IO Functionality Revision History
Revision |
Revision Date |
Description |
|||
C |
2021-11-30 |
C08896; Transition manual to docbuilder format - no technical info change. |
Module Manual - Module Common Registers Revision History
Revision |
Revision Date |
Description |
|||
C |
2023-08-11 |
ECO C10649, initial release of module common registers manual. |
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