The power-on self-test is performed on each channel automatically when power is applied and report the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.

The AD module supports two off-line Initiated Built-in Test, User Initiated BIT (UBIT) (“D0") and Initiated BIT (IBIT) (“D3").

UBIT test is used to check the card and interface. This test disconnects all A/D channels from the I/O and connects them across an internal D/A.

Test voltage is controlled by the user by setting the desired voltage in the UBIT Test Data register. While UBIT test is enabled, the A/D Reading register will reflect the value entered for the test voltage. Note the units of the A/D Reading may represent voltage, current or engineering units depending on the mode specified by setting the Enable Floating Point Mode register.

IBIT test starts an initiated BIT test that disconnects all A/D’s from the I/O and then connects them across an internal stimulus. Each channel will be checked to a test accuracy of 0.2% FS and monitored for open inputs. The IBIT test cycle is completed within 20 seconds (depending on the sample rate) and results can be read from the BIT Status registers after the IBIT bit changes from 1 to 0 indicating that the IBIT test is complete. The test can be enabled or disabled at any time by writing to the appropriate register.

Function: The value represents voltage, current or engineering units depending on mode.

Type: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: Values are dependent on Polarity and Range settings for the channel

Enable Floating Point Mode: 0 (Integer Mode)

Unipolar: 0x0000 0000 to 0x00FF FFFF

Bipolar (2’s complement. 24-bit value sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF

Enable Floating Point Mode: 1 (Floating Point Mode)

Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: Sets input format for polarity and range for each channel. Note, if the Enable Floating Point Mode register is set to 1, the Floating Point Scale register must be set to the Range.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R/W

Initialized Value: 0x0000 0010 (AD1: ± 10 V, AD2: ± 100 V, AD3: ± 25 mA)

Operational Settings: For bipolar/unipolar selection, program D4 bit as 0 for unipolar and 1 for bipolar as shown in table below.

Function: Sets the desired sample rate for all channels.

Type: unsigned binary word (32-bit)

Data Range: 1000 - 256000 (0x0000 03E8 to 0x0003 E800)

Read/Write: R/W

Initialized Value: 100000 (0x0001 86A0)

Operational Settings: Enter desired frequency for each channel between 10 Hz to 115.2 kHz as a 32-bit binary number (1 Hz LSB). The break frequency must not be less than 1% of the sample rate nor greater than 45% of the sample rate. For a sample rate of 2 kHz, the File Break Frequency should be no less than 20 Hz and no greater than 0.9 kHz. 0 disables filter.

Function: The break frequency is the 3 dB point of a digital, second-order, IIR low-pass filter.

Type: unsigned binary word (32-bit)

Data Range: 0 Hz to 115.2 kHz (0x0000 0000 to 0x0001 C200)

Read/Write: R/W

Initialized Value: AD1: 0 kHz (0x0000 0000), AD2: 20 kHz (0x0000 4E20), AD3: 1 kHz (0x0000 03E8)

Operational Settings: LSB is 1 Hz. The break frequency must not be less than 1% of the clock rate frequency. (Example: For a clock rate frequency of 2 kHz, the Filter Break Frequency should be no less than 20 Hz and no greater than 0.9 kHz). Set to 0 to disables filter.

Acquisition Time: 3.9 µs required to sample and hold input

Conversion Time: total time required to obtain digital result. It consists of acquisition, decimator group delay when engaged and IIR filter.

Conversion time will vary depending on sample rates. 4.4µs delay when sampling at 256kHz. Refer to the following chart for lower sample rates:

Function: Latches all A/D channels.

Type: unsigned binary word (32-bit)

Data Range: 0 to 1

Read/Write: R/W

Initialized Value: 0

Operational Settings: Set 1 to latch all A/D channels and 0 to unlatch all A/D channels.

Function: Sets bit to enable the associated Built-In Self-Test (BIST): IBIT, CBIT and UBIT.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R/W

Initialized Value: 0x4 (CBIT Test Enabled)

Operational Settings: BIT tests include an on-line (CBIT) test and two off-line (UBIT, IBIT) tests. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggers when the BIT testing detects failures.

Function: The module will write 55h in the Test CBIT Verify register during the on-line (CBIT) test (maximum one second).

Type: unsigned binary word (32-bit)

Data Range: 0x00 or 0x55

Read/Write: R/W

Initialized Value: 0x00

Operational Settings: User can clear to 00h and then read again, after approximately one second, to verify that background bit testing is activated.

Function: Specifies voltage to be applied for the A/D UBIT off-line test.

Type: signed binary word (32-bit)

Data Range: Voltage and Current values are dependent on Polarity and Range settings for the channel.

Unipolar: 0x0000 to 0x00FF FFFF

Bipolar (2’s complement. 24-bit value sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: LSB is dependent on the Range setting. Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: Specifies polarity of the test generator going into all channels.

Type: binary word (32-bit)

Data Range: 0x0000 0000 or 0x0000 0010

Read/Write: R/W

Initialized Value: 0x0000 0000

Operational Settings: Write 0 to D4 of register to set channels for unipolar. Write 1 to set all channels for bipolar.

Default: Unipolar

Function: Available data in the FIFO buffer can be retrieved, one word at a time. (LSB for 24-bit word resolution is dependent on the Polarity and Range setting).

Type:

Voltage (AD1, AD2) or Current (AD3): signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Timestamp (sample counter): unsigned binary word (32-bit)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)

Unipolar: 0x0000 0000 to 0x00FF FFFF

Bipolar (2’s complement. 24-bit value sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF

Enable Floating Point Mode: 1 (Floating Point Mode)

Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: This is a counter that reports the number of 24-bit words stored in the FIFO buffer.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R

Initialized Value: 0

Operational Settings: Every time a read operation is made from the A/D Data memory address, its corresponding Words in FIFO counter will be decremented by one. The maximum number of words that can be stored in the FIFO is 1 mega words.

The FIFO Almost Empty, FIFO Low Watermark, FIFO High Watermark, FIFO Almost Full and FIFO Buffer Size sets the threshold limits that are used to set the bits in the FIFO Status register.

Function: Sets the format of the samples to be stored in the FIFO buffer which is determined by the bitmapped table.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0014

Read/Write: R/W

Initialized Value: 0

Operational Settings: The Time Stamp data format (D4) requires one word of storage space from the FIFO buffer. For example, if (D4) is set to 0 and the FIFO Buffer Size register is set to 1, a FIFO write will put one word of data in the FIFO memory space per sample and discard the timestamp (sample counter). Since the maximum physical size of FIFO is 1M words for each channel, the value in the FIFO Buffer Size and Data Control registers could cause an overflow to the FIFO buffer. When an overflow condition occurs, any data that is not placed in the FIFO will be lost.

Function: Sets the number of delay samples before the actual FIFO data collection begins.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0x0

Operational Settings: The data collected during the delay period will be discarded.

Function: Sets how many samples to skip over when storing data in FIFO.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0 (No Skip Count (FIFO stores every sample))

Operational Settings: If the sample rate for a channel is 10 kHz, there would be a new sample every 100µs. By setting the FIFO skip count to 1, the FIFO will store a new sample every 200 µs, or at a 5 kHz rate.

Function: Clears FIFO by resetting the Words in FIFO count.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: W

Initialized Value: 0x0

Operational Settings: This resets the Words in FIFO to zero; Clear FIFO register does not clear data in the buffer. A read to the buffer data will give “aged" data. Write a 1 to reset the Words in FIFO for the channel.

Function: Resets the FIFO Timestamp counters (sample counters) for all channels.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: W

Initialized Value: 0x0

Operational Settings: Write a 1 to reset the FIFO Timestamp value.

Function: Starts/triggers FIFO. FIFO can be started/triggered by different sources.

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0x1FF

Read/Write: R/W

Initialized Value: 0 (Disable Trigger)

Operational Settings: For the current implementation, triggering of FIFO is by Software Trigger only. Hardware triggering will be implemented in a future release. Hardware triggering will be platform dependent based on pin-outs and I/O availability. See the tables that follow for the current and pending settings.

Function: Software trigger is used to start the FIFO buffer and the collection of data.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: W

Initialized Value: 0 (Not Triggered)

Operational Settings: To use this operation, the FIFO Trigger Control register must be set up as described in the FIFO Trigger Control register. Write a 1 to trigger FIFO collection for all channels.

Function: Sets all channels for floating point mode or integer module.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: R/W

Initialized Value: 0 (Integer mode)

Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode. Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples

Function: This register sets the floating point offset to add to AD data.

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

Read/Write: R/W

Initialized Value: 0.0

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: This register sets the floating point scale to multiply the AD data.

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

Read/Write: R/W

Initialized Value: 0

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Function: Indicates whether the module’s internal processing is converting the register values and internal values to the binary representation of the mode selected (Integer or Floating Point).

Type: unsigned binary word (32-bit)

Data Range: 0 to 1

Read/Write: R

Initialized Value: 0

Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

Function: Sets BIT Threshold value (in milliseconds) to use for all channels for BIT failure indication.

Type: unsigned binary word (32-bit)

Data Range: 1 ms to 65 seconds

Read/Write: R/W

Initialized Value: 5 ms

Operational Settings: The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count", the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count" based on the BIT interval for that module.

Function: Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: W

Initialized Value: 0

Operational Settings: Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.

Function: Determines whether to update the status for the channels. This feature can be used to “mask" status bits of unused channels in status

registers that are bitmapped by channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0FFF (Channel Status)

Read/Write: R/W

Initialized Value: 0x0000 0FFF

Operational Settings: When the bit corresponding to a given channel in the Channel Status Enable register is not enabled (0) the status will be masked and report “0" or “no failure". This applies to all statuses that are bitmapped by channel (BIT Status, Overcurrent Status and Summary Status).

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The BIT Status register will indicate an error when the voltage read is not within the error of the set value.

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0FFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0-D6 is used to show the different conditions of the buffer.

Function: Sets the corresponding bit associated with the FIFO status type; there is a separate register for each channel.

Type: binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 007F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. These registers are only applicable to the AD3 module when it is set for current mode.

Function: Sets the corresponding bit associated with the channel’s overcurrent error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0FFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the Open/Over-Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. These registers are only applicable to Module AD1.

Function: Sets the corresponding bit associated with the channel’s Open/Over-Voltage error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the External Power Loss Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

D0 = +12V External Power Loss

D1 = -12V External Power Loss

Function: Sets the corresponding bit associated with the channel’s External Power Loss error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0003

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

The Analog-to-Digital Modules provide registers that support threshold detection. Refer to “Analog-to-Digital Threshold and Saturation Programming Module Manual" for the register descriptions.

The Analog-to-Digital Modules provide registers that support saturation detection. Refer to “Analog-to-Digital Threshold and Saturation Programming Module Manual" for the register descriptions.

There are four registers associated with the Front-end Amplifier Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

These registers are only applicable to Module AD2 and AD3.

Function: Sets the corresponding bit associated with the channel’s Front-end Amplifier Failure error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0FFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Data is periodically transferred between the Lattice FPGA and the Xilinx FPGA. A CRC value is calculated and verified with each data transfer. A CRC error flag is sent from the Lattice FPGA to the Xilinx FPGA if a CRC error is detected. The Xilinx FPGA contains a counter that will increase by two when a CRC error is flagged and decremented by one when there is no CRC error. If the counter reaches ten, the Xilinx FPGA will set the Inter-FPGA Failure status bit and shut down the isolated power supply. In order to recover from an Inter-FPGA Failure, the module needs to be reset and re-initialized.

There are four registers associated with the Inter-FPGA Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. 0 = Normal; 0x0FFF = Inter-FPGA Communication Failure. The status represents the status for all channels on the module.

*

Function: Sets the corresponding bit associated with the channel’s Inter-FPGA Failure error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Function: Sets the corresponding bit if any fault (BIT, Overcurrent, Open, External Power Loss, or Inter-FPGA Failure) occurs on that channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0FFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.

In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

⁺⁺After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.

Overcurrent Status

AD3 Only

Open/Over-Voltage Status

AD1 Only

External Power Loss Status

Threshold Detect Status

The Analog-to-Digital Modules provide status registers for threshold detection. Refer to “Analog-to-Digital Threshold and Saturation Programming Module Manual" for the Threshold Status Function Register Map.

Front-End Amplifier Failure Status

AD2 & AD3 Only