Function: Sets channels as inputs or outputs.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0x 0000 0000

Operational Settings: Write 0 for input (default), 1 for output

Notes:

I/O Format

Function: Reads High (1) or Low (0) inputs or outputs as defined by internal TTL channel threshold values. Bitmapped by channel.

Type: binary word (32-bit)

Read/Write: R

Initialized Value: NA

Operational Settings: NA

Read I/O

Function: Output modes only − Sets data outputs High (1) or Low (0). Bit-mapped per channel.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write 1 for High output; write 0 for Low. Notes: • Each bit corresponds to one of 24 channels.

Write Outputs

Function: Enables user selection of external VCC source or internal 3.3 V source for each Channel Bank (6 channels per bank), for applications requiring output voltages other than the internal voltage.

Type: binary word (32-bit)

Data Range: 0x 0000 0000 to 0x 0000 000F

Read/Write: R/W

Initialized Value: 0x 0000 000F

Operational Settings: Write 0 for external VCC source or 1 for internal (3.3 V) for each bank.

Notes:

Vcc Select

Function: When the I/O Format register is set for Input mode, the input signal will have the debounce filtering applied based on this programmed value. This is selectable for each channel.

Type: binary word (32-bit)

Data Range: 0x 0000 0000 to 0x FFFF FFFF

Read/Write: R/W

Initialized Value: 0x10

Operational Settings: The Debounce register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Enter required debounce time into appropriate channel registers. LSB weight is 8 ns/bit (register may be programmed from 0 (debounce filter inactive) through a maximum of 32.36s (full scale w/ 8 ns resolution). Once a signal level is a logic voltage level period longer than the debounce time (Logic High and Logic Low ), a logic transition is validated. Signal pulse widths less than programmed debounce time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state. Enter a value of 0 to disable debounce filtering. Debounce defaults to 0080h upon reset.

Function: Read the VCC bank for a group of six channels.

Type: binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0FFF

Read/Write: R

Initialized Value: N/A

Operational Settings: The Read VCC Bank register reflects the Vcc voltage of a bank. The voltage can be calculated using the following equation: Vcc = (0.001221 * register_value) / 0.91.

Function: Channels set for Inputs – BIT Dynamic Status is set when a redundant measurement is inconsistent with the input measurement level detected. Channels set for Outputs – BIT Dynamic Status is set when a dedicated measurement circuit compares the commanded level with the actual output level and the measurement is inconsistent with the commanded level.

Type: binary word (32-bit)

Read/Write: R

Initialized Value: 0

Operational Settings: 1 is read when a fault is detected. 0 indicates no fault detected.

Notes: Considered “momentary” during the actual event when detected. Associated channel(s) bit set to 1) within 10 ms (pending characterization).

|Bit Dynamic Status

Function: Channels set for Inputs – BIT Latched Interrupt Status is set when a redundant measurement is inconsistent with the input measurement level detected. Channels set for Outputs – BIT Latched Interrupt Status is set when a dedicated measurement circuit compares the commanded level with the actual output level and the measurement is inconsistent with the commanded level.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: 1 is written when a fault is detected. 0 indicates no fault detected.

Notes: • Faults are detected (associated channel(s) bit set to 1) within 10 ms (pending characterization).

BIT Latched Status

Function: When enabled, interrupts are generated for each channel when the BIT Interrupt Enable register indicates a fault. (See BIT Error Interrupt Interval register.)

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to enable interrupts. Write a 0 to disable interrupts.

Notes

|BIT Interrupt Enable

Function: When the BIT Interrupt Enable register is enabled, this register determines whether the interrupt will be generated for either “sense on edge” or “sense on level” event detection. Sense on “edge” requires a change from “no-go” to “go” state to trigger the status detection, while sense on “level” is independent of the previous state.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge.

|BIT Set Edge/Level Interrupt

Function: Outputs only – senses an overcurrent or overload condition for each channel and provides real-time status. The output channel is also immediately disabled at time of overcurrent sensed condition.

Type: binary word (32-bit)

Read/Write: R

Initialized Value: 0

Operational Settings: 1 is read when overcurrent or overload condition transition is sensed. 0 indicates normal status.

Notes: • Status is indicated (associated channel(s) bit set to 1, based on BIT status), within 80 ms (pending characterization).

|Overcurrent Dynamic Status

Function: Outputs only – senses an overcurrent or overload condition for each channel and provides status. The output channel is also immediately disabled at time of overcurrent sensed condition.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: 1 is written when overcurrent or overload condition transition is sensed. 0 indicates no status.

Notes: • Status is indicated (associated channel(s) bit set to 1, based on BIT status), within 40 µs (pending characterization). • Channel(s) shut down by overcurrent sensed can be reset by writing to the Overcurrent Clear register

Function: When enabled, interrupts are generated for each channel when the Overcurrent Latched Interrupt Status register senses an overcurrent or overload condition for any channel.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to enable interrupts. Write a 0 to disable interrupts.

Notes: • A programmed valid Interrupt Vector should be assigned for typical ISR handling.

Function: This register controls whether the Overcurrent Latched Interrupt Status register will trigger on an edge or a level.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge.

|Overcurrent Set Edge/Level Interrupt

Function: Resets disabled channels in Overcurrent Latched Status register following an overcurrent condition. Bit-mapped per channel.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: 1 is written to reset disabled channels. Processor will write a 0 back to the Overcurrent Reset register when reset process is complete.

|Overcurrent Reset

Function: Inputs only – senses High to Low transitions for each channel and provides real-time status.

Type: binary word (32-bit)

Read/Write: R

Initialized Value: 0

Operational Settings: 1 is read when a rising edge transition is sensed. 0 indicates no status.

Notes:

|Hi-Lo Transition Dynamic Status

Function: Inputs only – senses High to Low transitions for each channel and provides status.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: 1 is written when a falling edge transition is sensed. 0 indicates no status.

Notes:

|Hi-Lo Transition Latched Status

Function: When enabled, interrupts are generated for each channel when the Hi-Lo Transition Latched Status register senses a High to Low transition for any channel.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to enable interrupts. Write a 0 to disable interrupts.

Notes:

|Hi-Lo Transition Interrupt Enable

Function: This register controls whether the Hi-Lo Transition Latched Status register will trigger on an edge or a level.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge.

|Hi-Lo Transition Set Edge/Level Interrup

Function: Inputs only – senses Low to High transitions for each channel and provides real-time status.

Type: binary word (32-bit)

Read/Write: R

Initialized Value: 0

Operational Settings: 1 is read when a rising edge transition is sensed. 0 indicates no status.

Notes: • Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 40 ns pending characterization).

|Lo-Hi Transition Dynamic Status

Function: Inputs only – senses Low to High transitions for each channel and provides status.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: 1 is written when a rising edge transition is sensed. 0 indicates no status.

Notes:

|Lo-Hi Transition Latched Status

Function: When enabled, interrupts are generated for each channel when the Lo-Hi Transition Latched Interrupt Status register senses a Low to High transition for any channel.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

*Operational Settings: *Write a 1 to enable interrupts. Write a 0 to disable interrupts.

Notes • A programmed valid Interrupt Vector should be assigned for typical ISR handling.

Function: This register controls whether the Lo-Hi Transition Latched Status register will trigger on an edge or a level.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge.

|Lo-Hi Transition Set Edge/Level Interrupt

Function: Sets up a threshold requirement of “successive” events to accumulate before a BIT Error is generated. Accumulated successive fault detections add +2 to the count and no-fault detections subtract 1 from the count to filter BIT errors prior to an actual interrupt generation. Once the count exceeds this register’s value, a BIT error is generated.

Type: binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0x 0000 0003

Operational Settings: Write a threshold to filter BIT errors prior to generating a BIT Error.

Notes: • Advantageous in “noisy”/unstable application environments or for general filtering purposes.

BIT Error Interrupt Interval D: [1 = Interrupt; 0 = No Errors Detected]

Function: Clears the BIT error.

Type: binary word (32-bit)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 1 to clear BIT errors.

BIT Count Error Clear

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

The User Watchdog Timer (UWDT) Capability is available on the following modules:

The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.

The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:

A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.

The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.

The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.

Figure 1. User Watchdog Timer Overview

Figure 2. User Watchdog Timer Example

Figure 3. User Watchdog Timer Failures

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

Key

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.