D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

Ch24

Ch23

Ch22

Ch21

Ch20

Ch19

Ch18

Ch17

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Ch16

Ch15

Ch14

Ch13

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Mode #

Hex

Description

1

0x0001

Measure “High” time: Write a 1 to the Start Output/Measure Enable register to enable measurement of the I/O state “High” time. It will not be measured if the bit is not set for that channel, i.e. 0. If a 1 is written to enable measurement on a channel while that channel’s I/O state is 1, then the internal counter will begin to count upon begin enabled.

2

0x0002

Measure “Low” time: Write a 1 to the Start Output/Measure Enable register to enable measurement of the I/O state “Low time”. It will not be measured if the bit is not set for that channel. If a 1 is written to enable measurement on a channel while that channel’s I/O state is 0, then the internal counter will begin to count upon being enabled.

3

0x0003

Time-stamp of all rising edges: Write a 1 to the Start Output/Measure Enable register and the timestamp counter will begin to count. A low-to-high transition on that channel will store the timestamp at the time of the transition in the FIFO. If that channel is then disabled by writing a 0, the timestamp counter will pause and any low-to-high transitions of the I/O state will not trigger FIFO storage. Write any value to the Reset Timer register to reset the timestamp counter.

4

0x0004

Time-stamp of all falling edges: Write a 1 to the Start Output/Measure Enable register and the timestamp counter will begin to count. A high-to-low transition on that channel will store the timestamp at the time of the transition in the FIFO. If that channel is then disabled by writing a 0, the timestamp counter will pause and any high-to-low transitions of the I/O state will not trigger a FIFO storage. Write any value to the Reset Timer register to reset the timestamp counter.

5

0x0005

Time-stamp of all edges: Write a 1 to the Start Output/Measure Enable register and the timestamp counter will begin to count. Any low-to-high or high-to-low transition on that channel will store the timestamp at the time of the transition in the FIFO. If that channel is then disabled by writing a 0, the timestamp counter will pause and any low-to-high or high-to-low transitions of the I/O state will not trigger FIFO storage. Write any value to the Reset Timer register to reset the timestamp counter.

6

0x0006

Count total number of rising edges (until FIFO reset): Write a 1 to the Start Output/Measure Enable register to begin tracking any low-to-high transition of that channel’s I/O state will increment the counter by one. If a 0 is written in the register for that channel, the count will not increment on any transitions. Write any value to the Reset Timer register to reset the counter.

7

0x0007

Count total number of falling edges (until FIFO reset): Write a 1 to the Start Output/Measure Enable register to begin tracking any high-to-low transition of that channel’s I/O state will increment the counter by one. If a 0 is written in the register for that channel, the count will not increment on any transitions. Write any value to the Reset Timer register to reset the counter.

8

0x0008

Count total number of all edges (until FIFO reset): Write a 1 to the Start Output/Measure Enable register to begin tracking any low-to-high transition or high-to-low transition of that channel’s I/O state will increment the counter by one. If a 0 is written in the register for that channel, the count will not increment on any transitions. Write any value to the Reset Timer register to reset the counter.

9

0x0009

Measure period from rising edge (L-H transition) to next rising edge: The first low-to-high transition of any enabled channel will start the counter. The next low-to-high transition will store the count in the FIFO, reset the counter, and begin the count again. This will repeat. After the waveform on the input has finished, write any value to the Reset Timer to reset it to zero.

10

0x000A

Measure frequency: The first low-to-high transition of any enabled channel will start the PWM Period counter. The counter will be incremented for every low-to-high transition that occurs within the defined period. Once the period counter reaches zero, the number of low-to-high transitions counted will be stored in FIFO and the process will restart. Write any value to the Reset Timer to reset it to zero.

32

0x20

PWM - output continuously: Will continuously (repeat) the pulse based on programmed Period and Pulse Width registers. Write a 1 to output the continuous waveform programed in the Period and Pulse Width registers. Write a 0 to disable the output.

33

0x21

PWM - output “n” times: Will repeat the pulse based on programmed Period and Pulse Width “n” times as programmed in the Number of Cycles register. Write a 1 to output the number of pulses written in the Number of Cycles register with the period and pulse width written in the Period and Pulse Width registers. Once the programmed number of pulses that was written to the register has been outputted, a 0 will be written back to the register for the channel that was enabled (self-clearing).

34

0x22

Output pattern data held in RAM: Outputs all mode selected channel(s) based on the pattern programmed in RAM. The output rate is set in the Pattern RAM Period register. The Pattern RAM Start Address register will determine where the pattern RAM output will begin when enabled. The Pattern RAM End Address register will determine where the pattern RAM output will end when enabled. After the pattern is outputted, it will loop back to the start address. Writing a 0x1 to the control register will loop the pattern continuously. While looping continuously, a 0x0 can be written to stop the output and bring the pattern back to the start address or a 0x5 can be written to pause the output wherever it may be in the pattern. Writing a 0x1 when the pattern is paused will resume the pattern at the same spot. Writing a 0x3 to the control register will burst the pattern from the start address to the end address for N number of times. N is determined by the value written in the Pattern RAM Period register. The Pattern RAM Period register determines how long the each address data will be output for. In other words, it is the time it takes for the output to change to the next address.

Mode 1 - 10

Input

Mode 32 - 34

Output

1

Mode(s) 1-10: FIFO storage occurs at 8 ns intervals (unless otherwise specified)

2

Mode(s) 7- 9: Applies to measurement “count” edges - the “count” is provided/updated at 8ns intervals in the first element of the FIFO only (no FIFO 'storage” - first element is dynamically updated).

3

Mode 10 (Measure frequency): In this mode, the captured FIFO data is essentially the number of transitions measured within a given user specified time interval (specified/programmed in the Pulse Width register). From this, the user calculates frequency by [FIFO Data (# of transitions) / Pulse Width], or, simply program the Pulse Width register to a time interval of 1 second, which then FIFO Data (# of transitions) directly correlates to measured frequency (Hz).

0x1038

I/O Format

R/W

0x1000

Read I/O

R

0x1024

Write Outputs

R/W

0x1020

Vcc Select

R/W

0x1200

Read Vcc Bank 1

R

0x1204

Read Vcc Bank 1

R

0x1208

Read Vcc Bank 1

R

0x120C

Read Vcc Bank 1

R

0x208C

Debounce Time Ch.1

R/W

0x210C

Debounce Time Ch.2

R/W

0x218C

Debounce Time Ch.3

R/W

0x220C

Debounce Time Ch.4

R/W

0x228C

Debounce Time Ch.5

R/W

0x230C

Debounce Time Ch.6

R/W

0x238C

Debounce Time Ch.7

R/W

0x240C

Debounce Time Ch.8

R/W

0x248C

Debounce Time Ch.9

R/W

0x250C

Debounce Time Ch.10

R/W

0x258C

Debounce Time Ch.11

R/W

0x260C

Debounce Time Ch.12

R/W

0x268C

Debounce Time Ch.13

R/W

0x270C

Debounce Time Ch.14

R/W

0x278C

Debounce Time Ch.15

R/W

0x280C

Debounce Time Ch.16

R/W

0x288C

Debounce Time Ch.17

R/W

0x290C

Debounce Time Ch.18

R/W

0x298C

Debounce Time Ch.19

R/W

0x2A0C

Debounce Time Ch.20

R/W

0x2A8C

Debounce Time Ch.21

R/W

0x2B0C

Debounce Time Ch.22

R/W

0x2B8C

Debounce Time Ch.23

R/W

0x2C0C

Debounce Time Ch.24

R/W

0x1100

Overcurrent Clear

R/W

0x101C

BIT Error Interrupt Interval

R/W

0x1014

BIT Count Error Clear

R/W

0x0800

BIT Dynamic Status

R

0x0804

BIT Latched Status*

R/W

0x0808

BIT Interrupt Enable

R/W

0x080C

BIT Set Edge/Level Interrupt

R/W

0x0810

Low-High Transition Dynamic Status

R

0x0814

Low-High Transition Latched Status*

R/W

0x0818

Lo-Hi Transition Interrupt Enable

R/W

0x081C

Lo-Hi Transition Set Edge/Level Interrupt

R/W

0x0820

High-Low Transition Dynamic Status

R

0x0824

High-Low Transition Latched Status*

R/W

0x0828

Hi-Lo Transition Interrupt Enable

R/W

0x082C

Hi-Lo Transition Set Edge/Level Interrupt

R/W

0x0830

Overcurrent Dynamic Status

R

0x0834

Overcurrent Latched Status*

R/W

0x0838

Overcurrent Interrupt Enable

R/W

0x083C

Overcurrent Set Edge/Level Interrupt

R/W

0x0500

Module 1 Interrupt Vector 1 - BIT

R/W

0x0504

Module 1 Interrupt Vector 2 - Low-High

R/W

0x0508

Module 1 Interrupt Vector 3 - High-Low

R/W

0x050C

Module 1 Interrupt Vector 4 - Overcurrent

R/W

0x0510 to 0x0568

Module 1 Interrupt Vector 5-27 - Reserved

R/W

0x056C

Module 1 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0570 to 0x057C

Module 1 Interrupt Vector 29-32 - Reserved

R/W

0x0600

Module 1 Interrupt Steering 1 - BIT

R/W

0x0604

Module 1 Interrupt Steering 2 - Low-High

R/W

0x0608

Module 1 Interrupt Steering 3 - High-Low

R/W

0x060C

Module 1 Interrupt Steering 4 - Overcurrent

R/W

0x0610 to 0x0668

Module 1 Interrupt Steering 5-27 - Reserved

R/W

0x066C

Module 1 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0670 to 0x067C

Module 1 Interrupt Steering 29-32 - Reserved

R/W

0x0700

Module 2 Interrupt Vector 1 - BIT

R/W

0x0704

Module 2 Interrupt Vector 2 - Low-High

R/W

0x0708

Module 2 Interrupt Vector 3 - High-Low

R/W

0x070C

Module 2 Interrupt Vector 4 - Overcurrent

R/W

0x0710 to 0x0768

Module 2 Interrupt Vector 5-27 - Reserved

R/W

0x076C

Module 2 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0770 to 0x077C

Module 2 Interrupt Vector 29-32 - Reserved

R/W

0x0800

Module 2 Interrupt Steering 1 - BIT

R/W

0x0804

Module 2 Interrupt Steering 2 - Low-High

R/W

0x0808

Module 2 Interrupt Steering 3 - High-Low

R/W

0x080C

Module 2 Interrupt Steering 4 - Overcurrent

R/W

0x0810 to 0x0868

Module 2 Interrupt Steering 5-27 - Reserved

R/W

0x086C

Module 2 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0870 to 0x087C

Module 2 Interrupt Steering 29-32 - Reserved

R/W

0x0900

Module 3 Interrupt Vector 1 - BIT

R/W

0x0904

Module 3 Interrupt Vector 2 - Low-High

R/W

0x0908

Module 3 Interrupt Vector 3 - High-Low

R/W

0x090C

Module 3 Interrupt Vector 4 - Overcurrent

R/W

0x0910 to 0x0968

Module 3 Interrupt Vector 5-27 - Reserved

R/W

0x096C

Module 3 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0970 to 0x097C

Module 3 Interrupt Vector 29-32 - Reserved

R/W

0x0A00

Module 3 Interrupt Steering 1 - BIT

R/W

0x0A04

Module 3 Interrupt Steering 2 - Low-High

R/W

0x0A08

Module 3 Interrupt Steering 3 - High-Low

R/W

0x0A0C

Module 3 Interrupt Steering 4 - Overcurrent

R/W

0x0A10 to 0x0A68

Module 3 Interrupt Steering 5-27 - Reserved

R/W

0x0A6C

Module 3 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0A70 to 0x0A7C

Module 3 Interrupt Steering 29-32 - Reserved

R/W

0x0B00

Module 4 Interrupt Vector 1 - BIT

R/W

0x0B04

Module 4 Interrupt Vector 2 - Low-High

R/W

0x0B08

Module 4 Interrupt Vector 3 - High-Low

R/W

0x0B0C

Module 4 Interrupt Vector 4 - Overcurrent

R/W

0x0B10 to 0x0B68

Module 4 Interrupt Vector 5-27 - Reserved

R/W

0x0B6C

Module 4 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0B70 to 0x0B7C

Module 4 Interrupt Vector 29-32 - Reserved

R/W

0x0C00

Module 4 Interrupt Steering 1 - BIT

R/W

0x0C04

Module 4 Interrupt Steering 2 - Low-High

R/W

0x0C08

Module 4 Interrupt Steering 3 - High-Low

R/W

0x0C0C

Module 4 Interrupt Steering 4 - Overcurrent

R/W

0x0C10 to 0x0C68

Module 4 Interrupt Steering 5-27 - Reserved

R/W

0x0C6C

Module 4 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0C70 to 0x0C7C

Module 4 Interrupt Steering 29-32 - Reserved

R/W

0x0D00

Module 5 Interrupt Vector 1 - BIT

R/W

0x0D04

Module 5 Interrupt Vector 2 - Low-High

R/W

0x0D08

Module 5 Interrupt Vector 3 - High-Low

R/W

0x0D0C

Module 5 Interrupt Vector 4 - Overcurrent

R/W

0x0D10 to 0x0D68

Module 5 Interrupt Vector 5-27 - Reserved

R/W

0x0D6C

Module 5 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0D70 to 0x0D7C

Module 5 Interrupt Vector 29-32 - Reserved

R/W

0x0E00

Module 5 Interrupt Steering 1 - BIT

R/W

0x0E04

Module 5 Interrupt Steering 2 - Low-High

R/W

0x0E08

Module 5 Interrupt Steering 3 - High-Low

R/W

0x0E0C

Module 5 Interrupt Steering 4 - Overcurrent

R/W

0x0E10 to 0x0E68

Module 5 Interrupt Steering 5-27 - Reserved

R/W

0x0E6C

Module 5 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0E70 to 0x0E7C

Module 5 Interrupt Steering 29-32 - Reserved

R/W

0x0F00

Module 6 Interrupt Vector 1 - BIT

R/W

0x0F04

Module 6 Interrupt Vector 2 - Low-High

R/W

0x0F08

Module 6 Interrupt Vector 3 - High-Low

R/W

0x0F0C

Module 6 Interrupt Vector 4 - Overcurrent

R/W

0x0F10 to 0x0F68

Module 6 Interrupt Vector 5-27 - Reserved

R/W

0x0F6C

Module 6 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x0F70 to 0x0F7C

Module 6 Interrupt Vector 29-32 - Reserved

R/W

0x1000

Module 6 Interrupt Steering 1 - BIT

R/W

0x1004

Module 6 Interrupt Steering 2 - Low-High

R/W

0x1008

Module 6 Interrupt Steering 3 - High-Low

R/W

0x100C

Module 6 Interrupt Steering 4 - Overcurrent

R/W

0x1010 to 0x1068

Module 6 Interrupt Steering 5-27 - Reserved

R/W

0x106C

Module 6 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure

R/W

0x1070 to 0x107C

Module 6 Interrupt Steering 29-32 - Reserved

R/W

0x300C

Mode Select Ch.1

R/W

0x308C

Mode Select Ch.2

R/W

0x310C

Mode Select Ch.3

R/W

0x318C

Mode Select Ch.4

R/W

0x320C

Mode Select Ch.5

R/W

0x328C

Mode Select Ch.6

R/W

0x330C

Mode Select Ch.7

R/W

0x338C

Mode Select Ch.8

R/W

0x340C

Mode Select Ch.9

R/W

0x348C

Mode Select Ch.10

R/W

0x350C

Mode Select Ch.11

R/W

0x358C

Mode Select Ch.12

R/W

0x360C

Mode Select Ch.13

R/W

0x368C

Mode Select Ch.14

R/W

0x370C

Mode Select Ch.15

R/W

0x378C

Mode Select Ch.16

R/W

0x380C

Mode Select Ch.17

R/W

0x388C

Mode Select Ch.18

R/W

0x390C

Mode Select Ch.19

R/W

0x398C

Mode Select Ch.20

R/W

0x3A0C

Mode Select Ch.21

R/W

0x3A8C

Mode Select Ch.22

R/W

0x3B0C

Mode Select Ch.23

R/W

0x3B8C

Mode Select Ch.24

R/W

0x2000

Start Output/Measure Enable

R/W

0x2004

Reset Timer

W

0x3000

Read FIFO/Read Count Ch.1

R

0x3080

Read FIFO/Read Count Ch.2

R

0x3100

Read FIFO/Read Count Ch.3

R

0x3180

Read FIFO/Read Count Ch.4

R

0x3200

Read FIFO/Read Count Ch.5

R

0x3280

Read FIFO/Read Count Ch.6

R

0x3300

Read FIFO/Read Count Ch.7

R

0x3380

Read FIFO/Read Count Ch.8

R

0x3400

Read FIFO/Read Count Ch.9

R

0x3480

Read FIFO/Read Count Ch.10

R

0x3500

Read FIFO/Read Count Ch.11

R

0x3580

Read FIFO/Read Count Ch.12

R

0x3600

Read FIFO/Read Count Ch.13

R

0x3680

Read FIFO/Read Count Ch.14

R

0x3700

Read FIFO/Read Count Ch.15

R

0x3780

Read FIFO/Read Count Ch.16

R

0x3800

Read FIFO/Read Count Ch.17

R

0x3880

Read FIFO/Read Count Ch.18

R

0x3900

Read FIFO/Read Count Ch.19

R

0x3980

Read FIFO/Read Count Ch.20

R

0x3A00

Read FIFO/Read Count Ch.21

R

0x3A80

Read FIFO/Read Count Ch.22

R

0x3B00

Read FIFO/Read Count Ch.23

R

0x3B80

Read FIFO/Read Count Ch.24

R

0x3004

Read FIFO Count Ch.1

R

0x3084

Read FIFO Count Ch.2

R

0x3104

Read FIFO Count Ch.3

R

0x3184

Read FIFO Count Ch.4

R

0x3204

Read FIFO Count Ch.5

R

0x3284

Read FIFO Count Ch.6

R

0x3304

Read FIFO Count Ch.7

R

0x3384

Read FIFO Count Ch.8

R

0x3404

Read FIFO Count Ch.9

R

0x3484

Read FIFO Count Ch.10

R

0x3504

Read FIFO Count Ch.11

R

0x3584

Read FIFO Count Ch.12

R

0x3604

Read FIFO Count Ch.13

R

0x3684

Read FIFO Count Ch.14

R

0x3704

Read FIFO Count Ch.15

R

0x3784

Read FIFO Count Ch.16

R

0x3804

Read FIFO Count Ch.17

R

0x3884

Read FIFO Count Ch.18

R

0x3904

Read FIFO Count Ch.19

R

0x3984

Read FIFO Count Ch.20

R

0x3A04

Read FIFO Count Ch.21

R

0x3A84

Read FIFO Count Ch.22

R

0x3B04

Read FIFO Count Ch.23

R

0x3B84

Read FIFO Count Ch.24

R

0x3008

Read FIFO Status Ch.1

R

0x3088

Read FIFO Status Ch.2

R

0x3108

Read FIFO Status Ch.3

R

0x3188

Read FIFO Status Ch.4

R

0x3208

Read FIFO Status Ch.5

R

0x3288

Read FIFO Status Ch.6

R

0x3308

Read FIFO Status Ch.7

R

0x3388

Read FIFO Status Ch.8

R

0x3408

Read FIFO Status Ch.9

R

0x3488

Read FIFO Status Ch.10

R

0x3508

Read FIFO Status Ch.11

R

0x3588

Read FIFO Status Ch.12

R

0x3608

Read FIFO Status Ch.13

R

0x3688

Read FIFO Status Ch.14

R

0x3708

Read FIFO Status Ch.15

R

0x3788

Read FIFO Status Ch.16

R

0x3808

Read FIFO Status Ch.17

R

0x3888

Read FIFO Status Ch.18

R

0x3908

Read FIFO Status Ch.19

R

0x3988

Read FIFO Status Ch.20

R

0x3A08

Read FIFO Status Ch.21

R

0x3A88

Read FIFO Status Ch.22

R

0x3B08

Read FIFO Status Ch.23

R

0x3B88

Read FIFO Status Ch.24

R

0x2008

Reset FIFO

W

0x3014

Period Ch.1

R/W

0x3094

Period Ch.2

R/W

0x3114

Period Ch.3

R/W

0x3194

Period Ch.4

R/W

0x3214

Period Ch.5

R/W

0x3294

Period Ch.6

R/W

0x3314

Period Ch.7

R/W

0x3394

Period Ch.8

R/W

0x3414

Period Ch.9

R/W

0x3494

Period Ch.10

R/W

0x3514

Period Ch.11

R/W

0x3594

Period Ch.12

R/W

0x3614

Period Ch.13

R/W

0x3694

Period Ch.14

R/W

0x3714

Period Ch.15

R/W

0x3794

Period Ch.16

R/W

0x3814

Period Ch.17

R/W

0x3894

Period Ch.18

R/W

0x3914

Period Ch.19

R/W

0x3994

Period Ch.20

R/W

0x3A14

Period Ch.21

R/W

0x3A94

Period Ch.22

R/W

0x3B14

Period Ch.23

R/W

0x3B94

Period Ch.24

R/W

0x3010

Pulse Width Ch. 1

R/W

0x3090

Pulse Width Ch. 2

R/W

0x3110

Pulse Width Ch. 3

R/W

0x3190

Pulse Width Ch. 4

R/W

0x3210

Pulse Width Ch. 5

R/W

0x3290

Pulse Width Ch. 6

R/W

0x3310

Pulse Width Ch. 7

R/W

0x3390

Pulse Width Ch. 8

R/W

0x3410

Pulse Width Ch. 9

R/W

0x3490

Pulse Width Ch. 10

R/W

0x3510

Pulse Width Ch. 11

R/W

0x3590

Pulse Width Ch. 12

R/W

0x3610

Pulse Width Ch. 13

R/W

0x3690

Pulse Width Ch. 14

R/W

0x3710

Pulse Width Ch. 15

R/W

0x3790

Pulse Width Ch. 16

R/W

0x3810

Pulse Width Ch. 17

R/W

0x3890

Pulse Width Ch. 18

R/W

0x3910

Pulse Width Ch. 19

R/W

0x3990

Pulse Width Ch. 20

R/W

0x3A10

Pulse Width Ch. 21

R/W

0x3A90

Pulse Width Ch. 22

R/W

0x3B10

Pulse Width Ch. 23

R/W

0x3B90

Pulse Width Ch. 24

R/W

0x3018

Number of Cycles Ch.1

R/W

0x3098

Number of Cycles Ch.2

R/W

0x3118

Number of Cycles Ch.3

R/W

0x3198

Number of Cycles Ch.4

R/W

0x3218

Number of Cycles Ch.5

R/W

0x3298

Number of Cycles Ch.6

R/W

0x3318

Number of Cycles Ch.7

R/W

0x3398

Number of Cycles Ch.8

R/W

0x3418

Number of Cycles Ch.9

R/W

0x3498

Number of Cycles Ch.10

R/W

0x3518

Number of Cycles Ch.11

R/W

0x3598

Number of Cycles Ch.12

R/W

0x3618

Number of Cycles Ch.13

R/W

0x3698

Number of Cycles Ch.14

R/W

0x3718

Number of Cycles Ch.15

R/W

0x3798

Number of Cycles Ch.16

R/W

0x3818

Number of Cycles Ch.17

R/W

0x3898

Number of Cycles Ch.18

R/W

0x3918

Number of Cycles Ch.19

R/W

0x3998

Number of Cycles Ch.20

R/W

0x3A18

Number of Cycles Ch.21

R/W

0x3A98

Number of Cycles Ch.22

R/W

0x3B18

Number of Cycles Ch.23

R/W

0x3B98

Number of Cycles Ch.24

R/W

0x200C

Output Polarity

R/W

0x201C

Pattern RAM Period

R/W

0x2014

Pattern RAM Start Address

R/W

0x2018

Pattern RAM End Address

R/W

0x2020

Pattern RAM Num of Cycles

R/W

0x2010

Pattern RAM Control

R/W