The 68PPC2 supports options for Power-On-Self-Test (POST) testing (memory, peripherals, etc.). The 68PPC2 also supports function modules with NAI’s flexible, leading-edge, fully programmable and continuous background built-in-test (BIT) enabled function. BIT tests both 68PPC2 on board functions and functions contained on expansion modules, making it a useful field service tool.

The U-boot firmware provides a foundation layer to interface between the raw board hardware. U-boot has programmable device set-up, setup flexibility, and supports booting supported Operating Systems with a straight-forward user interface. U-boot also allows booting from a number of different devices (check part numbering options).

VxWorks utilizes the WindRiver VxWorks Boot ROM. When specified/configured with VxWorks as an OS, a VxWorks Boot ROM image (with utilities) is pre-flashed at the factory supporting VxWorks development and FLASH download (check part numbering options).

Wind River VxWorks 7.x and HVP, DDC-I Deos

Contact NAI for availability of other operating systems.

CAUTION: The 68PPC2 contains an integrated heat sink and cover. Do not remove the heat sink. There are no user serviceable components, switches or programming jumpers under the heat sink. In the unlikely event the 68PPC2 becomes is inoperable, please return the unit to the factory for service.

The 68PPC2 Conduction cooled version has four I/O connectors P0, P1, P2 and J5. Connectors P1, and P2 at the rear of the module, are used for the OpenVPX interface and for user I/O. Connector J5 is utilized for GbE Ethernet interface option & RS-232 Serial debug/console access. J5 uses a Mini-HDMI connector for USB port1, asynchronous serial (debug port) and optionally Ethernet port 1. A J5 connector adapter cable/breakout board P/N 75SBC4-BB optional accessory kit is available for quick connect (contact factory).

The 68PPC2 may also be provided in an air-cooled version with front panel I/O accessibility. Please refer to part numbering options and contact factory for available mechanical options.

The 68PPC2 provides a total of 8 GB of ECC DDR3L memory. This memory is organized as 8 1Gb x 8 MT41K1G8 devices (parts may vary), with a ninth device providing storage for ECC data. The T2080 has an on chip 64-bit DDR3 memory controller. The controller has full ECC error-correction support, with the ability to detect multi-bit errors and correct single-bit errors within a nibble. Please consult the Micron data sheet for DDR3 device specific details.

Connected through the local bus, the 68PPC2 supports 256 Mbytes of flash. The Flash consists of a single soldered in Micron® Flash device MT28FW02GBBA1HPC device. Flash is configured as a 16-bit wide device, using the 16-bit asynchronous data access interface. The 256 MB flash is divided into two logical banks, one standard bank and one for recovery. The FPGA Local Bus controls which bank is accessible by setting the top bits of the address seen by the flash. The NOR Flash has an erase capacity of 100,000 cycles per sector and typical data retention of 20 years.

The FM25CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. The ferroelectric random-access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years. The 68PPC2 FRAM 64K bits are organized as 8,192 x 8 bits random access memory, connected to the T2080 CPU through the SPI controller, SPI_CS [0].

The T2080 CPU has two available on-chip SATA 2 type controllers. SATA port 1 is supported with SerDes12, and SATA port 2 is supported with SerDes13. The 68PPC2 SATA port 2 is connected to an on board SATA 2 Solid

State Drive. SATA2 is connected to Module Slot 2 (supports direct SATA 2 solid-state FLASH module, if fitted) or to an external storage device via a programmable switch.

SATA Port 1

The SATA port 1 controller interface on the T2080 CPU is directly connected to an on-board, solid-state drive. The SSD contains a single level cell NAND Flash together with a controller in a single multi-chip package. This multi-chip packaged device is soldered directly to the printed circuit board, for reliable electrical and mechanical connection.

The SSD has an external write protect signal HDW_WP. This signal is pinned out as rear I/O on connector P2. The HDW_WP signal must be switched to ground to enable any write to the SSD. The HDW_WP signal is pulled up on card by a 4.7 KΩ resistor to the internal 3.3 V supply.

The onboard SATA drive conforms to the follow specifications:

The standard ordering code for the 68PPC2 includes a 32GB SSD drive. Larger devices are available; please consult the factory for availability.

SATA Port 2

The SATA port 2 interface on the T2080 CPU is connected directly to a high-speed connector for Module Slot 2 or to an external storage device via a programmable switch. An optional SATA Flash drive is available for the 68PPC2; please consult the Factory for availability.

The T2080 supports two 10/100/1000Base-TX or two 1000Base-KX Ethernet ports. The 68PPC2 Ethernet ports support:

Ethernet port 1 can be routed as 10/100/1000Base-TX to the front, 10/100/1000Base-TX to the rear, or KX-Ethernet to the rear as build options.

Ethernet Port 2 can be routed as 10/100/1000Base-Tx to the rear or KX-Ethernet to the rear as build options.

I/O pin outs can be found in the Pinout Details section of this document.

The 68PPC2 supports two USB 3.0 ports. Contact factory for availability.

USB port 0 is available at the front of 68PPC2, on connector J5. The USB port can operate as a standalone host.

I²C is a two-wire, bidirectional single ended serial bus that provides efficient method of exchanging data between a master and slave device. The T2080 CPU contains three identical I²C controllers. The 68PPC2, I²C port 1 of the T2080 is connected to the die temperature monitor. I²C port 2 is connected to the real-time clock, and I²C port 3 is connected to the OpenVPX connector P2, and is available as rear I/O

Serial Peripheral Interface Bus or SPI is a synchronous serial data link standard. SPI operates in full duplex mode. SPI devices communicate in master/slave mode where the master device starts a frame and sources the clock. The T2080 CPU has one SPI controller with four device select pins (SPI_CS [3:0]). SPI_CS [0] is attached to an FRAM. SPI_C [1,2,3] are unconnected.

Linux device drivers are available to access FRAM features.

The 68PPC2 has one serial port to the front and to the rear of the card. Do not plug into the serial port from both the front and rear of the card at the same time. This will cause errors when communicating to the card through the serial port.

For U-boot, the console port is selected at compile time. The 68PPC2 is configured to use the first serial port (SER1), which is routed to the OpenVPX P0 connector at rear of the card.

For Linux, the console port is passed as a kernel parameter by U-boot when it loads Linux and so can be selected at run-time.

Input levels: TTL and CMOS compatible, single ended inputs Input levels:

Vin L (min): 0 V

Vin L (max): 0.8 V

Vin H (min): 2.0 V

Vin H (max): 5.0 V

Output levels: TTL/CMOS, single ended outputs

Drive Capability:

Vout L (min): 0 V min @ 24 mA (sink)

Vout L (max): 0.55 V max @ 24 mA (sink)

Vout H (min): 2.4 V @ 24 mA (source)

Vout H (max): 3.3 V VCC, (unloaded)

Rise/Fall time: 10 ns into a 50pf load

Function: TTL direction. Sets channels as inputs or outputs. Bitmapped per TTL channel.

Function Address Offset(s): 0x08

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value: 0x02

Operational Settings: Write 0 for input; 1 for output: Default is configured for Input. Data bits [4:0] correspond to one of 4 channels TTL_CH [4:1] respectively

Function: Reads the TTL output of a specific channel’s I/O pin. Write to this register to set the channel to drive high or low. Bitmapped per TTL channel.

Function Address Offset(s): 0x0C

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value: 0x00

Operational Settings: TTL_DIR register must be set for output (1). Write 0 for Low output; write 1 for High output: Data bits [3:0] correspond to one of 4 channels TTL_CH [4:1] respectively.

When TTL_DIR register has channel configured as an output (1): Write 0 for Low output; write 1 for High output.

When TTL_DIR register has channel configured as an input (0): Read corresponding bit for the state of the TTL input.

Function: Reads back TTL output channel(s) register contents. Bitmapped per TTL channel.

Function Address Offset(s): 0x0A

Type: binary word (16-bit)

Read/Write: R

Initialized Value: 0x00

Operational Settings: Reads the state of output register for each channel, regardless of the state of the I/O channel.

TTL IRQ Enable

Function: To configure a channel as an interrupt, its corresponding TTL_DIR register bit must be set for inputs (0). Setting the channel’s bit in this register selects the channel to be enabled for interrupt. Bitmapped per TTL channel.

When generated, the interrupt will be invoked on T2080 IRQ05 (see Hardware Interrupts section).

Function Address Offset(s): 0x14

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value: 0x00

Operational Settings: Write 1 to enable interrupts for selected channel. Write 0 for interrupts not enabled, is default.

Function: When the TTL IRQ Enable register is enabled, this register determines whether the interrupt will be generated for either “rising edge” or “falling edge” event detection. Bitmapped per TTL channel.

Sense on edge setting: Generates interrupt on a rising edge.

Sense on level setting: Generates interrupt when input is at a high level.

Function Address Offset(s): 0x16

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value: 0x00

Operational Settings: Write a 1 to sense on level and a 0 to sense on edge.

Function: When an interrupt for a channel or channels occurs, the corresponding bit for that channel will be set High in this register. Bitmapped per TTL channel.

Function Address Offset(s): 0x18

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value: 0x00

Operational Settings: When a TTL input channel generates an interrupt, the corresponding bit in the TTL_IRQ_STAT is set High (1). Once a bit is set by a transition on the input pin, the bit remains set until cleared by a register write. Writing a (1) to the corresponding bit resets the interrupt status to (0).

Function: Overrides temperature alarm auto shutdown.

Function Address Offset(s): 0x1A

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value: 0x0000

Operational Settings: Write a 1 to override the temperature alarm automatic shutdown. Default value = 0.

Function: Clears latched temperature alarm status.

Function Address Offset(s): 0x1E

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value: 0x0000

Operational Settings: Bit is set to a 1 if temperature alarm interrupt occurs. Write a 1 to clear the interrupt status. Default value = 0.

Function: Enables temperature alarm interrupt.

Function Address Offset(s): 0x20

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value: 0x0000

Operational Settings: Write a 1 to enable the temperature alarm interrupt. Default value = 0.

Function: Shuts down power to the board.

Function Address Offset(s): 0x1C

Type: binary word (16-bit)

Read/Write: R/W

Initialized Value: 0x000

Operational Settings: Write the proper sequence of words “0xDEAD” followed by "0xC0DE" to initiate a power shutdown.

*Programmer’s Reference Guide for NAI 68PPC2 Single Board Computer (TBD)

*68PPC2 Ethernet Download (TBD)

*68PPC2 USB Download (TBD)

*Standalone documents “pending/TBD”; currently, all reference documentation required are embedded within the specific OS 68PPC2 BSP/Support documentation (i.e. BSPx.x.x \ layers \ nai_bsp \ templates \ board \ nai68PPC2 \ (README) files (where x.x.x is the BSP version/revision available).

T2080 QorIQ Integrated Processor Hardware Specifications

T2080 QorIQ Integrated Multicore Communication Processor Family Reference Manual

e500mc Core Reference Manual

Function: Indicates that the module slots are ready to be addressed.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: 0xA5A5A5A5

Operational Settings: This register will contain the value of 0xA5A5A5A5 when the module addresses have been determined.

Function: Specifies the Base Address for the module in the specific slot position.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Based on board’s module configuration.

Operational Settings: 0x0000 0000 indicates no Module found.

Function: Specifies the Memory Size (in bytes) allocated for the module in the specific slot position.

Type: unsigned binary word (32-bit)

Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Assigned by factory for the module.

Operational Settings: 0x0000 0000 indicates no Module found.

Function: Specifies the Model ID for the module in the specified slot position.

Type: 4-character ASCII string

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Assigned by factory for the module.

Operational Settings: The Module ID is formatted as four ASCII bytes: three characters followed by a space. Module IDs are in little-endian order with a single space following the first three characters. For example, 'TL1' is '1LT', 'SC1' is '1CS' and so forth. Example below is for “TL1” (MSB justified). All value of 0000 0000 indicates no Module found.

Function: Specifies the Board Serial Number.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Initialized Value: Serial number assigned by factory for the board.

Operational Settings: N/A

Function: Specifies the Board Platform Identifier. Values are for the ASCII characters for the NAI valid platforms (Identifiers).

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Initialized Value: ASCII code is for the Platform Identifier of the board

Operational Settings: Valid NAI platform and the associated value for the platform is shown below:

Function: Specifies the Board Model Identifier. Value is for the ASCII characters for the NAI valid model.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Initialized Value: ASCII code is for the Model Identifier of the board

Operational Settings: Example of NAI model and the associated value for the model is shown below:

Function: Specifies the Board Generation. Identifier values are for the ASCII characters for the NAI valid generation identifiers.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Initialized Value: ASCII code is for the Generation Identifier of the board

Operational Settings: Example of NAI generation and the associated value for the generation is shown below:

Function: Specifies the Processor Count and Ethernet Count

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Operational Settings:

     Processor Count - Integer: indicates the number of unique processor types on the motherboard.

     Ethernet Interface Count - Indicates the number of Ethernet interfaces on the product motherboard. For example, Single Ethernet = 1; Dual Ethernet = 2.

Function: Specifies the Maximum Module Slot Count and ARM Platform Type.

Type: unsigned binary word (32-bit)

Data Range: See table below.

Read/Write: R

Operational Settings:

     Maximum Module Slot Count - Indicates the number of modules that can be installed on the product.

     ARM Platform - Altera = 1; Xilinx X1 = 2; Xilinx X2 = 3; UltraScale = 4

Function: Specifies the Version of the NAI factory provided Motherboard Core Application installed on the board.

Type: Two (2) unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Operational Settings: The motherboard firmware version consists of four components: Major, Minor, Minor 2 and Minor 3.

Function: Specifies the Build Date/Time of the NAI factory provided Motherboard Core Application installed on the board.

Type: Two (2) unsigned binary word (32-bit)

Data Range: N/A

Read/Write: R

Operational Settings: The motherboard firmware time consists of the Build Date and Build Time.

Function: Indicates the status of the motherboard software (MBCore) initialization.

Type: unsigned binary word (32-bit)

Data Range: 0 to 1

Read/Write: R

Initialized Value: 0

Operational Settings: Indicates whether the motherboard software initialization has not occurred (0) or has been completed (1). Any other value will indicate an error code.

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) for the processor and PCB for Zynq processor.

These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).

Function: Specifies the Measured Temperatures on Motherboard.

Type: signed byte (8-bits) for each temperature reading - Six (6) 32-bit words

Data Range: 0x0000 0000 to 0xFFFF 0000

Read/Write: R

Initialized Value: Value corresponding to the measured temperatures based on the table below.

Operational Settings: The 8-bit temperature readings are signed bytes. For example, if the following register contains the value 0x6955 0000:

Example:

The values would represent the following temperatures:

These registers provide higher precision readings of the current Zynq and PCB temperatures.

Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds.

Type: unsigned binary word (32-bits)

Data Range: See table below

Read/Write: R

Initialized Value: 0

Operational Settings: This register provides a summary for motherboard sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.

The registers listed in this section apply to each module sensor listed for the Motherboard Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring motherboard temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Zynq Core Temperature sensor as an example.

Function: Set an identifier for the interrupt.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Function: Sets where to direct the interrupt.

Type: unsigned binary word (32-bit)

Data Range: See table Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, the interrupt is sent as specified:

Function: Provides the ability to monitor factors may effect communication status of a Module.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Operational Settings: The Module Communications registers provide the ability to monitor factors that may effect the Communications Status of individual Modules. There is one register per Module. Each communication factor is bit mapped to the register as shown in the table below:

Module Powered-down: The user can request an individual Module be powered-down (see Module Control Command Requests). Once the request is detected and acted upon, this bit will be set. Once powered-down, you will not be able to communicate with the Module.

Module Not Detected: If a Module in this slot has not been detected, you will not be able to communicate with the Module.

Module LinkInit Not Done: Module communications is accomplished via SERDES. LinkInit is required to establish a connection to the Module. If the LinkInit has not been successfully completed, you will not be able to communicate with the Module.

Module Firmware Not Ready: Each Module has Firmware that is ready from Module QSPI and loaded for execution. If this Firmware was not loaded and started successfully, you may not be able to communicate with the Module.

Module Communications Error Detected: If at some point during run-time, communications with the Module has failed, this bit will be set.

Function: Provides the ability to monitor the individual Module BIT Status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R

Operational Settings: The Module BIT Status registers provide the ability to monitor individual Module BIT results as Latched and current value. A 1 in any bit field indicates BIT failure for the Module in that slot.

44-pin male connectors, 2mm, Harwin P/N M80-5114422.

Mate kit: "Custom Hood Kit" part # M80C108448C (or equivalent); Includes connector, backshell, pins & jackscrews. This mating connector kit may be purchased separately as NAI P/N 05-0119 (contact factory).

P0 - OpenVPX and Bus Controller interface only / 2mm 5x22 w/key, standard OpenVPX (AMP 352068-1 or equivalent).

P1 - Bus Controller and configured I/O / 2mm 5x22 wo/key, standard OpenVPX (AMP 5352152-1 or equivalent). See mod slot pin-out.

P2 - Configured I/O / 2mm 5x22 wo/key, standard OpenVPX (AMP 5352152-1 or equivalent). See mod slot pin-out.

Industry standard mini-HDMI (Type C receptacle).

P0 - Utility plane. Contains the following signal definitions:

P1 - Defined as primarily Data/Control Planes (User defined I/O secondary)

P2 - User defined I/O (primary)

The P0 (Utility) Plane contains the primary power, bus and utility signals for the OpenVPX board. Additionally, several of the user defined pins can be utilized for Geographical Addressing and a parallel SYSRST# signal. Signals defined as N/C currently have no functionality associated and is not required for general operation.

The 68PPC2 is a root-complex SBC with four (4) PCIe ver. 2.0 x1 high-speed serial interface fabric bus lanes. As defined in the OpenVPX payload slot specifications, the 68PPC2 provides two ‘fat pipes’ (one Tx and one Rx differential pair), which provides additional user I/O definition opportunity. Additionally, the 68PPC2 can be commanded/controlled via dual port Gig-E (options for either 10/100/1000Base-T and/or 1000Base-KX (SerDes) Interfaces). Additional module I/O is also defined on the P1 user defined plane. Signals defined as N/C currently have no functionality associated or are considered optional and are not required for general operation.

The following pages contain the 'user defined' I/O data area front and rear panel pin-outs with their respective signal designations for all module types currently offered/configured for the 68PPC2 platform. The card is designed to route the function module I/O signals to the front and rear I/O connector. The following I/O connector pin-out is based upon the function module designated in the module slot. Signals defined as N/C currently have no functionality associated or are considered optional and are not required for general operation.

Commercial Equivalent RJ45-type Ethernet cabling/wiring (for reference only):