Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
| Interrupt Vector | |
| Function: | Set an identifier for the interrupt. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | When an interrupt occurs, this value is reported as part of the interrupt mechanism. |
| Interrupt Steering | |
| Function: | Sets where to direct the interrupt. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | See table |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | When an interrupt occurs, the interrupt is sent as specified: |
| Direct Interrupt to VME | 1 |
|---|---|
| Direct Interrupt to ARM Processor (via SerDes) + (Custom App on ARM or NAI Ethernet Listener App) | 2 |
| Direct Interrupt to PCIe Bus | 5 |
| Direct Interrupt to cPCI Bus | 6 |