As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurement and
simulation, communications, Ethernet switch, and SBC functions. Our Pulse Timer Receiver & Generator module facilitates synchronization of an effective range of 1 PPS to 10 MHz signal input, in addition to providing capability for host processor RTC time stamping, other timer sync and output signal generation to other modules, boards and/or system components. This user manual is designed to help you get the most out of your PT1 smart function module.
PT1 Overview
NAI’s PT1 module offers a range of features designed to suit a variety of system requirements, including:
Two Inputs: The PT1 boasts two input channels which can be configured as single-ended or differential inputs, accommodating a wide voltage
range.
For differential inputs, the module accepts voltages ranging from -24V to +24V, making it suitable for a variety of signal
sources.
In single-ended mode, the module accepts voltages from -10V to +10V, offering flexibility in signal acquisition.
Additional input characteristics include:
Input impedance (Zin) that is programmable to 50Ω, 75Ω, 100Ω or a high-Z setting of approximately 100 kΩ, ensuring compatibility with various signal sources.
Input capacitance of around 50 pF, minimizing the impact of capacitive loading on the input signals.
Eight Outputs: The PT1 offers 8 output channels with distinct characteristics:
Two channels provide TTL-level signals with a maximum output current of ±24 mA, making them suitable for driving standard TTL logic circuits.
Two channels of RS-422 signals, ensuring robust and noise-resistant communication in industrial environments.
Two channels provide 5V signals, and two channels provide 12V signals. Each can drive 50Ω loads, which is advantageous for various voltage-level compatibility requirements.
Independent Serial Communication Ports: The PT1 module incorporates two independent RS-422/485 isolated asynchronous serial communication ports with high-speed data capabilities.
These ports are programmable to support data rates of up to 1 Mbps, making them suitable for applications requiring high-speed data capabilities.
Each port is equipped with 1KB (x 16) receive and transmit buffers, ensuring efficient data handling and reducing the risk of
data loss or overflow.
Additional Application Features:
The PT1 module is capable of transmitting 1 PPS to 10 MHz signals directly to the motherboard, facilitating seamless connections to
other modules on the same board and the motherboard processor (pending, please contact factory for details).
For applications demanding deterministic and low-latency time synchronization, the PT1 module offers direct motherboard processor
IRQ capability, ensuring precise timing and synchronization in applications where timing accuracy is critical (Note: motherboard
support is required to fully utilize this feature).
The PT1 module offers direct SMA coax connections, which can be beneficial for scenarios requiring impedance matching or
additional shielding (pending, please contact factory for details).
NAI’s PT1 Pulse Timer Receiver & Generator module is a versatile and adaptable device that provides extensive input and output options. Its
ability to handle a wide range of voltages, customizable input characteristics, and versatile output channels, along with high-speed serial
communication capabilities, positions it as a reliable and power component in various engineering applications where precision and flexibility are
paramount.
PRINCIPLE OF OPERATION
Configuration
Before the user can write to any configuration register, certain steps must be followed to ensure the module accepts the user specified
configuration. The steps are as follows:
Write a 0 to the Enable Channel bit of the Tx-Rx Configuration register to tell the hardware that we are about to change the configuration.
Wait for the Channel Configured status of the Realtime Channel Status register to read a 0.
Write all the desired configuration registers.
Set the Enable Channel bit of the Tx-Rx Configuration register to 1 to notify the hardware that it can read all the configuration registers.
Wait for the Channel Configured status in the Realtime Channel Status register to read a 1 before proceeding to send/receive data.
Async Mode
Two output channels are configured as independent isolated asynchronous RS485/422 serial ports for communications. These channels include independent Tx and Rx FIFO buffers and programmable baud rates up to 1 Mbps.
Gap Timeout Status
The Gap Timeout Occurred status gets set when there’s data in a channel’s receive buffer but there’s no activity on a channel’s receiver for approximately three byte-times. To use the Gap Timeout feature, set the Enable Gap Timeout bit in the Tx-Rx Configuration register to a 1. When receiving asynchronous data, monitor the Gap Timeout status bit of the Channel Status register to know if a timeout occurred. The status is cleared after all the data in the receive buffer is read or cleared.
Receiver Enable/Disable
A Receiver Enable/Disable function allows the user to turn selected receivers ON/OFF. When a receiver is disabled, no data will be placed in the
buffer.
Serial Data Transmit Enhancement
An additional asynchronous mode to support “Immediate Transmit” operation has been incorporated. This mode immediately transmits serial data anytime the transmit buffer is not empty. There is no requirement to set the Tx Initiate bit before each transmission, which simplifies system traffic and overhead, since only the actual data byte being transmitted needs be sent to the transmit buffer. Each channel has its own configurable Transmit and Receive buffer. The upper byte of each received word provides status information for that word.
Status and Interrupts
The PT1 Function Module provides registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.
Module Common Registers
The PT1 Function Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times,
unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the
detailed information.
REGISTER DESCRIPTIONS
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.
Input Registers
The Input Format register enables the input signal while allowing for the selection of the input connection format of the PT1. The Input Termination register enables the input termination and enables the user to select the appropriate impedance to match the source drive impedance. The Input Single-Ended Crossing Threshold register provides the ability to set the DAC threshold reference voltage for the single-ended (SE) input.
Input Format
Function:
Enables input signal and allows selection of input connection format.
Type:
unsigned binary word (32-bit).
Data Range:
See table
Read/Write:
R
Initialized Value:
0x0 (input channel disabled)
Operational Settings:
Setting based on the following table.
Note
If any invalid input configuration is written to the module (enabling multiple modes concurrently), it will ignore the command and remain at the previous valid configuration to protect the hardware from any damage. There should never be an invalid configuration, as it will be rejected. The register will always display the current configuration, so the user will see that the attempted command did not execute as an indication that there was a problem with the command.
Note
The firmware change described in the first note was implemented for FPGA version 1.4 and BM version 2.8 and later.
Input Format
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
D
D
D
D
D31:D4
Reserved
D3
SMA Select
D2
Differential Select
D1
Single-Ended Select
D0
Input Enable
Input Termination
Function:
Enables and selects the input termination to match the source drive impedance.
Type:
unsigned binary word (32-bit).
Data Range:
see table
Read/Write:
R/W
Initialized Value:
0x0 (Termination Disabled)
Operational Settings:
Input termination based on the following table.
Note
The system allows for the parallel combination of resistances in
selected termination configurations, optimizing the effectiveness of
termination resistance values. However, if the user selects multiple termination values, it is important to note that the changes in termination resistance may not yield the anticipated results.
Note
The firmware change described in the first note was implemented for FPGA version 1.4 and BM version 2.8 and later.
Note
Input termination functionality for single-ended and single-ended w/threshold modes was implemented for FPGA version 1.7 and later.
Input Termination
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
D
D
D31:D3
Reserved
D2
100 Ohm Enable
D1
75 Ohm Enable
D0
50 Ohm Enable
Input Single-Ended Crossing Threshold
Function:
Sets the DAC threshold reference voltage for the single-ended input.
Type:
signed binary word (32-bit).
Data Range:
0x00 to 0xFF
Read/Write:
R/W
Initialized Value:
0x95
Operational Settings:
(threshold Value) mV = (X 12)/94mV, where X is the decimal value to be set.<br>Example: With default setting of 0x95, (output voltage 12)/.094 = 0x95 → output voltage = (149(0x95) * .094V) - 12V = 2.006V. To get 10V output voltage the equation will be 10V = 12V/.094 = 234 = 0xEA
Input SE Crossing Threshold
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
D
D
D
D
D
D
D
D
Output Registers
The Clock Out Enable register provides the ability to choose either TTL
single-ended (SE) or RS-422 differential (DF) 3.3V output. The Output Enable register is used to enable 5V and 12V output 1 and 2.
Clock Out Enable
Function:
Enables the singled-ended and differential 3.3V output.
Type:
unsigned binary word (32-bit).
Data Range:
0x0 to 0x3
Read/Write:
R/W
Initialized Value:
0x0 (disabled)
Operational Settings:
Write a 0 to disable both outputs; write a 1 to enable single-ended; write a 2 to enable differential; write a 3’ to enable both outputs.
Clock Out Enable
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
D
0x3
Enable Single-Ended and Differential
0x2
Enable Differential
0x1
Enable Single-Ended
0x0
Disable
Output Enable
Function:
Enables both 5V and 12V outputs (1 & 2).
Type:
unsigned binary word (32-bit).
Data Range:
0x0 to 0x3
Read/Write:
R/W
Initialized Value:
0x0 (disabled)
Operational Settings:
Write a 0 to disable both outputs; write a 1 to enable 5V output; write a 2 to enable 12V output; write a 3 to enable both outputs.
Output Enable
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
D
Receive Registers
Serial data received are placed in the Receive FIFO Buffer register.
The Receive FIFO Buffer Word Count provide the count of the number of
elements in the Receive FIFO Buffer.
Receive FIFO Buffer
Function:
Received data is placed in this buffer.
Type:
unsigned binary word (32-bit).
Data Range:
0x0000 0000 to 0x0000 FFFF
Read/Write:
R
Initialized Value:
N/A
Operational Settings:
Data is received is based on Protocol.
Receive Buffer Asynchronous
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PE
PE
0
0
0
EOF
P
D
D
D
D
D
D
D
D
D
Asynchronous
PE
= Parity Error
A 1 indicates the calculated parity does not match the received parity bit.
FE
= Framing Error
A 1 indicates a framing error was detected.
EOF
= End of Frame
A 1 indicates an ETx character was received. Termination Character Detection must be turned on.
P
= Parity Bit
This bit carries the parity bit of the last received character.
Receive FIFO Buffer Word Count
Function:
Contains the number of words in the Receive FIFO Buffer waiting to be read back.
Type:
unsigned binary word (32-bits)
Data Range:
0 to 0x0000 0400 (Buffer Size)
Read/Write:
R
Initialized Value:
0
Operational Settings:
Reads Integers
Receive FIFO Buffer Almost Full
Function:
Specifies the maximum size, in bytes, of the receive buffer before the Receive FIFO Almost Full status bit D0 in the FIFO Status register is flagged (High True).
Type:
unsigned binary word (32-bits)
Data Range:
0 to 0x0000 0400 (Buffer Size)
Read/Write:
R/W
Initialized Value:
819 (0x0000 0333)
Operational Settings:
If the interrupt is enabled (see Interrupt Enable register), a System interrupt will be generated.
Transmit Registers
Serial data to be transmitted are placed in the Transmit FIFO Buffer
register.
Transmit FIFO Buffer
Function:
Data to be transmitted is placed in this buffer prior to transmission.
Type:
unsigned binary word (32-bits)
Data Range:
0x0000 0000 to 0x0000 01FF
Read/Write:
W
Initialized Value:
Not Applicable (NA)
Operational Settings:
Data words are 8-bit and occupy the register’s lowest significant bits (LSBs), or low byte.
Transmit Buffer
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
D1
D
D
D
D
D
D
D
D
Note 1: Data only in Asynchronous mode when data bits are set to 9.
Transmit FIFO Buffer Word Count
Function:
Contains the number of words in the Transmit FIFO Buffer waiting to be transmitted.
Type:
unsigned binary word (32-bits)
Data Range:
0 to 0x0000 0400 (Buffer Size)
Read/Write:
R
Initialized Value:
0
Operational Settings:
Transmits Integers
Transmit FIFO Buffer Almost Empty
Function:
Specifies the minimum size, in bytes, of the transmit buffer before the Transmit FIFO Almost Empty status bit D1 in the FIFO Status register is flagged (High True).
Type:
unsigned binary word (32-bits)
Data Range:
0 to 0x0000 0400 (Buffer Size)
Read/Write:
R/W
Initialized Value:
204 (0xCC)
Operational Settings:
If the interrupt is enabled (see Interrupt Enable register), a System interrupt will be generated.
Configuration Registers
PT1 configurations includes setting the Data Configuration, Baud Rate,
Termination Character and Time-Out Value registers.
Data Configuration
Function:
Channel data configuration.
Type:
unsigned binary word (32-bits)
Data Range:
See table
Read/Write:
R/W
Initialized Value:
0x108
Operational Settings:
Sets up the Serial channel configuration.
Data Configuration Register
Bit(s)
Name
Description
D31:D10
Reserved
Set Reserved bits to 0.
D9:D8
Stop Bits
The following sets the number of stop bits: (0:1) 1 Stop bit (1:0) 2 Stop bits
D7
Reserved
Set Reserved bits to 0.
D6:D4
Parity
The following sets the Parity: (0:0:0) No Parity (0:0:1) Space Parity (0:1:0) Reserved (0:1:1) Odd Parity (1:0:0) Reserved (1:0:1) Even Parity (1:1:1) Mark Parity
D3:D0
Number of Data Bits
Actual number of data bits between 5 and 9. For Asynchronous Protocol only.
Baud Rate
Function:
Sets the baud rate for communications.
Type:
unsigned binary word (32-bits)
Data Range:
300 bps to 20 Kbps
Read/Write:
R/W
Initialized Value:
9600 bps (0x2580)
Termination Character
Function:
Contains the termination character used for termination detection.
Type:
unsigned character (usually a member of the ASCII data set)
Data Range:
0x00 to 0xFF
Read/Write:
R/W
Initialized Value:
0x03
Operational Settings:
When using the Asynchronous mode, the receive data stream is monitored for the occurrence of the termination character. When this character is detected, the Rx COMPLETE / ETx RECEIVED bit is set in the Channel Status register, an interrupt is generated, if enabled.
Time Out Value
Function:
Determines the timeout period.
Type:
unsigned character (32-bits)
Data Range:
0 to 0xFFFF
Read/Write:
R/W
Initialized Value:
0x9C40 (1 second)
Operational Settings:
If there is no receive line activity for the configured period of time, a timeout is indicated in the Interrupt Status register, bit D10. LSB is 25µs. Modes Affected: Async.
Async Only Configuration
In Async mode, additional configuration includes setting the Tx-Rx
Configuration register.
Tx-Rx Configuration
Function:
Sets the transmit/receive configuration for the associated channel.
Type:
unsigned binary word (32-bits)
Data Range:
See table
Read/Write:
R/W
Initialized Value:
0
Operational Settings:
BIT - Set Enable Channel bit, D24 low (0) to clear the selected channel. Set Initiate BIT bit D27 high (1) to initiate BIT. After 5 msec, a 0 should be read, which indicates that the BIT test is complete. The BIT Status register reports the channel status.
Tx-Rx Configuration Register
Bit(s)
Name
Description
D31:D28
Reserved
Set Reserved bits to 0.
D27
Initiate BIT
Write a 1 to start built-in-test. The channel running BIT needs to be disabled, as well as it's channel pair. For common module functionality see the Test Enabled register.
D26:D25
Reserved
Set Reserved bits to 0.
D24
Enable Channel
0 = Disable, 1 = Enable.
D23:D21
Reserved
Set Reserved bits to 0.
D20
Enable Gap Timeout
0 = Ignore gap timeout 1 = Set Gap Timeout Occurred status when there is no activity on the receiver's bus for more than 3-byte times.
D19:D16
Reserved
Set Reserved bits to 0.
D15
Timeout Detection
Turns on timeout detection
D14:D13
Reserved
Set Reserved bits to 0.
D12
Termination Character Detection
0 = Ignore termination character 1 = Set Rx Complete/ETx Received status bit when termination character is received.
D11:D0
Reserved
Set Reserved bits to 0.
Control Registers
The Channel Control register provides control of the serial channel.
Channel Control
Function:
Channel control configuration.
Type:
unsigned binary word (32-bits)
Data Range:
See table.
Read/Write:
R/W
Initialized Value:
0
Operational Settings:
Real time control of the Serial channel.
Channel Control Register
Bit(s)
Name
Description
D31:D19
Reserved
Set Reserved bits to 0.
D18
Enable Receiver
D17
Tx Always (Async Only)
Transmit data as soon as data is buffered.
D16
Tx Initiate
Transmit data in Tx buffer. (The data bit is cleared when all data from the Tx Buffer is transmitted)
D15
Clear Tx FIFO
Clear all data in the Tx FIFO. The data bit is self-clearing.
D14
Clear Rx FIFO
Clear all data in the Rx FIFO. The data bit is self-clearing.
D13
Reset Channel FIFOs & UART
Clear both FIFOs and reset channel. Bit is not self-clearing.
D12:D11
Reserved
Set Reserved bits to 0.
D10
Set/Release Break
0 = Break not set, 1 = Pull transmitter low
D9
Reserved
Set Reserved bits to 0.
D8
Tristate Transmit Line
Tristate the transmit line after transmitting, for use with RS485 Multi-Drop mode.
D7:D0
Reserved
Set Reserved bits to 0.
Module Common Registers
Refer to “Module Common Registers Module Manual” for the register
descriptions.
Status and Interrupts Registers
The PT1 Module provides status registers for Serial Channel, Pulse Time, and
Channel FIFO.
Serial Channel Status
Function:
Sets the corresponding bit associated with each event type. There are separate registers for each channel.
Type:
unsigned binary word (32-bits)
Data Range:
See table.
Read/Write:
R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value:
0
Serial Channel Dynamic Status Register
Serial Channel Latched Status Register
Serial Channel Interrupt Enable Register
Serial Channel Set Edge/Level Interrupt Register
Bit(s)
Name
Configurable
Description
D31
Channel Configured
No
Module is configured and ready to operate.
D30
Built-in-Self Test Passed
No
Indicates the status of the last ran built-in self test.
D29:D18
Reserved
No
Set Reserved bits to 0.
D17
Gap Timeout Occurred
Yes
Rx FIFO has data in it, but there hasn't been activity on the bus in 3-byte times.
D16:D12
Reserved
No
Set Reserved bits to 0.
D11
Break/Abort
No
Break recognized.
D10
Timeout Occurred
Yes
No receive line activity within timeout value.
D9
Tx Complete
No
While transmitting, Tx FIFO count reaches zero.
D8
Tx FIFO Almost Empty
Yes
Transmit FIFO Almost Empty Threshold reached.
D7:D6
Reserved
No
Set Reserved bits to 0.
D5
Rx Overrun
No
Data was received while the Rx FIFO was full.
D4
Rx Data Available
No
Receive FIFO count is greater than zero.
D3
Rx Complete/ET x Received
No
Async: Termination character received (Only if termination detection is turned on.).
D2
Reserved
No
Set Reserved bits to 0.
D1
Rx FIFO Almost Full
Yes
Receive FIFO Almost Full Threshold
D0
Parity Error
No
Parity bit did not match.
Note
For the Latched Channel Status register, the interrupts are cleared when a (1) is written to the specific bit.
Pulse Time Channel Status
Function:
Sets the corresponding bit associated with each event type. There are separate registers for each channel.
Type:
unsigned binary word (32-bits)
Data Range:
See table.
Read/Write:
R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value:
0
Pulse Time Channel Dynamic Status Register
Pulse Time Channel Latched Status Register
Pulse Time Channel Interrupt Enable Register
Pulse Time Channel Set Edge/Level Interrupt Register
Bit(s)
Name
Configurable
Description
D31:D03
Reserved
No
Set Reserved bits to 0.
D2
Input Pulse Falling Edge
No
Set to a 1 when falling edge of the input pulse is detected; set back to 0 after that.
D1
Input Pulse Rising Edge
No
Set to a 1 when rising edge of the input pulse is detected; set back to 0 after that.
D0
Input State
No
Follows the state of the input pulse. If the input pulse is high, this bit is set to 1; otherwise, this bit is set to 0.
Note
For the Latched Channel Status register, the interrupts are cleared when a (1) is written to the specific bit.
Note
This register was implemented for FPGA version 1.6
Channel FIFO Status
Function:
Describes current FIFO Status.
Type:
unsigned binary word (32-bits)
Data Range:
See Table
Read/Write:
R
Initialized Value:
0
Operational Settings:
See Rx Almost Full, Tx Almost Empty, Rx High Watermark and Rx Low Watermark specific registers for function description and programming.
FIFO Status Register
Bit(s)
Name
Configurable?
Description
D5
Tx FIFO Full
No
Tx FIFO has reached maximum buffer size.
D4
Rx FIFO Empty
No
Rx FIFO count is zero.
D3
Reserved
No
Set Reserved bits to 0.
D2
Reserved
No
Set Reserved bits to 0.
D1
Tx FIFO Almost Empty
Yes
Tx FIFO Almost Empty Threshold reached.
D0
Rx FIFO Almost Full
Yes
Rx FIFO Almost Full Threshold reached.
FIFO Status Register
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
D
D
D
D
D
D
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.
In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
Interrupt Vector
Function:
Set an identifier for the interrupt.
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R/W
Initialized Value:
0
Operational Settings:
When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function:
Sets where to direct the interrupt.
Type:
unsigned binary word (32-bit)
Data Range:
See table
Read/Write:
R/W
Initialized Value:
0
Operational Settings:
When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME
1
Direct Interrupt to ARM Processor (via SerDes) + (Custom App on ARM or NAI Ethernet Listener App)
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
Input Registers
Addr (Hex)
Name
Read/Write
0x1600
Input Format Input 1
R/W
0x1680
Input Format Input 2
R/W
Addr (Hex)
Name
Read/Write
0x1604
Input Termination Input 1
R/W
0x1684
Input Termination Input 2
R/W
Addr (Hex)
Name
Read/Write
0x1608
Input Single-Ended Crossing Threshold Input 1
R/W
0x1688
Input Single-Ended Crossing Threshold Input 2
R/W
Output Registers
Addr (Hex)
Name
Read/Write
0x1200
Clock Out Enable Ch.1 (SE/DF)
R/W
0x1280
Clock Out Enable Ch.2 (SE/DF)
R/W
Addr (Hex)
Name
Read/Write
0x1300
Output Enable Ch.1 (5V/12V)
R/W
0x1380
Output Enable Ch.2 (5V/12V)
R/W
Receive Registers
Addr (Hex)
Name
Read/Write
0x1004
Receive FIFO Buffer Ch 1
R
0x1084
Receive FIFO Buffer Ch 2
R
Addr (Hex)
Name
Read/Write
0x1034
Receive FIFO Buffer Almost Full Ch 1
R/W
0x10B4
Receive FIFO Buffer Almost Full Ch 2
R/W
Addr (Hex)
Name
Read/Write
0x100C
Receive FIFO Buffer Word Count Ch 1
R
0x108C
Receive FIFO Buffer Word Count Ch 2
R
Transmit Registers
Addr (Hex)
Name
Read/Write
0x1000
Transmit FIFO Buffer Ch 1
W
0x1080
Transmit FIFO Buffer Ch 2
W
Addr (Hex)
Name
Read/Write
0x1008
Transmit FIFO Buffer Word Count Ch 1
R
0x1088
Transmit FIFO Buffer Word Count Ch 2
R
Addr (Hex)
Name
Read/Write
0x1030
Transmit FIFO Buffer Almost Empty Ch 1
R/W
0x10B0
Transmit FIFO Buffer Almost Empty Ch 2
R/W
Configuration Registers
Addr (Hex)
Name
Read/Write
0x1024
Data Configuration Ch 1
R/W
0x10A4
Data Configuration Ch 2
R/W
Addr (Hex)
Name
Read/Write
0x1028
Baud Rate Ch 1
R/W
0x10A8
Baud Rate Ch 2
R/W
Addr (Hex)
Name
Read/Write
0x1050
Termination Character Ch 1
R/W
0x10D0
Termination Character Ch 2
R/W
Addr (Hex)
Name
Read/Write
0x1054
Time Out Value Ch 1
R/W
0x10D4
Time Out Value Ch 2
R/W
Async Only Configuration Register
Addr (Hex)
Name
Read/Write
0x101C
Tx-Rx Configuration Ch 1
R/W
0x109C
Tx-Rx Configuration Ch 2
R/W
Control Registers
Addr (Hex)
Name
Read/Write
0x1020
Channel Control Ch 1
R/W
0x10A0
Channel Control Ch 2
R/W
Module Common Registers
Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.
Status Registers
Serial Channel Status
Addr (Hex)
Name
Read/Write
0x0810
Serial Channel Dynamic Status Ch 1
R
0x0814
Serial Channel Latched Status* Ch 1
R/W
0x0818
Serial Channel Interrupt Enable Ch 1
R/W
0x081C
Serial Channel Set Edge/Level Interrupt Ch1
R/W
Addr (Hex)
Name
Read/Write
0x0820
Serial Channel Dynamic Status Ch 2
R
0x0824
Serial Channel Latched Status* Ch 2
R/W
0x0828
Serial Channel Interrupt Enable Ch 2
R/W
0x082C
Serial Channel Set Edge/Level Interrupt Ch 2
R/W
Pulse Time Channel Status
Addr (Hex)
Name
Read/Write
0x0830
Pulse Time Channel Dynamic Status Ch 1
R
0x0834
Pulse Time Channel Latched Status* Ch 1
R/W
0x0838
Pulse Time Channel Interrupt Enable Ch 1
R/W
0x083C
Pulse Time Channel Set Edge/Level Interrupt Ch1
R/W
Addr (Hex)
Name
Read/Write
0x0840
Pulse Time Channel Dynamic Status Ch 2
R
0x0844
Pulse Time Channel Latched Status* Ch 2
R/W
0x0848
Pulse Time Channel Interrupt Enable Ch 2
R/W
0x084C
Pulse Time Channel Set Edge/Level Interrupt Ch 2
R/W
FIFO Status
Addr (Hex)
Name
Read/Write
0x1058
FIFO Status Ch 1
R
0x10D8
FIFO Status Ch 2
R
Interrupt Registers
The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.
Addr (Hex)
Name
Read/Write
0x0500
Module 1 Interrupt Vector 1 - Reserved
R/W
0x0504
Module 1 Interrupt Vector 2 - Serial Channel Status Ch 1
R/W
0x0508
Module 1 Interrupt Vector 3 - Serial Channel Status Ch 2
R/W
0x050C
Module 1 Interrupt Vector 4 - Pulse Time Channel Status Ch 1
R/W
0x0510
Module 1 Interrupt Vector 5 - Pulse Time Channel Status Ch 2
R/W
0x0514 to 0x057C
Module 1 Interrupt Vector 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x0600
Module 1 Interrupt Steering 1 - Reserved
R/W
0x0604
Module 1 Interrupt Steering 2 - Serial Channel Status Ch 1
R/W
0x0608
Module 1 Interrupt Steering 3 - Serial Channel Status Ch 2
R/W
0x060C
Module 1 Interrupt Steering 4 - Pulse Time Channel Status Ch 1
R/W
0x0610
Module 1 Interrupt Steering 5 - Pulse Time Channel Status Ch 2
R/W
0x0614 to 0x067C
Module 1 Interrupt Steering 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x0700
Module 2 Interrupt Vector 1 - Reserved
R/W
0x0704
Module 2 Interrupt Vector 2 - Serial Channel Status Ch 1
R/W
0x0708
Module 2 1Interrupt Vector 3 - Serial Channel Status Ch 2
R/W
0x070C
Module 2 Interrupt Vector 4 - Pulse Time Channel Status Ch 1
R/W
0x0710
Module 2 Interrupt Vector 5 - Pulse Time Channel Status Ch 2
R/W
0x0714 to 0x757C
Module 2 Interrupt Vector 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x0800
Module 2 Interrupt Steering 1 - Reserved
R/W
0x0804
Module 2 Interrupt Steering 2 - Serial Channel Status Ch 1
R/W
0x0808
Module 2 Interrupt Steering 3 - Serial Channel Status Ch 2
R/W
0x080C
Module 2 Interrupt Steering 4 - Pulse Time Channel Status Ch 1
R/W
0x0810
Module 2 Interrupt Steering 5 - Pulse Time Channel Status Ch 2
R/W
0x0814 to 0x087C
Module 2 Interrupt Steering 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x0900
Module 3 Interrupt Vector 1 - Reserved
R/W
0x0904
Module 3 Interrupt Vector 2 - Serial Channel Status Ch 1
R/W
0x0908
Module 3 Interrupt Vector 3 - Serial Channel Status Ch 2
R/W
0x090C
Module 3 Interrupt Vector 4 - Pulse Time Channel Status Ch 1
R/W
0x0910
Module 3 Interrupt Vector 5 - Pulse Time Channel Status Ch 2
R/W
0x0914 to 0x097C
Module 3 Interrupt Vector 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x0A00
Module 3 Interrupt Steering 1 - Reserved
R/W
0x0A04
Module 3 Interrupt Steering 2 - Serial Channel Status Ch 1
R/W
0x0A08
Module 3 Interrupt Steering 3 - Serial Channel Status Ch 2
R/W
0x0A0C
Module 3 Interrupt Steering 4 - Pulse Time Channel Status Ch 1
R/W
0x0A10
Module 3 Interrupt Steering 5 - Pulse Time Channel Status Ch 2
R/W
0x0A14 to 0x0A7C
Module 3 Interrupt Steering 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x0B00
Module 4 Interrupt Vector 1 - Reserved
R/W
0x0B04
Module 4 Interrupt Vector 2 - Serial Channel Status Ch 1
R/W
0x0B08
Module 4 Interrupt Vector 3 - Serial Channel Status Ch 2
R/W
0x0B0C
Module 4 Interrupt Vector 4 - Pulse Time Channel Status Ch 1
R/W
0x0B10
Module 4 Interrupt Vector 5 - Pulse Time Channel Status Ch 2
R/W
0x0B14 to 0x0B7C
Module 4 Interrupt Vector 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x0C00
Module 4 Interrupt Steering 1 - Reserved
R/W
0x0C04
Module 4 Interrupt Steering 2 - Serial Channel Status Ch 1
R/W
0x0C08
Module 4 Interrupt Steering 3 - Serial Channel Status Ch 2
R/W
0x0C0C
Module 4 Interrupt Steering 4 - Pulse Time Channel Status Ch 1
R/W
0x0C10
Module 4 Interrupt Steering 5 - Pulse Time Channel Status Ch 2
R/W
0x0C14 to 0x0C7C
Module 4 Interrupt Steering 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x0D00
Module 5 Interrupt Vector 1 - Reserved
R/W
0x0D04
Module 5 Interrupt Vector 2 - Serial Channel Status Ch 1
R/W
0x0D08
Module 5 Interrupt Vector 3 - Serial Channel Status Ch 2
R/W
0x0D0C
Module 5 Interrupt Vector 4 - Pulse Time Channel Status Ch 1
R/W
0x0D10
Module 5 Interrupt Vector 5 - Pulse Time Channel Status Ch 2
R/W
0x0D14 to 0x0D7C
Module 5 Interrupt Vector 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x0E00
Module 5 Interrupt Steering 1 - Reserved
R/W
0x0E04
Module 5 Interrupt Steering 2 - Serial Channel Status Ch 1
R/W
0x0E08
Module 5 Interrupt Steeringr 3 - Serial Channel Status Ch 2
R/W
0x0E0C
Module 5 Interrupt Steeringr 4 - Pulse Time Channel Status Ch 1
R/W
0x0E10
Module 5 Interrupt Steering 5 - Pulse Time Channel Status Ch 2
R/W
0x0E14 to 0x0E7C
Module 5 Interrupt Steering 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x0F00
Module 6 Interrupt Vector 1 - Reserved
R/W
0x0F04
Module 6 Interrupt Vector 2 - Serial Channel Status Ch 1
R/W
0x0F08
Module 6 Interrupt Vector 3 - Serial Channel Status Ch 2
R/W
0x0F0C
Module 6 Interrupt Vector 4 - Pulse Time Channel Status Ch 1
R/W
0x0F10
Module 6 Interrupt Vector 5 - Pulse Time Channel Status Ch 2
R/W
0x0F14 to 0x0F7C
Module 6 Interrupt Vector 6 to 32 - Reserved
R/W
Addr (Hex)
Name
Read/Write
0x1000
Module 6 Interrupt Steering 1 - Reserved
R/W
0x1004
Module 6 Interrupt Steering 2 - Serial Channel Status Ch 1
R/W
0x1008
Module 6 Interrupt Steering 3 - Serial Channel Status Ch 2
R/W
0x100C
Module 6 Interrupt Steering 4 - Pulse Time Channel Status Ch 1
R/W
0x1010
Module 6 Interrupt VSteering 5 - Pulse Time Channel Status Ch 2
R/W
0x1014 to 0x107C
Module 6 Interrupt Steering 6 to 32 - Reserved
R/W
APPENDIX: PINOUT DETAILS
Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals.
Module Signal (Ref Only)
44-Pin I/O
50-Pin I/O (Mod Slot 1-J3)
50-Pin I/O (Mod Slot 2-J4)
50-Pin I/O (Mod Slot 3-J3)
50-Pin I/O (Mod Slot 3-J4)
Pulse Timer (PT1)
DATIO1
2
10
1
2
RXDLO-CH1
DATIO2
24
35
26
27
RXDHI-CH1
DATIO3
3
11
2
3
TXDHI-CH1
DATIO4
25
36
27
28
TXDLO-CH1
DATIO5
5
13
4
5
GND-ISO-CH1
DATIO6
27
38
29
30
GND-D
DATIO7
7
14
5
6
CLK-OUT1-N
DATIO8
29
39
30
31
CLK-OUT1-P
DATIO9
8
15
6
7
CH1-IO-P
DATIO10
30
40
31
32
CH1-IO-N
DATIO11
10
17
8
9
OUT12V1_A*
DATIO12
32
42
33
34
OUT12V2_A*
DATIO13
12
18
9
17
TXDHI-CH2
DATIO14
34
43
34
42
TXDLO-CH2
DATIO15
13
19
10
18
RXDLO-CH2
DATIO16
35
44
35
43
RXDHI-CH2
DATIO17
15
21
12
20
GND-D
DATIO18
37
46
37
45
GND-ISO-CH2
DATIO19
17
22
13
21
CLK-OUT2-P
DATIO20
39
47
38
46
CLK-OUT2-N
DATIO21
18
23
14
22
CH2-IO-P
DATIO22
40
48
39
47
CH2-IO-N
DATIO23
20
25
16
24
OUT5V1_B*
DATIO24
42
50
41
49
OUT5V2_B*
DATIO25
4
12
3
4
OUT5V1_A*
DATIO26
26
37
28
29
OUT5V2_A*
DATIO27
9
16
7
8
CLK-OUT1-SE
DATIO28
31
41
32
33
N/C
DATIO29
14
20
11
19
OUT12V1_B*
DATIO30
36
45
36
44
OUT12V2_B*
DATIO31
19
24
15
23
CLK-OUT2-SE
DATIO32
41
49
40
48
N/C
DATIO33
6
DATIO34
28
DATIO35
11
DATIO36
33
DATIO37
16
DATIO38
38
DATIO39
21
DATIO40
43
N/A
Note
*For current 5V output configuration, please note that OUT5V1_A & OUT5V2_A correspond to channel 1, and OUT5V1_B & OUT5V2_B
correspond to channel 2. For current 12V output configuration, please note that OUT12V1_A & OUT12V2_A correspond to channel 1, and
OUT12V1_B & OUT12V2_B correspond to channel 2. These assignments may change in future iterations, so it is important to NOT assume that there is a fixed channel-to-output mapping.
REVISION HISTORY
Motherboard Manual - SG1 Revision History
Revision
Revision Date
Description
C
2023-12-06
ECO C11035, initial release of manual.
DOCS.NAII REVISIONS
Revision Date
Description
2025-11-10
Removed PBIT & CBIT from Principle of Operation. Corrected example in Input SE Xing Threshold. Removed Background BIT Threshold Programming register details & offsets. Removed BIT Status register and offsets. Removed IBIT reference from Serial Channel Status register bit 30 description. Added Pulse Time Channel Status register details & offsets; added Note regarding when register was added to FPGA.
2025-12-12
Added note to Input Termination register to state that SE / SE with Threshold support for termination was implemented for FPGA version 1.7 and later.
STATUS AND INTERRUPTS
Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.
For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.
Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.
Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).
Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.
Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).
Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edge-triggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Interrupt Trigger Types
In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.
Example 1: Fault detection
This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.
Example 2: Threshold detection
This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.
Dynamic and Latched Status Registers Examples
The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.
Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States
No Clearing of Latched Status
Clearing of Latched Status (Edge-Triggered)
Clearing of Latched Status(Level-Triggered)
Time
Dynamic Status
Latched Status
Action
Latched Status
Action
Latched
T0
0x0
0x0
Read Latched Register
0x0
Read Latched Register
0x0
T1
0x1
0x1
Read Latched Register
0x1
0x1
T1
0x1
0x1
Write 0x1 to Latched Register
Write 0x1 to Latched Register
T1
0x1
0x1
0x0
0x1
T2
0x0
0x1
Read Latched Register
0x0
Read Latched Register
0x1
T2
0x0
0x1
Read Latched Register
0x0
Write 0x1 to Latched Register
T2
0x0
0x1
Read Latched Register
0x0
0x0
T3
0x2
0x3
Read Latched Register
0x2
Read Latched Register
0x2
T3
0x2
0x3
Write 0x2 to Latched Register
Write 0x2 to Latched Register
T3
0x2
0x3
0x0
0x2
T4
0x2
0x3
Read Latched Register
0x1
Read Latched Register
0x3
T4
0x2
0x3
Write 0x1 to Latched Register
Write 0x3 to Latched Register
T4
0x2
0x3
0x0
0x2
T5
0xC
0xF
Read Latched Register
0xC
Read Latched Register
0xE
T5
0xC
0xF
Write 0xC to Latched Register
Write 0xE to Latched Register
T5
0xC
0xF
0x0
0xC
T6
0xC
0xF
Read Latched Register
0x0
Read Latched
0xC
T6
0xC
0xF
Read Latched Register
0x0
Write 0xC to Latched Register
T6
0xC
0xF
Read Latched Register
0x0
0xC
T7
0x4
0xF
Read Latched Register
0x0
Read Latched Register
0xC
T7
0x4
0xF
Read Latched Register
0x0
Write 0xC to Latched Register
T7
0x4
0xF
Read Latched Register
0x0
0x4
T8
0x4
0xF
Read Latched Register
0x0
Read Latched Register
0x4
Interrupt Examples
The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.
Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled
Time
Latched Status (Edge-Triggered - Clear Multi-Channel)
Latched Status (Edge-Triggered - Clear Single Channel) 2+
Latched Status (Level-Triggered - Clear Multi-Channel)
Action
Latched
Action
Latched
Action
Latched
T1 (Int 1)
Interrupt Generated++``+ Read Latched Registers
0x1
Interrupt Generated++``+ Read Latched Registers
0x1
Interrupt Generated++``+ Read Latched Registers
0x1
T1 (Int 1)
Write 0x1 to Latched Register
Write 0x1 to Latched Register
Write 0x1 to Latched Register
T1 (Int 1)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear until T2.
0x1
T3 (Int 2)
Interrupt Generated++``+ Read Latched Registers
0x2
Interrupt Generated++``+ Read Latched Registers
0x2
Interrupt Generated++``+ Read Latched Registers
0x2
T3 (Int 2)
Write 0x2 to Latched Register
Write 0x2 to Latched Register
Write 0x2 to Latched Register
T3 (Int 2)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear until T7.
0x2
T4 (Int 3)
Interrupt Generated++``+ Read Latched Registers
0x1
Interrupt Generated++``+ Read Latched Registers
0x1
Interrupt Generated++``+ Read Latched Registers
0x3
T4 (Int 3)
Write 0x1 to Latched Register
Write 0x1 to Latched Register
Write 0x3 to Latched Register
T4 (Int 3)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.
0x3
T4 (Int 3)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear until T7.
0x2
T6 (Int 4)
Interrupt Generated++``+ Read Latched Registers
0xC
Interrupt Generated++``+ Read Latched Registers
0xC
Interrupt Generated++``+ Read Latched Registers
0xE
T6 (Int 4)
Write 0xC to Latched Register
Write 0x4 to Latched Register
Write 0xE to Latched Register
T6 (Int 4)
0x0
Interrupt re-triggers++``+ Write 0x8 to Latched Register
0x8
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.
0xE
T6 (Int 4)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.
0xC
T6 (Int 4)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.
0x4
REVISION HISTORY
Motherboard Manual - Status and Interrupts Revision History
Revision
Revision Date
Description
C
2021-11-30
C08896; Transition manual to docbuilder format - no technical info change.
DOCS.NAII REVISIONS
Revision Date
Description
2026-03-02
Formatting updates to document; no technical changes.
The registers described in this document are common to all NAI Generation 5 modules.
Module Information Registers
The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.
FPGA Version Registers
The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.
FPGA Revision
Function:
FPGA firmware revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the revision of the board's FPGA
Operational Settings:
The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
FPGA Compile Timestamp
Function:
Compile Timestamp for the FPGA firmware.
Type:
unsigned binary word (32-bit)
Data Range:
N/A
Read/Write:
R
Initialized Value:
Value corresponding to the compile timestamp of the board's FPGA
Operational Settings:
The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
day (5-bits)
month (4-bits)
year (6-bits)
hr
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
hour (5-bits)
minutes (6-bits)
seconds (6-bits)
FPGA SerDes Revision
Function:
FPGA SerDes revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the SerDes revision of the board's FPGA
Operational Settings:
The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
FPGA Template Revision
Function:
FPGA Template revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the template revision of the board's FPGA
Operational Settings:
The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
FPGA Zynq Block Revision
Function:
FPGA Zynq Block revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the Zynq block revision of the board's FPGA
Operational Settings:
The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
Bare Metal Version Registers
The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.
Bare Metal Revision
Function:
Bare Metal firmware revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the revision of the board's Bare Metal
Operational Settings:
The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
Bare Metal Compile Time
Function:
Provides an ASCII representation of the Date/Time for the Bare Metal compile time.
Type:
24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range:
N/A
Read/Write:
R
Initialized Value:
Value corresponding to the ASCII representation of the compile time of the board's Bare Metal
Operational Settings:
The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32
Note
little-endian order of ASCII values
Word 1 (Ex. 0x2079614D)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Space (0x20)
Month ('y' - 0x79)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Month ('a' - 0x61)
Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Year ('2' - 0x32)
Space (0x20)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Day ('7' - 0x37)
Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Space (0x20)
Year ('9' - 0x39)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Year ('1' - 0x31)
Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Hour ('1' - 0x31)
Space (0x20)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
'a' (0x74)
't' (0x61)
Word 5 (Ex. 0x38333A35)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Minute ('8' - 0x38)
Minute ('3' - 0x33)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
':' (0x3A)
Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
NULL (0x00)
Seconds ('2' - 0x32)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Seconds ('3' - 0x33)
':' (0x3A)
FSBL Version Registers
The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).
FSBL Revision
Function:
FSBL firmware revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the revision of the board's FSBL
Operational Settings:
The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
FSBL Compile Time
Function:
Provides an ASCII representation of the Date/Time for the FSBL compile time.
Type:
24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range:
N/A
Read/Write:
R
Initialized Value:
Value corresponding to the ASCII representation of the Compile Time of the board's FSBL
Operational Settings:
The six 32-bit words provide an ASCII representation of the Date/Time.
The hexadecimal values in the field below represent: May 17 2019 at 15:38:32
Note
little-endian order of ASCII values
Word 1 (Ex. 0x2079614D)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Space (0x20)
Month ('y' - 0x79)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Month ('a' - 0x61)
Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Year ('2' - 0x32)
Space (0x20)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Day ('7' - 0x37)
Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Space (0x20)
Year ('9' - 0x39)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Year ('1' - 0x31)
Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Hour ('1' - 0x31)
Space (0x20)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
'a' (0x74)
't' (0x61)
Word 5 (Ex. 0x38333A35)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Minute ('8' - 0x38)
Minute ('3' - 0x33)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
':' (0x3A)
Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
NULL (0x00)
Seconds ('2' - 0x32)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Seconds ('3' - 0x33)
':' (0x3A)
Module Serial Number Registers
The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.
Interface Board Serial Number
Function:
Unique 128-bit identifier used to identify the interface board.
Type:
16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range:
N/A
Read/Write:
R
Initialized Value:
Serial number of the interface board
Operational Settings:
This register is for information purposes only.
Functional Board Serial Number
Function:
Unique 128-bit identifier used to identify the functional board.
Type:
16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range:
N/A
Read/Write:
R
Initialized Value:
Serial number of the functional board
Operational Settings:
This register is for information purposes only.
Module Capability
Function:
Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0x0000 0107
Read/Write:
R
Initialized Value:
0x0000 0107
Operational Settings:
A “1” in the bit associated with the capability indicates that it is supported.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
Flt-Pt
0
0
0
0
0
Pack
FIFO Blk
Blk
Module Memory Map Revision
Function:
Module Memory Map revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the Module Memory Map Revision
Operational Settings:
The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
Module Measurement Registers
The registers in this section provide module temperature measurement information.
Temperature Readings Registers
The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.
Interface Board Current Temperature
Function:
Measured PCB and Zynq Core temperatures on Interface Board.
Type:
signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:
0x0000 0000 to 0x0000 FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the measured PCB and Zynq core temperatures based on the table below
Operational Settings:
The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PCB Temperature
Zynq Core Temperature
Functional Board Current Temperature
Function:
Measured PCB temperature on Functional Board.
Type:
signed byte (8-bits) for PCB
Data Range:
0x0000 0000 to 0x0000 00FF
Read/Write:
R
Initialized Value:
Value corresponding to the measured PCB on the table below
Operational Settings:
The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
PCB Temperature
Interface Board Maximum Temperature
Function:
Maximum PCB and Zynq Core temperatures on Interface Board since power-on.
Type:
signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:
0x0000 0000 to 0x0000 FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings:
The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PCB Temperature
Zynq Core Temperature
Interface Board Minimum Temperature
Function:
Minimum PCB and Zynq Core temperatures on Interface Board since power-on.
Type:
signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:
0x0000 0000 to 0x0000 FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings:
The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PCB Temperature
Zynq Core Temperature
Functional Board Maximum Temperature
Function:
Maximum PCB temperature on Functional Board since power-on.
Type:
signed byte (8-bits) for PCB
Data Range:
0x0000 0000 to 0x0000 00FF
Read/Write:
R
Initialized Value:
Value corresponding to the measured PCB on the table below
Operational Settings:
The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
PCB Temperature
Functional Board Minimum Temperature
Function:
Minimum PCB temperature on Functional Board since power-on.
Type:
signed byte (8-bits) for PCB
Data Range:
0x0000 0000 to 0x0000 00FF
Read/Write:
R
Initialized Value:
Value corresponding to the measured PCB on the table below
Operational Settings:
The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
PCB Temperature
Higher Precision Temperature Readings Registers
These registers provide higher precision readings of the current Zynq and PCB temperatures.
Higher Precision Zynq Core Temperature
Function:
Higher precision measured Zynq Core temperature on Interface Board.
Type:
signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Measured Zynq Core temperature on Interface Board
Operational Settings:
The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.
signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Measured Interface PCB temperature
Operational Settings:
The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.
signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Measured Functional PCB temperature
Operational Settings:
The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Signed Integer Part of Temperature
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Fractional Part of Temperature
Module Health Monitoring Registers
The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.
Module Sensor Summary Status
Function:
The corresponding sensor bit is set if the sensor has crossed any of its thresholds.
Type:
unsigned binary word (32-bits)
Data Range:
See table below
Read/Write:
R
Initialized Value:
0
Operational Settings:
This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.
Bit(s)
Sensor
D31:D6
Reserved
D5
Functional Board PCB Temperature
D4
Interface Board PCB Temperature
D3:D0
Reserved
Module Sensor Registers
The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.
Sensor Threshold Status
Function:
Reflects which threshold has been crossed
Type:
unsigned binary word (32-bits)
Data Range:
See table below
Read/Write:
R
Initialized Value:
0
Operational Settings:
The associated bit is set when the sensor reading exceed the corresponding threshold settings.
Bit(s)
Description
D31:D4
Reserved
D3
Exceeded Upper Critical Threshold
D2
Exceeded Upper Warning Threshold
D1
Exceeded Lower Critical Threshold
D0
Exceeded Lower Warning Threshold
Sensor Current Reading
Function:
Reflects current reading of temperature sensor
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R
Initialized Value:
N/A
Operational Settings:
The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Minimum Reading
Function:
Reflects minimum value of temperature sensor since power up
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R
Initialized Value:
N/A
Operational Settings:
The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Maximum Reading
Function:
Reflects maximum value of temperature sensor since power up
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R
Initialized Value:
N/A
Operational Settings:
The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Lower Warning Threshold
Function:
Reflects lower warning threshold of temperature sensor
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R/W
Initialized Value:
Default lower warning threshold (value dependent on specific sensor)
Operational Settings:
The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.
Sensor Lower Critical Threshold
Function:
Reflects lower critical threshold of temperature sensor
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R/W
Initialized Value:
Default lower critical threshold (value dependent on specific sensor)
Operational Settings:
The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.
Sensor Upper Warning Threshold
Function:
Reflects upper warning threshold of temperature sensor
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R/W
Initialized Value:
Default upper warning threshold (value dependent on specific sensor)
Operational Settings:
The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.
Sensor Upper Critical Threshold
Function:
Reflects upper critical threshold of temperature sensor
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R/W
Initialized Value:
Default upper critical threshold (value dependent on specific sensor)
Operational Settings:
The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.
Motherboard Manual - Module Common Registers Revision History
Revision
Revision Date
Description
C
2023-08-11
ECO C10649, initial release of module common registers manual.
C1
2024-05-15
ECO C11522, removed Zynq Core/Aux/DDR Voltage register descriptions from Module Measurement Registers. Pg.16, updated Module Sensor Summary Status register to add PS references; updated Bit Table to change voltage/current bits to 'reserved'. Pg.16, updated Module/Power Supply Sensor Registers description to better describe register functionality and to add figure. Pg.17, added 'Exceeded' to threshold bit descriptions. Pg.17-18, removed voltage/current references from sensor descriptions. Pg.20, removed Zynq Core/Aux/DDR Voltage register offsets from Module Measurement Registers. Pg.20, updated Module Health Monitoring Registers offset tables.
C2
2024-07-10
ECO C11701, pg.16, updated Module Sensor Summary Status register to remove PS references;updated Bit Table to change PS temperature bits to 'reserved'. Pg.16, updated Module SensorRegisters description to remove PS references. Pg.20, updated Module Health MonitoringRegisters offset tables to remove PS temperature register offsets.
DOCS.NAII REVISIONS
Revision Date
Description
2025-11-05
Corrected register offsets for Interface Board Min Temp and Function Board Min & Max Temps.
2026-03-02
Formatting updates to document; no technical changes.
North Atlantic Industries (NAI) is a leading independent supplier of Embedded I/O Boards, Single Board Computers, Rugged Power Supplies, Embedded Systems and Motion Simulation and Measurement Instruments for the Military, Aerospace and Industrial Industries. We accelerate our clients’ time-to-mission with a unique approach based on a Configurable Open Systems Architecture™ (COSA®) that delivers the best of both worlds: custom solutions from standard COTS components.
We have built a reputation by listening to our customers, understanding their needs, and designing, testing and delivering board and system-level products for their most demanding air, land and sea requirements. If you have any applications or questions regarding the use of our products, please contact us for an expedient solution.
Please visit us at: www.naii.com or select one of the following for immediate assistance:
Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States
Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled
