DATA SHEET
Click here for the LDx data sheet
INTRODUCTION
This module manual provides information about the North Atlantic Industries, Inc. (NAI) LVDT or RVDT Function Modules: LD1-LD5. These modules are compatible with all NAI Generation 5 motherboards.
Modules LD1, LD2, LD3, LD4, and LD5 provide Linear Variable Differential Transformer (LVDT) or Rotary Variable Differential Transformer (RVDT) measurement. An LVDT is a type of electrical transformer/transducer used for measuring linear displacement (position). The RVDT is like an LVDT in that it measures a positional displacement, however, the displacement, which is still a linear proportional function, is based on rotary instead of linear positional movement. Both types provide output signals (voltages) as a proportional linear function based upon an AC Reference source. The AC Reference source applied at the transformer primary winding causes a magnetic flux generated on the transformer secondary windings by a moveable core, which causes output signal(s) proportional to the linear displacement position being gauged.
Both deliver signals proportional to the linear displacement of the moveable core. LD1-LD5 convert these signals to a digital output corresponding to position. See the following table for each model’s operating parameters.
For the remainder of this document, LVDT and RVDT acronyms may be used interchangeably as the fundamental operation and interface for both are essentially the same.
| Module ID | No. of Ch. | Description |
|---|---|---|
| LD1 | 4 | 2-28 Vrms Input, 47 Hz -1 KHz |
| LD2 | 4 | 2-28 Vrms Input, 1 KHz - 5 KHz |
| LD3 | 4 | 2-28 Vrms Input, 5 KHz - 10 KHz |
| LD4 | 4 | 2-28 Vrms Input, 10 KHz - 20 KHz |
| LD5 | 4 | 28-90 Vrms Input, 47 Hz - 1 KHz |
FEATURES
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With isolated excitation and signal input covering 2, 3, or 4-wire transducer interfaces and a normalized digital position word based on a percentage of full-scale travel, the LVDT/RVDT modules are able to interface to virtually any type LVDT or RVDT transformer.
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The channels include many other useful application features such as signal, reference, and frequency measurements as well as signal under- and over-voltage detection, and reference under- and over-voltage detections.
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All channels have continuous background Built-In-Test (BIT).
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The modules also include extended LVDT FIFO buffering capabilities for greater storage/management of the incoming signal samples (data) for post processing applications. Programmable FIFO buffer thresholds maximize data flow control (in and out of the FIFO).
PRINCIPLE OF OPERATION
The modules cover a wide range of reference voltages/frequencies, so they can interface to almost any transducer. With isolated reference and signal input covering 2-, 3-, or 4-wire transducer interfaces and a normalized digital position word based on a percentage of full-scale travel, these modules can interface to virtually any type LVDT or RVDT transformer.
The conversion of input signals to position is performed as a tracking, ratio-metric calculation. This conversion uses phase sensitive demodulation, and band limiting techniques. This enhances the accuracy and performance by reducing the sensitivity to the noise and quadrature, in the input signals (caused by stray capacitive coupling, in the wiring.).
Two common connection methods are:
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Primary as reference (2-wire system)
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Derived reference (3- or 4-wire system)
Figure 1. Various LVDT Configurations
2-Wire System
In a 2-Wire LVDT system, when the primary coil is excited with an excitation voltage (Excitation IN), this voltage produces a current in the windings (function of the input impedance). The variable current generates a variable magnetic flux which induces voltages in the secondary windings, Va and Vb, as a function of the core position The secondary windings are connected in series to produce the differential voltage Va - Vb. The amplitude of the differential output voltage (Va-Vb) is proportional to the core position. The phase of (Va-Vb) with respect to the excitation, is typically 5 to 10 deg, and is usually specified by the manufacture.
The 2-Wire LVDT system allows the minimum numbers of electrical connections to the LVDT, as only 4 are required (2 for the excitation and 2 for the differential output). In this configuration (refer to Figure 1), connect “a-b” LVDT output to Signal A (A HI and A LO) and the Excitation-toExcitation Ref Hi and Excitation Ref Lo.
This Excitation signal will be scaled by the value in the Transformation Ratio (TR) Value register, to adjust the full-scale value of the output position to +/- 100%. The Excitation signal will also be phase compensated with the phase shift in the phase shift register. This will reduce the sensitivity to Quadrature signals caused by the system wiring and null voltage of the LVDT. The Position of the LVDT will be calculated as the ratio of the Signal A to this adjusted Excitation signal. This excitation signal is monitored for signal level and the converter will report if signal level is not within levels specified in reference level registers.
Some of the drawbacks of the 2 Wire LVDT system are the variation in TR and Phase Shift from LVDT to LVDT and over temperature can produce degraded positional accuracies.
In a 2-Wire LVDT system the position is measured as *(Va-Vb) / (TR ** VEXCITATION )
Where TR is the transformation ratio of the LVDT, specified by manufacturer.
This position ratio is determined using a tracking algorithm that is Phase sensitive, which rejects the null error signal, as well as errors from quadrature signals caused by coupling, in the system wiring. The phase information is derived from the Excitation Ref inputs. Programmable fixed phase shift compensation is provided.
This algorithm is also bandwidth limited to reduce errors due to noise in input signals. The bandwidth is programmable to allow users to increase filtering in noisy environments.
Operational Note:
Programming a channel for 2-wire mode essentially doubles the channel count by ‘splitting’ independent channels into two separate, ACReference (Excitation) dependent channel pairs.
Example: Independent channel CHx is “split” into dependent channel pairs: CHxA & CHxB. 2-wire mode channel pairs require and expect to use the single CHx REF Hi/Lo inputs. Since these channel pairs are dependent, any LVDT operating characteristic parameters must be consistent with the common AC Reference (Excitation) source which is applied to each of the channel pairs.
Each channel of a channel pair can interface to independent LVDTs and provide two independent position (and signal) related measurements. However, because the same AC Reference (Excitation) source is applied and is being utilized by both channels of the pair, it is also implied that the programmable characteristics of the channel pairs must be the same. In other words, LVDT characteristics (e.g., transformation ratio (TR)) must be the same for the CHxA and CHxB). Therefore, there is no “B-side” TR register; as the channel B-side of the pair will use the same programmed TR as the “A-side”.
For operational consistency, it is recommended that the independent LVDTs interfaced to the 2-wire mode channel pairs are of the same model/type with similar operating characteristics.
3-Wire or 4-Wire System
In 3-Wire and 4-Wire LVDT systems, the LVDT is designed to maintain a constant sum of the secondary voltages (Va+Vb) over the measuring stroke length. This allows the system to be insensitive to temperature effects, phase shifts and oscillator instability.
In the 3-Wire configuration (refer to Figure 1), connect the “a” and “b” (Hi) LVDT outputs to the A HI and B HI inputs respectively and the common center tap (“a” and “b” (Lo)) to A LO and B LO inputs.
In the 4-Wire configuration (refer to Figure 1), connect the “a” (Hi, Lo) outputs to A HI and A LO and “b” (Hi, Lo) outputs to B HI and B LO.
Note that the Reference is not used in calculating the position but should be connected to enable the channel to initially phase lock to the excitation voltage, and to monitor and report if the Reference level is not within levels specified in reference level registers.
In a 3-Wire and 4-Wire LVDT system the position is measured as (Va-Vb) / (Va+Vb).
This position ratio is determined using a tracking algorithm that is Phase sensitive, which rejects the null error signal, as well as errors from quadrature signals caused by coupling, in the system wiring. The phase information is derived from the ( Va + Vb ) signal
This algorithm is also bandwidth limited to reduce errors due to noise in input signals. The bandwidth is programmable to allow users to increase filtering in noisy environments.
Position Measurement
The LVDT/RVDT channels measure the LVDT position as a percentage of full-scale coupling (+/- FS) If the coupling is limited by the linear range of the LVDT, the output can be scaled to indicate full scale travel at a limited coupling position, with the use of the LVDT/RVDT scaling register. i.e., 85 % coupling can be scaled to indicate 100 % travel position.
3 or 4-wire configured channels provide a single LVDT position. 2-wire configured channels can provide two independent LVDT positions, as long as they share the same excitation signal. it reads the position of the signal on the “Va” input as Position A and “Vb” input as Position B
Velocity Measurement
The conversion of input signals to position is performed using a tracking algorithm. This algorithm produces a value that is proportional to the rate of change of the Output position. This value is supplied as the velocity of the output and is updated at every sample time.
Bandwidth Setting
The conversion of input signals to position is performed using a bandlimited tracking algorithm. The Bandwidth of this algorithm can be set manually or set automatically by the internal processor. Settings are from 2 Hz up to 1280 Hz. Auto Bandwidth mode will set the bandwidth to 1/10 of the excitation frequency up to 1280 Hz.
Signal/Reference Measurements
The Signal and Excitation RMS values (10 mV resolution) are available as well as the Excitation Frequency (1 Hz resolution).
Built-In Test (BIT)/Diagnostic Capability
The board supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are stored in the BIT Dynamic Status and BIT Latched Status registers.
Power-On Self-Test (POST)/Power-on BIT (PBIT)/Start-up BIT (SBIT)
This board features a power-on self-test that will do an accuracy check of each channel and report the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Latched Status.
Continuous Background Built-In Test
All LVDT/RVDT measurement modules feature a background self-test capability or Continuous BIT (CBIT) (“D2”) test. The modules incorporate major diagnostics that ensure that the user is alerted to channel malfunction. This approach reduces bus traffic because the Status Registers need not be constantly polled. In addition to specialized design algorithms, the modules include many other useful applications features such signal voltage, reference voltage and frequency measurements, reference low/high (under-/over-voltage) fault detection, and signal low/high (under-/over-voltage) fault detection.
The CBIT test enables reporting of automatic background BIT (accuracy) testing. Seamlessly and transparently, each channel is in the “background” while operating normally to a default accuracy tolerance of 0.1% full-scale range. Any channel exceeding the tolerance is flagged in the BIT Status registers. The testing is totally transparent to the user, requires no external programming, and has no effect on the standard operation of the module. This test checks 72 unique positions for each channel sequentially and can take approximately 2 minutes to complete. Each position cycles through all 4 channels within 1.65 seconds. The user can verify that the background BIT testing is executing by writing a value other than 0x0055 to the Test CBIT Verify register and then reading the Test CBIT Verify register after 10ms. The value reported back will be 0x0055 while the background bit testing is active.
In addition to the above accuracy tests, Signal Fault Low Status, Reference Fault Low Status, Signal Fault High Status, Reference Fault High Status, and Delta Position are always being monitored.
Initiate Built-In Test
The LVDT/RVDT module support two off-line Initiated Built-in Test, User Initiated BIT (UBIT) (“D0”) and Initiated BIT (IBIT) (“D3”).
UBIT is used to check the channel functionality without the need for external sources. All channels use an internal source to simulate LVDT positions that the user can set and then to read the data from the interface. All channels acquire data from this internal source. External reference is not required.
IBIT test starts an initiated BIT test that utilizes an internal stimulus to generate and test the full-scale positional range to a default test accuracy of 0.1% full scale range. IBIT test cycle is completed within 30 seconds and the result can be read from the BIT status registers when IBIT bit changes from 1 to 0.
Note
UBIT and IBIT tests only check the accuracy of the LVDT/RVDT channels and are individual tests and will not operate concurrently. For example, if the UBIT mode is set, and the user would like to perform the IBIT test, the UBIT mode must be stopped (inactive) before the IBIT test will run. The same holds true when the IBIT test is active. For the UBIT test to be activated, the user must disable the IBIT test. The CBIT test, however, can be set and the board can still perform with either the UBIT or IBIT tests. The CBIT test will momentarily stop while either of these tests are active and will return when the tests have completed.
Note
the default error limit that the BIT tests check to is 0.1%. The user has the option to program their own limits, per channel, by writing to the BIT Error Limit registers. There is on BIT Error Limit register per channel and is expressed as an IEEE-754 floating point number.
LVDT/RVDT Threshold Programming
In addition to Built-in Tests, the LVDT/RVDT modules provide the ability to monitor Signal faults (under and over-voltage conditions), Reference faults (under and over-voltage conditions), and Open detects.
LVDT/RVDT FIFO Buffering
The LVDT/RVDT modules include LVDT/RVDT FIFO Buffering for greater control of the incoming signal (data) for analysis and display. When initialized and triggered, the LVDT/RVDT buffer will accept/store the data at the same rate specified in the FIFO Sample Rate register. Programmable buffer sample thresholds can be utilized for data flow control.
Status and Interrupts
The LVDT/RVDT Modules provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.
Module Common Registers
The LVDT/RVDT Modules include module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.
Engineering Scaling Conversions
The LVDT/RVDT Threshold and Measurement registers can be programmed to be utilized as Single Precision Floating Point Value (IEEE-754) values or as 32-bit integer values. There are separate floating-point scale and offset registers for position, velocity, 2-wire position “B-side”, and 2- wire velocity “B-side” for each channel.
It is very often necessary to convert LVDT reading into a more useful value such as inches, etc. For example, when measuring distance, it would be more beneficial to read the data as inches instead of percentage of full scale. When the Enable Floating Point Mode register is set to 1, the values entered for the Floating Point Scale register and Floating Point Offset register will be used to convert the data (i.e., LVDT Position and Velocity Data and FIFO Buffer Data registers) to the associated engineering unit as follows:
LVDT Data in Engineering Units (Floating Point) =
(LVDT Value (Volts/Current) * Floating Point Scale) + Floating Point Offset
LVDT Data in Engineering Units (Floating Point) =
(LVDT Value (Percentage of Full-Scale) * Floating Point Scale) + Floating Point Offset
The purpose for providing this feature is to offload the processing that is normally performed by the mission processor to convert the integer values to engineering unit values. When the Enable Floating Point Mode register is set to 1 (Floating Point Mode) the following registers are formatted as Single Precision Floating Point Value (IEEE-754):
- Position Data
- Velocity Data
- Measured Reference RMS Voltage
- Measured Signal RMS Voltage
- Measured Frequency
- FIFO Buffer Data
- Threshold Detect Level* (Signal Faults, Reference Faults)
- UBIT Test Position*
- Delta Position*
*When the Enable Floating Point Mode register is set to 1, it is important that these registers are updated with the Single Precision Floating Point (IEEE-754) representation of the value for proper operation of the channel. Conversely, when the Enable Floating Point Mode register is set to 0, these registers must be updated with the Integer 32-bit representation of the value.
Note
When changing the Enable Floating Point Mode from Integer Mode to Floating Point Mode or vice versa, the following step should be followed to avoid faults from falsely being generated because data registers (such as Thresholds) or internal registers may have the incorrect binary representation of the values:
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Set the Enable Floating Point Mode register to the desired mode (Integer = 0 or Floating Point = 1).
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Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete. Data registers will be converted to the units specified and can be read in that specified format.
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Initialize configuration and control registers with the values in the units specified (Integer or Floating Point).
The following registers are formatted as Single Precision Floating Point Value (IEEE-754) regardless of the value in the Enable Floating Point Mode register:
- Va, Vb, Va+Vb RMS Voltages
- Va, Vb Detect Values
- Open and Short Detect Thresholds
- BIT Error Limit
- Position and Velocity Floating Point Scales and Offsets
REGISTER DESCRIPTIONS
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.
LVDT/RVDT Measurement Registers
When the Enable Floating Point Mode is enabled, the register values are formatted as Single Precision Floating Point Value (IEEE-754) values. In addition, the Floating-Point Scale and register Floating Point Offset will be applied to convert the position value to engineering units.
Position Data
Function: The value represents the position as a percentage of full scale (FS) in each channel for 3-Wire or 4-Wire applications. In 2-wire mode, the value is the position of the signal on the “Va” input with respect to the reference. The value for the position of the signal on “Vb” input with respect to the reference is stored in the Position B_2W register.
Type: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: -100% to +100%
Integer Mode (Enable Floating Point Mode register = 0)
32-bit two's complement (Lower 8 bits fixed at “0”)
-Full Scale (0x8000 0000) to +Full Scale (0x7FFF FF00)
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings:
Integer Mode:
Data Format (2-Wire): The value is computed as Va / REF and represents a % of ± Full Scale (FS). This value is formatted as a two’s complement value. The maximum positive excursion is 0x7FFF FF00, 0 = 0x0000 0000, and the maximum negative excursion is 0x8000 0000.
Data Format (3-Wire/4-Wire): The value is computed as (Va-Vb) / (Va+Vb) and represents a % of ±FS. This value is formatted as a two’s complement value. The maximum positive excursion is 0x7FFF FF00, 0 = 0x0000 0000, and the maximum negative excursion is 0x8000 0000.
Position Data (Integer Mode)
| -100 | 50 | 25 | 12.5 | 6.25 | 3.125 | 1.5625 | 0.78125 | 0.390625 | 0.195313 | 0.097656 | 0.048828 | 0.024414 | 0.012207 | 0.006104 | 0.003052 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| D | D | D | D | D | D | D | D | D | D | D | D | D | D | D | D |
| 1.525879E-03 | 7.629395E-04 | 3.814697E-04 | 1.907349E-04 | 9.536743E-05 | 4.768372E-05 | 2.384186E-05 | 1.192093E-05 | 5.960464E-06 | 2.980232E-06 | 1.490116E-06 | 7.450581E-07 | 3.725290E-07 | 1.862645E-07 | 9.313226E-08 | 4.656613E-08 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| D | D | D | D | D | D | D | D | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Note
The per bit position values in the following table are approximate.
Floating Point Mode:
Read as Single Precision Floating Point Value (IEEE-754).
Velocity Data
Function: The value represents the constant velocity for each channel in for 3-Wire or 4-Wire. In 2-Wire mode, the value is the velocity of the “Va” input signal. The value for the velocity of the “Vb” input signal is stored in the Velocity B_2W register.
Type: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: +/-100.0% / sec
Integer Mode (Enable Floating Point Mode register = 0)
-32-bit two's complement
-Full Scale (0x8000 0000) to +Full Scale (0x7FFF FFFF)
Floating Point Mode (Enable Floating Point Mode register = 1)
-Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings:
Integer Mode:
Velocity registers of each channel are read as a two’s complement word when in “integer” mode, with 0x7FFF FFFF being maximum in positive velocity, and 0x8000 0000 being maximum negative velocity. Units are in decimal-percent/second
Va RMS
Function: The value represents the RMS value of the “Va” input.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0.0 to 30.0
Read/Write: R
Initialized Value: N/A
Operational Settings: N/A
Vb RMS
Function: The value represents the RMS value of the “Vb” input.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0.0 to 30.0
Read/Write: R
Initialized Value: N/A
Operational Settings: N/A
Position B_2W
Function: The value represents the position of the signal on the “Vb” input with respect to the reference when in 2-Wire mode only.
Type: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: -100% to +100%
Integer Mode (Enable Floating Point Mode register = 0)
32-bit two's complement (Lower 8 bits fixed at “0”)
-Full Scale (0x8000 0000) to +Full Scale (0x7FFF FF00)
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings:
Integer Mode:
The value is computed as Vb / REF and represents a % of ± Full Scale (FS). This value is formatted as a two’s complement value. The maximum positive excursion is 0x7FFF FF00, 0 = 0x0000 0000, and the maximum negative excursion is 0x8000 0000.
Position B_2W
| -100 | 50 | 25 | 12.5 | 6.25 | 3.125 | 1.5625 | 0.78125 | 0.390625 | 0.195313 | 0.097656 | 0.048828 | 0.024414 | 0.012207 | 0.006104 | 0.003052 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| D | D | D | D | D | D | D | D | D | D | D | D | D | D | D | D |
| 1.525879E-03 | 7.629395E-04 | 3.814697E-04 | 1.907349E-04 | 9.536743E-05 | 4.768372E-05 | 2.384186E-05 | 1.192093E-05 | 5.960464E-06 | 2.980232E-06 | 1.490116E-06 | 7.450581E-07 | 3.725290E-07 | 1.862645E-07 | 9.313226E-08 | 4.656613E-08 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| D | D | D | D | D | D | D | D | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Note
The per bit position values in the following table are approximate.
Floating Point Mode:
Read as Single Precision Floating Point Value (IEEE-754).
Velocity B_2W
Function: The value represents the velocity of the signal on the “Vb” input with respect to the reference when in 2-Wire mode only.
Type: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:
Integer Mode (Enable Floating Point Mode register = 0)
32-bit two's complement
-Full Scale (0x8000 0000) to +Full Scale (0x7FFF FFFF)
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings:
Integer Mode:
Velocity registers of each channel are read as a two’s complement word when in “integer” mode, with 0x7FFF FFFF being maximum in positive velocity, and 0x8000 0000 being maximum negative velocity. Units are in decimal-percent/second.
Floating Point Mode:
Read as Single Precision Floating Point Value (IEEE-754).
Measured Reference (RMS)
Function: Measures individual channel input reference voltage.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0-140
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings:
Integer Mode:
Read integer value and multiply value by LSB (10 mV) to compute the reference voltage.
Floating Point Mode:
Read as Single Precision Floating Point Value (IEEE-754).
Measured Frequency (Hz)
Function: Measures individual channel input reference frequency.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0-20 kHz
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 1 Hz.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: Each individual channel input reference frequency is measured, and the value is reported to a corresponding register.
Integer Mode:
The integer value represents the reference frequency in Hz.
Floating Point Mode:
Read as Single Precision Floating Point Value (IEEE-754).
Va Detect Value
Function: Reports a numeric value based on the connection status of the Va input from the LVDT/RVDT.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0 to 200,000
Read/Write: R
Initialized Value: N/A
Operational Settings: This register will display a value typically in the hundreds when the LVDT/RVDT is connected normally and is functional. If one of the inputs, Va(hi) or Vb(lo) is disconnected from the LVDT, this value will increase into the thousands. If the Va and Vb winding is shorted, the value will be close to “0”. This value is used in comparison with the Open and Short Detect threshold values to alert the user of a faulty connection.
Vb Detect Value
Function: Reports a numeric value based on the connection status of the Vb input from the LVDT/RVDT.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0 to 200,000
Read/Write: R
Initialized Value: N/A
Operational Settings: Refer to Va Detect Value register description.
3- or 4-Wire Specific Register
The following registers apply when the LVDT is configured for 3- or 4-Wire mode.
Measured Signal (RMS)
Function: The value represents the total sum RMS value of the “Va” and “Vb” signals added together regardless of phase.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0-60
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: Note: In 3- or 4-Wire mode, this should be a constant output corresponding to the LVDT/RVDT output windings. In 2-Wire mode, the value is not applicable since it includes both the “A” & “B” sides.
Integer Mode:
Read integer value and multiply value by LSB (10 mV) to compute the signal voltage.
Floating Point Mode:
Read as Single Precision Floating Point Value (IEEE-754).
Va+Vb RMS
Function: The value represents the total sum RMS value of the “Va” and “Vb” signals added together regardless of phase.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0.0 to 60.0
Read/Write: R
Initialized Value: N/A
Operational Settings: Applicable when in 3-Wire or 4-Wire Mode. In 3- or 4-Wire mode, this should be a constant output corresponding to the LVDT/RVDT output windings. In 2-Wire mode, the value is not applicable since it includes both the “A” & “B” sides.
LVDT/RVDT Control Registers
The LVDT/RVDT control registers provide the ability to specify the mode, LVDT/RVDT scaling and bandwidth. In addition, there are control registers that provide the ability to normalize the reference input voltage to the signal voltage, the ability to invert the Va, Vb, or excitation voltage, as well as the ability to specify the position measurement algorithm.
Mode Select
Function: Configures for 3-Wire/4-Wire or 2-Wire LVDT/RVDT signal format measurement.
Type: unsigned binary word (32-bit)
Data Range: See table.
Read/Write: R/W
Initialized Value: 0x0000 0001
Operational Settings: Set the Mode as specified in the table.
| Mode Select Value | Description |
|---|---|
| 1 | 3-Wire/4-Wire |
| 2 | 2-Wire |
Mode Select
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Mode | Mode |
LVDT/RVDT Scale
Function: This register will allow the user to scale the LVDT/RVDT output to represent full scale.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0xFFFF FFFF
Operational Settings: Used only for Integer mode. When set to 0xFFFF FFFF, it represents a scale of ‘1’. If the user wants to set the channel to represent +/- 100% with less than full excursion of the LVDT, this register needs to be adjusted.
TR Value (Transformation Ratio Value)
Function: This register will allow the user to normalize the Reference input to the Signal output (“A” side and “B” side). This is only applicable in 2-wire mode and should not be modified from the default value while in 3/4 wire mode.
Type: unsigned binary word (32-bit)
Read/Write: R/W
Initialized Value: 0xFFFFFFFF
Operational Settings:
Example: If the Reference voltage is 10V and the LVDT/RVDT outputs 10V at full excursion (full scale), then the ratio between the reference and the signal is 1:1 and this value would be at 0xFFFFFFFF. If, however, the LVDT/RVDT under test has a reference voltage of 6V applied and it produces a full-scale voltage of 4V, then the TR value should be set to 0xAAAAAAAA (4V / 6V). This will allow the module to normalize the output of the LVDT/RVDT to the reference so that the position will be reported correctly.
Bandwidth Select
Function: Sets the bandwidth control to use. Bandwidth settings can be set manually or automatically by the module’s internal processor.
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: R/W
Initialized Value: 0
Operational Settings: Set to Manual (0) to use the value in the Bandwidth register. Set to Automatic (1) to have the module automatically set the bandwidth will be set to 1/10 of the excitation frequency up to 1280 Hz. The Bandwidth register will contain the calculated bandwidth when in Bandwidth Select is set to automatic. The bandwidth setting will only update when there is a 12.5% change in frequency. For example, if the frequency is at 1Khz and the bandwidth is set to 100hz, a change in frequency less than 125Hz will result in no change to the bandwidth setting.
| Bandwidth Select Value | Description |
|---|---|
| 0 | Manual |
| 1 | Automatic |
Bandwidth Select
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D |
Bandwidth (Hz)
Function: Sets the bandwidth when the Bandwidth Select register is set for “Manual” or contains the bandwidth set by the module’s internal processor when the Bandwidth Select register is set for “Automatic”.
Type: unsigned binary word (32-bit)
Data Range: 2 to 1280 Hz
Read/Write: R/W
Initialized Value: 40 Hz
Operational Settings: When the Bandwidth Select register is set for “Manual” mode, the bandwidth is programmable, between 2 and 1280 Hz. The LSB is 1 Hz. The resolution is 2Hz. All values greater than 1280 will be processed as 1280Hz. All values less than 2 will be processed as 2 Hz.
Note
The bandwidth should not be set to more than ¼ of the reference frequency. A higher BW setting will result in a quicker response to a change in position but will be at the expense of greater noise in the reading. A lower BW value will result in a much quieter reading but will take longer to settle.
When the Bandwidth Select register is set for “Automatic” mode, the bandwidth will be internally calculated and written to this register. The bandwidth value will be set to 1/10 the carrier frequency with a minimum BW of 2 Hz, and a maximum BW of 1280 Hz. The change will occur only when a frequency change of 12.5% or greater is detected as illustrated in the table.
Example: Bandwidth Select = Automatic
| Reference Frequency | Bandwidth Value | Description |
|---|---|---|
| Current Reference frequency at 400 Hz | Bandwidth sets to 40Hz | a 12.5% change would be 50 Hz |
| Reference Frequency changes to 12Khz | Bandwidth sets to 1200Hz | 3000% change from 400Hz |
| Reference Frequency changes to 13Khz | Bandwidth sets to 1200Hz | 8.333% change from 12Khz (not enough to trigger a change) |
| Reference Frequency changes to 14Khz | Bandwidth sets to 1280Hz | 16.666% change from 12Khz |
Delta Position
Function: Sets the value of position change that is required to alert the user that a change has occurred.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0x002D E00D to 0x4000 0000 (Integer mode) or 0.14% to 50% (Floating Point Mode)
Read/Write: R/W
Initialized Value: 0
Operational Settings: Set the minimum differential position to trigger a position change alert.
Integer Mode:
Set the Delta Position based on the bit weighs shown in the table.
Delta Position (Integer Mode)
| -100 | 50 | 25 | 12.5 | 6.25 | 3.125 | 1.5625 | 0.78125 | 0.390625 | 0.195313 | 0.097656 | 0.048828 | 0.024414 | 0.012207 | 0.006104 | 0.003052 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| D | D | D | D | D | D | D | D | D | D | D | D | D | D | D | D |
| 1.525879E-03 | 7.629395E-04 | 3.814697E-04 | 1.907349E-04 | 9.536743E-05 | 4.768372E-05 | 2.384186E-05 | 1.192093E-05 | 5.960464E-06 | 2.980232E-06 | 1.490116E-06 | 7.450581E-07 | 3.725290E-07 | 1.862645E-07 | 9.313226E-08 | 4.656613E-08 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| D | D | D | D | D | D | D | D | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Note
The per bit position values in the following table are approximate.
Floating Point Mode:
Set as Single Precision Floating Point Value (IEEE-754).
Initiate Delta Position
Function: Initiates the monitored for position change alert.
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: W
Initialized Value: 0
Operational Settings: Used in conjunction with the Delta Position register. Writing a “1” to the Initiate Delta Position register will capture the current position and use this value to detect a change of +/- the value written in the Delta Position register. If the position exceeds this limit, the corresponding bit in the Delta Position Status registers (Dynamic and Latched) will be set.
Note
Since the dynamic registers in general give you the current state of the channel, the bit will be set and then cleared within 4.096 µs and might not be observed in the dynamic register. The bit in the Delta Position Latched Status register, however, will remain set until cleared.
Initiate Delta Position
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D |
Track/Hold
Function: Latches channels.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R/W
Initialized Value: 0
Operational Settings: Setting the bit for the associated channel to a “1” will latch the data for the corresponding channel. Internally, the channel will continue to track the input, but the data in the Position Data register for the corresponding channel will be latched at the LVDT/RVDT position when the latch was initiated. Once the Position Data register is read, the hardware will disengage the latch for that channel and will continue to update the current LVDT/RVDT position. It will automatically clear the bit associated with the channel. Once set, you can always return to updating the position by clearing the corresponding channel bit.
Note
This feature can be used to acquire a snapshot of all channels simultaneously.
Track/Hold
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Inverse Signal Control
Function: Enables the inversion of the phase of the Va, Vb and Reference signals. Also enables the changing of the algorithm used for position measurement.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 - 0x0000 000F
Read/Write: R/W
Initialized Value: 0
Operational Settings: The feature provides the ability to invert the phase of the Va, Vb and Reference signals and change the algorithm used for position measurements.
| Bit | Description |
|---|---|
| D3 | 0: Uses (Va - Vb) / (Va Vb) algorithm; 1: Uses (**Vb - Va**) / (Va Vb) |
| D2 | 0: Non-Inverted; 1: Inverts Reference |
| D1 | 0: Non-Inverted; 1: Inverts Vb |
| D0 | 0: Non-Inverted; 1: Inverts Va |
Inverse Signal Control
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D | D | D | D |
Threshold Programming Registers
The Signal Fault Low Threshold, Signal Fault High Threshold, Reference Fault Low Threshold, Reference Fault High Threshold, Open Detect Threshold and Short Detect Threshold registers set the threshold limits to the Signal Fault Low Status, Signal Fault High Status, Reference Fault Low Status, Reference Fault High Status, Open Detect Status, and Short Detect Status registers respectively.
Reference Fault Low Threshold
Function: Sets the “under-voltage” threshold at which a fault will be reported in the Reference Fault Low Status register.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0-135 Vrms
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 1820 decimal (18.2V)
Operational Settings: The reference fault detection circuitry will report a fault in the Reference Fault Low Status register when the measured reference signal is below the value set in Reference Fault Low Threshold register.
Reference Fault High Threshold
Function: Sets the “over-voltage” threshold at which a fault will be reported in the Reference Fault High Status register.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0-135 Vrms
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 2800 decimal (28.00V)
Operational Settings: The reference fault detection circuitry will report a fault in the Reference Fault High Status register when the measured reference signal is above the value set in Reference Fault High Threshold register.
Open Detect Threshold
Function: Sets the threshold at which “open” signal will be reported in the Open Detect Status register.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0.0 - 100,000.0
Read/Write: R/W
Initialized Value: 10,000.0
Operational Settings: This register value is used as a comparison for the Va Detect Value and Vb Detect Value register values. Since LVDT/RVDTs vary, this value will need to be “tuned” and will be described in the Va Detect Value and Vb Detect Value registers section. Note, setting this register to 100,000 will disable this feature.
Short Detect Threshold
Function: Sets the threshold at which a “shorted” signal will be reported in the Short Detect Status register.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: 0.0 - 100,000.0
Read/Write: R/W
Initialized Value: 0.0
Operational Settings: This register value is used as a comparison for the Va Detect Value and Vb Detect Value register values. Since LVDT/RVDTs vary, this value will need to be “tuned” and will be described in the Va Detect Value and Vb Detect Value registers section.
Note
Setting this register to 0.0 will disable this feature.
3-Wire/4-Wire Signal Fault Register
The following registers apply when the LVDT is configured for 3-Wire or 4-Wire mode.
Signal Fault Low Threshold
Function: Sets the “under-voltage” threshold at which a fault will be reported in the Signal Fault Low Status register.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0 - 30Vrms (LD1-LD4), 0 - 95Vrms (LD5)
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: LD1 - LD4 modules (826 decimal) (8.26V), LD5 module (6300 decimal) (63.00V)
Operational Settings: The signal fault detection circuitry will report a fault in the Signal Fault Low Status register when the measured signal is below the value set in Signal Fault Low Threshold register.
Signal Fault High Threshold
Function: Sets the “over-voltage” threshold at which a fault will be reported in the Signal Fault High Status register.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0 - 30Vrms (LD1-LD4), 0 - 9Vrms (LD5)
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: LD1 - LD4 modules (1685 decimal) (16.85V), LD5 module (9500 decimal) (95.00V)
Operational Settings: The signal fault detection circuitry will report a fault in the Signal Fault High Status register when the measured signal is above the value set in Signal Fault High Threshold register.
2-Wire Signal Fault Register
The following registers apply when the LVDT is configured for 2-Wire mode (Contact factory for availability).
Va Fault High Threshold
Function: Sets the “over-voltage” threshold at which a fault will be reported in the Va Fault High Status register.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0 - 30Vrms (LD1-LD4), 0 - 95Vrms (LD5)
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: LD1 - LD4 modules (1685 decimal) (16.85V), LD5 module (11700 decimal) (117.00V)
Operational Settings: The signal fault detection circuitry will report a fault in the Signal Fault Low Status register when the measured signal is below the value set in Signal Fault High Threshold register.
Vb Fault High Threshold
Function: Sets the “over-voltage” threshold at which a fault will be reported in the Vb Fault High Status register.
Type: unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: 0 - 30Vrms (LD1-LD4), 0 - 9Vrms (LD5)
Integer Mode (Enable Floating Point Mode register = 0)
LSB = 10 mV rms.
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: LD1 - LD4 modules (1685 decimal) (16.85V), LD5 module (11700 decimal) (117.00V)
Operational Settings: The signal fault detection circuitry will report a fault in the Signal Fault High Status register when the measured signal is above the value set in Signal Fault High Threshold register.
LVDT/RVDT Test Registers
Three different tests, one on-line (CBIT) and two off-line (UBIT, IBIT), can be selected. External reference voltage is not required for any of these tests.
Test Enabled
Function: Set bit in this register to enable associated Built-In Self-Test IBIT, CBIT and UBIT.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 to 0x000D
Read/Write: R/W
Initialized Value: 0x4 (CBIT Test Enabled)
Operational Settings: BIT tests include an on-line (CBIT) test and two off-line (UBIT, IBIT) tests. Failures in the BIT tests are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects a failure. UBIT and IBIT will not operate concurrently. When UBIT is enabled, the IBIT should not be enabled, and vice versa. CBIT can be set with either UBIT or IBIT enabled. Note: IBIT, when enabled, will run until the test completes (within 5 seconds).
Test Enabled
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | IBIT Test D | CBITTest 1 | 0 | UBIT Test D |
Test CBIT Verify
Function: Allows user to verify if the CBIT test is running.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: User can write any value to this register. If CBIT test is running, after a minimum of 10ms the value read back will be 0x0000 0055, otherwise the value read back will be the value written.
UBIT Test Position
Function: Specifies position to be applied by LVDT/RVDT UBIT test.
Type: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range: -100% to +100%
Integer Mode (Enable Floating Point Mode register = 0)
32-bit two's complement
-Full Scale (0x8000 0000) to +Full Scale (0x7FFF FFFF)
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: 0x1555 5555 (16.66%)
Operational Settings:
Integer Mode:
Set the UBIT Test Position based on the bit weighs shown in the table.
UBIT Test Position (Integer Mode)
| -100 | 50 | 25 | 12.5 | 6.25 | 3.125 | 1.5625 | 0.78125 | 0.390625 | 0.195313 | 0.097656 | 0.048828 | 0.024414 | 0.012207 | 0.006104 | 0.003052 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| D | D | D | D | D | D | D | D | D | D | D | D | D | D | D | D |
| 1.525879E-03 | 7.629395E-04 | 3.814697E-04 | 1.907349E-04 | 9.536743E-05 | 4.768372E-05 | 2.384186E-05 | 1.192093E-05 | 5.960464E-06 | 2.980232E-06 | 1.490116E-06 | 7.450581E-07 | 3.725290E-07 | 1.862645E-07 | 9.313226E-08 | 4.656613E-08 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| D | D | D | D | D | D | D | D | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Note
The per bit position values in the following table are approximate.
Floating Point Mode:
Set as Single Precision Floating Point Value (IEEE-754).
BIT Error Limit
Function: Allows the user to set the error limit for the CBIT, UBIT and IBIT tests.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Positive value - setting this value to zero will most likely result in a BIT Status failure.
Read/Write: R/W
Initialized Value: 0.1
Operational Settings: The default error limit that the BIT tests check to is 0.1. In some systems the noise characteristics may result in larger errors than the default error limit. Setting BIT Error Limit registers with a value that better suited for these systems may help lower the possibility of reporting “false-positives” for the channel in the BIT Status registers during BIT testing.
FIFO Registers
The FIFO registers are configurable for each channel.
FIFO Buffer Data
Function: Available data in the FIFO buffer can be retrieved, one word at a time (32-bits).
Type:
Position and Velocity: signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Timestamp: unsigned binary word (32-bit)
Data Range: Varies based on Data type. Reading Position & Velocity can be either integer or float format. Time stamp will always be in integer format.
Integer Mode (Enable Floating Point Mode register = 0)
32-bit two's complement
-Full Scale (0x8000 0000) to +Full Scale (0x7FFF FFFF)
Floating Point Mode (Enable Floating Point Mode register = 1)
Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: 0
Operational Settings: Data for the Position & Velocity will be stored in either the integer format or IEEE floating point standard based on the state of the Enable Floating Point Mode register.
FIFO Word Count
Function: This is a counter that reports the number of 32-bit words currently in the FIFO Buffer Data register.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R
Initialized Value: 0
Operational Settings: Each time the module writes to the FIFO, the word count will be incremented by 1. Any read operations made from the FIFO Buffer Data memory address, its corresponding Words in FIFO counter will be decremented by one. The maximum number of words that can be stored in the FIFO is 4,194,304 (4 Meg) (0x0040 0000).
FIFO Thresholds
The FIFO Almost Empty Threshold, FIFO Low Watermark Threshold, FIFO High Watermark Threshold, FIFO Almost Full Threshold and FIFO Buffer Size registers set the threshold limits that are used to set the bits in the FIFO Status registers.
Note
It is important that the almost empty threshold/low watermark threshold be set less than the almost full threshold/high watermark threshold, respectively, for valid operation.
FIFO Almost Empty
Function: The FIFO Almost Empty threshold level is used as a comparison value to determine when to set the “almost empty” bit in the FIFO Status register.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R/W
Initialized Value: 0x0000 0032
Operational Settings: When the number of words in the FIFO Word Count register is less than or equal to the value stored in this register, the “almost empty” bit (D1) of the FIFO Status register will be set. When the number of words in FIFO Word Count is greater than the value stored in this register, the “almost empty” bit (D1) of the FIFO Status register will be reset.
FIFO Low Watermark
Function: The FIFO Low Watermark threshold level is used as a comparison value to determine when to set the “low watermark” bit in the FIFO Status register.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R/W
Initialized Value: 0x0000 0064
Operational Settings: When the number of words in FIFO Word Count register is less than or equal to the value stored in this register, the “low watermark” bit (D2) of the FIFO Status register will be set. When the number of words in FIFO Word Count is greater than the value stored in this register, the “low watermark” bit (D2) of the FIFO Status register will be reset.
FIFO High Watermark
Function: The FIFO High Watermark threshold level is used as a comparison value to determine when to set the “high watermark” bit in the FIFO Status register.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R/W
Initialized Value: 0x003F 0000
Operational Settings: When the number of words in FIFO Word Count register is greater than or equal than the value stored in this register, the “high watermark” bit (D3) of the FIFO Status register will be set. When the number of words in FIFO Word Count is less than the value stored in the register, the “high watermark” bit (D3) of the FIFO Status register will be reset.
FIFO Almost Full
Function: The FIFO Almost Full threshold level is used as a comparison value to determine when to set the “almost full” bit in the FIFO Status register.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R/W
Initialized Value: 0x003F FF00
Operational Settings: When the number of words in the FIFO Word Count register is greater than or equal to the value stored in this register, the “almost full” bit (D4) of the FIFO Status register will be set. When the number of words in FIFO Word Count is less than the value stored in this register, the “almost full” bit (D4) of the FIFO Status register will be reset.
FIFO Buffer Size
Function: The FIFO Buffer Size sets the number of samples to be taken and placed into the FIFO when a trigger occurs.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0040 0000
Read/Write: R/W
Initialized Value: 0x0000 2000
Operational Settings: When the number of samples set in this register are sent to the FIFO, the “sample done” bit (D6) in the FIFO Status register is set. If another trigger is sent the “sample done” bit is cleared and set again once all data has been transferred. The largest number of samples that may be collected is 4,194,304 (0x0040 0000). If the buffer size is greater than the number of words available in the FIFO, only the number of words that are available will be stored and the remaining words lost.
FIFO Buffer Control
Function: The FIFO Buffer Control register defines the type of data that is stored in the FIFO Buffer Data register for each channel.
Type: unsigned binary word (32-bit)
Data Range: See table
Read/Write: R/W
Initialized Value: 0
Operational Settings: The following data types are available:
FIFO Buffer Control Description
| Bit | Description |
|---|---|
| D31-D6 | Reserved - Set to 0. |
| D5 | Store Velocity “B” Data (contact factory) |
| D4 | Store Position “B” Data (contact factory) |
| D3 | Reserved - Set to 0. |
| D2 | Store Timestamp. An integer counter that counts from 0 to 4,194,304 and wraps around when it overflows |
| D1 | Store Velocity Data |
| D0 | Store Position Data |
Note
Each data format (D0-D5) requires one word of storage from the FIFO buffer. For example: If D0, D1 and D2 are set (0x07) and the FIFO Buffer Size register is set to 1, a FIFO write will only put the Position data to the FIFO memory.
If the FIFO Buffer Size is set to 10, it will store 4 Position values, 3 Velocity values & 3 timestamp values. Data will be stored in the order of Position, Velocity then timestamp. Since the maximum physical size of FIFO is 4,194,304 for each channel, the value in the FIFO Buffer Size register could cause an overflow to the FIFO Word Count register. When an overflow occurs, any data not placed in the FIFO will be lost.
FIFO Sample Rate
Function: The FIFO Sample Rate register sets the sampling rate for FIFO data collection for each channel.
Type: unsigned binary word (32-bit)
Data Range: 1 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 1
Operational Settings: Sample rate is based on the product of 4.096 µsec x the integer set in the register. For example: if the rate is set to 2, the FIFO buffer sample rate will be, 4.096 µsec x 2 = 8.192 µsec
FIFO Sample Delay
Function: The FIFO Sample Delay register sets the number of delay samples before the actual FIFO data collection begins.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: The data collected during the delay period will be discarded.
Note
If timestamp is included as part of the FIFO data, it will begin as soon as the trigger is initiated. For example, if the FIFO Buffer Size register is set to 10, FIFO Sample Delay is set to 7, FIFO Sample Rate is at 1, and the Position is also selected to be stored, the data written into the FIFO would be
,8, ,9, ,10, ,11, ,12.
FIFO Clear
Function: The FIFO Clear register clears FIFO data and sets the FIFO Word Count register to zero.
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: W
Initialized Value: N/A
Operational Settings: Write a ‘1’ to this register to reset the FIFO Word Count register to zero and clear the FIFO of any data in the buffer. After writing a ‘1’ to the FIFO Clear register, the FIFO Buffer will only stay empty if all data has been sent (DONE bit set in the FIFO Status register). If data is still in the process of being written to the FIFO, any current data will be cleared, but the FIFO will continue to fill with new data until the number of samples sent equals the number of samples that was set in the FIFO Buffer Size register.
Clear FIFO
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D |
FIFO Trigger Control
Function: Sets the FIFO Buffer Triggering options. FIFO can be started/triggered by different sources.
Type: unsigned binary word (32-bit)
Data Range: See tables
Read/Write: R/W
Initialized Value: 2 (Software Trigger, Trigger Disabled)
Operational Settings: To Enable triggering, set D5 to 1. When set up for software triggering, write a 1 to the FIFO Software Trigger register to start the transfer of data to the FIFO. If in external mode and Positive slope is set (D4 = 0), a rising edge of the external trigger input will start the transfer of data to the FIFO. If in external mode and Negative slope is selected (D4 = 1), a falling edge of the external trigger input will start the transfer of data to the FIFO.
Note
Disabling the trigger while data is being transferred, does NOT stop the data from being written to the FIFO.
FIFO Trigger Control Description
| Bit | Description |
|---|---|
| D31-D7 | Reserved - Set to 0. |
| D6 | Enable Trigger Always (contact factory) |
| D5 | Trigger Enable |
| D4 | Trigger Slope (0 = Positive, 1 = Negative) |
| D3-D2 | Reserved - Set to 0. |
| D1-D0 | 0:0 - External Trigger 0:1 - N/A 1:0 - Software Trigger 1:1 - N/A |
FIFO Trigger Control
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D | D | D | D | D | D | D | D |
FIFO Software Trigger
Function: Software trigger is used to kick start the FIFO buffer and the collection of data.
Type: unsigned binary word (32-bit)
Data Range: 0 or 1
Read/Write: W
Initialized Value: 0 (Not Triggered)
Operational Settings: To use this operation, the FIFO Trigger Control register must be set up as software trigger (D1 = 1) and Trigger Enable is enabled (D5 = 1). Write a 1 to this register to trigger FIFO collection for all channels. This register will automatically be cleared.
FIFO Software Trigger
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D |
Engineering Scaling Conversion Registers
The LVDT/RVDT Module Threshold and Measurement registers can be programmed to be utilized as IEEE-754 single-precision floating-point values or as 32-bit integer values.
Enable Floating Point Mode
Function: Sets all channels for floating point mode or integer mode.
Type: unsigned binary word (32-bit)
Data Range: 0 or 1
Read/Write: R/W
Initialized Value: 0 (Integer mode)
Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode.
Enable Floating Point Mode
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D |
Floating Point Offset
Function: Sets the floating-point offset to add to data. There are separate floating-point offset registers for Position, Velocity, 2-wire Position “B”, and 2-wire Velocity “B” for each channel.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: N/A*
Read/Write: R/W
Initialized Value: 0.0
Operational Settings: Writing a value to one of these registers will add to the Position, Velocity, 2-wire Position “B”, or 2-wire Velocity “B” value based on which register is chosen (when floating-point mode is enabled). For example, if the position is currently at 10.000%, the position floating-point offset register is at 0.000, and floating-point mode is enabled, writing a 2.00 to the position floating-point offset register will result in the position reading 12.000%. If the value written is -1.7, then the position will be at 8.300%.
*Data Range is any acceptable 32-bit IEEE-754 value. Usage is application dependent - see examples within this document.
Floating Point Scale
Function: Sets the floating-point scale to modify the data. The data is multiplied by the floating-point scale divided by 100. There are separate floating-point scale registers for position, velocity, 2-wire position b, and 2-wire velocity b for each channel.
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: N/A*
Read/Write: R/W
Initialized Value: 100
Operational Settings: Writing a value to one of these registers will multiply the position, velocity, 2-wire position b, or 2-wire velocity b value by the register value divided by 100 based on which register is chosen (when floating-point mode is enabled). For example, if the position is currently at 10.000%, the position floating-point scale register is at 100.000, and floating-point mode is enabled, writing a 50.00 to the position floating-point scale register will result in the position reading 5.000%.
*Data Range is any acceptable 32-bit IEEE-754 value. Usage is application dependent - see examples within this document.
Floating Point State
Function: Indicates the state of the mode selected (Integer or Floating Point).
Type: unsigned binary word (32-bit)
Data Range: 0 to 1
Read/Write: R
Initialized Value: 0
Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).
Floating Point State
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D |
Module Common Registers
Refer to “Module Common Registers Module Manual” for the register descriptions.
Status and Interrupt Registers
The LVDT/RVDT Modules provide status registers for BIT, Signal Fault Low, Signal Fault High, Reference Fault Low, Reference Fault High, Delta Position, FIFO, Open Detect, and Short Detect.
Channel Status Enable
Function: Determines whether to update the Latched and Real-Time status states for the channels. The default is channel status enable off (no failure).
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 - 0x0000 000F
Read/Write: R/W
Initialized Value: 0x0000 0000
Operational Settings: When the bit corresponding to a given channel in the Channel Status Enable register is enabled (1), it will allow the statuses for that channel to be updated. When the bit corresponding to a given channel is disabled (0), the statuses for that channel will be masked and reported as “0” or “no failure”.
Channel Status Enable
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
BIT Status
There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
BIT Status
| BIT Dynamic Status | |||||||||||||||
| BIT Latched Status | |||||||||||||||
| BIT Interrupt Enable | |||||||||||||||
| BIT Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Sets the corresponding bit associated with the channel’s BIT error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
3-Wire/4-Wire Fault Status
The following registers apply when the LVDT is configured for 3-Wire or 4-Wire mode.
Signal Fault Low Status
There are four registers associated with the Signal Fault Low Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Signal Fault Low Status
| Signal Fault Low Dynamic Status | |||||||||||||||
| Signal Fault Low Latched Status | |||||||||||||||
| Signal Fault Low Interrupt Enable | |||||||||||||||
| Signal Fault Low Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Sets the corresponding bit associated with the channel’s Signal Fault Low error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Signal Fault High Status
There are four registers associated with the Signal Fault High Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Signal Fault High Status
| Signal Fault High Dynamic Status | |||||||||||||||
| Signal Fault High Latched Status | |||||||||||||||
| Signal Fault High Interrupt Enable | |||||||||||||||
| Signal Fault High Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Sets the corresponding bit associated with the channel’s Signal Fault High error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
2-Wire Fault Status
The following registers apply when the LVDT is configured for 2-Wire mode. Contact factory for availability.
Va Fault High Status
There are four registers associated with the Va Fault High Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Va Fault High Status
| Va Fault High Dynamic Status | |||||||||||||||
| Va Fault High Latched Status | |||||||||||||||
| Va Fault High Interrupt Enable | |||||||||||||||
| Va Fault High Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Sets the corresponding bit associated with the channel’s Va Fault High error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Vb Fault High Status
There are four registers associated with the Vb Fault High Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Vb Fault High Status
| Vb Fault High Dynamic Status | |||||||||||||||
| Vb Fault High Latched Status | |||||||||||||||
| Vb Fault High Interrupt Enable | |||||||||||||||
| Vb Fault High Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Sets the corresponding bit associated with the channel’s Vb Fault High error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Reference Fault Low Status
There are four registers associated with the Reference Fault Low Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Reference Fault Low Status
| Reference Fault Low Dynamic Status | |||||||||||||||
| Reference Fault Low Latched Status | |||||||||||||||
| Reference Fault Low Interrupt Enable | |||||||||||||||
| Reference Fault Low Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Sets the corresponding bit associated with the channel’s Reference Fault Low error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Reference Fault High Status
There are four registers associated with the Reference Fault High Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Reference Fault High Status
| Reference Fault High Dynamic Status | |||||||||||||||
| Reference Fault High Latched Status | |||||||||||||||
| Reference Fault High Interrupt Enable | |||||||||||||||
| Reference Fault High Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Sets the corresponding bit associated with the channel’s Reference Fault High error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Delta Position Status
There are four registers associated with the Delta Position Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Delta Position Status
| Delta Position Dynamic Status | |||||||||||||||
| Delta Position Latched Status | |||||||||||||||
| Delta Position Interrupt Enable | |||||||||||||||
| Delta Position Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Sets the corresponding bit associated with the channel’s Delta Position change.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
FIFO Status
There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0-D6 is used to show the different conditions of the buffer.
| Bits | Description | Configurable? |
|---|---|---|
| D0 | Empty; 1 when FIFO Count = 0 | No |
| D1 | Almost Empty; 1 when FIFO Count ⇐ “FIFO Almost Empty” register | Yes |
| D2 | Low Watermark; 1 when FIFO Count ⇐ “FIFO Low Watermark” register | Yes |
| D3 | High Watermark; 1 when FIFO Count >= “FIFO High Watermark” register | Yes |
| D4 | Almost Full; 1 when FIFO Count >= “FIFO Almost Full” register | Yes |
| D5 | Full; 1 when FIFO Count = 4 Meg (0x0040 0000) | No |
| D6 | Sample Done; 1 when all data has been sent to the FIFO | No |
FIFO Status
| FIFO Dynamic Status | |||||||||||||||
| FIFO Latched Status | |||||||||||||||
| FIFO Interrupt Enable | |||||||||||||||
| FIFO Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D | D | D | D | D | D | D |
Function: Sets the corresponding bit associated with the FIFO status type; there are separate registers for each channel.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0x0000 007F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Notes:
-
Shown below is an example of interrupts generated for the High Watermark. As shown, the interrupt is generated as the FIFO count crosses the High Watermark. The interrupt will not be generated a second time until the count goes below the watermark and then above it again.
-
The FIFO Latched Status register must be cleared for a 2 interrupt to occur.
Open Detect Status
There are four registers associated with the Open Detect Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Open Detect Status
| Open Detect Status Dynamic Status | |||||||||||||||
| Open Detect Status Latched Status | |||||||||||||||
| Open Detect Status Interrupt Enable | |||||||||||||||
| Open Detect Status Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Sets the corresponding bit associated with the channel’s Open Detect error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Short Detect Status
There are four registers associated with the Short Detect Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Short Detect Status
| Short Detect Status Dynamic Status | |||||||||||||||
| Short Detect Status Latched Status | |||||||||||||||
| Short Detect Status Interrupt Enable | |||||||||||||||
| Short Detect Status Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Sets the corresponding bit associated with the channel’s Short Detect error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value: 0
Summary Status
There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Summary Status
| Summary Status Dynamic Status | |||||||||||||||
| Summary Status Latched Status | |||||||||||||||
| Summary Status Interrupt Enable | |||||||||||||||
| Summary Status Set Edge/Level Interrupt | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch.4 | Ch.3 | Ch.2 | Ch1 |
Function: Indicates a summary of all failures per channel (BIT, Signal Fault Low, Signal Fault High, Reference Fault Low, Reference Fault High, Open Detect and Short Detect).
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 000F
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value: 0
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
Interrupt Vector Function: Set an identifier for the interrupt. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R/W Initialized Value: 0 Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering Function: Sets where to direct the interrupt. Type: unsigned binary word (32-bit) Data Range: See table Read/Write: R/W Initialized Value: 0 Operational Settings: When an interrupt occurs, the interrupt is sent as specified: Link to original
Direct Interrupt to VME 1 Direct Interrupt to ARM Processor (via SerDes) +
(Custom App on ARM or NAI Ethernet Listener App)2 Direct Interrupt to PCIe Bus 5 Direct Interrupt to cPCI Bus 6
FUNCTION REGISTER MAP
Key:
Bold Italic = Configuration/Control
Bold Underline = Measurement/Status
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a ‘1’ to a bit set to ‘1’ will set the bit to ‘0’).
**Data is available in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode.
~ Data is always in Floating Point.
LVDT/RVDT Measurement Registers
| 0x1000 | Position Data Ch 1** | R |
|---|---|---|
| 0x1050 | Position Data Ch 2** | R |
| 0x10A0 | Position Data Ch 3** | R |
| 0x10F0 | Position Data Ch 4** | R |
| 0x1004 | Velocity Ch 1** | R |
|---|---|---|
| 0x1054 | Velocity Ch 2** | R |
| 0x10A4 | Velocity Ch 3** | R |
| 0x10F4 | Velocity Ch 4** | R |
| 0x1150 | Position B 2W Ch 1** | R |
|---|---|---|
| 0x1154 | Position B 2W Ch 2** | R |
| 0x1158 | Position B 2W Ch 3** | R |
| 0x115C | Position B 2W Ch 4** | R |
| 0x1008 | Velocity B 2W Ch 1** | R |
|---|---|---|
| 0x1058 | Velocity B 2W Ch 2** | R |
| 0x10A8 | Velocity B 2W Ch 3** | R |
| 0x10F8 | Velocity B 2W Ch 4** | R |
| 0x1040 | Va RMS Ch 1~ | R |
|---|---|---|
| 0x1090 | Va RMS Ch 2~ | R |
| 0x10E0 | Va RMS Ch 3~ | R |
| 0x1130 | Va RMS Ch 4~ | R |
| 0x1044 | Vb RMS Ch 1~ | R |
|---|---|---|
| 0x1094 | Vb RMS Ch 2~ | R |
| 0x10E4 | Vb RMS Ch 3~ | R |
| 0x1134 | Vb RMS Ch 4~ | R |
| 0x1048 | Va + Vb Ch 1~ | R |
|---|---|---|
| 0x1098 | Va + Vb Ch 2~ | R |
| 0x10E8 | Va + Vb Ch 3~ | R |
| 0x1138 | Va + Vb Ch 4~ | R |
| 0x1024 | Measured Reference (RMS) Ch 1** | R |
|---|---|---|
| 0x1074 | Measured Reference (RMS) Ch 2** | R |
| 0x10C4 | Measured Reference (RMS) Ch 3** | R |
| 0x1114 | Measured Reference (RMS) Ch 4** | R |
| 0x1028 | Measured Signal (RMS) Ch 1** | R |
|---|---|---|
| 0x1078 | Measured Signal (RMS) Ch 2** | R |
| 0x10C8 | Measured Signal (RMS) Ch 3** | R |
| 0x1118 | Measured Signal (RMS) Ch 4** | R |
| 0x102C | Measured Frequency (Hz) Ch 1** | R |
|---|---|---|
| 0x107C | Measured Frequency (Hz) Ch 2** | R |
| 0x10CC | Measured Frequency (Hz) Ch 3** | R |
| 0x111C | Measured Frequency (Hz) Ch 4** | R |
| 0x11A0 | Va Detect Value Ch 1~ | R |
|---|---|---|
| 0x11A8 | Va Detect Value Ch 2~ | R |
| 0x11B0 | Va Detect Value Ch 3~ | R |
| 0x11B8 | Va Detect Value Ch 4~ | R |
| 0x11A4 | Vb Detect Value Ch 1~ | R |
|---|---|---|
| 0x11AC | Vb Detect Value Ch 2~ | R |
| 0x11B4 | Vb Detect Value Ch 3~ | R |
| 0x11BC | Vb Detect Value Ch 4~ | R |
LVDT/RVDT Control Registers
| 0x1038 | Mode Select Ch 1 | R/W |
|---|---|---|
| 0x1088 | Mode Select Ch 2 | R/W |
| 0x10D8 | Mode Select Ch 3 | R/W |
| 0x1128 | Mode Select Ch 4 | R/W |
| 0x103C | LVDT/RVDT Scale Ch 1 | R/W |
|---|---|---|
| 0x108C | LVDT/RVDT Scale Ch 2 | R/W |
| 0x10DC | LVDT/RVDT Scale Ch 3 | R/W |
| 0x112C | LVDT/RVDT Scale Ch 4 | R/W |
| 0x1350 | TR Value Ch 1A (integer only) | R/W |
|---|---|---|
| 0x1354 | TR Value Ch 2A (integer only) | R/W |
| 0x1358 | TR Value Ch 3A (integer only) | R/W |
| 0x135C | TR Value Ch 4A (integer only) | R/W |
| 0x1360 | N/A | R/W |
|---|---|---|
| 0x1364 | N/A | R/W |
| 0x1368 | N/A | R/W |
| 0x136C | N/A | R/W |
| 0x1010 | Bandwidth Selection Ch 1 | R/W |
|---|---|---|
| 0x1060 | Bandwidth Selection Ch 2 | R/W |
| 0x10B0 | Bandwidth Selection Ch 3 | R/W |
| 0x1100 | Bandwidth Selection Ch 4 | R/W |
| 0x100C | Bandwidth (Hz) Ch 1 | R/W |
|---|---|---|
| 0x105C | Bandwidth (Hz) Ch 2 | R/W |
| 0x10AC | Bandwidth (Hz) Ch 3 | R/W |
| 0x10FC | Bandwidth (Hz) Ch 4 | R/W |
| 0x1018 | Delta Position Ch 1** | R/W |
|---|---|---|
| 0x1068 | Delta Position Ch 2** | R/W |
| 0x10B8 | Delta Position Ch 3** | R/W |
| 0x1108 | Delta Position Ch 4** | R/W |
| 0x101C | Initiate Delta Position Ch 1 | R/W |
|---|---|---|
| 0x106C | Initiate Delta Position Ch 2 | R/W |
| 0x10BC | Initiate Delta Position Ch 3 | R/W |
| 0x110C | Initiate Delta Position Ch 4 | R/W |
| 0x11E0 | Track / Hold | R/W |
|---|
| 0x104C | Inverse Signal Control Ch 1 | R/W |
|---|---|---|
| 0x109C | Inverse Signal Control Ch 2 | R/W |
| 0x10EC | Inverse Signal Control Ch 3 | R/W |
| 0x113C | Inverse Signal Control Ch 4 | R/W |
Threshold Programming Registers
| 0x1034 | Reference Fault Low Threshold Ch 1** | R/W |
|---|---|---|
| 0x1084 | Reference Fault Low Threshold Ch 2** | R/W |
| 0x10D4 | Reference Fault Low Threshold Ch 3** | R/W |
| 0x1124 | Reference Fault Low Threshold Ch 4** | R/W |
| 0x1170 | Reference Fault High Threshold Ch 1** | R/W |
|---|---|---|
| 0x1174 | Reference Fault High Threshold Ch 2** | R/W |
| 0x1178 | Reference Fault High Threshold Ch 3** | R/W |
| 0x117C | Reference Fault High Threshold Ch 4** | R/W |
| 0x1180 | Open Detect Threshold Ch 1~ | R/W |
|---|---|---|
| 0x1188 | Open Detect Threshold Ch 2~ | R/W |
| 0x1190 | Open Detect Threshold Ch 3~ | R/W |
| 0x1198 | Open Detect Threshold Ch 4~ | R/W |
| 0x1184 | Short Detect Threshold Ch 1~ | R/W |
|---|---|---|
| 0x118C | Short Detect Threshold Ch 2~ | R/W |
| 0x1194 | Short Detect Threshold Ch 3~ | R/W |
| 0x119C | Short Detect Threshold Ch 4~ | R/W |
3-Wire/4-Wire Signal Fault Register
| 0x1030 | Signal Fault Low Threshold Ch 1** | R/W |
|---|---|---|
| 0x1080 | Signal Fault Low Threshold Ch 2** | R/W |
| 0x10D0 | Signal Fault Low Threshold Ch 3** | R/W |
| 0x1120 | Signal Fault Low Threshold Ch 4** | R/W |
| 0x1160 | Signal Fault High Threshold Ch 1** | R/W |
|---|---|---|
| 0x1164 | Signal Fault High Threshold Ch 2** | R/W |
| 0x1168 | Signal Fault High Threshold Ch 3** | R/W |
| 0x116C | Signal Fault High Threshold Ch 4** | R/W |
2-Wire Signal Fault Register (Contact Factory)
| 0x1030 | Va Fault High Threshold Ch 1** | R/W |
|---|---|---|
| 0x1080 | Va Fault High Threshold Ch 2** | R/W |
| 0x10D0 | Va Fault High Threshold Ch 3** | R/W |
| 0x1120 | Va Fault High Threshold Ch 4** | R/W |
| 0x1160 | Vb Fault High Threshold Ch 1** | R/W |
|---|---|---|
| 0x1164 | Vb Fault High Threshold Ch 2** | R/W |
| 0x1168 | Vb Fault High Threshold Ch 3** | R/W |
| 0x116C | Vb Fault High Threshold Ch 4** | R/W |
Note
The Signal Thresholds for 3-Wire/4-Wire Signal Fault and 2-Wire Signal Fault registers are at the same location, but they differ in meaning depending if the channel is configured for 3-Wire/4-Wire or 2-Wire mode.
FIFO Registers
| 0x1200 | FIFO Buffer Data Ch 1** | R |
|---|---|---|
| 0x1240 | FIFO Buffer Data Ch 2** | R |
| 0x1280 | FIFO Buffer Data Ch 3** | R |
| 0x12C0 | FIFO Buffer Data Ch 4** | R |
| 0x1204 | FIFO Word Count Ch 1** | R |
|---|---|---|
| 0x1244 | FIFO Word Count Ch 2** | R |
| 0x1284 | FIFO Word Count Ch 3** | R |
| 0x12C4 | FIFO Word Count Ch 4** | R |
| 0x121C | FIFO Sample Rate Ch 1 | R/W |
|---|---|---|
| 0x125C | FIFO Sample Rate Ch 2 | R/W |
| 0x129C | FIFO Sample Rate Ch 3 | R/W |
| 0x12DC | FIFO Sample Rate Ch 4 | R/W |
| 0x1214 | FIFO Sample Delay Ch 1 | R/W |
|---|---|---|
| 0x1254 | FIFO Sample Delay Ch 2 | R/W |
| 0x1294 | FIFO Sample Delay Ch 3 | R/W |
| 0x12D4 | FIFO Sample Delay Ch 4 | R/W |
| 0x1224 | FIFO Buffer Control Ch 1 | R/W |
|---|---|---|
| 0x1264 | FIFO Buffer Control Ch 2 | R/W |
| 0x12A4 | FIFO Buffer Control Ch 3 | R/W |
| 0x12E4 | FIFO Buffer Control Ch 4 | R/W |
| 0x1228 | FIFO Trigger Control Ch 1 | R/W |
|---|---|---|
| 0x1268 | FIFO Trigger Control Ch 2 | R/W |
| 0x12A8 | FIFO Trigger Control Ch 3 | R/W |
| 0x12E8 | FIFO Trigger Control Ch 4 | R/W |
| 0x1220 | FIFO Clear Ch 1 | W |
|---|---|---|
| 0x1260 | FIFO Clear Ch 2 | W |
| 0x12A0 | FIFO Clear Ch 3 | W |
| 0x12E0 | FIFO Clear Ch 4 | W |
| 0x1300 | FIFO Software Trigger | W |
|---|
FIFO Thresholds
| 0x1210 | FIFO Low Watermark Ch 1 | R/W |
|---|---|---|
| 0x1250 | FIFO Low Watermark Ch 2 | R/W |
| 0x1290 | FIFO Low Watermark Ch 3 | R/W |
| 0x12D0 | FIFO Low Watermark Ch 4 | R/W |
| 0x120C | FIFO High Watermark Ch 1 | R/W |
|---|---|---|
| 0x124C | FIFO High Watermark Ch 2 | R/W |
| 0x128C | FIFO High Watermark Ch 3 | R/W |
| 0x12CC | FIFO High Watermark Ch 4 | R/W |
| 0x1230 | FIFO Almost Empty Ch 1 | R/W |
|---|---|---|
| 0x1270 | FIFO Almost Empty Ch 2 | R/W |
| 0x12B0 | FIFO Almost Empty Ch 3 | R/W |
| 0x12F0 | FIFO Almost Empty Ch 4 | R/W |
| 0x122C | FIFO Almost Full Ch 1 | R/W |
|---|---|---|
| 0x126C | FIFO Almost Full Ch 2 | R/W |
| 0x12AC | FIFO Almost Full Ch 3 | R/W |
| 0x12EC | FIFO Almost Full Ch 4 | R/W |
| 0x1218 | FIFO Buffer Size Ch 1 | R/W |
|---|---|---|
| 0x1258 | FIFO Buffer Size Ch 2 | R/W |
| 0x1298 | FIFO Buffer Size Ch 3 | R/W |
| 0x12D8 | FIFO Buffer Size Ch 4 | R/W |
Engineering Scaling Conversion Registers
| 0x02B4 | Enable Floating Point Mode | R/W |
|---|---|---|
| 0x0264 | Floating Point State | R |
| 0x1400 | Position Floating Point Scale Ch 1~ | R/W |
|---|---|---|
| 0x1404 | Position Floating Point Scale Ch 2~ | R/W |
| 0x1408 | Position Floating Point Scale Ch 3~ | R/W |
| 0x140C | Position Floating Point Scale Ch 4~ | R/W |
| 0x1410 | Position Floating Point Offset Ch 1~ | R/W |
|---|---|---|
| 0x1414 | Position Floating Point Offset Ch 2~ | R/W |
| 0x1418 | Position Floating Point Offset Ch 3~ | R/W |
| 0x141C | Position Floating Point Offset Ch 4~ | R/W |
| 0x1420 | Velocity Floating Point Scale Ch 1 | R/W |
|---|---|---|
| 0x1424 | Velocity Floating Point Scale Ch 2 | R/W |
| 0x1428 | Velocity Floating Point Scale Ch 3 | R/W |
| 0x142C | Velocity Floating Point Scale Ch 4 | R/W |
| 0x1430 | Velocity Floating Point Offset Ch 1~ | R/W |
|---|---|---|
| 0x1434 | Velocity Floating Point Offset Ch 2~ | R/W |
| 0x1438 | Velocity Floating Point Offset Ch 3~ | R/W |
| 0x143C | Velocity Floating Point Offset Ch 4~ | R/W |
| 0x1440 | Position ‘B’ Floating Point Scale Ch 1~ | R/W |
|---|---|---|
| 0x1444 | Position ‘B’ Floating Point Scale Ch 2~ | R/W |
| 0x1448 | Position ‘B’ Floating Point Scale Ch 3~ | R/W |
| 0x144C | Position ‘B’ Floating Point Scale Ch 4~ | R/W |
| 0x1450 | Position ‘B’ Floating Point Offset Ch 1~ | R/W |
|---|---|---|
| 0x1454 | Position ‘B’ Floating Point Offset Ch 2~ | R/W |
| 0x1458 | Position ‘B’ Floating Point Offset Ch 3~ | R/W |
| 0x145C | Position ‘B’ Floating Point Offset Ch 4~ | R/W |
| 0x1460 | Velocity ‘B’ Floating Point Scale Ch 1~ | R/W |
|---|---|---|
| 0x1464 | Velocity ‘B’ Floating Point Scale Ch 2~ | R/W |
| 0x1468 | Velocity ‘B’ Floating Point Scale Ch 3~ | R/W |
| 0x146C | Velocity ‘B’ Floating Point Scale Ch 4~ | R/W |
| 0x1470 | Velocity ‘B’ Floating Point Offset Ch 1~ | R/W |
|---|---|---|
| 0x1474 | Velocity ‘B’ Floating Point Offset Ch 2~ | R/W |
| 0x1478 | Velocity ‘B’ Floating Point Offset Ch 3~ | R/W |
| 0x147C | Velocity ‘B’ Floating Point Offset Ch 4~ | R/W |
Module Common Registers
Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.
Status Registers
| 0x02B0 | Channel Status Enable | R/W |
|---|
BIT Status
| 0x0800 | Dynamic Status | R |
|---|---|---|
| 0x0804 | Latched Status* | R/W |
| 0x0808 | Interrupt Enable | R/W |
| 0x080C | Set Edge/Level Interrupt | R/W |
Test Registers
| 0x0294 | UBIT Test Position**** | R/W |
|---|---|---|
| 0x0248 | Test Enabled | R/W |
| 0x024C | Test CBIT Verify | R/W |
Bit Error Limit
| 0x1330 | BIT Error Limit Ch 1~ | R/W |
|---|---|---|
| 0x1334 | BIT Error Limit Ch 2~ | R/W |
| 0x1338 | BIT Error Limit Ch 3~ | R/W |
| 0x133C | BIT Error Limit Ch 4~ | R/W |
| 0x02AC | Power-on BIT Complete++ | R |
|---|
++ After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.
Status Registers
3-Wire/4-Wire Signal Fault Status*
Signal Fault Low
| 0x0810 | Dynamic Status | R |
|---|---|---|
| 0x0814 | Latched Status* | R/W |
| 0x0818 | Interrupt Enable | R/W |
| 0x081C | Set Edge/Level Interrupt | R/W |
Signal Fault High Status
| 0x08B0 | Dynamic Status | R |
|---|---|---|
| 0x08B4 | Latched Status* | R/W |
| 0x08B8 | Interrupt Enable | R/W |
| 0x08BC | Set Edge/Level Interrupt | R/W |
2-Wire Signal Fault Status*
Va Fault Low (contact factory)
| 0x0810 | Dynamic Status | R |
|---|---|---|
| 0x0814 | Latched Status* | R/W |
| 0x0818 | Interrupt Enable | R/W |
| 0x081C | Set Edge/Level Interrupt | R/W |
Vb Fault High (contact factory)
| 0x08B0 | Dynamic Status | R |
|---|---|---|
| 0x08B4 | Latched Status* | R/W |
| 0x08B8 | Interrupt Enable | R/W |
| 0x08BC | Set Edge/Level Interrupt | R/W |
Note
- The Signal Fault Status for 3-Wire/4-Wire Signal Fault and 2-Wire Signal Fault registers are at the same location, but they differ in meaning depending if the channel is configured for 3-Wire/4-Wire or 2-Wire mode
Reference Fault Low Status
| 0x0820 | Dynamic Status | R |
|---|---|---|
| 0x0824 | Latched Status* | R/W |
| 0x0828 | Interrupt Enable | R/W |
| 0x082C | Set Edge/Level Interrupt | R/W |
Reference Fault High Status
| 0x08C0 | Dynamic Status | R |
|---|---|---|
| 0x08C4 | Latched Status* | R/W |
| 0x08C8 | Interrupt Enable | R/W |
| 0x08CC | Set Edge/Level Interrupt | R/W |
Delta Position Status
| 0x0840 | Dynamic Status | R |
|---|---|---|
| 0x0844 | Latched Status* | R/W |
| 0x0848 | Interrupt Enable | R/W |
| 0x084C | Set Edge/Level Interrupt | R/W |
Open Detect Status
| 0x0890 | Dynamic Status | R |
|---|---|---|
| 0x0894 | Latched Status* | R/W |
| 0x0898 | Interrupt Enable | R/W |
| 0x089C | Set Edge/Level Interrupt | R/W |
Short Detect Status
| 0x0840 | Dynamic Status | R |
|---|---|---|
| 0x0844 | Latched Status* | R/W |
| 0x0848 | Interrupt Enable | R/W |
| 0x084C | Set Edge/Level Interrupt | R/W |
Summary Status
| 0x09A0 | Dynamic Status | R |
|---|---|---|
| 0x09A4 | Latched Status* | R/W |
| 0x09A8 | Interrupt Enable | R/W |
| 0x09AC | Set Edge/Level Interrupt | R/W |
FIFO Status
| CH1 | ||
| 0x0850 | Dynamic Status | R |
| 0x0854 | Latched Status* | R/W |
| 0x0858 | Interrupt Enable | R/W |
| 0x085C | Set Edge/Level Interrupt | R/W |
| CH2 | ||
| 0x0860 | Dynamic Status | R |
| 0x0864 | Latched Status* | R/W |
| 0x0868 | Interrupt Enable | R/W |
| 0x086C | Set Edge/Level Interrupt | R/W |
| CH3 | ||
| 0x0870 | Dynamic Status | R |
| 0x0874 | Latched Status* | R/W |
| 0x0878 | Interrupt Enable | R/W |
| 0x087C | Set Edge/Level Interrupt | R/W |
| CH4 | ||
| 0x0880 | Dynamic Status | R |
| 0x0884 | Latched Status* | R/W |
| 0x0888 | Interrupt Enable | R/W |
| 0x088C | Set Edge/Level Interrupt | R/W |
Interrupt Registers
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.
| 0x0500 | Module 1 Interrupt Vector 1 - BIT | R/W |
|---|---|---|
| 0x0504 | Module 1 Interrupt Vector 2 - Signal Fault Low / Va Fault High | R/W |
| 0x0508 | Module 1 Interrupt Vector 3 - Reference Fault Low | R/W |
| 0x050C | Module 1 Interrupt Vector 4 - Reserved | R/W |
| 0x0510 | Module 1 Interrupt Vector 5 - Delta Position | R/W |
| 0x0514 | Module 1 Interrupt Vector 6 - FIFO Ch 1 | R/W |
| 0x0518 | Module 1 Interrupt Vector 7 - FIFO Ch 2 | R/W |
| 0x051C | Module 1 Interrupt Vector 8 - FIFO Ch 3 | R/W |
| 0x0520 | Module 1 Interrupt Vector 9 - FIFO Ch 4 | R/W |
| 0x0524 | Module 1 Interrupt Vector 10 - Open Detect | R/W |
| 0x0528 | Module 1 Interrupt Vector 11 - Short Detect | R/W |
| 0x052C | Module 1 Interrupt Vector 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0530 | Module 1 Interrupt Vector 13 - Reference Fault High | R/W |
| 0x0534-0x0564 | Module 1 Interrupt Vector 14-26 - Reserved | R/W |
| 0x0568 | Module 1 Interrupt Vector 27 - Summary | R/W |
| 0x056C-0x057C | Module 1 Interrupt Vector 28-32 - Reserved | R/W |
| 0x0600 | Module 1 Interrupt Steering 1 - BIT | R/W |
|---|---|---|
| 0x0604 | Module 1 Interrupt Steering 2 - Signal Fault Low / Va Fault High | R/W |
| 0x0608 | Module 1 Interrupt Steering 3 - Reference Fault Low | R/W |
| 0x060C | Module 1 Interrupt Steering 4 - Reserved | R/W |
| 0x0610 | Module 1 Interrupt Steering 5 - Delta Position | R/W |
| 0x0614 | Module 1 Interrupt Steering 6 - FIFO Ch 1 | R/W |
| 0x0618 | Module 1 Interrupt Steering 7 - FIFO Ch 2 | R/W |
| 0x061C | Module 1 Interrupt Steering 8 - FIFO Ch 3 | R/W |
| 0x0620 | Module 1 Interrupt Steering 9 - FIFO Ch 4 | R/W |
| 0x0624 | Module 1 Interrupt Steering 10 - Open Detect | R/W |
| 0x0628 | Module 1 Interrupt Steering 11 - Short Detect | R/W |
| 0x062C | Module 1 Interrupt Steering 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0630 | Module 1 Interrupt Steering 13 - Reference Fault High | R/W |
| 0x0634-0x0664 | Module 1 Interrupt Steering 14-26 - Reserved | R/W |
| 0x0668 | Module 1 Interrupt Steering 27 - Summary | R/W |
| 0x066C-0x067C | Module 1 Interrupt Steering 28-32 - Reserved | R/W |
| 0x0700 | Module 2 Interrupt Vector 1 - BIT | R/W |
| --- | --- | --- |
| 0x0704 | Module 2 Interrupt Vector 2 - Signal Fault Low / Va Fault High | R/W |
| 0x0708 | Module 2 Interrupt Vector 3 - Reference Fault Low | R/W |
| 0x070C | Module 2 Interrupt Vector 4 - Reserved | R/W |
| 0x0710 | Module 2 Interrupt Vector 5 - Delta Position | R/W |
| 0x0714 | Module 2 Interrupt Vector 6 - FIFO Ch 1 | R/W |
| 0x0718 | Module 2 Interrupt Vector 7 - FIFO Ch 2 | R/W |
| 0x071C | Module 2 Interrupt Vector 8 - FIFO Ch 3 | R/W |
| 0x0720 | Module 2 Interrupt Vector 9 - FIFO Ch 4 | R/W |
| 0x0724 | Module 2 Interrupt Vector 10 - Open Detect | R/W |
| 0x0728 | Module 2 Interrupt Vector 11 - Short Detect | R/W |
| 0x072C | Module 2 Interrupt Vector 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0730 | Module 2 Interrupt Vector 13 - Reference Fault High | R/W |
| 0x0734-0x0764 | Module 2 Interrupt Vector 14-26 - Reserved | R/W |
| 0x0768 | Module 2 Interrupt Vector 27 - Summary | R/W |
| 0x076C-0x077C | Module 2 Interrupt Vector 28-32 - Reserved | R/W |
| 0x0800 | Module 2 Interrupt Steering 1 - BIT | R/W |
|---|---|---|
| 0x0804 | Module 2 Interrupt Steering 2 - Signal Fault Low / Va Fault High | R/W |
| 0x0808 | Module 2 Interrupt Steering 3 - Reference Fault Low | R/W |
| 0x080C | Module 2 Interrupt Steering 4 - Reserved | R/W |
| 0x0810 | Module 2 Interrupt Steering 5 - Delta Position | R/W |
| 0x0814 | Module 2 Interrupt Steering 6 - FIFO Ch 1 | R/W |
| 0x0818 | Module 2 Interrupt Steering 7 - FIFO Ch 2 | R/W |
| 0x081C | Module 2 Interrupt Steering 8 - FIFO Ch 3 | R/W |
| 0x0820 | Module 2 Interrupt Steering 9 - FIFO Ch 4 | R/W |
| 0x0824 | Module 2 Interrupt Steering 10 - Open Detect | R/W |
| 0x0828 | Module 2 Interrupt Steering 11 - Short Detect | R/W |
| 0x082C | Module 2 Interrupt Steering 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0830 | Module 2 Interrupt Steering 13 - Reference Fault High | R/W |
| 0x0834-0x0864 | Module 2 Interrupt Steering 14-26 - Reserved | R/W |
| 0x0868 | Module 2 Interrupt Steering 27 - Summary | R/W |
| 0x086C-0x087C | Module 2 Interrupt Steering 28-32 - Reserved | R/W |
| 0x0900 | Module 3 Interrupt Vector 1 - BIT | R/W |
|---|---|---|
| 0x0904 | Module 3 Interrupt Vector 2 - Signal Fault Low | R/W |
| 0x0908 | Module 3 Interrupt Vector 3 - Reference Fault Low / Va Fault High | R/W |
| 0x090C | Module 3 Interrupt Vector 4 - Reserved | R/W |
| 0x0910 | Module 3 Interrupt Vector 5 - Delta Position | R/W |
| 0x0914 | Module 3 Interrupt Vector 6 - FIFO Ch 1 | R/W |
| 0x0918 | Module 3 Interrupt Vector 7 - FIFO Ch 2 | R/W |
| 0x091C | Module 3 Interrupt Vector 8 - FIFO Ch 3 | R/W |
| 0x0920 | Module 3 Interrupt Vector 9 - FIFO Ch 4 | R/W |
| 0x0924 | Module 3 Interrupt Vector 10 - Open Detect | R/W |
| 0x0928 | Module 3 Interrupt Vector 11 - Short Detect | R/W |
| 0x092C | Module 3 Interrupt Vector 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0930 | Module 3 Interrupt Vector 13 - Reference Fault High | R/W |
| 0x0934-0x0964 | Module 3 Interrupt Vector 14-26 - Reserved | R/W |
| 0x0968 | Module 3 Interrupt Vector 27 - Summary | R/W |
| 0x096C-0x097C | Module 3 Interrupt Vector 28-32 - Reserved | R/W |
| 0x0A00 | Module 3 Interrupt Steering 1 - BIT | R/W |
|---|---|---|
| 0x0A04 | Module 3 Interrupt Steering 2 - Signal Fault Low | R/W |
| 0x0A08 | Module 3 Interrupt Steering 3 - Reference Fault Low / Va Fault High | R/W |
| 0x0A0C | Module 3 Interrupt Steering 4 - Reserved | R/W |
| 0x0A10 | Module 3 Interrupt Steering 5 - Delta Position | R/W |
| 0x0A14 | Module 3 Interrupt Steering 6 - FIFO Ch 1 | R/W |
| 0x0A18 | Module 3 Interrupt Steering 7 - FIFO Ch 2 | R/W |
| 0x0A1C | Module 3 Interrupt Steering 8 - FIFO Ch 3 | R/W |
| 0x0A20 | Module 3 Interrupt Steering 9 - FIFO Ch 4 | R/W |
| 0x0A24 | Module 3 Interrupt Steering 10 - Open Detect | R/W |
| 0x0A28 | Module 3 Interrupt Steering 11 - Short Detect | R/W |
| 0x0A2C | Module 3 Interrupt Steering 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0A30 | Module 3 Interrupt Steering 13 - Reference Fault High | R/W |
| 0x0A34-0x0A64 | Module 3 Interrupt Steering 14-26 - Reserved | R/W |
| 0x0A68 | Module 3 Interrupt Steering 27 - Summary | R/W |
| 0x0A6C-0x0A7C | Module 3 Interrupt Steering 28-32 - Reserved | R/W |
| 0x0B00 | Module 4 Interrupt Vector 1 - BIT | R/W |
|---|---|---|
| 0x0B04 | Module 4 Interrupt Vector 2 - Signal Fault Low / Va Fault High | R/W |
| 0x0B08 | Module 4 Interrupt Vector 3 - Reference Fault Low | R/W |
| 0x0B0C | Module 4 Interrupt Vector 4 - Reserved | R/W |
| 0x0B10 | Module 4 Interrupt Vector 5 - Delta Position | R/W |
| 0x0B14 | Module 4 Interrupt Vector 6 - FIFO Ch 1 | R/W |
| 0x0B18 | Module 4 Interrupt Vector 7 - FIFO Ch 2 | R/W |
| 0x0B1C | Module 4 Interrupt Vector 8 - FIFO Ch 3 | R/W |
| 0x0B20 | Module 4 Interrupt Vector 9 - FIFO Ch 4 | R/W |
| 0x0B24 | Module 4 Interrupt Vector 10 - Open Detect | R/W |
| 0x0B28 | Module 4 Interrupt Vector 11 - Short Detect | R/W |
| 0x0B2C | Module 4 Interrupt Vector 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0B30 | Module 4 Interrupt Vector 13 - Reference Fault High | R/W |
| 0x0B34-0x0B64 | Module 4 Interrupt Vector 14-26 - Reserved | R/W |
| 0x0B68 | Module 4 Interrupt Vector 27 - Summary | R/W |
| 0x0B6C-0x0B7C | Module 4 Interrupt Vector 28-32 - Reserved | R/W |
| 0x0C00 | Module 4 Interrupt Steering 1 - BIT | R/W |
|---|---|---|
| 0x0C04 | Module 4 Interrupt Steering 2 - Signal Fault Low / Va Fault High | R/W |
| 0x0C08 | Module 4 Interrupt Steering 3 - Reference Fault Low | R/W |
| 0x0C0C | Module 4 Interrupt Steering 4 - Reserved | R/W |
| 0x0C10 | Module 4 Interrupt Steering 5 - Delta Position | R/W |
| 0x0C14 | Module 4 Interrupt Steering 6 - FIFO Ch 1 | R/W |
| 0x0C18 | Module 4 Interrupt Steering 7 - FIFO Ch 2 | R/W |
| 0x0C1C | Module 4 Interrupt Steering 8 - FIFO Ch 3 | R/W |
| 0x0C20 | Module 4 Interrupt Steering 9 - FIFO Ch 4 | R/W |
| 0x0C24 | Module 4 Interrupt Steering 10 - Open Detect | R/W |
| 0x0C28 | Module 4 Interrupt Steering 11 - Short Detect | R/W |
| 0x0C2C | Module 4 Interrupt Steering 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0C30 | Module 4 Interrupt Steering 13 - Reference Fault High | R/W |
| 0x0C34-0x0C64 | Module 4 Interrupt Steering 14-26 - Reserved | R/W |
| 0x0C68 | Module 4 Interrupt Steering 27 - Summary | R/W |
| 0x0C6C-0x0C7C | Module 4 Interrupt Steering 28-32 - Reserved | R/W |
| 0x0D00 | Module 5 Interrupt Vector 1 - BIT | R/W |
|---|---|---|
| 0x0D04 | Module 5 Interrupt Vector 2 - Signal Fault Low / Va Fault High | R/W |
| 0x0D08 | Module 5 Interrupt Vector 3 - Reference Fault Low | R/W |
| 0x0D0C | Module 5 Interrupt Vector 4 - Reserved | R/W |
| 0x0D10 | Module 5 Interrupt Vector 5 - Delta Position | R/W |
| 0x0D14 | Module 5 Interrupt Vector 6 - FIFO Ch 1 | R/W |
| 0x0D18 | Module 5 Interrupt Vector 7 - FIFO Ch 2 | R/W |
| 0x0D1C | Module 5 Interrupt Vector 8 - FIFO Ch 3 | R/W |
| 0x0D20 | Module 5 Interrupt Vector 9 - FIFO Ch 4 | R/W |
| 0x0D24 | Module 5 Interrupt Vector 10 - Open Detect | R/W |
| 0x0D28 | Module 5 Interrupt Vector 11 - Short Detect | R/W |
| 0x0D2C | Module 5 Interrupt Vector 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0D30 | Module 5 Interrupt Vector 13 - Reference Fault High | R/W |
| 0x0D34-0x0D64 | Module 5 Interrupt Vector 14-26 - Reserved | R/W |
| 0x0D68 | Module 5 Interrupt Vector 27 - Summary | R/W |
| 0x0D6C-0x0D7C | Module 5 Interrupt Vector 28-32 - Reserved | R/W |
| 0x0E00 | Module 5 Interrupt Steering 1 - BIT | R/W |
|---|---|---|
| 0x0E04 | Module 5 Interrupt Steering 2 - Signal Fault Low / Va Fault High | R/W |
| 0x0E08 | Module 5 Interrupt Steering 3 - Reference Fault Low | R/W |
| 0x0E0C | Module 5 Interrupt Steering 4 - Reserved | R/W |
| 0x0E10 | Module 5 Interrupt Steering 5 - Delta Position | R/W |
| 0x0E14 | Module 5 Interrupt Steering 6 - FIFO Ch 1 | R/W |
| 0x0E18 | Module 5 Interrupt Steering 7 - FIFO Ch 2 | R/W |
| 0x0E1C | Module 5 Interrupt Steering 8 - FIFO Ch 3 | R/W |
| 0x0E20 | Module 5 Interrupt Steering 9 - FIFO Ch 4 | R/W |
| 0x0E24 | Module 5 Interrupt Steering 10 - Open Detect | R/W |
| 0x0E28 | Module 5 Interrupt Steering 11 - Short Detect | R/W |
| 0x0E2C | Module 5 Interrupt Steering 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0E30 | Module 5 Interrupt Steering 13 - Reference Fault High | R/W |
| 0x0E34-0x0E64 | Module 5 Interrupt Steering 14-26 - Reserved | R/W |
| 0x0E68 | Module 5 Interrupt Steering 27 - Summary | R/W |
| 0x0E6C-0x0E7C | Module 5 Interrupt Steering 28-32 - Reserved | R/W |
| 0x0F00 | Module 6 Interrupt Vector 1 - BIT | R/W |
|---|---|---|
| 0x0F04 | Module 6 Interrupt Vector 2 - Signal Fault Low / Va Fault High | R/W |
| 0x0F08 | Module 6 Interrupt Vector 3 - Reference Fault Low | R/W |
| 0x0F0C | Module 6 Interrupt Vector 4 - Reserved | R/W |
| 0x0F10 | Module 6 Interrupt Vector 5 - Delta Position | R/W |
| 0x0F14 | Module 6 Interrupt Vector 6 - FIFO Ch 1 | R/W |
| 0x0F18 | Module 6 Interrupt Vector 7 - FIFO Ch 2 | R/W |
| 0x0F1C | Module 6 Interrupt Vector 8 - FIFO Ch 3 | R/W |
| 0x0F20 | Module 6 Interrupt Vector 9 - FIFO Ch 4 | R/W |
| 0x0F24 | Module 6 Interrupt Vector 10 - Open Detect | R/W |
| 0x0F28 | Module 6 Interrupt Vector 11 - Short Detect | R/W |
| 0x0F2C | Module 6 Interrupt Vector 12 - Signal Fault High / Vb Fault High | R/W |
| 0x0F30 | Module 6 Interrupt Vector 13 - Reference Fault High | R/W |
| 0x0F34-0x0F64 | Module 6 Interrupt Vector 14-26 - Reserved | R/W |
| 0x0F68 | Module 6 Interrupt Vector 27 - Summary | R/W |
| 0x0F6C-0x0F7C | Module 6 Interrupt Vector 28-32 - Reserved | R/W |
| 0x1000 | Module 6 Interrupt Steering 1 - BIT | R/W |
|---|---|---|
| 0x1004 | Module 6 Interrupt Steering 2 - Signal Fault Low / Va Fault High | R/W |
| 0x1008 | Module 6 Interrupt Steering 3 - Reference Fault Low | R/W |
| 0x100C | Module 6 Interrupt Steering 4 - Reserved | R/W |
| 0x1010 | Module 6 Interrupt Steering 5 - Delta Position | R/W |
| 0x1014 | Module 6 Interrupt Steering 6 - FIFO Ch 1 | R/W |
| 0x1018 | Module 6 Interrupt Steering 7 - FIFO Ch 2 | R/W |
| 0x101C | Module 6 Interrupt Steering 8 - FIFO Ch 3 | R/W |
| 0x1020 | Module 6 Interrupt Steering 9 - FIFO Ch 4 | R/W |
| 0x1024 | Module 6 Interrupt Steering 10 - Open Detect | R/W |
| 0x1028 | Module 6 Interrupt Steering 11 - Short Detect | R/W |
| 0x102C | Module 6 Interrupt Steering 12 - Signal Fault High / Vb Fault High | R/W |
| 0x1030 | Module 6 Interrupt Steering 13 - Reference Fault High | R/W |
| 0x1034-0x1064 | Module 6 Interrupt Steering 14-26 - Reserved | R/W |
| 0x1068 | Module 6 Interrupt Steering 27 - Summary | R/W |
| 0x106C-0x107C | Module 6 Interrupt Steering 28-32 - Reserved | R/W |
APPENDIX A: INTEGER/FLOATING POINT MODE PROGRAMMING
Integer Mode Programming
Position, Velocity, and FIFO Buffering Data Programming
Position: The value read in the Position or FIFO Buffer Data (position data) register, while in Integer Mode, is dependent on an “LSB” value. The LSB value is defined as Full Scale Range / 232 . Since full scale range is ±100.00%, the LSB will be calculated as follows: (LSB = 200 / 232 = ~4.6566e-8).
Note
The per bit position values in the following table are approximate.
Position Data Calculation:
| Position Data Register Value (Decimal Value/Hex Value) | LSB | Position |
|---|---|---|
| 536870912 (0x2000 0000) | 4.6566e-8 | 536870912 * LSB = 25.00% |
| -214748416 (0xF333 3300) | 4.6566e-8 | -214748416 * LSB = -10% |
| 1755567872 (0x68A3 D700) | 4.6566e-8 | 1755567872 * LSB = 81.75% |
Normalized positional measurement voltage-displacement identities:
Velocity: The value read in the Velocity or FIFO Buffer Data (velocity data) register, while in Integer Mode, has an LSB weight of 0.1%
Velocity Data Calculation:
| Velocity Data Register Value (Decimal Value/Hex Value) | LSB | Velocity |
|---|---|---|
| 218 (0x0000 00DA) | 0.1 | 218 * LSB = 21.8% / sec |
| -2 (0xFFFF FFFE) | 0.1 | -2 * LSB = -0.2% / sec |
| 50 (0x0000 0032) | 0.1 | 50 * LSB = 5.0% / sec |
FIFO Buffer Data:
Note
An additional item that can be stored in the FIFO Buffer Data register is a Timestamp. This value will always be represented as an integer even when the Enable Floating Point Mode register is set to “1” (Floating point mode)
Timestamp value from FIFO Data Buffer:
| FIFO Buffer Data Timestamp Value (Decimal Value/Hex Value) | Value |
|---|---|
| 77 (0x0000 004D) | 77 |
UBIT Testing Programming
The value to set in the UBIT Test Position register, while in Integer Mode, is dependent on an “LSB” value. The LSB value is defined as Full Scale Range / 2^ . Since full scale range is ±100.00%, the LSB will be calculated as follows. (LSB = 200 / 2^ = ~4.6566e-8).
Note
Engineering Scaling Conversions will not be used for Test Position in UBIT mode.
Test Position:
UBIT Test Value
| UBIT Test Position | LSB | Binary Value Integer Mode |
|---|---|---|
| 25.00% | 4.6566e-8 | 25.00 / LSB = 536870912 = 0x2000 0000 |
| -10.00% | 4.6566e-8 | -10.00 / LSB = -214748416 = 0xF333 3300 |
| 81.75% | 4.6566e-8 | 81.75 / LSB = 175556787= 0x68A3 D700 |
Threshold and Delta Position Programming
To set the threshold value for Signal and Reference Faults, divide the value desired by the LSB weight (0.01) and write it to the corresponding threshold register.
Signal and Reference Fault Low and High Thresholds:
Example:
You want to be alerted when the reference voltage either drops below 6.00Vrms or exceeds 10.00Vrms. In addition, you also want to be alerted when the signal drops below 1.00Vrms or exceeds 5.00Vrms. Write the following values to the corresponding threshold registers. See table below.
| Register | Value written to the register (Decimal Value/Hex Value) | LSB | Voltage (rms) |
|---|---|---|---|
| Reference Fault Low Threshold | 600 (0x0000 0258) | 0.01 | 600 * LSB = 6.00 Vrms |
| Reference Fault High Threshold | 1000 (0x0000 03E8) | 0.01 | 1000 * LSB = 10.00 Vrms |
| Signal Fault Low Threshold | 100 (0x0000 0064) | 0.01 | 100 * LSB = 1.00 Vrms |
| Signal Fault High Threshold | 500 (0x000 001F4) | 0.01 | 500 * LSB = 5.00 Vrms |
Delta Position:
Example:
To be alerted when the position changes more than 3%, write the following value to the Delta Position register. See table below. Note: For this detection to function properly, you must set a “trigger” position by setting the Initiate Delta Position register as described in the Initiate Delta Position section.
| Register | Value written to the register (Decimal Value/Hex Value) | LSB | Delta Position |
|---|---|---|---|
| Delta Position | 64463616 (0x03D7 A300) | 4.6566e-8 | 64463616 * LSB = 3.00% |
Open and Short Detect Thresholds:
Note
Open and Short Detect Threshold programming is not valid in integer mode and will be described in the Floating-Point Mode section.
RMS Voltage Reading
The value read in the Signal and Reference RMS Voltage registers is a 32-bit unsigned value. To calculate the RMS voltage, you must multiply this value by an LSB weight. The LSB = 0.01 (10 mv). For example, if the value read is 2600 (0x0A28), the RMS value will be 26.00Vrms.
| Value read from Measured Signal or Measured Reference registers (Decimal Value/Hex Value) | LSB | RMS Voltage (Volts) |
|---|---|---|
| 2600 (0x0000 0A28) | 0.01 | 26.00 |
| 1150 (0x0000 047E) | 0.01 | 11.50 |
| 275 (0x0000 0113) | 0.01 | 2.75 |
Frequency Reading
The value read in the Frequency registers is a 32-bit unsigned value. To calculate the frequency, you must multiply this value by an LSB weight. The LSB = 1 (1Hz). For example, if the value read is 2500 (0x09C4), the frequency value will be 2500Hz.
| Value read from Measured Frequency registers (Decimal Value/Hex Value) | LSB | Frequency (Hz) |
|---|---|---|
| 2500 (0x0000 09C4) | 1.0 | 2500 |
| 1000 (0x0000 03E8) | 1.0 | 1000 |
| 400 (0x0000 0190) | 1.0 | 400 |
LVDT/RVDT Scale Programming
Example:
If full scale travel is 4 inches, and you want 3.5 inches to represent full scale, take 3.5, divide it by 4, then multiply by 2147483647 (0x7FFF FFFF):
(3.5/4.0) * 2147483647 = 1879048191 (0x6FFF FFFF)
Set LVDT/RVDT Scale register value to 0x6FFF FFFF.
Floating Point Mode Position/Velocity Programming
Position, Velocity, and FIFO Buffering Data Programming
Position: The value read in the Position or FIFO Buffer Data (position data) register, while in Floating Point Mode, is represented in Single Precision Floating Point Value (IEEE-754) format.
| Position Data Register Value Single Precision Floating Point Value (IEEE-754) |
|---|
| Position Data |
| 0x41C8 0000 25.00% |
| 0xC120 0000 -10.00% |
| 0x42A3 8000 81.75% |
Velocity: The value read in the Velocity or FIFO Buffer Data (velocity data) register, while in Floating Point Mode, is simply the IEEE-754 single precision formatted value.
| Velocity Data Register Value Single Precision Floating Point Value (IEEE-754) |
|---|
| Velocity Data |
| 0x41AE 6666 21.8% / sec |
| 0xBE4C CCCD -0.2% / sec |
| 0x40A0 0000 5.0% / sec |
Timestamp value from FIFO Data Buffer:
Note
Timestamp is always represented as an Integer and cannot be read as a Floating-Point value
UBIT Testing Programming
The value to set in the UBIT Test Position register, while in Floating-Point Mode, is simply the IEEE-754 floating point value for the position desired.
Test Position:
| UBIT Test Position | Test Position Register Value Single Precision Floating Point Value (IEEE-754) |
|---|---|
| 25.00% | 0x41C8 0000 |
| -10.00% | 0xC120 0000 |
| 81.75% | 0x42A3 8000 |
Threshold and Delta Position Programming
The value to set in the Threshold registers, while in Floating-Point Mode, is represented in Single Precision Floating Point Value (IEEE-754) format.
Signal and Reference Fault Low and High Thresholds:
Example:
You want to be alerted when the reference voltage either drops below 6.00Vrms or exceeds 10.00Vrms. In addition, you also want to be alerted when the signal drops below 1.00Vrms or exceeds 5.00Vrms. Write the following values to the corresponding threshold registers. See table below.
| Register | Value written to the register Single Precision Floating Point Value (IEEE-754) | Voltage(rms) |
|---|---|---|
| Reference Fault Low Threshold | 0x40C0 0000 | 6.00 Vrms |
| Reference Fault High Threshold | 0x4120 0000 | 10.00 Vrms |
| Signal Fault Low Threshold | 0x3F80 0000 | 1.00 Vrms |
| Signal Fault High Threshold | 0x40A0 0000 | 5.00 Vrms |
Delta Position:
Example:
To be alerted when the position changes more than 3%, write the following value to the Delta Position register. See table below.
Note
For this detection to function properly, you must set a “trigger” position by setting the Initiate Delta Position register as described in the Initiate Delta Position section.
| Register | Value written to the register Single Precision Floating Point Value (IEEE-754) | Delta Position |
|---|---|---|
| Delta Position | 0x4040 0000 | 3.00% |
Open and Short Detect Thresholds:
Example:
To be alerted when either an OPEN or SHORTED winding occurs. Under normal operating conditions, the LVDT/RVDT sensor 4000HR in 4 wire mode, will produce values between 400 & 1200 depending on the position of the shaft. With one of the 4 wires disconnected, the value increases to approximately 5000. With either the Va or Vb pair disconnected, the value jumps to about 10000. When either the Va or Vb windings are shorted, the value decreases to near zero. Knowing this Info, it would be recommended to set the thresholds as follows. Open Detect Threshold: 3500 Short Detect Threshold: 100
| Register Value written to the register Single Precision Floating Point Value (IEEE-754) | Threshold Value | Open Detect Threshold |
|---|---|---|
| 0x455A C000 | 3500 | Short Detect Threshold |
| 0x42C8 0000 | 100 |
RMS Voltage Reading
The value read in the Signal and Reference RMS Voltage registers is in Single Precision Floating Point Value (IEEE-754) format.
| Value read from Measured Signal or Measured Reference registers Single Precision Floating Point Value (IEEE-754) | RMS Voltage (Volts) |
|---|---|
| 0x41D0 0000 | 26.00 |
| 0x4138 0000 | 11.50 |
| 0x4030 0000 | 2.75 |
Frequency Reading
The value read in the Frequency registers is in Single Precision Floating Point Value (IEEE-754) format.
| Value read from Measured Frequency registers Single Precision Floating Point Value (IEEE-754) | Frequency (Hz) |
|---|---|
| 0x451C 4000 | 2500 |
| 0x453B 8000 | 3000 |
| 0x449F 6000 | 1275 |
Floating Point Mode Engineering Units Programming
Position, Velocity, and FIFO Buffer Data
Example:
Set the channel up to read full scale excursion of the LVDT in inches as opposed to a percentage. The LVDT has full scale excursion of 4.5 inches. The default value in the Position Floating Point Scale register is set to 100, which represents full scale being 100%.
Write 4.5 to the Position Floating Point Scale register, full scale will now display 4.500.
When the LVDT is at ½ scale, the Position Data register will read 2.250.
If you want to adjust the offset by +¼ of an inch, write 0.25 to the Position Floating Point Offset register.
The value in the Position Data register will now be at 2.500.
Note
The scale will always multiply first before any offset is adjusted.
| Register | Binary Value written to register | Value |
|---|---|---|
| Position Floating Point Offset | 0x3E80 0000 | 0.25 |
| Position Floating Point Scale | 0x4090 0000 | 4.5 |
APPENDIX B: REGISTER NAME CHANGES FROM PREVIOUS RELEASES
This section provides a mapping of the register names used in this document against register names used in previous releases.
| Rev B - Register Names | Rev A - Register Names |
| LVDT/RVDT Measurement Registers | |
| Position Data | Position Data |
| Velocity Data | - |
| Va RMS | - |
| Vb RMS | - |
| Va Vb RMS | - |
| Position B_2W | - |
| Velocity B_2W | - |
| Measured Reference (RMS) | Measured Reference (Excitation) (RMS) |
| Measured Signal (RMS) | Measured Signal (RMS) |
| Measured Frequency (Hz) | Measured Frequency (Hz) |
| Va Detect Value | - |
| Vb Detect Value | - |
| LVDT/RVDT Control Registers | |
| Mode Select | Mode Select |
| LVDT/RVDT Scale | - |
| TR Value | - |
| Bandwidth Select | Bandwidth Select |
| Bandwidth (Hz) | Bandwidth (Hz) |
| Delta Position | Delta Position |
| Initiate Delta Position | Init Delta Angle |
| Channel Status Enable | Status Enable |
| Track/Hold | Track/Hold |
| Inverse Signal Control | - |
| Threshold Programming Registers | |
| Signal Fault Low Threshold/Va Fault High | Signal Loss Threshold |
| Signal Fault High Threshold/Vb Fault High | - * |
| Reference Fault Low Threshold | Reference (Excitation) Loss Threshold |
| Reference Fault High Threshold | - |
| Open Detect Threshold | - |
| Short Detect Threshold | - |
| LVDT/RVDT Test Registers | |
| Test Enabled | Test Enable (D0, D2, D3) |
| Test CBIT Verify | Test D2 Verify |
| UBIT Test Position | Test Position |
| BIT Error Limit | - |
| FIFO Registers | |
| FIFO Buffer Data | FIFO Buffer Data (per channel) |
| FIFO Word Count | FIFO Word Count (per channel) |
| FIFO Almost Empty | - |
| FIFO Low Watermark | FIFO Lo Threshold (per channel) |
| FIFO High Watermark | FIFO Hi Threshold (per channel) |
| FIFO Almost Full | - |
| FIFO Buffer Size | FIFO Number of Samples (per channel) |
| FIFO Buffer Control | FIFO Data Type (per channel) |
| FIFO Sample Rate | FIFO Sample Rate (per channel) |
| FIFO Sample Delay | FIFO Sample Delay (per channel) |
| FIFO Clear | FIFO Clear (per channel) |
| FIFO Trigger Control | FIFO Trigger Mode (per channel) |
| FIFO Software Trigger | - |
| Engineering Scaling Conversions Registers | |
| Enable Floating Point Mode | - |
| Floating Point Offset | - |
| Floating Point Scale | - |
| Floating Point State | - |
| Status and Interrupt Registers | |
| BIT Dynamic Status | BIT Dynamic Status |
| BIT Latched Status | BIT Latched Status |
| BIT Interrupt Enable | BIT Interrupt Enable |
| BIT Set Edge/Level Interrupt | BIT Set Edge/Level Interrupt |
| Signal Fault Low Dynamic Status/Va Fault High Dynamic Status | Signal Loss Dynamic Status |
| Signal Fault Low Latched Status/Va Fault High Latch Status | Signal Loss Latched Status |
| Signal Fault Low Interrupt Enable/Va Fault High Interrupt Enable | Signal Loss Interrupt Enable |
| Signal Fault Low Set Edge/Level Interrupt/ Va Fault High Set Edge/Level Interrupt | Signal Loss Set Edge/Level Interrupt |
| Signal Fault High Dynamic Status/Vb Fault High Dynamic Status | - |
| Signal Fault High Latched Status/Vb Fault High Latched Status | - |
| Signal Fault High Interrupt Enable/Vb Fault High Interrupt Enable | - |
| Signal Fault High Set Edge/Level Interrupt/Vb Fault High Set Edge/Level Interrupt | - |
| Reference Fault Low Dynamic Status | Reference (Excitation) Loss Dynamic Status |
| Reference Fault Low Latched Status | Reference (Excitation) Loss Latched Status |
| Reference Fault Low Interrupt Enable | Reference (Excitation) Loss Interrupt Enable |
| Reference Fault Low Set Edge/Level Interrupt | Reference (Excitation) Loss Set Edge/Level Interrupt |
| Reference Fault High Dynamic Status | - |
| Reference Fault High Latched Status | - |
| Reference Fault High Interrupt Enable | - |
| Reference Fault High Set Edge/Level Interrupt | - |
| Delta Position Dynamic Status | Delta Angle Dynamic Status |
| Delta Position Latched Status | Delta Angle Latched Status |
| Delta Position Interrupt Enable | Delta Angle Interrupt Enable |
| Delta Position Set Edge/Level Interrupt | Delta Angle Set Edge/Level Interrupt |
| FIFO Dynamic Status | - |
| FIFO Latched Status | FIFO Status |
| FIFO Interrupt Enable | - |
| FIFO Set Edge/Level Interrupt | - |
| Open Detect Dynamic Status | - |
| Open Detect Latched Status | - |
| Open Detect Interrupt Enable | - |
| Open Detect Set Edge/Level Interrupt | - |
| Short Detect Dynamic Status | - |
| Short Detect Latched Status | - |
| Short Detect Interrupt Enable | - |
| Short Detect Set Edge/Level Interrupt | - |
| Summary Dynamic Status | - |
| Summary Latched Status | - |
| Summary Interrupt Enable | - |
| Summary Set Edge/Level Interrupt | - |
| Interrupt Vector | - |
| Interrupt Steering | - |
APPENDIX C: PIN-OUT DETAILS
Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals
| Module Signal (Ref Only) | 44-Pin I/O | 50-Pin I/O (Mod Slot 1-J3) | 50-Pin I/O (Mod Slot 2-J4) | 50-Pin I/O (Mod Slot 3-J3) | 50-Pin I/O (Mod Slot 3-J4) | LRDT/LVDT (LDx) |
|---|---|---|---|---|---|---|
| DATIO1 | 2 | 10 | 1 | 2 | CH1_A-Lo | |
| DATIO2 | 24 | 35 | 26 | 27 | CH1_A-Hi | |
| DATIO3 | 3 | 11 | 2 | 3 | CH1_B-Hi | |
| DATIO4 | 25 | 36 | 27 | 28 | CH1_B-Lo | |
| DATIO5 | 5 | 13 | 4 | 5 | CH1-Rhi | |
| DATIO6 | 27 | 38 | 29 | 30 | CH1-Rlo | |
| DATIO7 | 7 | 14 | 5 | 6 | CH2_A-Lo | |
| DATIO8 | 29 | 39 | 30 | 31 | CH2_A-Hi | |
| DATIO9 | 8 | 15 | 6 | 7 | CH2_B-Hi | |
| DATIO10 | 30 | 40 | 31 | 32 | CH2_B-Lo | |
| DATIO11 | 10 | 17 | 8 | 9 | CH2-Rhi | |
| DATIO12 | 32 | 42 | 33 | 34 | CH2-Rlo | |
| DATIO13 | 12 | 18 | 9 | 17 | CH3_A-Lo | |
| DATIO14 | 34 | 43 | 34 | 42 | CH3_A-Hi | |
| DATIO15 | 13 | 19 | 10 | 18 | CH3_B-Hi | |
| DATIO16 | 35 | 44 | 35 | 43 | CH3_B-Lo | |
| DATIO17 | 15 | 21 | 12 | 20 | CH3-Rhi | |
| DATIO18 | 37 | 46 | 37 | 45 | CH3-Rlo | |
| DATIO19 | 17 | 22 | 13 | 21 | CH4_A-Lo | |
| DATIO20 | 39 | 47 | 38 | 46 | CH4_A-Hi | |
| DATIO21 | 18 | 23 | 14 | 22 | CH4_B-Hi | |
| DATIO22 | 40 | 48 | 39 | 47 | CH4_B-Lo | |
| DATIO23 | 20 | 25 | 16 | 24 | CH4-Rhi | |
| DATIO24 | 42 | 50 | 41 | 49 | CH4-Rlo | |
| DATIO25 | 4 | 12 | 3 | 4 | ||
| DATIO26 | 26 | 37 | 28 | 29 | ||
| DATIO27 | 9 | 16 | 7 | 8 | ||
| DATIO28 | 31 | 41 | 32 | 33 | ||
| DATIO29 | 14 | 20 | 11 | 19 | ||
| DATIO30 | 36 | 45 | 36 | 44 | ||
| DATIO31 | 19 | 24 | 15 | 23 | ||
| DATIO32 | 41 | 49 | 40 | 48 | ||
| DATIO33 | 6 | |||||
| DATIO34 | 28 | |||||
| DATIO35 | 11 | |||||
| DATIO36 | 33 | |||||
| DATIO37 | 16 | |||||
| DATIO38 | 38 | |||||
| DATIO39 | 21 | |||||
| DATIO40 | 43 | |||||
| N/A |
LVDT/RVDT HARDWARE BLOCK DIAGRAM
Figure 2. LD1 - LD5 Hardware Block Diagram
STATUS AND INTERRUPTS
Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.
For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.
Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.
Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).
Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.
Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).
Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edge-triggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Interrupt Trigger Types
In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.
Example 1: Fault detection
This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.
Example 2: Threshold detection
This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.
Dynamic and Latched Status Registers Examples
The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.
Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States
No Clearing of Latched Status Clearing of Latched Status (Edge-Triggered) Clearing of Latched Status(Level-Triggered) Time Dynamic Status Latched Status Action Latched Status Action Latched T0 0x0 0x0 Read Latched Register 0x0 Read Latched Register 0x0 T1 0x1 0x1 Read Latched Register 0x1 0x1 T1 0x1 0x1 Write 0x1 to Latched Register Write 0x1 to Latched Register T1 0x1 0x1 0x0 0x1 T2 0x0 0x1 Read Latched Register 0x0 Read Latched Register 0x1 T2 0x0 0x1 Read Latched Register 0x0 Write 0x1 to Latched Register T2 0x0 0x1 Read Latched Register 0x0 0x0 T3 0x2 0x3 Read Latched Register 0x2 Read Latched Register 0x2 T3 0x2 0x3 Write 0x2 to Latched Register Write 0x2 to Latched Register T3 0x2 0x3 0x0 0x2 T4 0x2 0x3 Read Latched Register 0x1 Read Latched Register 0x3 T4 0x2 0x3 Write 0x1 to Latched Register Write 0x3 to Latched Register T4 0x2 0x3 0x0 0x2 T5 0xC 0xF Read Latched Register 0xC Read Latched Register 0xE T5 0xC 0xF Write 0xC to Latched Register Write 0xE to Latched Register T5 0xC 0xF 0x0 0xC T6 0xC 0xF Read Latched Register 0x0 Read Latched 0xC T6 0xC 0xF Read Latched Register 0x0 Write 0xC to Latched Register T6 0xC 0xF Read Latched Register 0x0 0xC T7 0x4 0xF Read Latched Register 0x0 Read Latched Register 0xC T7 0x4 0xF Read Latched Register 0x0 Write 0xC to Latched Register T7 0x4 0xF Read Latched Register 0x0 0x4 T8 0x4 0xF Read Latched Register 0x0 Read Latched Register 0x4 Interrupt Examples
The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.
Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled
Time Latched Status (Edge-Triggered - Clear Multi-Channel) Latched Status (Edge-Triggered - Clear Single Channel) 2+ Latched Status (Level-Triggered - Clear Multi-Channel) Action Latched Action Latched Action Latched T1 (Int 1) Interrupt Generated++``+
Read Latched Registers0x1 Interrupt Generated++``+
Read Latched Registers0x1 Interrupt Generated++``+
Read Latched Registers0x1 T1 (Int 1) Write 0x1 to Latched Register Write 0x1 to Latched Register Write 0x1 to Latched Register T1 (Int 1) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T2.0x1 T3 (Int 2) Interrupt Generated++``+
Read Latched Registers0x2 Interrupt Generated++``+
Read Latched Registers0x2 Interrupt Generated++``+
Read Latched Registers0x2 T3 (Int 2) Write 0x2 to Latched Register Write 0x2 to Latched Register Write 0x2 to Latched Register T3 (Int 2) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T7.0x2 T4 (Int 3) Interrupt Generated++``+
Read Latched Registers0x1 Interrupt Generated++``+
Read Latched Registers0x1 Interrupt Generated++``+
Read Latched Registers0x3 T4 (Int 3) Write 0x1 to Latched Register Write 0x1 to Latched Register Write 0x3 to Latched Register T4 (Int 3) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.0x3 T4 (Int 3) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T7.0x2 T6 (Int 4) Interrupt Generated++``+
Read Latched Registers0xC Interrupt Generated++``+
Read Latched Registers0xC Interrupt Generated++``+
Read Latched Registers0xE T6 (Int 4) Write 0xC to Latched Register Write 0x4 to Latched Register Write 0xE to Latched Register T6 (Int 4) 0x0 Interrupt re-triggers++``+
Write 0x8 to Latched Register0x8 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.0xE T6 (Int 4) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.0xC T6 (Int 4) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.0x4 REVISION HISTORY
Motherboard Manual - Status and Interrupts Revision History Revision Revision Date Description C 2021-11-30 C08896; Transition manual to docbuilder format - no technical info change. DOCS.NAII REVISIONS
Link to original
Revision Date Description 2026-03-02 Formatting updates to document; no technical changes.
MODULE COMMON REGISTERS
The registers described in this document are common to all NAI Generation 5 modules.
Module Information Registers
The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.
FPGA Version Registers
The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.
FPGA Revision Function: FPGA firmware revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the revision of the board's FPGA Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number
FPGA Compile Timestamp Function: Compile Timestamp for the FPGA firmware. Type: unsigned binary word (32-bit) Data Range: N/A Read/Write: R Initialized Value: Value corresponding to the compile timestamp of the board's FPGA Operational Settings: The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 day (5-bits) month (4-bits) year (6-bits) hr D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 hour (5-bits) minutes (6-bits) seconds (6-bits)
FPGA SerDes Revision Function: FPGA SerDes revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the SerDes revision of the board's FPGA Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number
FPGA Template Revision Function: FPGA Template revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the template revision of the board's FPGA Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number
FPGA Zynq Block Revision Function: FPGA Zynq Block revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the Zynq block revision of the board's FPGA Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number Bare Metal Version Registers
The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.
Bare Metal Revision Function: Bare Metal firmware revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the revision of the board's Bare Metal Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number
Bare Metal Compile Time Function: Provides an ASCII representation of the Date/Time for the Bare Metal compile time. Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit) Data Range: N/A Read/Write: R Initialized Value: Value corresponding to the ASCII representation of the compile time of the board's Bare Metal Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32 Note
little-endian order of ASCII values
Word 1 (Ex. 0x2079614D) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Space (0x20) Month ('y' - 0x79) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Month ('a' - 0x61) Month ('M' - 0x4D) Word 2 (Ex. 0x32203731) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Year ('2' - 0x32) Space (0x20) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Day ('7' - 0x37) Day ('1' - 0x31) Word 3 (Ex. 0x20393130) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Space (0x20) Year ('9' - 0x39) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Year ('1' - 0x31) Year ('0' - 0x30) Word 4 (Ex. 0x31207461) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Hour ('1' - 0x31) Space (0x20) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 'a' (0x74) 't' (0x61) Word 5 (Ex. 0x38333A35) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Minute ('8' - 0x38) Minute ('3' - 0x33) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ':' (0x3A) Hour ('5' - 0x35) Word 6 (Ex. 0x0032333A) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 NULL (0x00) Seconds ('2' - 0x32) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Seconds ('3' - 0x33) ':' (0x3A) FSBL Version Registers
The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).
FSBL Revision Function: FSBL firmware revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the revision of the board's FSBL Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number
FSBL Compile Time Function: Provides an ASCII representation of the Date/Time for the FSBL compile time. Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit) Data Range: N/A Read/Write: R Initialized Value: Value corresponding to the ASCII representation of the Compile Time of the board's FSBL Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32
Note
little-endian order of ASCII values
Word 1 (Ex. 0x2079614D) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Space (0x20) Month ('y' - 0x79) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Month ('a' - 0x61) Month ('M' - 0x4D) Word 2 (Ex. 0x32203731) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Year ('2' - 0x32) Space (0x20) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Day ('7' - 0x37) Day ('1' - 0x31) Word 3 (Ex. 0x20393130) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Space (0x20) Year ('9' - 0x39) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Year ('1' - 0x31) Year ('0' - 0x30) Word 4 (Ex. 0x31207461) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Hour ('1' - 0x31) Space (0x20) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 'a' (0x74) 't' (0x61) Word 5 (Ex. 0x38333A35) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Minute ('8' - 0x38) Minute ('3' - 0x33) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ':' (0x3A) Hour ('5' - 0x35) Word 6 (Ex. 0x0032333A) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 NULL (0x00) Seconds ('2' - 0x32) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Seconds ('3' - 0x33) ':' (0x3A) Module Serial Number Registers
The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.
Interface Board Serial Number Function: Unique 128-bit identifier used to identify the interface board. Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit) Data Range: N/A Read/Write: R Initialized Value: Serial number of the interface board Operational Settings: This register is for information purposes only.
Functional Board Serial Number Function: Unique 128-bit identifier used to identify the functional board. Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit) Data Range: N/A Read/Write: R Initialized Value: Serial number of the functional board Operational Settings: This register is for information purposes only.
Module Capability Function: Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 0107 Read/Write: R Initialized Value: 0x0000 0107 Operational Settings: A “1” in the bit associated with the capability indicates that it is supported.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 Flt-Pt 0 0 0 0 0 Pack FIFO Blk Blk
Module Memory Map Revision Function: Module Memory Map revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the Module Memory Map Revision Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number Module Measurement Registers
The registers in this section provide module temperature measurement information.
Temperature Readings Registers
The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.
Interface Board Current Temperature Function: Measured PCB and Zynq Core temperatures on Interface Board. Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R Initialized Value: Value corresponding to the measured PCB and Zynq core temperatures based on the table below Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PCB Temperature Zynq Core Temperature
Functional Board Current Temperature Function: Measured PCB temperature on Functional Board. Type: signed byte (8-bits) for PCB Data Range: 0x0000 0000 to 0x0000 00FF Read/Write: R Initialized Value: Value corresponding to the measured PCB on the table below Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 PCB Temperature
Interface Board Maximum Temperature Function: Maximum PCB and Zynq Core temperatures on Interface Board since power-on. Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R Initialized Value: Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PCB Temperature Zynq Core Temperature
Interface Board Minimum Temperature Function: Minimum PCB and Zynq Core temperatures on Interface Board since power-on. Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R Initialized Value: Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PCB Temperature Zynq Core Temperature
Functional Board Maximum Temperature Function: Maximum PCB temperature on Functional Board since power-on. Type: signed byte (8-bits) for PCB Data Range: 0x0000 0000 to 0x0000 00FF Read/Write: R Initialized Value: Value corresponding to the measured PCB on the table below Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 PCB Temperature
Functional Board Minimum Temperature Function: Minimum PCB temperature on Functional Board since power-on. Type: signed byte (8-bits) for PCB Data Range: 0x0000 0000 to 0x0000 00FF Read/Write: R Initialized Value: Value corresponding to the measured PCB on the table below Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 PCB Temperature Higher Precision Temperature Readings Registers
These registers provide higher precision readings of the current Zynq and PCB temperatures.
Higher Precision Zynq Core Temperature Function: Higher precision measured Zynq Core temperature on Interface Board. Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Measured Zynq Core temperature on Interface Board Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Signed Integer Part of Temperature D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Fractional Part of Temperature
Higher Precision Interface PCB Temperature Function: Higher precision measured Interface PCB temperature. Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Measured Interface PCB temperature Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Signed Integer Part of Temperature D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Fractional Part of Temperature
Higher Precision Functional PCB Temperature Function: Higher precision measured Functional PCB temperature. Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Measured Functional PCB temperature Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Signed Integer Part of Temperature D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Fractional Part of Temperature Module Health Monitoring Registers
The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.
Module Sensor Summary Status Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds. Type: unsigned binary word (32-bits) Data Range: See table below Read/Write: R Initialized Value: 0 Operational Settings: This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.
Bit(s) Sensor D31:D6 Reserved D5 Functional Board PCB Temperature D4 Interface Board PCB Temperature D3:D0 Reserved Module Sensor Registers
The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.
Sensor Threshold Status Function: Reflects which threshold has been crossed Type: unsigned binary word (32-bits) Data Range: See table below Read/Write: R Initialized Value: 0 Operational Settings: The associated bit is set when the sensor reading exceed the corresponding threshold settings.
Bit(s) Description D31:D4 Reserved D3 Exceeded Upper Critical Threshold D2 Exceeded Upper Warning Threshold D1 Exceeded Lower Critical Threshold D0 Exceeded Lower Warning Threshold
Sensor Current Reading Function: Reflects current reading of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R Initialized Value: N/A Operational Settings: The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Minimum Reading Function: Reflects minimum value of temperature sensor since power up Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R Initialized Value: N/A Operational Settings: The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Maximum Reading Function: Reflects maximum value of temperature sensor since power up Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R Initialized Value: N/A Operational Settings: The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Lower Warning Threshold Function: Reflects lower warning threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default lower warning threshold (value dependent on specific sensor) Operational Settings: The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.
Sensor Lower Critical Threshold Function: Reflects lower critical threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default lower critical threshold (value dependent on specific sensor) Operational Settings: The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.
Sensor Upper Warning Threshold Function: Reflects upper warning threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default upper warning threshold (value dependent on specific sensor) Operational Settings: The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.
Sensor Upper Critical Threshold Function: Reflects upper critical threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default upper critical threshold (value dependent on specific sensor) Operational Settings: The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius. FUNCTION REGISTER MAP
KEY
Configuration/Control Measurement/Status/Board Information
MODULE INFORMATION REGISTERS OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS 0x003C FPGA Revision R 0x0074 Bare Metal Revision R 0x0030 FPGA Compile Timestamp R 0x0080 Bare Metal Compile Time (Bit 0-31) R 0x0034 FPGA SerDes Revision R 0x0084 Bare Metal Compile Time (Bit 32-63) R 0x0038 FPGA Template Revision R 0x0088 Bare Metal Compile Time (Bit 64-95) R 0x0040 FPGA Zynq Block Revision R 0x008C Bare Metal Compile Time (Bit 96-127) R 0x0090 Bare Metal Compile Time (Bit 128-159) R 0x0094 Bare Metal Compile Time (Bit 160-191) R 0x007C FSBL Revision R 0x00B0 FSBL Compile Time (Bit 0-31) R 0x00B4 FSBL Compile Time (Bit 32-63) R 0x00B8 FSBL Compile Time (Bit 64-95) R 0x00BC FSBL Compile Time (Bit 96-127) R 0x00C0 FSBL Compile Time (Bit 128-159) R 0x00C4 FSBL Compile Time (Bit 160-191) R 0x0000 Interface Board Serial Number (Bit 0-31) R 0x0010 Functional Board Serial Number (Bit 0-31) R 0x0034 Interface Board Serial Number (Bit 32-63) R 0x0014 Functional Board Serial Number (Bit 32-63) R 0x0008 Interface Board Serial Number (Bit 64-95) R 0x0018 Functional Board Serial Number (Bit 64-95) R 0x000C Interface Board Serial Number (Bit 96-127) R 0x001C Functional Board Serial Number (Bit 96-127) R 0x0070 Module Capability R 0x01FC Module Memory Map Revision R MODULE MEASUREMENTS REGISTERS OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS 0x0200 Interface Board PCB/Zynq Current Temp R 0x0208 Functional Board PCB Current Temp R 0x0218 Interface Board PCB/Zynq Max Temp R 0x0228 Functional Board PCB Max Temp R 0x0220 Interface Board PCB/Zynq Min Temp R 0x0230 Functional Board PCB Min Temp R 0x02C0 Higher Precision Zynq Core Temperature R 0x02C4 Higher Precision Interface PCB Temperature R 0x02E0 Higher Precision Functional PCB Temperature R MODULE HEALTH MONITORING REGISTERS OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS 0x07F8 Module Sensor Summary Status R  REVISION HISTORY
Motherboard Manual - Module Common Registers Revision History Revision Revision Date Description C 2023-08-11 ECO C10649, initial release of module common registers manual. C1 2024-05-15 ECO C11522, removed Zynq Core/Aux/DDR Voltage register descriptions from Module Measurement Registers. Pg.16, updated Module Sensor Summary Status register to add PS references; updated Bit Table to change voltage/current bits to 'reserved'. Pg.16, updated Module/Power Supply Sensor Registers description to better describe register functionality and to add figure. Pg.17, added 'Exceeded' to threshold bit descriptions. Pg.17-18, removed voltage/current references from sensor descriptions. Pg.20, removed Zynq Core/Aux/DDR Voltage register offsets from Module Measurement Registers. Pg.20, updated Module Health Monitoring Registers offset tables. C2 2024-07-10 ECO C11701, pg.16, updated Module Sensor Summary Status register to remove PS references;updated Bit Table to change PS temperature bits to 'reserved'. Pg.16, updated Module SensorRegisters description to remove PS references. Pg.20, updated Module Health MonitoringRegisters offset tables to remove PS temperature register offsets. DOCS.NAII REVISIONS
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Revision Date Description 2025-11-05 Corrected register offsets for Interface Board Min Temp and Function Board Min & Max Temps. 2026-03-02 Formatting updates to document; no technical changes.
Revision History
| Module Manual - LD1-LD5 Revision History | Revision | Revision Date |
|---|---|---|
| Description | C | 2022-10-24 |
| ECO C09737, transition to docbuilder format. Replace ‘Specifications’ with ‘Data Sheet’. Pg.8, removed automatic bandwidth shifting bullet. Pg.11, removed ‘logically ORed together and’ from BIT/Diagnostic Capability. Pg.12, updated CBIT test timing. Pg.12, updated 2nd IBIT note to ‘expressed as an IEEE-754 floating point number’. Pg.12, removed Short detects reference from LVDT/RVDT Threshold Programming. Pg.20, removed ‘to-do’ reference from Measured Signal (RMS) & Va+Vb RMS. op settings. Pg.27, updated Va & Vb Fault High Threshold initial values. Pg.27/32/33/38/47/51, added contact factory note. Added Appendix C: Pin-Out Details. |
| Module Manual - Status and Interrupts Revision History | Revision | Revision Date |
|---|---|---|
| Description | C | 2021-11-30 |
| C08896; Transition manual to docbuilder format - no technical info change. |
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