INTRODUCTION
This manual provides information about the North Atlantic Industries, Inc. (NAI) 68CB6 3U OpenVPX Multifunction I/O Board. The 68CB6 is a 3U OpenVPX multifunction I/O and communications board that is designed with six inboard functions providing 10 different I/O, measurement and communications functions:
An inboard-optimized combination function (CF) module that provides:
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Twelve channels of discrete input
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Two channels of CAN bus input featuring flexible data (FD) rate, which extends data rate speed by a factor of 8 (64 bytes) of the arbitration bit rate.
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Two channels of digital-to-analog output
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Two channels of AC/DC analog-to-digital input
Two channels of Linear Variable Differential Transformation (LVDT) to digital measurement, plus two channels of AC Reference output (one for each channel)
Eight channels that can be individually programmed as either a Thermocouple (TC) or a Resistance Temperature Detector (RTD) measurement interface
Sixteen channels with 16-bit, individual Successive Approximation Register (SAR) analog-to-digital (A/D) converters for each channel
Five channels of full-bridge Strain Gauge (SG) measurement
Four channels of Chip Detect (CD) measurement with Fuzz Burn capability
SOFTWARE SUPPORT
The ENAIBL Software Support Kit (SSK) is supplied with all system platform based board level products. This platform’s SSK contents include html format help documentation which defines board specific library functions and their respective parameter requirements. A board specific library and its source code is provided (module level ‘C’ and header files) to facilitate function implementation independent of user operating system (O/S). Portability files are provided to identify Board Support Package (BSP) dependent functions and help port code to other common system BSPs. With the use of the provided help documentation, these libraries are easily ported to any 32-bit O/S such as RTOS or Linux.
The latest version of a board specific SSK can be downloaded from our website www.naii.com in the software downloads section. A Quick-Start Software Manual is also available for download where the SSK contents are detailed, Quick-Start Instructions provided and GUI applications are described therein. For other operating system support, contact factory.
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Specifications
General for the Motherboard
Signal Logic Level: Supports LVDS PCIe ver. 3.0 bus (x1) Power (Motherboard): +12 VDC @ <1 A (est. typical)
+3.3V_AUX @ <100 mA (typical)
Then add power for each individual moduleTemperature, Operating: “C” =0° C to +70° C, “H” =-40° C to +85° C (see part number) Storage Temperature: -55° C to +105° C Temperature Cycling: Each board is cycled from -40° C to +85° C for option “H” General size: Height: 3.94” / 100 mm (3U) Width: 1.0” / 25.4 mm (5 HP) air cooled front panel options Depth: 6.3“ / 160 mm deep Weight: 21.5 oz. (610 g) unpopulated (approx.) (convection or conduction cooled)
>> then add weight for each module (typically 1.5 oz. (42 g) each)Specifications are subject to change without notice.
Environmental
Unless otherwise specified, the following table outlines the general Environmental Specifications design guidelines for board level products of North Atlantic Industries. All our cPCI, VME and OpenVPX boards are designed for either air or conduction cooling. All boards also incorporate appropriate stiffening to ensure performance during shock and vibration but also to assure reliable operation (lower fatigue stresses) over the service life of the product.
Parameters Level 1 / Commercial-AC (Air Cooled) 2 / Rugged-AC (Air Cooled) 3 / Rugged-CC (Conduction Cooled) Temperature – Operating 0° C to 70° C, Ambient -40° C to 85° C, Ambient -40° C to 85° C, at wedge lock thermal interface Temperature - Storage -40° C to 85° C -55° C to 105° C -55° C to 105° C Humidity – Operating 0 to 95%, non-condensing 0 to 95%, non-condensing 0 to 95%, non-condensing Humidity - Storage 0 to 95%, non-condensing 0 to 95%, non-condensing 0 to 95%, non-condensing Vibration – Sine 2 g peak, 15 Hz – 2 kHz 6 g peak, 15 Hz – 2 kHz 10 g peak, 15 Hz – 2 kHz Vibration – Random .002 g /Hz, 15 Hz – 2 kHz 0.04 g /Hz, 15 Hz – 2 kHz 0.1 g /Hz, 15 Hz – 2 kHz Shock 20 g peak, half-sine, 11 ms 30 g peak, half-sine 11 ms 40 g peak, half-sine, 11 ms Low Pressure Up to 15,000 ft. Up to 50,000 ft. Up to 50,000 ft. Notes:
A. Based on sweep duration of ten minutes per axis on each of the three mutually perpendicular axes. B. Displacement limited to 0.10 D.A. from 15 to 44 Hz. C. Displacement limited to 0.436 D.A. from 15 to 21 Hz. D. 60 minutes per axis on each of the three mutually perpendicular axes. E. Per MIL-STD-810G, Method 5.14.6 Procedure I, Fig.514.6C-6 Category 7 tailored (11.65 Grms): 15 Hz – 2 kHz; ASD (PSD) at 0.04 g2/Hz between 15 Hz - 150 Hz, increasing @ 4 dB/octave from 0.04 g2/Hz to 0.1 g /Hz between 150 Hz – 300 Hz, 0.1 g2/Hz between 300 Hz - 1000 Hz, decreasing @ 6 dB/octave from 0.1 g2/Hz to 0.025 g2/Hz between 1000 Hz – 2000 Hz. Three hits per direction per axis (total of 18 hits). F. Three hits per direction per axis (total of 18 hits). G. For altitudes higher than 50,000 ft., contact NAI. H. High temperature operation requires 350 lfm minimum air flow across cover/heatsink (module dependent). I. High temperature operation requires 600 lfm minimum air flow across cover/heatsink (module dependent).
Specifications subject to change without notice
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REGISTER MEMORY MAP ADDRESSING
The register map address consists of the following:
• cPCI/PCIe BAR or Base Address for the Board • Module Slot Base Address • Function Offset Address
Board Base Address
The table below lists the BAR used for access to the motherboard and module registers. The second BAR is used internally for motherboard and module firmware updates. The other cPCI/PCIe BARs not listed are not used.
NAI Boards Device ID Bus Motherboard and Module Register Access Motherboard and Module Firmware Updates Slave Boards 75G5 0x7581 cPCI BAR 0 Size: Module Dependent (minimum 64K Bytes) BAR 1 Size: 1M Bytes 79G5 0x7981 PCIe BAR 1 Size: Module Dependent (minimum 64K Bytes) BAR 2 Size: 1M Bytes 68G5/68G5P/68DT1/68CB6 0x6881 PCIe 68SDP 0x6805 PCIe 67G6 0x6781 PCIe 64G5 N/A VME Slave Window 1 Size: 8M Bytes Addressing: Geographical Addressing or DIP Switches on board. Slave Window 2 Size: 8M Bytes 74SD5 0x7405 PMC 64K Bytes N/A Controller/Master Boards 75G5/75ARM1 0x7581 cPCI BAR 0 Size: Module Dependent (minimum 64K bytes) BAR 1 Size: 1M bytes 75INT2 0x7584 cPCI BAR 1 Size: Module Dependent (minimum 64K bytes) BAR 2 Size: 1M Bytes 75PPC1 0x7584 cPCI 68ARM1 0x6884 PCIe 68ARM2 0x6886 PCIe 68PPC2 0x6884 PCIe 67PPC2 0x6784 PCIe 64ARM1 N/A VME Slave Window 1 Size: 8M Bytes Slave Window 2 Size: 8M Bytes NANO NIU1A N/A N/A Direct Memory Access Internal Direct Memory Access NIU2A N/A N/A Module Slot and Function Addresses
The memory map for the modules are dependent on the types of modules on the board and the order in which the modules are installed on the board as well as the firmware installed on the motherboard. The function modules are enumerated allowing for dynamic memory space allocation and therefore the “start” address of the module function register area is factory pre-defined (and read from) the Module Address register. Refer to Figure 1 for an example.
Motherboard Registers:
Read/Write access to the motherboard registers starts with the base address for the board and then the motherboard base offset address.
For example, to address Module Slot 1 Start Address register (i.e. register address = 0x0400):
- Start with the base address for the board.
- Add the motherbase register address offset.
Motherboard Address = Base Address
Motherboard Address Offset= 0x0000 0400 0x0000 0000 + 0x0400 Module Registers:
Read/Write access to the Function module’s registers start with the base address of the board. Add the “content” for the Module Start Address and then, add the specific module function register offset.
For example, to address an appropriate/specific function module with a register offset:
- Start with the base address for the board.
- Add the value (contents) from the module base address offset register (contents/value of Motherboard Memory register for Module 1 (i.e., @ 0x0400) = 0x4000.
- Then add the specific module function Register Offset of interest (i.e., A/D Reading Ch 1 @ 0x1000)
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(Function Specific) Address = Base Address + Module Base Address Offset + Function Register Offset = 0x0000 5000 0x0000 0000 0x4000 0x1000
MOTHERBOARD REGISTER DESCRIPTIONS
Module Information Registers
The Module Slot Address, Module Slot Size and Module Slot ID provide information about the modules detected on the board.
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Module Slot Address Function: Specifies the Base Address for the module in the specific slot position. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Based on board's module configuration. Operational Settings: 0x0000 0000 indicates no Module found.
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Module Slot Size Function: Specifies the Memory Size (in bytes) allocated for the module in the specific slot position. Type: unsigned binary word (32-bit) Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Assigned by factory for the module. Operational Settings: 0x0000 0000 indicates no Module found.
Module Slot ID Function: Specifies the Model ID for the module in the specified slot position. Type: 4-character ASCII string Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Assigned by factory for the module. Operational Settings: The Module ID is formatted as four ASCII bytes: three characters followed by a space. Module IDs are in little-endian order with a single space following the first three characters. For example, 'TL1' is '1LT', 'SC1' is '1CS' and so forth. Example below is for “TL1” (MSB justified). All value of 0000 0000 indicates no Module found. Link to original
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 ASCII Character (ex: 'T' - 0x54) ASCII Character (ex: 'L' - 0x4C) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ASCII Character (ex: '1' - 0x31) ASCII Space (' ' - 0x20)
Hardware Information Registers
The registers identified in this section provide information about the board’s hardware.
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Product Serial Number Function: Specifies the Board Serial Number. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Serial number assigned by factory for the board. Operational Settings: N/A
Platform
Function: Specifies the Board Platform Identifier. Values are for the ASCII characters for the NAI valid platforms (Identifiers).
Type: 4-character ASCII string
Data Range: See table below.
Read/Write: R
Initialized Value: ASCII code is for the Platform Identifier of the board
Operational Settings: NAI platform for this board is shown below:
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NAI Platform Platform Identifier ASCII Binary Values (Note: little-endian order of ascii values) 6U VME 64 0x0000 3436 6U VPX 67 0x0000 3736 3U VPX 68 0x0000 3836 3U VPX 67 0x0000 3736 ARM N/A 0x004D 5241 cPCI 75 0x0000 3537 NIU 00 0x0000 0303
Model
Function: Specifies the Board Model Identifier. Values are for the ASCII characters for the NAI valid models.
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Initialized Value: ASCII code is for the Model Identifier of the board
Operational Settings: Examples of NAI models and the associated values for these models are shown below:
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NAI Model ASCII Binary Values (Note: little-endian order of ascii values) ARM 0x004D 5241 G 0x0000 0047 PPC 0x0043 5050 CB 0x0000 4243 DT 0x0000 5444 INT 0x0054 4E49 NIU 0x0055 494E
Generation
Function: Specifies the Board Generation. Identifier values are for the ASCII characters for the NAI valid generation identifiers.
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Initialized Value: ASCII code is for the Generation Identifier of the board
Operational Settings: Examples of NAI generations and the associated values for these generations are shown below:
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NAI Generation ASCII Binary Values (Note: little-endian order of ascii values) 1 0x0000 0031 2 0x0000 0032 3E 0x0000 4533 5 0x0000 0035 6 0x0000 0036
Ethernet Interface Count/Processor Count
Function: Specifies the Ethernet Interface Count and Processor Count
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Operational Settings:
Ethernet Interface Count - Indicates the number of Ethernet interfaces on the product motherboard.
Processor Count - Indicates the number of unique processor types on the motherboard
Ethernet Interface/Processor Count
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D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Ethernet Interface Count (0x0002) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Processor Count (0x0001)
ARM Platform Type/Maximum Module Slot Count
Function: Specifies the ARM Platform Type and Maximum Module Slot Count.
Type: unsigned binary word (32-bit)
Data Range: See table below.
Read/Write: R
Operational Settings:
ARM Platform Type – UltraScale+ = 3
ARM Platform Type/Maximum Module Slot Count
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D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 16 ARM Platform Type = 0x0003 (UltraScale) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Maximum Module Slot = 0x0003 (example)
Processor Operating System Registers
The registers in this section provide information about the Operating System that is running on the host processor on the motherboard. For boards that have more than one processor (ex. 75PPC1, 75INT2, 68PPC2, etc), the host processor would be the Power-PC or Intel processor.
ARM Processor Platform
Function: Specifies the ARM Processor on the motherboard. Values are for the ASCII characters for the NAI host processor platforms specified by the Operating System. Type: 8-character ASCII string - Two (2) unsigned binary word (32-bit) Data Range: N/A Read/Write: R Initialized Value: ASCII code is for the Host Platform Identifier of the board. Operational Settings: Valid NAI platforms based on Operating System loaded to host processor. Link to original
Processor Platform (Note: 8-character ASCII string) (“aarch64”) Word 1 (0x6372 6161 = “craa”) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 'c' (0x63) 'r' (0x72) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 'a' (0x61) 'a' (0x61) Word 2 (0x0034 3668 = “ 46h”) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 null (0x00) '4' (0x34) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 '6' (0x36) 'h' (0x68)
Processor Operating System
Function: Specifies the Operating System installed for the host processor. Values are for the ASCII characters for the NAI supported operating systems. Type: 12-character ASCII string - Three (3) unsigned binary word (32-bit) Data Range: N/A Read/Write: R Operational Settings: ASCII, 12 characters; ('Linux', 'VxWorks', 'RTOS', ...) Link to original
Processor Platform (Note: 12-character ASCII string) (“Linux”) Word 1 (0x756E 694C = “uniL”) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 'u' (0x75) 'n' (0x6E) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 'i' (0x69) 'L' (0x4C) Word 2 (0x0000 0078 = “ x”) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 null (0x00) null (0x00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 null (0x00) null (0x00) Word 3 (0x0000 0000 = “ ”) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 null (0x00) null (0x00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 null (0x00) null (0x00)
Motherboard Firmware Information Registers
The registers in this section provide information on the revision of the firmware installed on the motherboard.
Motherboard Core (MBCore) Firmware Version Function: Specifies the Version of the NAI factory provided Motherboard Core Application installed on the board. Type: Two (2) unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Operational Settings: The motherboard firmware version consists of four components: Major, Minor, Minor 2 and Minor 3. Link to original
Motherboard Core Firmware Version (Note: little-endian order in register) (ex. 4.7.0.0) Word 1 (Ex. 0007 0004 = 4.7 (Major.Minor) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Minor (ex: 0x0007 = 7) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Major (ex: 0x0004 = 4) Word 2 (Ex. 0x0000 0000 = 0000 = 0.0 (Minor2.Minor3)) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Minor 3 (ex: 0x000 = 0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor 2 (ex: 0x000 = 0)
Motherboard Firmware Build Time/Date Function: Specifies the Build Date/Time of the NAI factory provided Motherboard Core Application installed on the board. Type: Two (2) unsigned binary word (32-bit) Data Range: N/A Read/Write: R Operational Settings: The motherboard firmware time consists of the Build Date and Build Time. NOTE: On some builds the the Date/Time fields are fixed to 0000 0000 to maintain binary consistency across builds. Link to original
Motherboard Firmware Build Time (Note: little-endian order in register) Word 1 - Build Date (ex. 0x030C 07E2 = 2018-12-03) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Day (ex: 0x03 = 3) Month (ex: 0x0C = 12) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Year (ex: 0x07E2 = 2018) Word 2 - Build Time (ex. 0x001B 3B0A = 10:59:27) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 null (0x00) Seconds (ex: 0x1B = 27) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minutes (ex: 0x3B = 59) Hours (ex: 0x0A = 10)
Motherboard FPGA Firmware Version
Function: Specifies the Version of the NAI factory provided Motherboard FPGA installed on the board. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Operational Settings: The motherboard FPGA firmware version consists of two components: Major, Minor. Link to original
Motherboard FPGA Firmware Version (ex. 0x0005 0008 = 5.8) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major (ex: 0x0005 = 5) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor (ex: 0x0008 = 8)
Motherboard FPGA Compile Date/Time
Function: Specifies the Compile Date/Time of the NAI factory provided Motherboard FPGA installed on the board. Type: unsigned binary word (32-bit) Data Range: N/A Read/Write: R Operational Settings: The motherboard firmware time consists of the Build Date and Time in the following format: Link to original
Motherboard FPGA Compile Time (ex. 0xD12A 01B8 = 02/26/21 00:06:56) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Day (D31:D27) Month (D26:D23) Year (D22:D17) ex. 0xD ex. 0x1 0x2 0xA 1 1 0 1 0 0 1 0 0 0 1 0 1 0 1 1 Day = 0x1A = 26 Month = 0x2 = 2 Year = 0x15 = 21 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hour (D16:D12) Minutes (D11:D6) Seconds (D5:D0) ex. 0x0 ex. 0x1 ex. 0xB ex. 0x8 Hour = 0x00 = 0 Minutes = 0x06 = 06 Seconds = 0x38 = 56
Motherboard Monitoring Registers
The registers in this provide motherboard voltage and temperature measurement information.
UltraScale Core Voltage
Function: Specifies the Measured UltraScale Core Voltage.
Type: unsigned word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Measured UltraScale Core Voltage (based on the conversion below)
Operational Settings: The upper 16-bits are the Integer part of the Voltage, and the lower 16-bits is the Fractional part of the Voltage. For example, if the register contains the value 0x0000 0342, this represents 0.834 Volts.
UltraScale Core Voltage
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D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Integer part of Voltage D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Fractional part of Voltage
UltraScale Aux Voltage
Function: Specifies the Measured UltraScale Aux Voltage.
Type: unsigned word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Measured UltraScale Aux Voltage (based on the conversion below)
Operational Settings: The upper 16-bits are the Integer part of the Voltage, and the lower 16-bits is the Fractional part of the Voltage. For example, if the register contains the value 0x0001 0317, this represents 1.791 Volts.
UltraScale Aux Voltage
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D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Integer part of Voltage D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Fractional part of Voltage
Temperature Readings Register
The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) for the processor and PCB for UltraScale processor, and Host and Slave processors measurements for boards that have these additional processors.
Function: Specifies the Measured Temperatures on Motherboard.
Type: signed byte (8-bits) for each temperature reading – Six (6) 32-bit words
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the measured temperatures based on the table below.
Operational Settings: The 8-bit temperature readings are signed bytes. For example, if the following register contains the value 0x0000 3B3B:
Example:
Word 1 (Current Host & UltraScale Temperatures)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Host Core Temperature (0x00) (N/A) Host PCB Temperature (0x00) (NA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 UltraScale Core Temperature UltraScale PCB Temperature The values would represent the following temperatures:
Temperature Measurements Data Bits Value Temperature (Celsius) Host Core Temperature D31:D24 0x00 0° (N/A) Host PCB Temperature D23:D16 0x00 0° (N/A) UltraScale Core Temperature D15:D8 0x3B +59° UltraScale PCB Temperature D7:D0 0x3B +59° Temperature Readings
Word 1 (Current Host & UltraScale Temperatures)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Host Core Temperature (0x00) (N/A) Host PCB Temperature (0x00) (NA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 UltraScale Core Temperature UltraScale PCB Temperature Word 2 (Max Host Temperatures & Current Slave Zynq Temperatures)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Max Host Core Temperature (0x00) (N/A) Max Host PCB Temperature (0x00) (N/A) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Slave Zynq Core Temperature (0x00) (N/A) Slave Zynq PCB Temperature (0x00) (N/A) Word 3 (Min Host Temperatures & Max UltraScale Temperatures)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Min Host Core Temperature (0x00) (N/A) Min Host PCB Temperature (0x00) (N/A) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Max UltraScale Core Temperature Max UltraScale PCB Temperature Word 4 (Max Slave Zynq Temperatures)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Max Slave Zynq Core Temperature (0x00) (N/A) Max Slave Zynq PCB Temperature (0x00) (N/A) Word 5 (Min UltraScale Temperatures)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Min UltraScale Core Temperature Min UltraScale PCB Temperature Word 6 (Min Slave Zynq Temperatures)
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D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Min Slave Zynq Core Temperature (0x00) (N/A) Min Slave Zynq PCB Temperature (0x00) (N/A)
Higher Precision Temperature Readings Registers
These registers provide higher precision readings of the current UltraScale Core and PCB temperatures.
Higher Precision UltraScale Core Temperature
Function: Specifies the Higher Precision Measured UltraScale Core temperature on Motherboard Board. Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Measured UltraScale Core temperature on Motherboard Board Operational Settings: The upper 16-bits represent the signed integer part of the temperature, and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents UltraScale Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius. Link to original
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Signed Integer Part of Temperature D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Fractional Part of Temperature
Higher Precision Motherboard PCB Temperature Function: Specifies the Higher Precision Measured Motherboard PCB temperature. Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Measured Motherboard PCB temperature Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius. Link to original
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Signed Integer Part of Temperature D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Fractional Part of Temperature
Ethernet Configuration Registers
The registers in this section provide information about the Ethernet Configuration for the two ports on the board.
Important: Regardless if the board is configured for one or two Ethernet ports, the second IP address cannot be on the same Subnet as the First IP Address. The table below provides examples of valid and invalid IP Addresses and Subnet Mask Addresses.
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First Port (A) IP Address First Port (A) Subnet Mask Second Port (B) IP Address Second Port (B) Subnet Mask Result 192.168.1.5 255.255.255.0 192.168.2.5 255.255.255.0 Good 192.168.1.5 255.255.0.0 192.168.2.5 255.255.0.0 Conflict 192.168.1.5 255.255.0.0 192.168.2.5 255.255.255.0 Conflict 10.0.0.15 255.0.0.0 192.168.1.5 255.255.255.0 Good
Ethernet MAC Address and Ethernet Settings Function: Specifies the Ethernet MAC Address and Ethernet Settings for the Ethernet port. Type: Two (2) unsigned binary word (32-bit) Data Range: See table. Read/Write: R Operational Settings: The Ethernet MAC Address consists of six octets. The Ethernet Settings are defined in table.
Bits Description Values D31:D23 Reserved 0 D22:D21 Duplex 00 = Not Specified, ` 01 = Half Duplex, ` 10 = Full Duplex, + 11 = Reserved D20:D18 Speed 000 = Not Specified, ` 001 = 10 Mbps, ` 010 = 100 Mbps, ` 011 = 1000 Mbps, ` 100 = 2500 Mbps, ` 101 = 10000 Mbps, ` 110 = Reserved, + 111 = Reserved D17 Auto Negotiate 0 = Enabled, + 1 = Disabled D16 Static IP Address 0 = Enabled, + 1 = Disabled Link to original
Ethernet MAC Address and Ethernet Settings (Note: little-endian order in register) Word 1 (Ethernet MAC Address (Octets 1-4)) (ex: aa:bb:cc:dd:ee:ff) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 MAC Address Octet 4 (ex: 0xDD) MAC Address Octet 3 (ex: 0xCC) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MAC Address Octet 2 (ex: 0xBB) MAC Address Octet 1 (ex: 0xAA) Word 2 (Ethernet MAC Address (Octets 5-6) and Ethernet Settings) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Ethernet Settings (See table) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MAC Address Octet 6 (ex: 0xFF) MAC Address Octet 5 (ex: 0xEE)
Ethernet Interface Name Function: Specifies the Ethernet Interface Name for the Ethernet port. Type: 8-character ASCII string Data Range: See table. Read/Write: R Operational Settings: The Ethernet Interface Name (eth0, eth1, etc) for the Ethernet port. Link to original
Ethernet Interface Name (Note: ascii string in register) (ex. “eth0”) Word 1 (Bit 0-31) (ex: 0x3068 7465 = “0hte”) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 ASCII Character (ex: '0' - 0x30) ASCII Character (ex: 'h' - 0x68) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ASCII Character (ex: 't' - 0x74) ASCII Character (ex: 'e' - 0x65) Word 2 (Bit 32-63) (ex: 0x0000 0000) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 ASCII Character (ex: null - 0x00) ASCII Character (ex: null - 0x00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ASCII Character (ex: null - 0x00) ASCII Character (ex: null - 0x00)
Ethernet IPv4 Address Function: Specifies the Ethernet IPv4 Address for the Ethernet port. Type: Three (3) unsigned binary word (32-bit) Data Range: See table. Read/Write: R Operational Settings: The Ethernet IPv4 Address consists of three parts: IPv4 Address, IPv4 Subnet Mask and IPv4 Gateway. Link to original
Ethernet IPv4 Address (Note: little-endian order in register) Word 1 (Ethernet IPv4 Address) (ex: 0x1001 A8C0 = 192.168.1.16) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 IPv4 Address Octet 4 (ex: 0x10 = 16) IPv4 Address Octet 3 (ex: 0x01 = 1) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IPv4 Address Octet 2 (ex: 0xA8 = 168) IPv4 Address Octet 1 (ex: 0xC0 = 192) Word 2 (Ethernet IPv4 Subnet) (ex: 0x00FF FFFF = 255.255.255.0) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 IPv4 Subnet Octet 4 (ex: 0x00 = 0) IPv4 Subnet Octet 3 (ex: 0xFF = 255) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IPv4 Subnet Octet 2 (ex: 0xFF = 255) IPv4 Subnet Octet 1 (ex: 0xFF = 255) Word 3 (Ethernet IPv4 Gateway) (ex: 0x0101 A8C0 = 192.168.1.1) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 IPv4 Gateway Octet 4 (ex: 0x01 = 1) IPv4 Gateway Octet 3 (ex: 0x01 = 1) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IPv4 Gateway Octet 2 (ex: 0xA8 = 168) IPv4 Gateway Octet 1 (ex: 0xC0 = 192)
Ethernet IPv6 Address Function: Specifies the Ethernet IPv6 Address for the Ethernet port. Type: Five (5) unsigned binary word (32-bit) Data Range: See table. Read/Write: R Operational Settings: The IPv6 Prefix length indicates the network portion of an IPv6 address using the following format: IPv6 address/prefix length ` Prefix length can range from 0 to 128 ` * Typical prefix length is 64 The following is an illustration of IPv6 addressing with IPv6 Prefix length of 64.
64 bits 64 bits Prefix Interface ID Prefix 1 Prefix 2 Prefix 3 Subnet ID Interface ID 1 Interface ID 2 Interface ID 3 Interface ID 4 Example: 2002:c0a8:101:0:7c99:d118:9058:1235/64 2002 C0A8 0101 0000 7C99 D118 9058 1235 Link to original
Ethernet IPv6 Address (Note: little-endian order within 32-bit and 16-bit words in register) (ex. IPv6 Address: 2002:c0a8:201:0:7c99:d118:9058:1235 IPv6 Prefix: 64) Word 1 (Ethernet IPv6 Address (Prefix 1-2)) (ex:0xA8C0 0220 = 2002 C0A8) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Prefix 2 (ex: 0xA8C0 = C0A8) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Prefix 1 (ex: 0x0220 = 2002) Word 2 (Ethernet IPv6 Address (Prefix 3/Subnet ID)) + (ex:0x000 0101 = 0101 0000) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Subnet ID (ex: 0x0000 = 0000) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Prefix 3 (ex: 0x0101 = 0101) Word 3 (Ethernet IPv6 Address (Interface ID 1-2)) + (ex: 0x18D1 997C = 7C99 D118) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Interface ID 2 (ex: 0x18D1 = D118) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Interface ID 1 (ex: 0x997C = 7C99) Word 4 (Ethernet IPv6 Address (Interface ID 3-4)) + (ex: 0x3512 5890 = 9058 1235) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Interface ID 4 (ex: 0x3512 = 1235) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Interface ID 3 (ex: 0x5890 = 9058) Word 5 (Ethernet IPv6 Prefix Length) + (ex:0x0000 0040) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Prefix Length (ex: 0x0040 = 64)
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
Interrupt Vector Function: Set an identifier for the interrupt. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R/W Initialized Value: 0 Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering Function: Sets where to direct the interrupt. Type: unsigned binary word (32-bit) Data Range: See table Read/Write: R/W Initialized Value: 0 Operational Settings: When an interrupt occurs, the interrupt is sent as specified: Link to original
Direct Interrupt to VME 1 Direct Interrupt to ARM Processor (via SerDes) +
(Custom App on ARM or NAI Ethernet Listener App)2 Direct Interrupt to PCIe Bus 5 Direct Interrupt to cPCI Bus 6
Motherboard Health Monitoring Registers
The registers in this section provide motherboard voltage, current and temperature measurement information.
Motherboard Sensor Summary Alarm Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds. Type: unsigned binary word (32-bits) Data Range: See table below Read/Write: R Initialized Value: 0 Operational Settings: This register provides a summary for motherboard sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event. Link to original
Bit(s) Sensor D31:D5 Reserved D4 Motherboard PCB Temperature D3 Zynq Core Temperature D2:D0 Reserved
Motherboard Sensor Registers
The registers listed in this section apply to each module sensor listed for the Motherboard Sensor Summary Status register.
Sensor Threshold Status Function: Reflects which threshold has been crossed Type: unsigned binary word (32-bits) Data Range: See table below Read/Write: R Initialized Value: 0 Operational Settings: The associated bit is set when the sensor reading exceed the corresponding threshold settings. Link to original
Bit(s) Description D31:D4 Reserved D3 Exceeded Upper Critical Threshold D2 Exceeded Upper Warning Threshold D1 Exceeded Lower Critical Threshold D0 Exceeded Lower Warning Threshold
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Sensor Current Reading Function: Reflects current reading of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R Initialized Value: N/A Operational Settings: The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
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Sensor Minimum Reading Function: Reflects minimum value of temperature sensor since power up Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R Initialized Value: N/A Operational Settings: The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
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Sensor Maximum Reading Function: Reflects maximum value of temperature sensor since power up Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R Initialized Value: N/A Operational Settings: The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
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Sensor Lower Warning Threshold Function: Reflects lower warning threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default lower warning threshold (value dependent on specific sensor) Operational Settings: The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.
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Sensor Lower Critical Threshold Function: Reflects lower critical threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default lower critical threshold (value dependent on specific sensor) Operational Settings: The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.
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Sensor Upper Warning Threshold Function: Reflects upper warning threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default upper warning threshold (value dependent on specific sensor) Operational Settings: The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.
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Sensor Upper Critical Threshold Function: Reflects upper critical threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default upper critical threshold (value dependent on specific sensor) Operational Settings: The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.
Module Health Monitoring Registers
Module BIT Status
Function: Provides the ability to monitor the individual Module BIT Status. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Operational Settings: The Module BIT Status registers provide the ability to monitor individual Module BIT results as Latched and current value. A 1 is any bit field indicates BIT failure for the Module in that slot. Link to original
Bit(s) Description D31:D20 Reserved D19 Module Slot 3 BIT Failure (current value) D18 Module Slot 2 BIT Failure (current value) D17 Module Slot 1 BIT Failure (current value) D16 Reserved D15:D4 Reserved D3 Module Slot 3 BIT Failure - Latched D2 Module Slot 2 BIT Failure - Latched D1 Module Slot 1 BIT Failure - Latched D0 Reserved
Scratchpad Area
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Scratchpad Area Function: Registers reserved as scratch pad for customer use. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R/W Operational Settings: This area in memory is reserved for customer use.
Key: Bold Underline = Measurement/Status/Board Information Bold Italic = Configuration/Control
Module Information Registers
| 0x0400 | Module Slot 1 Address | R |
|---|---|---|
| 0x0404 | Module Slot 2 Address | R |
| 0x0408 | Module Slot 3 Address | R |
| 0x040C | Module Slot 4 Address | R |
| 0x0410 | Module Slot 5 Address | R |
| 0x0414 | Module Slot 6 Address | R |
| 0x0430 | Module Slot 1 Size | R |
|---|---|---|
| 0x0434 | Module Slot 2 Size | R |
| 0x0438 | Module Slot 3 Size | R |
| 0x043C | Module Slot 4 Size | R |
| 0x0440 | Module Slot 5 Size | R |
| 0x0444 | Module Slot 6 Size | R |
| 0x0460 | Module Slot 1 ID | R |
|---|---|---|
| 0x0464 | Module Slot 2 ID | R |
| 0x0468 | Module Slot 3 ID | R |
| 0x046C | Module Slot 4 ID | R |
| 0x0470 | Module Slot 5 ID | R |
| 0x0474 | Module Slot 6 ID | R |
Hardware Information Registers
| 0x0020 | Product Serial Number | R |
|---|
| 0x0024 | Platform | R |
|---|---|---|
| 0x0028 | Model | R |
| 0x002C | Generation | R |
| 0x0030 | Processor Count/Ethernet Count | R |
|---|---|---|
| 0x0034 | Maximum Module Slot Count/ARM Platform Type | R |
| 0x0038 | Processor Platform (Bit 0-31) | R |
|---|---|---|
| 0x003C | Processor Platform (Bit 32-63) | R |
| 0x0040 | Processor Operating System (Bit 0-31) | R |
|---|---|---|
| 0x0044 | Processor Operating System (Bit 32-63) | R |
| 0x0048 | Processor Operating System (Bit 64-95) | R |
| 0x004C | Processor Operating System Version (Bit 0-31) | R |
|---|---|---|
| 0x0050 | Processor Operating System Version (Bit 32-63) | R |
Motherboard Firmware Information Registers
Motherboard Core Information
| 0x0100 | MB Core Major/Minor Version | R |
|---|---|---|
| 0x0104 | MB Core Minor 2/3 Version | R |
| 0x0108 | MB Core Build Date (Bit 0-31) | R |
| 0x010C | MB Core Build Date (Bit 32-63) | R |
Motherboard FPGA Information
| 0x0270 | MB FPGA Revision | R |
|---|---|---|
| 0x0274 | MB FPGA Compile Date/Time | R |
Motherboard Measurement Registers
| 0x0218 | UltraScale Core Voltage | R |
|---|---|---|
| 0x021C | UltraScale Aux Voltage | R |
Temperature Readings
| 0x0200 | Current Host & UltraScale Temperatures | R |
|---|---|---|
| 0x0204 | Max Host Temperatures & Current Slave Zynq Temp | R |
| 0x0208 | Min Host Temperatures & Max UltraScale Temp | R |
| 0x020C | Max Slave Zynq Temperatures | R |
| 0x0210 | Min UltraScale Temperatures | R |
| 0x0214 | Min Slave Zynq Temperatures | R |
Higher Precision Temperature Readings
| 0x0230 | Current UltraScale Core Temperature | R |
|---|---|---|
| 0x0234 | Current UltraScale PCB Temperature | R |
Ethernet Configuration Registers
| 0x0070 | Ethernet A MAC (Octets 1-4) | R |
|---|---|---|
| 0x0074 | Ethernet A MAC (Octets 5-6)/Misc Settings | R |
| 0x0078 | Ethernet A Interface Name (Bit 0-31) | R |
|---|---|---|
| 0x007C | Ethernet A Interface Name (Bit 32-63) | R |
| 0x0080 | Ethernet A IPv4 Address | R |
|---|---|---|
| 0x0084 | Ethernet A IPv4 Subnet Mask | R |
| 0x0088 | Ethernet A IPv4 Gateway | R |
| 0x008C | Ethernet A IPv6 Address (Prefix 1-2) | R |
|---|---|---|
| 0x0090 | Ethernet A IPv6 Address (Prefix 3/Subnet ID) | R |
| 0x0094 | Ethernet A IPv6 Address (Interface ID 1-2) | R |
| 0x0098 | Ethernet A IPv6 Address (Interface ID 3-4) | R |
| 0x009C | Ethernet A IPv6 Prefix Length | R |
| 0x00A0 | Ethernet B MAC (Octets 1-4) | R |
|---|---|---|
| 0x00A4 | Ethernet B MAC (Octets 5-6)/Misc Settings | R |
| 0x00A8 | Ethernet B Interface Name (Bit 0-31) | R |
|---|---|---|
| 0x00AC | Ethernet B Interface Name (Bit 32-63) | R |
| 0x00B0 | Ethernet B IPv4 Address | R |
|---|---|---|
| 0x00B4 | Ethernet B IPv4 Subnet Mask | R |
| 0x00B8 | Ethernet B IPv4 Gateway | R |
| 0x00BC | Ethernet B IPv6 Address (Prefix 1-2) | R |
|---|---|---|
| 0x00C0 | Ethernet B IPv6 Address (Prefix 3/Subnet ID) | R |
| 0x00C4 | Ethernet B IPv6 Address (Interface ID 1-2) | R |
| 0x00C8 | Ethernet B IPv6 Address (Interface ID 3-4) | R |
| 0x00CC | Ethernet B IPv6 Prefix Length | R |
Interrupt Vector and Steering
| 0x0500 –0x057C | Module 1 Interrupt Vector 1 - 32 | R/W |
|---|---|---|
| 0x0700 –0x077C | Module 2 Interrupt Vector 1 - 32 | R/W |
| 0x0900 –0x097C | Module 3 Interrupt Vector 1 - 32 | R/W |
| 0x0B00 –0x0B7C | Module 4 Interrupt Vector 1 - 32 | R/W |
| 0x0D00 –0x0D7C | Module 5 Interrupt Vector 1 - 32 | R/W |
| 0x0F00 –0x0F7C | Module 6 Interrupt Vector 1 - 32 | R/W |
| 0x0600 –0x067C | Module 1 Interrupt Steering 1 - 32 | R/W |
|---|---|---|
| 0x0800 –0x087C | Module 2 Interrupt Steering 1 - 32 | R/W |
| 0x0A00 –0x0A7C | Module 3 Interrupt Steering 1 - 32 | R/W |
| 0x0C00 –0x0C7C | Module 4 Interrupt Steering 1 - 32 | R/W |
| 0x0E00 –0x0E7C | Module 5 Interrupt Steering 1 - 32 | R/W |
| 0x1000 –0x107C | Module 6 Interrupt Steering 1 - 32 | R/W |
Motherboard Health Monitoring Registers
| 0x20F8 | Motherboard Sensor Summary Status 1 | R |
|---|
Module Health Monitoring Registers
Module BIT Status
| 0x0128 | Module BIT Status (current and latched) | R |
|---|
Scratchpad Area
| 0x3800 –0x3BFF | Scratchpad Registers | R/W |
|---|
INBOARD FUNCTIONAL OVERVIEW
The 68CB6 is a unique configuration of re-packaged NAI COSA® module types embedded and accessed as “inboard” functions. The following sections describe the principle of operation, register descriptions, and register memory map for each of these specific functions.
COMBINATION FUNCTION (CF1) MODULE - DISCRETE INPUT FUNCTION
Principle of Operation
The inboard Discrete (DT) Input Function provides up to 12 individual digital input channels with BIT fault detection, which enables flagging of non-compliant outputs or inconsistent input readings between dual input measurements.
When channels are programmed as inputs, they can be used for either voltage or contact sensing. Channels set for contact sensing (e.g. sensing a relay contact position; OPEN-CLOSED) can be configured with a programmable “pull-up” or “pull-down” (current source or sink) which effectively provides the proper voltage level change to sense the open state of the contact. This unique design eliminates the need for external resistors or mechanical jumpers. Instead, this design offers a current source/sink (in banks of 6 channels) that the user programs to a desired current (0-5 mA) level.
The 12 channels are configured as 2 banks of 6 channels. Each bank is provided with a separate external input VCC and a ground return (GND) pin. The GND pins are common within the module but are isolated from system (power) GND.
Operational requirements/assumptions:
An external source VCC supply must be wired for proper:
- Input operation when requiring a programmed pull-up current (i.e. programmed “pull-up” for input contact sense; OPEN/GND detect/state change).
An external source Ground/Return must be wired for all input configurations. The Ground/Return must be the input signal or the load current sink ground/reference.
ETHERNET
(For detailed supplement, please visit the NAI web-site specific product page and refer to: Ethernet Interface for Generation 5 SBC and Embedded IO Boards Specification)
Note
For products capable of 10/100/1000Base-KX functionality - the product Ethernet PHY supports 1000BASE-X. Product interoperability with 10/100/1000BASE-KX is supported with 1000BASE-X (provided that auto-negotiation is disabled).
The Ethernet Interface Option allows communications and control access to all function modules either via the system BUS or Ethernet ports 1 or 2.
Ethernet 1 Ethernet 2 Ethernet 3* Ethernet 4* (REF PORT A) (REF PORT B) (REF PORT C) (REF PORT D) The default IP address: 192.168.1.16 192.168.2.16 192.168.3.16 192.168.4.16 The default subnet: 255.255.255.0 255.255.255.0 255.255.255.0 255.255.255.0 The default gateway: 192.168.1.1 192.168.2.1 192.168.3.1 192.168.4.1 *see Part Number Designation for applicability.
Note
Actual “as shipped” card Ethernet default IP addresses may vary based upon final ATP configuration(s).
The NAI interface supports IPv4 and IPv6 and both the TCP and UDP protocols. The Ethernet Operation Mode Command Listener application running on the motherboard host processor implements the operation interface. The listener is operational on startup through the nai_MBStartup process and listen on specific ports for commands to process. The default ports are listed below:
- TCP1 - Port 52801
- TCP2 - Port 52802
- UDP1 - Port 52801
- UDP2 - Port 52802
While the listener is active, note that interrupts from the motherboard do not trigger. The listener can be disabled by turning off the nai_MBStartup process through the Motherboard EEPROM. To turn off nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 1 in the console, either by serial port or telnet to the motherboard, and then reboot the system. To turn on the nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 0 in the console, either by serial port or telnet to the motherboard, and then reboot the system.
Ethernet Message Framework
The interface uses a specific message framework for all commands and responses. All messages begin with a Preamble code and end with a Postamble code. The message framework is shown below.
Preamble
2 bytes Always
0xD30FSequenceNo
2 bytesType Code
2 byteMessage Length
(2 bytes)Payload
(0..1414 bytes)Postamble
2 bytes
Always
0xF03DMessage Elements
Preamble The Preamble is used to delineate the beginning of a message frame.
The Preamble is always 0xD30F.SequenceNo The SequenceNo is used to associate Commands with Responses. Type Code Type Codes are used to define the type of Command or Response the message contains. Message Length The Message Length is the number of bytes in the complete message frame starting with and including the
Preamble and ending with and including the Postamble.Payload The Payload contains the unique data that makes up the command or response.
Payloads vary based on command type.Postamble The Postamble is use to delineate the end of a message frame.
The Postamble is always 0xF03D.Notes
- The messaging protocol applies only to card products.
- Messaging is managed by the connected (client) computer. The client computer will send a single message and wait for a reply from the card. Multiple cards may be managed from a single computer, subject to channel and computer capacity.
Board Addressing
The interface provides two main addressing areas: Onboard and Off-board.
Onboard addressing refers to accessing resources located on the board that is implementing the operation interface (including its modules).
Off-board addressing refers to accessing resources located on another board reachable via VME, PCI, or other bus. Off-board addressing requires a Master/Slave configuration.
The user must always specify if a particular address is Onboard or Off-board. See the command descriptions for the onboard and off-board flags.
Within a particular board (Onboard or Off-board), the address space is broken up into two areas: Motherboard Common Address Space and Module Address Space. All addresses are 32-bit.
Motherboard Common Address Space starts at 0x00000000 and ends at 0x00004000. This is a 4Kx32-bit address space (16 kbytes).
Module Address Space starts at 0x00004000. Module addressing is dynamically configured at startup. NAI boards support between 1 and 6 modules. The minimum module address space size is 4Kx32 (16 kbytes) and module sizes are always a multiple of 4Kx32.
Module addressing is dynamic and cumulative. The first detected module (starting with Slot 1) is given an address of 0x00004000. The 2nd detected Module is given an address of:
First_Detected_Module_Address + First_Detected_Module_Size
Note
Slots do not define addresses.
If no module is detected in a module slot, that slot is not given an address. Therefore, if the first detected Module is in Slot 2, then that module address will be 0x00004000. If the next detected module is in Slot 4, then the address of that Module will be:
Second_Detected_Module_Address = First_Detected_Module_Address + First_Detected_Module_Size
If a 3rd Module is detected in Slot 6, then the address of that Module will be:
Third_Detected_Module_Address = Second_Detected_Module_Address + Second_Detected_Module_Size
Note
Module addresses are calculated at each board startup when the modules are detected. Therefore, if a module should fail to be detected due to malfunction or because it was removed from the motherboard, the addresses of the modules that follow it in the slot sequence will be altered. This is important to note when programming to this interface.
Users can always retrieve the Module Addresses, Module Sizes and Module IDs from the fixed Motherboard Common address area. This data is set upon each board startup. While the Module Addressing is dynamic, the address where these addresses are stored is fixed. For example, to find the startup address of the module location in Slot 3, refer to the MB Common Address 0x00000408 from the Motherboard Common Addresses table that follows.
Ethernet Wiring Convention
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RJ-45 Pin T568A Color T568B Color 10/100Base-T 1000BASE-T NAI wiring convention 1 white/green stripe white/orange stripe TX+ DA+ ETH-TP0+ 2 green orange TX- DA- ETH-TP0- 3 white/orange stripe white/green stripe RX+ DB+ ETH-TP1+ 4 blue blue DC+ ETH-TP2+ 5 white/blue stripe white/blue stripe DC- ETH-TP2- 6 orange green RX- DB- ETH-TP1- 7 white/brown stripe white/brown stripe DD+ ETH-TP3+ 8 brown brown DD- ETH-TP3-
68CB6 CONNECTOR/PIN-OUT INFORMATION
Front and Rear Panel Connectors
The 68CB6 3U OpenVPX Multifunction I/O board is available in two configurations: convection-cooled and conduction-cooled. The 68CB6 follows the OpenVPX “Payload Slot Profile” configured as:
Slot profile: SLT3-PER-1U-14.3.3
Module profile: MOD3-PER-1U-16.3.3-2
User I/O is available through OpenVPX user defined rear I/O connectors P1, P2 (see part number and pin-out information).
Notes:
The following notes apply unless otherwise specified:
-
Maximum ratings for the Tyco MultiGig-RT2 type rear I/O connectors are as follows (per Tyco 108-2072): 50 V peak AC or 50 VDC 1A (@ 30 ºC)
-
DO NOT CONNECT TO ANY UNDESIGNATED or (N/C) PINS
Utility Connector J5
Industry standard mini-HDMI type (type-A receptacle).
Panel LEDs
Front Panel LEDs indications (only available on air-cooled units)
| LED | ILLUMINATED | EXTINGUISHED |
|---|---|---|
| GRN: | Blinking: Initializing Steady On: Power-On/Ready | Power off |
| RED: | Module BIT error | No BIT fault |
| YEL:(flash) | Card access (bus or Gig-E activity) | No card activity |
Chassis Ground
Front Panel: No dedicated chassis GND pins available. Jack screw sockets are chassis GND.
Rear connector key guides are chassis ground.
Front I/O Utility Connector J5 (Convection and Conduction-Cooled)
The 68CB6 utilizes a Mini-HDMI type card edge connector J5, available on either convection or conduction-cooled configurations that provides the following signals:
Serial (port 1) Ethernet port 1 (factory configuration option – Ethernet port1 may be redirected to rear I/O J2)
NAI also provides an optional “breakout” adapter board (NAI P/N 75SBC4-BB) with a mini-HDMI to mini-HDMI type cable. The “breakout” adapter board and a Micro-HDMI cable (NAI P/N 75SBC4-BB) allow for standard I/O connections to Ethernet and asynchronous serial (DB9). Consult the factory for availability.
Signal Descriptions J5
| Signal Name | Description |
|---|---|
| ETH1-TPx | Ethernet port 1 signals (4 pair) 10/100/1000 twisted pair signals (Optional) |
| SER1-TXD | Asynchronous transmit serial data port 1 (out) / RS232 debug/console port only |
| SER1-RXD | Asynchronous received serial data port 1 (in) / RS232 debug/console port only |
| GND | System Ground (return) |
Rear I/O VPX Connectors P0-P2 (Conduction-Cooled)
The 68CB6 3U OpenVPX multifunction I/O board provides interface via the rear VPX connectors.
Rear I/O Summary
Signals defined as N/C currently have no functionality associated and are not required for general operation.
P0 - Utility plane. Contains the following signal definitions:
Power: Primary +5V, 3.3V_AUX, /- 12V and System GND
Geographical Address Pins: GA0# - GA4#, GAP#
Card reset: SYSRST# signal
VPX AUX/REF CLK (Not used)
P1 - Defined as primarily Data/Control Planes (User defined I/O secondary)
High Speed Switched Fabric Interface: One ultra-thin pipe option (PCIe ver. 2.0 (x1) or SRIO (1x)).
Ethernet: Gig-E port option(s) are available and defined (See Part Number Designation section)
P2 - User defined I/O (primary)
Rear I/O Utility Plane (P0)
The P0 (Utility) Plane contains the primary power, bus and utility signals for the OpenVPX board. Additionally, several of the user defined pins can be utilized for Geographical Addressing and a parallel SYSRST# signal. Signals defined as N/C currently have no functionality associated and is not required for general operation.
| UTILITY | Row | Row | Row | Row | Row | Row | Row |
|---|---|---|---|---|---|---|---|
| P0 | G | F | E | D | C | B | A |
| 1 | N/C (VS1_G1) | N/C (VS1_F1) | N/C (VS1_E1) | N/C (NCD1) | N/C (VS2_C1) | N/C (VS2_B1) | N/C (VS2_A1) |
| 2 | N/C (VS1_G2) | N/C (VS1_F2) | N/C (VS1_E2) | N/C (NCD2) | N/C (VS2_C2) | N/C (VS2_B2) | N/C (VS2_A2) |
| 3 | (`)5V (VS3) | (`)5V (VS3) | (`)5V (VS3) | N/C (NCD3) | (`)5V (VS3) | (`)5V (VS3) | (`)5V (VS3) |
| 4 | IMPB-SCL-B (N/C) | IMPB-SDA-B (N/C) | GND | (-)12V (-12V_AUX) | GND | SYSRST# | N/C (NVMRO) |
| 5 | GAP# | GA4# | GND | (+)3.3V (+3.3V_AUX) | GND | IMPB-SCL-A (N/C) | IMPB-SDA-A (N/C) |
| 6 | GA3# | GA2# | GND | (+)12V (+12V_AUX) | GND | GA1# | GA0# |
| 7 | N/C (TCK) | GND | N/C (TDO) | N/C (TDI) | GND | N/C (TMS) | N/C (TRST) |
| 8 | GND | N/C*1 (REFCLK-25MHz-) | N/C*1 (REFCLK-25MHz+) | GND | N/C*1 (AUX-CLK-) | N/C*1 (AUX-CLK+) | GND |
Rear I/O Data/Control Planes (P1)
The 68CB6 has the configuration option for specifying a high-speed serial interface fabric bus connections – PCIe ver. 2.0 (x1). As defined in the OpenVPX bridge or payload slot specifications, the 68CB6 requires only one ‘ultra-thin pipe’ (one Tx and one Rx differential pair), which provides additional user I/O definition opportunity. Additionally, the 68CB6 can be commanded/controlled via a front panel Gig-E interface (10/100/1000BaseT). Additional I/O is also defined on the P1 user defined plane. Signals defined as N/C currently have no functionality associated or are considered optional and are not required for general operation.
| Data Plane | Row | Row | Row | Row | Row | Row | Row |
|---|---|---|---|---|---|---|---|
| P1 | G | F | E | D | C | B | A |
| 1 | N/C | GND | PCIE-SRIO-TXN | PCIE-SRIO-TXP | GND | PCIE-SRIO-RX-N | PCIE-SRIO-RX-P |
| 2 | GND | AC_AD_LINE_IN2_RTN | AC_AD_LINE_IN2 | GND | AC_AD_LINE_IN1_RTN | AC_AD_LINE_IN1 | GND |
| 3 | N/C (RTC STDBY) | GND | S2_LVDT1 | S3_LVDT1 | GND | RLO_LVDT1 | RHI_LVDT1 |
| 4 | GND | N/C | S1_S4_LVDT1 | GND | RTD_DRV_N_CH8 | RTD_DRV_P_CH8 | GND |
| 5 | N/C | GND | CD_28VIN_RTN (ISO-A) | CD_28VIN | GND | RTD_SNS_N_CH8 | RTD_SNS_P_CH8 |
| 6 | GND | RLO_LVDT2 | RHI_LVDT2 | GND | CD_VOUT_CH2 | CD_VOUT_CH1 | GND |
| 7 | N/C | GND | RTD_DRV_N_CH7 | RTD_DRV_P_CH7 | GND | RTD_SNS_N_CH7 | RTD_SNS_P_CH7 |
| 8 | GND | CD_VOUT_CH4 | CD_VOUT_CH3 | GND | RTD_DRV_N_CH6 | RTD_DRV_P_CH6 | GND |
| 9 | S2_LVDT2 | GND | RTD_SNS_N_CH6 | RTD_SNS_P_CH6 | GND | RTD_DRV_N_CH5 | RTD_DRV_P_CH5 |
| 10 | GND | RTD_SNS_N_CH5 | RTD_SNS_P_CH5 | GND | RTD_DRV_N_CH4 | RTD_DRV_P_CH4 | GND |
| 11 | S1_S4_LVDT2 | GND | RTD_SNS_N_CH4 | RTD_SNS_P_CH4 | GND | RTD_DRV_N_CH3 | RTD_DRV_P_CH3 |
| 12 | GND | RTD_SNS_N_CH3 | RTD_SNS_P_CH3 | GND | RTD_DRV_N_CH2 | RTD_DRV_P_CH2 | GND |
| 13 | S3_LVDT2 | GND | RTD_SNS_N_CH2 | RTD_SNS_P_CH2 | GND | RTD_DRV_N_CH1 | RTD_DRV_P_CH1 |
| 14 | GND | RTD_SNS_N_CH1 | RTD_SNS_P_CH1 | GND | AD_IN16_N | AD_IN16_P | GND |
| 15 | N/C | GND | AD_IN15_N | AD_IN15_P | GND | AD_IN14_N | AD_IN14_P |
| 16 | GND | CANL_CH2 | CANH_CH2 | GND | CANL_CH1 | CANH_CH1 | GND |
USER I/O - Defined Area (User Defined I/O) (P2)
The following pages contain the ‘user defined’ I/O data area front and rear panel pin-outs with their respective signal designations for all module types currently offered/configured for the 68CB6 platform. The card is designed to route the function module I/O signals to the front and rear I/O connector. The following I/O connector pin-out is based upon the function module designated in the module slot. Signals defined as N/C currently have no functionality associated or are considered optional and are not required for general operation.
| Data Plane | Row | Row | Row | Row | Row | Row | Row |
|---|---|---|---|---|---|---|---|
| P2 | A | B | C | D | E | F | G |
| 1 | AD_IN12_P | AD_IN12_N | GND | AD_IN13_P | AD_IN13_N | GND | DAC_VOUT_CH1 |
| 2 | GND | AD_IN10_P | AD_IN10_N | GND | AD_IN11_P | AD_IN11_N | GND |
| 3 | AD_IN08_P | AD_IN08_N | GND | AD_IN09_P | AD_IN09_N | GND | DAC_VOUT_CH2 |
| 4 | GND | AD_IN06_P | AD_IN06_N | GND | AD_IN07_P | AD_IN07_N | GND |
| 5 | AD_IN03_P | AD_IN03_N | GND | AD_IN04_P | AD_IN04_N | GND | AD_IN05_N |
| 6 | GND | AD_IN01_P | AD_IN01_N | GND | AD_IN02_P | AD_IN02_N | GND |
| 7 | SG_DRV_H_SNS_CH5 | SG_DRV_L_SNS_CH5 | GND | SG_DRV_H_CH5 | SG_DRV_L_CH5 | GND | AD_IN05_P |
| 8 | GND | SG_DRV_H_CH4 | SG_DRV_L_CH4 | GND | SG_BRG_H_CH5 | SG_BRG_L_CH5 | GND |
| 9 | SG_BRG_H_CH4 | SG_BRG_L_CH4 | GND | SG_DRV_H_SNS_CH4 | SG_DRV_L_SNS_CH4 | GND | SG_DRV_L_CH3 |
| 10 | GND | SG_BRG_H_CH3 | SG_BRG_L_CH3 | GND | SG_DRV_H_SNS_CH3 | SG_DRV_L_SNS_CH3 | GND |
| 11 | SG_DRV_H_SNS_CH2 | SG_DRV_L_SNS_CH2 | GND | SG_DRV_H_CH2 | SG_DRV_L_CH2 | GND | SG_DRV_H_CH3 |
| 12 | GND | SG_DRV_H_CH1 | SG_DRV_L_CH1 | GND | SG_BRG_H_CH2 | SG_BRG_L_CH2 | GND |
| 13 | DT_IN_CH12 | SG_BRG_H_CH1 | GND | SG_BRG_L_CH1 | SG_DRV_H_SNS_CH1 | GND | SG_DRV_L_SNS_CH1 |
| 14 | GND | DT_IN_CH10 | DT_IN_CH11 | GND | VCC_DT GND_DT | GND | 15 |
| DT_IN_CH05 | DT_IN_CH06 | GND | DT_IN_CH07 | DT_IN_CH08 | GND | DT_IN_CH09 | 16 |
| GND | DT_IN_CH01 | DT_IN_CH02 | GND | DT_IN_CH03 | DT_IN_CH04 | GND |
MECHANICAL DETAILS
General Outline
Note
The following mechanical outline detail examples are provided for reference only. Dimensions are in inches unless otherwise specified.
Conduction Cooled
Convection Cooled
Part Number Designation
Notes
| 1. | MFIO Combination Functions “357” Definition Front I/O: 32 pins I/O standard. Rear I/O: 40 pins I/O standard The 68CB6 has (six) inboard function IDs: 1. CF1 – Four-function combination module (Inboard Optimized): a. DT1-Type, 12-Ch. Discrete I/O b. CB8-Type, 2-Ch. CANBus w/FD Communications input c. DA1-Type, 2-Ch. Digital-to-Analog output d. 2-Ch. AC/DC Analog-to-Digital input, isolated (115 Vrms typical) 2. LD6 – LD2-Type, 2-Ch. LVDT-to-Digital measurement plus 2-Ch. AC Reference output (one for each channel), 2-28 Vrms input, 2-12 Vrms AC Reference, ~2 kHz, 50 mA maximum (AC Reference output) 3. TR1 – 8-Ch. Thermocouple (multi-type)/RTD (2,3 or 4-wire) measurement, programmable per channel 4. ADF – 16-Ch. ±100 V Analog-to-Digital measurement, individual SAR, 16-bit, simultaneous sampling, 200 ksps 5. SG2 – SG1-Type, 5-Ch. Strain Gauge, full bridge 5. SG2 – SG1-Type, 5-Ch. Strain Gauge, full bridge 6. CD2 – CD1-Type, 2-Ch. Chip Detect & Fuzz Burn function capable |
|---|---|
| 2. | Mechanical Options Rear I/O Only |
| 3. | IPMC Definition 0. OPTION “0”: DEFAULT. The board will not provide IPMC functionality. The board in this default configuration will bootnormally without a Chassis Manager being present. 1. OPTION “1”: The board will provide VITA 46.11 Tier 2 compliant basic IPMC functionality. The board will be configuredexpecting Chassis Manager communication on boot-up and requires the +3.3V-AUX power supply (PS) to be available on the backplane (provision of +3.3V-AUX is a VPX requirement). |
SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES
Select the Digital-to-Synchro (DSx), Digital-to-Resolver (DRx) or Digital-to-LVDT/RVDT (DLx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. Frequency/voltage band tolerances +/- 10%. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.
- Single Channel module pending availability (contact factory)
Module ID Format Channel(s) Output Voltage VL-L (Vrms) Reference Voltage (Vrms) Frequency Range (Hz) Power / CH maximum (VA) Notes DS1 SYN 1* 2 - 28 2 - 115 47 - 1 K 3 DR1 RSL DL1 LVDT/RVDT DS2 SYN 1* 2 - 28 2 - 115 1 K - 5 K 3 DR2 RSL DL2 LVDT/RVDT DS3 SYN 1* 2 - 28 2 - 115 5 K - 10 K 3 DR3 RSL DL3 LVDT/RVDT DS4 SYN 1* 2 - 28 2 - 115 10 K - 20 K 3 DR4 RSL DL4 LVDT/RVDT DS5 SYN 1* 28 - 90 2 - 115 47 - 1 K 3 DR5 RSL DL5 LVDT/RVDT DSX SYN 1* X X X X X = TBD; special configuration, requires special part number code designation, contact factory DRX RSL DLX LVDT/RVDT DSA SYN 2 2 - 28 2 - 115 47 - 1 K 1.5 DRA RSL DLA LVDT/RVDT DSB SYN 2 2 - 28 2 - 115 1 K - 5 K 1.5 DRB RSL DLB LVDT/RVDT DSC SYN 2 2 - 28 2 - 115 5 K - 10 K 1.5 DRC RSL DLC LVDT/RVDT DSD SYN 2 2 - 28 2 - 115 10 K - 20 K 1.5 DRD RSL DLD LVDT/RVDT DSE SYN 2 28 - 90 2 - 115 47 - 1 K 2.2 DRE RSL DLE LVDT/RVDT DSY SYN 2 Y Y Y Y Y = TBD; special configuration, requires special part number code designation, contact factory DRY RSL DLY LVDT/RVDT DSJ SYN 3 2 - 28 2 - 115 47 - 1 K 0.5 DRJ RSL DLJ LVDT/RVDT DSK SYN 3 2 - 28 2 - 115 1 K - 5 K 0.5 DRK RSL DLK LVDT/RVDT DSL SYN 3 2 - 28 2 - 115 5 K - 10 K 0.5 DRL RSL DLL LVDT/RVDT DSM SYN 3 2 - 28 2 - 115 10 K - 20 K 0.5 DRM RSL DLM LVDT/RVDT DSN SYN 3 28 - 90 2 - 115 47 - 1 K 0.5 DRN RSL DLN LVDT/RVDT DSZ SYN 3 Z Z Z Z Z = TBD; special configuration, requires special part number code designation, contact factory DRZ RSL DLZ LVDT/RVDT SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES
SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL)
Select the Synchro/Resolver-to-Digital (SDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.
Frequency/voltage band tolerances +/- 10%.
Module ID Input Voltage V (Vrms) Reference Voltage + (Vrms) Frequency Range + (Hz) Notes SD1 2 - 28 2 - 115 47 - 1 K SD2 2 - 28 2 - 115 1K - 5 K SD3 2 - 28 2 - 115 5K - 10 K SD4* 2 - 28 2 - 115 10K - 20 K SD5 28 - 90 2 - 115 47 - 1 K SDX* X X X X = TBD; special configuration, requires special part number code designation, contact factory *Consult factory for availability
LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)
Select the LVDT/RVDT-to-Digital (LDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Excitation voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.
Frequency/voltage band tolerances +/- 10%.
Module ID Input Signal Voltage V + (Vrms) Excitation Voltage + (Vrms) Frequency Range + (Hz) Notes LD1 2 - 28 2 - 115 47 - 1 K LD2 2 - 28 2 - 115 1K - 5 K LD3 2 - 28 2 - 115 5K - 10 K LD4* 2 - 28 2 - 115 10K - 20 K LD5 28 - 90 2 - 115 47 - 1 K LDX* X X X X = TBD; special configuration, requires special part number code designation, contact factory *Consult factory for availability
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Revision History
Motherboard Manual - 68CB6 Revision History
| Revision | Revision Date | Description |
|---|---|---|
| C | 2022-06-23 | ECO C09407, transition to docbuilder format. Pg.9, removed ‘Isolated’ from ADF reference in description paragraph. Pg.12, added ‘+3.3_AUX’ power spec to General Specifications. Pg.39, removed Module 7 Interrupt vector/steering. Pg.105, changed ‘isolated’ to ‘non-isolated’ in Principle of Operation. Pg.142, changed ‘…eight individual isolated…’ to ‘…eight individual nonisolated…’ in Thermocouple Capability. Pg.213, changed ‘…five independent, isolated…’ to ‘…five independent, non-isolated…’ in Principle of Operation. Pg.247, added ‘+3.3_AUX’ to P0 summary. Pg.248-250, tables updated per VPX standard. Pg.254, added Single Channel note. Pg.254, changed DS/R/LE ‘Power/CH maximum (VA)’ from 1.5 to 2.2. |
NAI Cares
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