NAI I/O embedded cards run through an initial “factory” calibration at the time of build. This “factory” calibration involves verifications utilizing external instruments where measurements are taken; gain/offset adjustments are calculated and may be downloaded. The initial calibration is performed and downloaded to the card’s defined operating parameters (i.e., voltage/frequency, etc.). This is determined at the time of build and is defined in the full part number of the specific product. Once this calibration has been completed, full card operation and operation-calibration verification tests are performed. Other than VXI cards, our I/O cards are considered embedded-type platforms and do not fall under the same category as typical bench top instruments. These cards are designed with state-of-the-art digital signal processing techniques. Integral to the operation loop, there is built-in-testing (BIT) and “self-adjustments” where the health and operation of the card is monitored and/or adjusted (transparent to the user) to insure proper operation throughout. BIT Status is reported to the user. The card(s) rarely deviate from specification and if a card is deemed out of specification this would typically be captured by status indication, where repair is then usually required.

Calibration and/or calibration verification is up to the customer and/or end user. For those customers that wish periodic calibration verification, there are two options:

Customers may perform their own calibration verification routines comparing test results to the published specifications of the instrument. NAI can provide a periodic calibration verification service for an associated fee to ensure the card performs within specifications. NAI would provide a calibration certificate traceable to NIST standards and test data. I want to use NAI A/D modules for real-time control application, so low-latency is critical. Is there any way to reduce group converter delay? Use an A/D module that has a dedicated Sigma-Delta (or sometimes Delta-Sigma) A/D converter on each individual channel. Inherent to the Sigma-Delta design implementation is an oversampling delay on the input to produce the first digital conversion. (Subsequent data samples occur at the programmed sample rate.) At a 200 kHz sample rate, the group delay is approximately 6 samples (i.e. group delay = (6) x 5 µs = 30 µs). This cannot be reduced.