Overview

Once your application is on the hardware and you have a terminal open (see Connecting to Boards for that), launching an NAI sample application brings up a short configuration menu. This guide walks through the prompts and explains which answers to pick based on where your application is running and how it reaches the modules — the two questions that actually shape the flow.

How the menu works

Every NAI sample application asks the same three questions on launch:

  1. What kind of system do you have? Type N for a Nano (NIU), S for an SIU, or B for a board.
  2. Where is the application running? Type 1 for an external host computer, 2 for the local NAI processor card, or 3 for a non-NAI processor card on the same board.
  3. How does the application reach the modules? For external-host setups, choose ethernet or the host’s PCI/PCIe slot. For onboard setups, no further transport is needed — modules are reached over the local hardware.

Your answers fall into one of four scenarios. Pick the scenario that matches your setup and follow the section below.

Choose your scenario

App runs onReaches modules viaSectionReference systems
External host PCEthernetA — External host, ethernetNIU1A/2A/3A; single NAI SBCs; SIU3x masters
External host PCPCIe / cPCI / VME busB — External host, direct bus79G5 (PCIe), 79C3 (cPCI), VME variants
NAI processor (single SBC)Local hardwareC — Onboard, single SBCNIU1A/2A/3A; 64ARM1, 68ARM2/4, 75ARM1; 68INT5/6/6H, 75INT2; 67PPC2/68PPC2/75PPC1/75SBC4
NAI master SBCBackplane bus to slavesD — Onboard master, backplane slavesSIU3x chassis with master cards (e.g., 75G5, 79G5, 68PPC2, 64G5 in legacy chassis; current ARM/Intel masters in newer chassis)

A. External host, ethernet

Your application runs on a host PC and talks to NAI hardware over a network. The NAI Ethernet Listener runs on the target and accepts the connection from your host, then relays commands to the modules. See tools-at-a-glance for the listener’s role and Ethernet How-to FAQ for the default ports.

Single unit (Nano or single NAI board)

flowchart LR
    PC([Host PC<br/>application]) -- Ethernet --> LS[NAI Ethernet Listener]
    subgraph Target [NAI unit]
        LS --> Mods[Local modules]
    end

Reference systems: NIU1A, NIU2A, NIU3A (Nano); any single NAI SBC reachable over ethernet (e.g., 64ARM1, 68ARM2, 68INT6, 75G5).

SIU master + backplane slaves

flowchart LR
    PC([Host PC<br/>application]) -- Ethernet --> LS
    subgraph SIU [SIU chassis]
        subgraph Master [Master SBC]
            LS[NAI Ethernet Listener]
        end
        LS -- Backplane bus --> Slave[Slave card<br/>+ modules]
    end

For an SIU, the NAI Ethernet Listener runs on the SIU’s master SBC. Your host PC connects to the master over ethernet, and the master uses the chassis backplane (cPCI, VME, or PCIe depending on the SIU model) to reach modules on slave cards.

Reference systems: SIU31, SIU33, SIU34, SIU35, SIU36, SIU36S — anything in the SIU3x family. Master cards inside the chassis (e.g., 75G5, 79G5, 68PPC2, 64G5 in legacy chassis; current ARM/Intel masters in newer chassis) host the listener.

B. External host, direct bus (PCIe / cPCI / VME)

flowchart LR
    PC([Host PC<br/>application]) -- PCIe / cPCI / VME bus --> Board[NAI board<br/>in host backplane]
    Board --> Mods[Modules]

Your application runs on a host PC, and the NAI board is plugged directly into the host’s backplane (PCIe slot, cPCI chassis, or VME chassis). There’s no ethernet listener in this flow — the host enumerates the board over the bus and the SSK driver speaks to it directly.

Reference systems: 79G5 (PCIe), 79C3 (cPCI), VME variants.

C. Onboard, single SBC

flowchart LR
    subgraph Unit [NAI unit]
        App([Application<br/>running onboard]) --> Mods[Local modules]
    end

Your application runs on the NAI hardware’s own processor — a Nano (NIU) or a single NAI SBC running an onboard OS. There is no network or bus traversal in this flow: the application is on the same processor as the modules, so the menu just needs to know it’s running locally.

Reference systems: NIU1A, NIU2A, NIU3A (Nano); 64ARM1, 68ARM2, 68ARM4, 75ARM1 (ARM SBCs); 68INT5, 68INT6, 68INT6H, 75INT2 (Intel SBCs with onboard Linux); 67PPC2, 68PPC2, 75PPC1, 75SBC4 (PowerPC SBCs).

D. Onboard master, backplane slaves

flowchart LR
    subgraph SIU [SIU chassis]
        subgraph Master [Master SBC]
            App([Application<br/>running on master])
        end
        App -- Backplane bus --> Slave[Slave card<br/>+ modules]
    end

Your application runs on an SIU’s master SBC and reaches modules on slave cards over the backplane (cPCI, VME, or PCIe depending on the chassis). No external host and no ethernet listener — the master communicates with slaves directly over the bus.

Reference systems: SIU3x chassis with the application installed on the master SBC (legacy masters: 75G5, 79G5, 68PPC2, 64G5; current ARM/Intel masters in newer chassis).

Where to go next

  • ESP2 Quick Start — Code-free testing of modules via NAI’s host-side GUI. Useful for confirming hardware is working before running your own applications.
  • Opening a Software Handle to Your Board — How to connect to the board programmatically (no menu prompts) when you start writing your own application.
  • Sample App Guides — Function-by-function walkthroughs of every NAI sample application, with code snippets you can lift into your own project.