Pulse Timer Family Guide

Overview

The PT family is NAI’s line of pulse timer modules. A pulse timer sits between an external timing signal and the rest of your system, and it does three things: it receives a timing reference, it generates clock/timing outputs, and it can interrupt and timestamp the host the instant a pulse arrives. Concretely, the PT1 can lock onto an input anywhere from 1 PPS up to 10 MHz (single-ended, differential, or SMA coax), drive that timing back out on several output types, and raise a low-latency interrupt to the motherboard processor so software can timestamp each edge. It also carries two independent isolated asynchronous serial ports for good measure.

That combination makes the PT1 a time-synchronization and signal-distribution building block — the piece that takes a system’s master timing reference (a GPS 1 PPS, an external oscillator, another module’s clock) and fans it out, time-stamps it, or hands it to the processor as an interrupt. It is not a data bus like 1553, ARINC, or CAN; it moves timing, not messages.

The PT family currently has a single member, the PT1, so this guide is specific to it — there are no transformer/direct or channel-count variants to choose between. (NAI’s communication / data-bus families, by contrast: the FT family for MIL-STD-1553/1760, the AR family for ARINC 429/575, the CB family for CANbus, and the SC family for freeform serial.)

This page is the starting point for the PT1 — understand what it does, wire a signal onto it, confirm a channel responds, and run your first input-capture and interrupt-timestamp tests.

PT1 at a glance

The PT1 is a two-channel module: each channel is an independent timing interface with its own input, outputs, serial port, and status. Everything you do — configuring an input, enabling an output, connecting an interrupt — happens per channel.

Capability	What the PT1 provides
Inputs	2 channels, each selectable single-ended (−10 V to +10 V), differential (−24 V to +24 V), or SMA coax. Input impedance programmable to 50 Ω / 75 Ω / 100 Ω / ~100 kΩ (Hi-Z); ~50 pF input capacitance. Frequency range 1 PPS to 10 MHz.
Outputs	8 channels: 2× TTL (±24 mA), 2× RS-422 differential, 2× 5 V, and 2× 12 V (each driving 50 Ω loads). 3.3 V clock output is selectable single-ended or differential.
Serial ports	2 independent isolated RS-422/485 async ports, programmable to 1 Mbps, each with 1 KB (×16) Tx/Rx FIFO buffers.
Interrupts / sync	Pulse-timer interrupt with host timestamping, plus direct motherboard-processor IRQ capability for deterministic, low-latency synchronization.
Form factor	6U VPX and 3U VPX.

Note

Several PT1 features — transmitting the 1 PPS to 10 MHz signal directly to the motherboard, direct motherboard-processor IRQ, and the SMA coax connections — depend on motherboard support and are listed as pending / contact factory in the PT1 Manual. Confirm availability for your platform before designing around them.

View the PT1 data sheet · PT1 Manual

Physical setup

Unlike a data-bus module, the PT1 isn’t wired onto a shared bus — each channel has its own input (the signal you want to receive/measure) and its own set of outputs (the timing signals it drives), brought out as individual pins. The wiring pattern is the same as any NAI function module:

Identify the PT1’s slot number on your NAI motherboard or system.
Bring the channel’s signals out through the breakout board, where the slot’s pins appear as generic IO# numbers.
Map IO# pins to the PT1’s per-channel signals using the pinout in the PT1 Manual appendix (or the module’s overlay card).
Connect your source to the channel’s input and your loads to whichever outputs you’ve enabled.

Each channel exposes a consistent set of signals (the manual’s pinout lists them as …-CH1 / …-CH2):

Input — CHx-IO-P / CHx-IO-N, the differential input pair. Drive it single-ended (−10 V to +10 V), differential (−24 V to +24 V), or — where fitted — via the SMA coax connection. Match the input termination (50 / 75 / 100 Ω, or leave Hi-Z ~100 kΩ) to your source’s drive impedance.
Clock outputs — CLK-OUTx-P / CLK-OUTx-N (the RS-422 differential 3.3 V output) and CLK-OUTx-SE (the single-ended/TTL 3.3 V output). Either, both, or neither can be enabled per channel.
Voltage outputs — OUT5Vx_* and OUT12Vx_*, the 5 V and 12 V outputs (each able to drive a 50 Ω load).
Serial port — TXDHI/LO-CHx and RXDHI/LO-CHx, the RS-422/485 transmit and receive pairs, with an isolated ground GND-ISO-CHx.

A few things to keep in mind for wiring:

Termination is about impedance matching, not bus topology. A 1553/CAN bus is terminated at its far ends; the PT1’s termination is per-input, chosen to match the impedance of your source so the received signal is clean. Pick 50/75/100 Ω to match (e.g. 50 Ω for typical coax), or leave it Hi-Z if your source is already terminated elsewhere.
Single-ended vs differential vs SMA is a per-input choice set in software (Input Format), and only one mode is valid at a time — see Software and Common pitfalls.
Don’t assume a fixed channel-to-output mapping. The manual explicitly notes the 5 V/12 V output-to-channel assignments (OUT5V1_A, OUT5V2_A, etc.) may change in future module iterations — always confirm against the pinout for your revision rather than hard-coding pin numbers.

Software

There’s nothing PT-specific about which software stack you run. The NAI SSK (naibrd library) is identical across every OS and architecture — PetaLinux, VxWorks, DEOS, Windows — and which one you’re on is set by your motherboard/SBC, not by the PT1. The only PT-specific part is which API functions you call: the PT1 is driven by the naibrd_PT_* family of calls.

Note

The naibrd_PT_* configuration API is the same in SSK 1.x and 2.x — identical function names and signatures — so the calls below work on either version. Only two things are SSK 2.x-specific: the pulse-timer interrupt functions (naibrd_Connect_PulseTimer_ISR; see Pulse-timer interrupts) have no 1.x counterpart, and the PT sample applications ship for 2.x. The 1.x SSK shipped the register-level PRNT BasicOps sample, but the naibrd_PT_* library calls are available on 1.x as well.

The configure handshake. Before changing a channel’s configuration, the PT1 wants a specific enable/disable handshake so the hardware reads a consistent set of registers (this is the Tx-Rx Configuration register’s Enable Channel bit and the realtime Channel Configured status):

Write 0 to the channel’s Enable Channel bit to tell the hardware a configuration change is coming.
Wait for the Channel Configured status to read 0.
Write all the configuration registers you want (input format, termination, clock/output enables, serial settings).
Write 1 to the Enable Channel bit so the hardware re-reads the configuration.
Wait for Channel Configured to read 1 before sending/receiving.

The naibrd_PT_Set* calls and the sample apps handle the mechanics for you, but it’s worth knowing this is happening — it’s why a configuration write can appear to “not take” if the channel wasn’t disabled first.

Where to find what you need:

Which functions/registers to call — the PT1 Manual documents every register (input, output, serial Tx/Rx FIFO, configuration, control, status, interrupt) and is the reference behind the naibrd_PT_* calls.
Building and deploying on your platform — Connecting to Boards covers the toolchain, deployment, and terminal access for PetaLinux/ARM Linux, VxWorks, DEOS, and Windows.
Launching the app on the board itself — Running Applications from the Target walks through loading and launching your executable on the target.

Confirm communication

The PT1 isn’t a bus, so there’s no two-node loopback to run — the quickest “is everything talking?” check is to configure a channel and read its settings back. If a write takes and the read-back reflects it, your board connection, the SSK, and the module are all confirmed.

The PT BasicOps sample does exactly this interactively: it connects to the board, asks for a channel, and presents a menu to set the clock output, output voltage, input format, termination, and crossing threshold — then displays the resulting per-channel status after every command. A good first pass:

Run pt_basic_ops and connect to your board (card index, then module slot).
Pick channel 1, set the Input format to single-ended, and set the Clock output to single-ended.
Confirm the status table redraws showing Input Format = Single Ended, Enabled and Clock Out = SingleEnded for that channel.

Under the hood that’s a naibrd_PT_SetInputFormat() / naibrd_PT_SetClockOutEnable() followed by the matching naibrd_PT_Get*() reads — the same calls you’ll lift into your own code. If the read-back matches what you wrote, the channel is alive. To prove the signal path end-to-end (a real pulse in, a real clock out), wire a source and scope per Physical setup and use the interrupt-timestamp test in Try it.

Features

Everything you do with the PT1 happens per channel, and the two channels are independent — each has its own input, outputs, serial port, and status, and they can be configured differently and run at the same time. In software you select a channel (1 or 2) and pass it to each naibrd_PT_* call; naibrd_PT_GetChannelCount() tells you how many channels the module has (2 for the PT1).

Every function starts from the standard connection flow (naiapp_RunBoardMenu() → naiapp_query_CardIndex() / naiapp_query_ModuleNumber() → cardIndex / module / channel; see Opening a Software Handle to Your Board). The features below are the things you can make a channel do — the input side (receive a signal), the output side (generate signals), the interrupt side (get notified and timestamp), and the serial ports.

Full register/parameter detail for every call is in the PT1 Manual; the snippets and workflow order are in Try it further down.

Signal input — receive and condition

What it does / when: configures how a channel receives its input signal — the connection format, the impedance match, and (for single-ended) the voltage threshold the hardware uses to decide a logic crossing. This is the first thing you set on any channel you intend to capture or interrupt on.

Relevant APIs:

nai_status_t naibrd_PT_SetInputFormat(int32_t cardIndex, int32_t module, int32_t channel, naibrd_pt_input_format_t io_select);
nai_status_t naibrd_PT_GetInputFormat(int32_t cardIndex, int32_t module, int32_t channel, naibrd_pt_input_format_t* io_select);
nai_status_t naibrd_PT_SetInputTermination(int32_t cardIndex, int32_t module, int32_t channel, naibrd_pt_input_termination_t input_term);
nai_status_t naibrd_PT_GetInputTermination(int32_t cardIndex, int32_t module, int32_t channel, naibrd_pt_input_termination_t* input_term);
nai_status_t naibrd_PT_SetCrossingThreshold(int32_t cardIndex, int32_t module, int32_t channel, float64_t cross_thresh);
nai_status_t naibrd_PT_GetCrossingThreshold(int32_t cardIndex, int32_t module, int32_t channel, float64_t* cross_thresh);

Format — NAIBRD_PT_INPUTFORMAT_DISABLED, …_SINGLEENDED_ENABLED, …_DIFFERENTIAL_ENABLED, …_SMA_ENABLED, …_SINGLEENDED_CROSS_THRESH_ENABLED. Only one is valid at a time.
Termination — NAIBRD_PT_INPUT_DISABLED, …_50_OHM, …_75_OHM, …_100_OHM.
Crossing threshold — a float64_t voltage, used in the single-ended-with-threshold format.

Exercise it: PT BasicOps (Input / Term / Cross commands).

Signal output — generate clocks and levels

What it does / when: enables the channel’s output drivers — the 3.3 V clock output (single-ended and/or RS-422 differential) and the 5 V / 12 V outputs. Use it to fan a timing reference out to other modules, boards, or instruments.

Relevant APIs:

nai_status_t naibrd_PT_SetClockOutEnable(int32_t cardIndex, int32_t module, int32_t channel, naibrd_pt_clock_out_enable_t clock_mode);
nai_status_t naibrd_PT_GetClockOutEnable(int32_t cardIndex, int32_t module, int32_t channel, naibrd_pt_clock_out_enable_t* p_outclock);
nai_status_t naibrd_PT_SetOutputEnable(int32_t cardIndex, int32_t module, int32_t channel, naibrd_pt_output_type_t output_type);
nai_status_t naibrd_PT_GetOutputEnable(int32_t cardIndex, int32_t module, int32_t channel, naibrd_pt_output_type_t* p_output_type);

Clock out — NAIBRD_PT_CLOCK_DISABLE, NAIBRD_PT_CLOCK_SINGLEENDED, NAIBRD_PT_CLOCK_DIFF (enable single-ended, differential, or both by combining).
Output enable — NAIBRD_PT_OUTPUT_DISABLE, NAIBRD_PT_OUTPUT_5V, NAIBRD_PT_OUTPUT_12V, NAIBRD_PT_OUTPUT_5V_AND_12V.

Exercise it: PT BasicOps (Clock / Output commands).

Pulse-timer interrupts and timestamping

What it does / when: registers a callback that fires on each pulse-timer interrupt event, so software is notified the instant a pulse arrives and can timestamp it. This is the PT1’s signature capability — measuring interrupt latency, pulse intervals, and synchronizing software to an external timing reference. It uses a dedicated pulse-timer ISR connection rather than the general naibrd_ConnectISR().

Applies to: SSK 2.x only (no 1.x counterpart), on platforms that support pulse-timer interrupts (primarily Petalinux on ARM), with the BSP built with NAIBSP_SYS_CONFIG_PULSETIMER enabled (set to 1). If that flag is off, these calls are compiled out.

Relevant APIs:

nai_status_t naibrd_Connect_PulseTimer_ISR(int32_t cardIndex, nai_isr_t isr);
nai_status_t naibrd_Disconnect_PulseTimer_ISR(int32_t cardIndex);

nai_isr_t is the SSK’s callback typedef — typedef void (*nai_isr_t)(uint32_t vector) — the same type naibrd_ConnectISR() takes. The vector identifies the source; for the PT1 it’s a four-character code (0x50543120, 'PT1 ').
Capture a high-resolution timestamp inside the callback (e.g. clock_gettime(CLOCK_REALTIME, …)) to measure timing. Keep ISR work minimal in production — set a flag and defer heavy work to a task.
The interrupt path is intended for input rates below ~500 Hz; faster pulse streams are better measured by other means.

Exercise it: PT MB Interrupts (configures a channel for single-ended input, connects the pulse-timer ISR, and prints a timestamp per event).

Independent async serial ports

What it does / when: each channel includes an independent, isolated RS-422/485 asynchronous serial port — useful for an out-of-band control/telemetry link alongside the timing function. Each port has its own Tx/Rx FIFO buffers (1 KB ×16), programmable baud rate up to 1 Mbps, and supports gap-timeout detection, termination-character detection, and an “immediate transmit” mode that sends data as soon as the transmit buffer is non-empty (no per-message Tx-initiate needed).

How it’s accessed: the serial ports are register-driven — there’s a full set of Receive/Transmit FIFO, Data Configuration, Baud Rate, Termination Character, Time Out, and Tx-Rx Configuration registers per channel in the PT1 Manual. The PT SSK sample applications don’t exercise the serial ports, so this guide doesn’t show serial naibrd_PT_* snippets; drive them via the register offsets documented in the manual. The same configure handshake from Software applies (disable the channel, write the config registers, re-enable).

Reference: PT1 Manual — Receive, Transmit, Configuration, and Control register sections.

Try it

The snippets below show the order of naibrd_PT_* calls for the two things you’ll do most — configure a channel’s I/O, and capture pulse-timer interrupts with timestamps. Drop them into the body of an NAI sample app (after the standard connection flow described in Software above) and you have a working test. Each snippet is the conceptual sequence, not a fully-buildable program; the PT BasicOps and PT MB Interrupts samples are the full reference.

Try it — configure a channel’s input and output

Set the input format and termination, set the clock output, and read everything back to confirm it took.

/* configure channel I/O (same calls on SSK 1.x and 2.x) */
int32_t maxChannels = naibrd_PT_GetChannelCount(moduleID);   /* 2 for the PT1 */
 
/* Input side: single-ended, 50 ohm termination, threshold at 2.0 V */
naibrd_PT_SetInputFormat(cardIndex, module, channel, NAIBRD_PT_INPUTFORMAT_SINGLEENDED_ENABLED);
naibrd_PT_SetInputTermination(cardIndex, module, channel, NAIBRD_PT_INPUT_50_OHM);
naibrd_PT_SetCrossingThreshold(cardIndex, module, channel, 2.0);
 
/* Output side: 3.3 V single-ended clock out, plus 5 V output */
naibrd_PT_SetClockOutEnable(cardIndex, module, channel, NAIBRD_PT_CLOCK_SINGLEENDED);
naibrd_PT_SetOutputEnable(cardIndex, module, channel, NAIBRD_PT_OUTPUT_5V);
 
/* Read back to confirm */
naibrd_pt_input_format_t fmt;
naibrd_pt_clock_out_enable_t clk;
naibrd_PT_GetInputFormat(cardIndex, module, channel, &fmt);
naibrd_PT_GetClockOutEnable(cardIndex, module, channel, &clk);

Try it — capture pulse-timer interrupts with timestamps

Configure the channel’s input, connect the dedicated pulse-timer ISR, and timestamp each event in the callback. Requires a BSP built with NAIBSP_SYS_CONFIG_PULSETIMER set to 1.

/* SSK 2.x — pulse-timer interrupt + timestamp */
static int32_t irqCount = 0;
static struct timespec ts0;
 
static void SampleCallBack(uint32_t vector)
{
   irqCount++;
   clock_gettime(CLOCK_REALTIME, &ts0);   /* nanosecond timestamp at ISR time */
   naiif_printf("%d, timestamp=%lld, %ld, VECTOR=%X\n",
                irqCount, ts0.tv_sec, ts0.tv_nsec, vector);
}
 
/* ... after connecting to the board and selecting card/module/channel ... */
naibrd_PT_SetInputFormat(cardIndex, module, channel, NAIBRD_PT_INPUTFORMAT_SINGLEENDED_ENABLED);
 
#if (NAIBSP_SYS_CONFIG_PULSETIMER == 1u)
naibrd_Connect_PulseTimer_ISR(cardIndex, SampleCallBack);   /* fires on each pulse event */
/* ... wait for pulses (e.g. until the user quits) ... */
naibrd_Disconnect_PulseTimer_ISR(cardIndex);
#endif

Building and running the SSK samples. The snippets above are condensed for orientation. For full, buildable programs see PT BasicOps and PT MB Interrupts, and Using NAI SSK 2.x Sample Applications for build/run instructions across platforms.

Hardware capabilities and status monitoring

This section covers what the hardware provides and what you can monitor — for how to drive each function, see Features and Try it above.

Input conditioning. Each input accepts single-ended (−10 V to +10 V), differential (−24 V to +24 V), or SMA coax, over a 1 PPS to 10 MHz range, with programmable termination (50 / 75 / 100 Ω / Hi-Z) and a programmable single-ended crossing threshold (DAC reference). The hardware rejects invalid input configurations — enabling multiple input modes at once is ignored and the previous valid configuration is retained, so the register always reflects the real state (FPGA 1.4 / BM 2.8 and later).

Output drive. Per channel: 3.3 V clock output (single-ended TTL and/or RS-422 differential), plus 5 V and 12 V outputs able to drive 50 Ω loads, and the TTL (±24 mA) / RS-422 output channels described in PT1 at a glance.

Synchronization. The PT1 is built to fan timing into the system: it can (where the motherboard supports it) pass the 1 PPS–10 MHz signal directly to the motherboard and raise a direct motherboard-processor IRQ for deterministic, low-latency sync. As noted in the Overview, these and the SMA connections are pending / contact factory — confirm for your platform.

Statuses you can monitor programmatically (per channel; each has Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt variants):

Status group	What it tells you
Pulse Time Channel Status	Input pulse rising-edge and falling-edge events and the current input state (high/low) — the core of edge detection and interrupt timestamping (FPGA 1.6+).
Serial Channel Status	Per-channel serial health: Channel Configured, BIST Passed, Rx Data Available, Tx Complete, Tx FIFO Almost Empty, Rx FIFO Almost Full, Rx Overrun, Gap/Timeout Occurred, Break/Abort, Parity Error.
Channel FIFO Status	Current serial FIFO levels against the Rx Almost-Full / Tx Almost-Empty watermarks.
Error Summary / module common	Module-level error roll-up plus the shared module-common registers (revisions, serial number, temperature/voltage/current monitoring).

Latched status bits are write-1-to-clear — write a 1 back to the bit you read set to clear it.

Common pitfalls

Skipping the configure handshake. If a configuration write seems to “not take,” the channel probably wasn’t disabled first. Clear the Enable Channel bit, wait for Channel Configured = 0, write your config, re-enable, and wait for Channel Configured = 1 (see Software).
Enabling more than one input mode. Single-ended, differential, SMA, and single-ended-with-threshold are mutually exclusive. The hardware rejects an invalid combination and keeps the previous valid config — read the register back to see what’s actually set.
Termination mismatch. The PT1’s input termination is for impedance matching to your source, not bus topology. A wrong value (or Hi-Z when you needed 50 Ω) gives a degraded or noisy received signal. Match it to the source’s drive impedance.
Crossing threshold out of range or unset. The single-ended crossing threshold sets the voltage at which a logic edge is detected; if it’s wrong for your signal levels, edges won’t register. Use the threshold formula/range in the PT1 Manual.
NAIBSP_SYS_CONFIG_PULSETIMER not enabled. If the pulse-timer ISR calls don’t exist at link time, the BSP wasn’t built with the flag set to 1 — the connect/disconnect calls are compiled out otherwise. Rebuild with the flag enabled (primarily a Petalinux/ARM path).
Driving the interrupt path too fast. The pulse-timer interrupt route is intended for input rates below ~500 Hz. Faster streams produce irregular timestamps; measure those another way.
Doing heavy work in the ISR. The sample prints from the callback for demonstration only. In production, set a flag and defer printing/processing to a task-level handler.
Assuming a fixed output pin mapping. The manual warns the 5 V/12 V output-to-channel pin assignments may change across module revisions — confirm against the pinout for your hardware, don’t hard-code pins.
Expecting motherboard sync features everywhere. Direct MB signal passthrough, direct processor IRQ, and SMA connections depend on motherboard support and are listed pending / contact factory. Verify availability before designing around them.

PT1 Manual — the PT1 module manual (all registers and the full naibrd_PT_* reference)
PT BasicOps — configure clock output, voltage output, input format/termination, and crossing threshold (SSK 2.x)
PT MB Interrupts — connect the pulse-timer ISR and timestamp interrupt events (SSK 2.x)
PRNT BasicOps — register-level sample shipped with SSK 1.x (the naibrd_PT_* API is available on 1.x too)
FT Family Guide · AR Family Guide · CB Family Guide · SC Family Guide — NAI’s communication / data-bus families
Download the SSK — get the library and sample apps
Connecting to Boards — power, network, terminal, and file transfer to your board
Opening a Software Handle to Your Board — establish the connection your naibrd_PT_* calls run against
Running Applications from the Target — load and launch a built sample on the board

NAI Documentation

Explorer

PT Module Guide

Pulse Timer Family Guide

Overview

PT1 at a glance

Physical setup

Software

Confirm communication

Features

Signal input — receive and condition

Signal output — generate clocks and levels

Pulse-timer interrupts and timestamping

Independent async serial ports

Try it

Try it — configure a channel’s input and output

Try it — capture pulse-timer interrupts with timestamps

Hardware capabilities and status monitoring

Common pitfalls

Table of Contents

Backlinks

NAI Documentation

Explorer

PT Module Guide

Pulse Timer Family Guide

Overview

PT1 at a glance

Physical setup

Software

Confirm communication

Features

Signal input — receive and condition

Signal output — generate clocks and levels

Pulse-timer interrupts and timestamping

Independent async serial ports

Try it

Try it — configure a channel’s input and output

Try it — capture pulse-timer interrupts with timestamps

Hardware capabilities and status monitoring

Common pitfalls

Related resources

Table of Contents

Backlinks