DT3 Manual

DT3 I/O Modules Discrete IO - Multichannel,Programmable Function Modules

Discrete Output, 4-Channel, High Current (to 2 A)

The DT3 provides four isolated, high current & voltage (up to 2 A, 65 VDC) discrete output switching channels. Arranged and power sourced in channel pairs, the individual module channel(s) can control and switch load outputs for either single or dual power supply applications. With a single source power supply (VCC & GND), the channel(s) can be connected to a load and provide either hi-side (current source) or lo-side (current sink) discrete load current switching. With dual power supply sources (VCC & VSS), the channel(s) can be connected to a load to provide push-pull discrete load current switching (dual source current switching from both a positive and negative power supply).

Features

Discrete Output 4 isolated, independent channels Paired VCC and VSS Source Inputs High Current Switching 2 A (max), load dependent High Input Voltage Power Supply Range ±5 to ±35 VDC (VCC & VSS dual source) 5 to 65 VDC (VCC single source)

Discrete Mode Functions PUSH-PULL Output commands; current source or sink PWM Output command PWM Continuous or Burst modes (n-times) Up to 500 kHz maximum OFF command = channel tri-state, high-Z

Standard NAI COSA Smart Function SerDes Interface (to motherboard) Standard I/O (32) pinout set

Built-in Test & Functions Input & Output Voltage measurements Output Current measurements Over-current protection/status

Specifications

ID/Type		High-current, individual, discrete isolated current switches; DT3: 4-Channel (2-channels are paired and share VCC/VSS power supply source inputs)
Voltage Range:		±5 to ±35 VDC / Channel max. (external supplied dual source VCC & VSS); 5 to 65 VDC / Channel max. (external supplied single source VCC & GND); Note:Channel pair power input sources are/must be referenced to the channel pair ISO_GND
Overvoltage Surge Protection		75 VDC max. (clamped)
Output Mode Formats (programmable per channel)		Mode 0: Standard mode. User has two registers: “Drive Output H/L/T” and“Output Format”. Mode 1: PWM mode. PWM Output command; PWMContinuous or Burst modes (n-times)
Channel Off (tristate)		High-Z (>2 MΩ)
Output Current		2 A per channel, maximum
Output Impedance		<0.1 Ω	System Protection
	All output(s) are set to “OFF” (at Power-ON and reset). No voltage transients on power-on or power-off.		Load & Channel Protection
	Short circuit protected. Channel shuts “off” and a flag is set when current exceeds 10% maximum current rating > 50ms. Channel over-current reset by control/status register command.		Switching Frequency
	Up to 350 kHz maximum (for PWM mode).		+VCC & -VSS Voltage Measurement
	User can read source voltage(s). Voltage: LSB = 100 mV; Accuracy: ±1V		Output Voltage Measurement
	User can read voltage of each channel. Voltage: LSB = 100 mV; Accuracy:±300 mV		Output Current Measurement
	User can read current of each channel. Current: LSB = 1 mA; Accuracy: ±20 mA		Isolation
	Module power source (ISO-GND) and I/O to system ground is ≥500 VDC		Power
	5 VDC / 105 mA (max) (does not include source powered load)		Weight
	1.5 oz. (42 g)		PWM Output Mode Operation
	Individual Output Mode: PWM Continuous or PWM Burst (n-times)

Specifications (Continued)

Example Applications

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Architected for Versatility

NAI’s Custom-On-Standard Architecture™ (COSA®) offers a choice of over 40 Intelligent I/O, communications, or Ethernet switch functions, providing the highest packaging density and greatest flexibility of any 3U SBC in the industry. Preexisting, fully-tested functions can be combined in an unlimited number of ways quickly and easily.

Board Support Package and Software Support

The 75PPC1 includes BSP and SDK support for Wind River® VxWorks®. In addition, software support kits are supplied, with source code and board-specific library I/O APIs, to facilitate system integration. Each I/O function has dedicated processing, unburdening the SBC from unnecessary data management overhead.

Background Built-In-Test (BIT)

BIT continuously monitors the status of all I/O during normal operations and is totally transparent to the user. SBC resources are not consumed while executing BIT routines. This simplifies maintenance, assures operational readiness, reduces life-cycle costs and— keeps your systems mission ready.

One-Source Efficiencies

Eliminate man-months of integration with a configured, field-proven system from NAI. Specification to deployment is a seamless experience as all design, state-of-the-art manufacturing, assembly and test are performed— by one trusted source. All facilities are in the U.S. and optimized for high-mix/low volume production runs and extended lifecycle support.

Product Lifecycle Management

From design-in to production, and beyond, NAI’s product lifecycle management strategy ensures the long-term availability of COTS products through configuration management, technology refresh, and obsolescence component purchase and storage.

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DT3 DATA SHEET

Click here for the DT3 data sheet

INTRODUCTION

As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurements and simulation, communications, Ethernet switch, and SBC functions. Our DT3 Discrete Output smart function module provides four isolated, high current and voltage (up to 2 A, 65 VDC) discrete output switching channels that can control and switch load outputs for either single or dual power supply applications. This user manual is designed to help you get the most out of our discrete I/O smart function modules.

DT3 Overview

NAI’s DT3 module offers a range of features designed to suit a variety of system requirements, including:

Four (4) Isolated, Independent Channels: The DT3 module provides four separate channels, each equipped with paired VCC and VSS source inputs, ensuring precise and independent control.

High Current Switching: With a maximum current rating of 2A (load dependent), the DT3 module is capable of high current switching, making it suitable for a wide range of applications.

High Input Voltage Power Supply Range: The module supports a versatile power supply range, accommodating various voltage requirements:

• With VCC & VSS dual source inputs, the DT3 accepts a wide range of input voltages from ±5 to ±35 VDC.
• With a VCC single source input, the input voltage range extends from 5 to 65 VDC.

This power supply range versatility ensures compatibility with your specific setup.

Push-Pull Output Commands: Users can configure the DT3 module to operating in push-pull mode, enabling both current sourcing and sinking capabilities for increased operational flexibility.

Individual PWM Output Commands: The DT3 module offers individual Pulse Width Modulation (PWM) output commands with options for continuous or burst modes, allowing for the generation of precise PWM signals tailored to the user’s application needs.

Standard NAI COSA®: The module features a SerDes interface for seamless communication with the motherboard. With its standard 32-pin I/O pinout set, integration into existing systems is straightforward.

Built-In Test & Functions: The DT3 module comes equipped with built-in test and diagnostic functions, including:

• Built-in capabilities for measuring input and output voltages, providing valuable diagnostic information.
• Ability to monitor output currents to ensure the module is operating within specified limit.
• Over-current protection, providing status information to prevent damage and ensure reliable operation.

These features make the monitoring and maintenance of the user’s system performance easier.

PRINCIPLE OF OPERATION

The DT3 provides 4 independent, isolated, high current (up to 2 A per channel) and voltage (±65 V for a single source power supply, ±35 V for a dual source power supply). This module includes diode clamping on each channel. Clamping is useful for inductive loads, such as relays and short circuit protection.

The 4 channels are galvanically isolated in pairs (VCC1/VSS1 for Ch.1/2, VCC2/VSS2 for Ch.3/4) from both system ground and from each other. With a single source power supply (VCC & GND), the channel(s) can connect to a load to provide high-side (current source) or low-side (current sink) discrete load current switching. With dual power supply sources (VCC and VSS), the channel(s) can connect to a load to provide push-pull discrete load current switching (dual source current switching from both a positive and negative power supply) with three states: drive high (VCC), drive low (VSS) or tristate (high-impedance). Current and Voltage measurements are available as both instantaneous (sampled) and averaged (RMS).

This module provides an automatic background built-in-test (BIT) for each channel. The BIT functions are always enabled and continually check that each channel is functioning properly.

The module design utilizes state of the art galvanic isolation that is superior to alternatives such as optocoupler devices. The galvanic isolation eliminates typical optocoupler design concerns such as uncertain current transfer ratios, nonlinear transfer functions and temperature/lifetime degradation effects.

Channel Interface

Each channel contains a dual n-channel MOSFET pair configured as an isolated solid-state relay (SSR). The SSR is energized so both AC and DC current can flow through the channels I/O pins. The MOSFET presents a low ~7mΩ on-impedance. The module contains circuitry to measure the current through, and the voltage present on the output pins.

PWM Output

There are two PWM output modes: continuous PWM and burst PWM. The PWM output is precise with low jitter. In PWM output mode, the PWM Burst Count register value determines whether the output will be a continuous or burst output. The value written to the PWM Period register specifies the period of the PWM output. The value written to the PWM Pulse Width register specifies the time in which the output will be driven ‘high’ (VCC), while the remainder of the period will be driven ‘low’ (VSS). For PWM Burst mode, a value greater than zero in the PWM Burst Count register specifies the number of cycles that will appear on the output when triggered.

Continuous PWM

Figure 1 and Figure 2 illustrate examples of continuous PWM outputs. The configured PWM output is enabled and disabled with the PWM Enable register.

PWM Burst

Figure 3 and Figure 4 illustrate examples of PWM burst outputs. The configured PWM output is enabled with the PWM Enable register. After the number of pulses that were requested is outputted, the value in the PWM Enable register will be reset (self-clearing) to allow for the output to be re-enabled.

Automatic Background Built-In Test (BIT)/Diagnostic Capability

The discrete module supports automatic background BIT testing that verifies channel health. The testing is transparent to the user, requires no external programming, and has no effect on the operation of the module. The background BIT (D2) checks the voltage at the output pin and compares that value with the VCC voltage (when driving high) or VSS voltage (when driving low). The compared values must match within a range of ±1 V. If they do not, a BIT fault will be set. The results of the tests are stored in the BIT Dynamic Status and BIT Latched Status registers.

The technique used by the continuous background BIT (CBIT) test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. Note, the interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained; i.e. at a ten second interval, not a 10-millisecond interval). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state.

In addition to BIT, the discrete module tests for overcurrent conditions, VCC/VSS undervoltage, VCC/VSS overvoltage, VCC/VSS surge suppressor fault, and FET driver overtemperature.

User Watchdog Timer Capability

The Discrete Output Function Module provides registers that support User Watchdog Timer Capability. Refer to “User Watchdog Timer Module Manual” for the Principle of Operation description.

Module Common Registers

The Discrete Output Function Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

Status and Interrupts

The Discrete Output Function Module provides registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

REGISTER DESCRIPTIONS

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Discrete Output Registers

Each channel can be configured for either commanded output or PWM mode. The PWM Period, PWM Pulse Width, and PWM Burst Count registers configure the PWM output characteristics. The Drive Output High/Low/Tristate register drives the output based on the configured Output Format, and the Output Format register configures the output drivers for each channel.

Output Mode

Function: Sets how the output is controlled for each channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 0 to set the channel for user commanded output (output state is controlled by the Drive Output High/Low/Tristate register). Write a 1 to set the channel for PWM mode. Bit-mapped per channel.

Note

for both output command and PWM modes, the Output Format register takes priority if the output is set to high-impedance.

Output Mode

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

PWM Period

Function: When Output Mode is set for PWM mode, the value in the PWM Period register is used as the time interval for the PWM output.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: N/A

Operational Settings: Set the PWM Period (LSB = 8 ns). The PWM Period must be greater than the value set in the PWM Pulse Width register.

PWM Pulse Width

Function: When Output Mode is set for PWM mode, the value in the PWM Pulse Width register is used as the time interval of “drive high (VCC)” for the PWM output.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: N/A

Operational Settings: Set the PWM Pulse Width (LSB = 8 ns). The PWM Pulse Width must be less than the value set in the PWM Period register.

Drive Output High/Low/Tristate

Function: Drives the output based on the configured Output Format.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R/W

Initialized Value: 0x0000 0000

Operational Settings: See below table for complete list of settings. Bit-mapped per channel.

Off (Tristate/High-Z)	No effect
Low-side drive	1 to tristate, 0 to drive output low (Vss)
High-side drive	1 to drive output high (Vcc), 0 to tristate
Push-pull	1 to drive output high (Vcc), 0 to drive output low (Vss)

Drive Output High/Low/Tristate

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

Output Format

Function: Configures the output drivers for channels 1-4.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 00FF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write integer 0 for Off (Tristate/High-Z); 1, 2, or 3 for specific output format.

Integer	DH	DL	(2 bits per channel)
0	0	0	Off (Tristate/High-Z)
1	0	1	Low-side drive
2	1	0	High-side drive
3	1	1	Push-pull

Output Format

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	Ch4	Ch4	Ch3	Ch3	Ch2	Ch2	Ch1	Ch1

PWM Enable

Function: Enables the PWM output (Output Mode register for the channel must be set for PWM mode).

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R/W

Initialized Value: 0x0000 0000

Operational Settings: Write a 1 to enable PWM output. If a burst count greater than zero is programmed, the bit will clear once the number of cycles has completed. Bit-mapped per channel.

PWM Enable

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

PWM Burst Count

Function: Sets the PWM number of cycles for burst mode.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0 (continuous mode)

Operational Settings: Set the number of times to output the PWM signal. Set to 0 for continuous mode.

Discrete Output Control Registers

The discrete output control registers provide the ability to specify the configuration of the bridge mode and the maximum/minimum voltage values for the VCC and VSS supplies. The discrete output channels are monitored to detect overcurrent conditions and will automatically disable the discrete output (set to high-impedance). In the event of an overcurrent condition, the discrete channel needs to be ‘reset’ by writing to the Overcurrent Reset register (the channel will also enter tristate mode upon detection of an overcurrent condition). The discrete Current Limit register provides the ability to set or change the threshold for overcurrent detection for each channel.

Full Bridge Enable

Function: Sets the channel pairs for half-bridge or full-bridge mode.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0003

Read/Write: R/W

Initialized Value: 0 (half-bridge for all channels)

Operational Settings: Write a 0 to set the channel for half-bridge mode. Write a 1 to set the channel for full-bridge mode. Bit-mapped per VCC/VSS bank.

Note

When D0 Bit is set to 1, channels 1 and 2 operate as a full-bridge; when D1 Bit is set to 1, channels 3 and 4 operate as a full-bridge.

Note

When full-bridge mode is enabled, both channels in the pair MUST be configured to push-pull in Output Format, otherwise the channels in the pair will continue to operate as half-bridge.

Full Bridge Enable

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	D	D

Current Limit

Function: Sets the overcurrent threshold for each channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0898 (0 to 2.2A)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing milliamps. LSB = 1mA.

Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision

  Floating Point Value (IEEE-754) in amps.

Read/Write: R/W

Initialized Value: 0x898 (2.2A)

Operational Settings: This setting is the value that is used for the overcurrent threshold for each channel. This value is applied to both positive and negative currents.

Note

The maximum value for the Current Limit is 2.2A (the maximum continuous current is 2A, but it is recommended that the threshold be programmed to an additional 10%, which equals 2.2A).

Overcurrent Reset

Function: Resets tri-stated channels in Overcurrent Latched Status register following an overcurrent condition as measured by the Drive Current Measured register.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: W

Initialized Value: 0

Operational Settings: 1 is written to reset disabled channels. Processor will write a 0 back to the Overcurrent Reset register when reset process is complete.

Overcurrent Reset

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

VCC Minimum Voltage Value

Function: Sets the threshold for the minimum VCC supply voltage. If the measured voltage drops below this value, the status bit for VCC Undervoltage will be set.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: 0xFFFF FD76 to 0x0000 028A (-65.0V to +65.0V)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing volts. LSB = 100mV.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in volts.

Read/Write: R/W

Initialized Value: 0x104 (+26.0V)

Operational Settings: This register only affects when the status bit is set, the drive will not be disabled by this threshold.

VCC Maximum Voltage Value

Function: Sets the threshold for the maximum VCC supply voltage. If the measured voltage rises above this value, the status bit for power VCC Overvoltage will be set.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: 0xFFFF FD76 to 0x0000 028A (-65.0V to +65.0V)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing volts. LSB = 100mV.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision  Floating Point Value (IEEE-754) in volts.

Read/Write: R/W

Initialized Value: 0x12C (+30.0V)

Operational Settings: This register only affects when the status bit is set, the drive will not be disabled by this threshold.

VSS Minimum Voltage Value

Function: Sets the threshold for the minimum VSS supply voltage. If the measured voltage drops below this value, the status bit for VSS Undervoltage will be set.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: 0xFFFF FD76 to 0x0000 028A (-65.0V to +65.0V)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing volts. LSB = 10 mV.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in volts.

Read/Write: R/W

Initialized Value: 0xFFFF FF38 (-2.0V)

Operational Settings: This register only affects when the status bit is set, the drive will not be disabled by this threshold.

VSS Maximum Voltage Value

Function: Sets the threshold for the maximum VSS supply voltage. If the measured voltage rises above this value, the status bit for VSS Overvoltage will be set.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: 0xFFFF FD76 to 0x0000 028A (-65.0V to +65.0V)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing volts. LSB = 100mV.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in volts.

Read/Write: R/W

Initialized Value: 0xC8 (+2.0V)

Operational Settings: This register only affects when the status bit is set, the drive will not be disabled by this threshold.

Discrete Output Measurement Registers

The measured voltage and current for the discrete output and the supply, as well as the drive temperature, can be read for each discrete channel.

Drive Voltage (Sampled)

Function: Reads actual voltage at the output pin per individual channel.

Type: signed binary word (32-bit)

Data Range: 0xFFFF FD76 to 0x0000 028A (-65.0V to +65.0V)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing volts. LSB = 100mV.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in volts.

Read/Write: R

Initialized Value: Updated by module as per conditions

Operational Settings: Value is a signed binary 32-bit word, where LSB = 100mV. Data is read as 2’s complement number. For example, if output voltage word is 0x00F0 (240d), actual voltage is 24.0V.

Drive Voltage (Sampled)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Drive Voltage (RMS)

Function: Reads averaged RMS voltage at output pin per individual channel.

Type: signed binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 028A (0.0V to 65.0V)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing volts. LSB = 100mV.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in volts.

Read/Write: R

Initialized Value: Updated by module as per conditions

Operational Settings: Value is a signed binary 32-bit word, where LSB = 100mV. Data is read as 2’s complement number. For example, if output voltage word is 0x00F0 (240d), actual voltage is 24.0V.

Drive Voltage (RMS)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Drive Current (Sampled)

Function: Reads the output current through the output pin per individual channel.

Type: signed binary word (32-bit)

Data Range: 0xFFFF F768 to 0x0000 0898 (-2.2A to 2.2A)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing milliamps. LSB = 1mA.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision  Floating Point Value (IEEE-754) in amps.

Read/Write: R

Initialized Value: Updated by module as per conditions

Operational Settings: Value is a signed binary 32-bit word, where LSB = 1mA. Data is read as 2’s complement number. For example, if output current word is 0x0064 (100d), actual current is 100mA.

Drive Current (Sampled)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Drive Current (RMS)

Function: Reads averaged RMS output current through the output pin per individual channel.

Type: signed binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0898 (0.0A to 2.2A)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing milliamps. LSB = 1mA.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in amps.

Read/Write: R

Initialized Value: Updated by module as per conditions

Operational Settings: Value is a signed binary 32-bit word, where LSB = 1 mA. Data is read as 2’s complement number. For example, if output current word is 0x0064 (100d), actual current is 100mA.

Drive Current (RMS)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

VCC Voltage Measured

Function: Measures the user-applied VCC voltage.

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: 0xFFFF FD76 to 0x0000 028A (-65.0V to +65.0V)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing volts. LSB = 100mV.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in volts.

Read/Write: R

Initialized Value: N/A

Operational Settings: Value is a signed binary 32-bit word, where LSB = 100mV. Data is read as 2’s complement number. For example, if output voltage word is 0x00F0 (240d), actual voltage is 24.0V.

VCC Voltage Measured

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

VCC Current Measured

Function: Measures the VCC power supply current.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: 0xFFFF F768 to 0x0000 0898 (-2.2A to 2.2A)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing milliamps. LSB = 1mA.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in amps.

Read/Write: R

Initialized Value: N/A

Operational Settings: Value is a signed binary 32-bit word, where LSB = 1 mA. Data is read as 2’s complement number. For example, if output current word is 0x0064 (100d), actual current is 100mA.

VCC Current Measured

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

VSS Voltage Measured

Function: Measures the user-applied VSS voltage.

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: 0xFFFF FD76 to 0x0000 028A (-65.0V to +65.0V)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing volts. LSB = 100mV.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in volts.

Read/Write: R

Initialized Value: N/A

Operational Settings: Value is a signed binary 32-bit word, where LSB = 100mV. Data is read as 2’s complement number. For example, if output voltage word is 0x00F0 (240d), actual voltage is 24.0V.

VSS Voltage Measured

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

VSS Current Measured

Function: Measures the VSS power supply current.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: 0xFFFF F768 to 0x0000 0898 (-2.2A to 2.2A)

Enable Floating Point Mode: 0 (Integer Mode)

  Signed 32-bit value representing milliamps. LSB = 1mA.

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in amps.

Read/Write: R

Initialized Value: N/A

Value is a signed binary 32-bit word, where LSB = 1 mA. Data is read as 2’s complement number. For example, if output current word is 0x0064 (100d), actual current is 100mA.

VSS Current Measured

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Driver Temperature

Function: Driver temperature near the FETs in degrees Celsius.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: N/A.

Enable Floating Point Mode: 0 (Integer Mode)

  (2's compliment signed 32-bit value) with LSB = 1°C

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754) in degrees Celsius.

Read/Write: R

Initialized Value: N/A

Watchdog Timer Registers

Refer to ‘Watchdog Timer Module Manual’ for the Watchdog Timer register descriptions.

Module Common Registers

Refer to “Module Common Registers Module Manual” for the register descriptions.

Status and Interrupt Registers

The Discrete Output Function Module provides status registers for BIT, overcurrent, VCC/VSS undervoltage, VCC/VSS overvoltage, VCC/VSS surge suppressor fault, driver over-temperature and watchdog timer fault.

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

BIT Status

BIT Dynamic Status
BIT Latched Status
BIT Interrupt Enable
BIT Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Overcurrent Status

There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Overcurrent Status

Overcurrent Dynamic Status
Overcurrent Latched Status
Overcurrent Interrupt Enable
Overcurrent Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Function: Sets the corresponding bit associated with the channel’s Overcurrent error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

VCC Undervoltage

There are four registers associated with the VCC Undervoltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

VCC Undervoltage Status

VCC Undervoltage Dynamic Status
VCC Undervoltage Latched Status
VCC Undervoltage Interrupt Enable
VCC Undervoltage Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Bank2	Bank1

Function: Sets the corresponding bit associated with the channel’s VCC Undervoltage error.

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0x3

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

VCC Overvoltage

There are four registers associated with the VCC Overvoltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

VCC Overvoltage Status

VCC Overvoltage Dynamic Status
VCC Overvoltage Latched Status
VCC Overvoltage Interrupt Enable
VCC Overvoltage Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Bank2	Bank1

Function: Sets the corresponding bit associated with the channel’s VCC Overvoltage error.

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0x3

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

VCC Surge Suppressor Fault

There are four registers associated with the VCC Surge Suppressor Fault Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

VCC Surge Suppressor Fault Status

VCC Surge Suppressor Fault Dynamic Status
VCC Surge Suppressor Fault Latched Status
VCC Surge Suppressor Fault Interrupt Enable
VCC Surge Suppressor Fault Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Bank2	Bank1

Function: Sets the corresponding bit associated with the channel’s VCC Surge Suppressor fault error.

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0x3

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

VSS Undervoltage

There are four registers associated with the VSS Undervoltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

VSS Undervoltage Status

VSS Undervoltage Dynamic Status
VSS Undervoltage Latched Status
VSS Undervoltage Interrupt Enable
VSS Undervoltage Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Bank2	Bank1

Function: Sets the corresponding bit associated with the channel’s VSS Undervoltage error.

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0x3

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

VSS Overvoltage

There are four registers associated with the VSS Overvoltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

VSS Overvoltage Status

VSS Overvoltage Dynamic Status
VSS Overvoltage Latched Status
VSS Overvoltage Interrupt Enable
VSS Overvoltage Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Bank2	Bank1

Function: Sets the corresponding bit associated with the channel’s VSS Overvoltage error.

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0x3

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

VSS Surge Suppressor Fault

There are four registers associated with the VSS Surge Suppressor Fault Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

VSS Surge Suppressor Fault

VSS Surge Suppressor Fault Dynamic Status
VSS Surge Suppressor Fault Latched Status
VSS Surge Suppressor Fault Interrupt Enable
VSS Surge Suppressor Fault Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Bank2	Bank1

Function: Sets the corresponding bit associated with the channel’s VSS Surge Suppressor Fault error.

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0x3

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Driver Over-Temperature Fault

There are four registers associated with the Driver Over-Temperature Fault Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Driver Over-Temperature Fault Status

Driver Over-Temperature Fault Dynamic Status
Driver Over-Temperature Fault Latched Status
Driver Over-Temperature Fault Interrupt Enable
Driver Over-Temperature Fault Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Bank2	Bank1

Function: Sets the corresponding bit associated with the channel’s Driver Over-Temperature Fault error.

Type: unsigned binary word (32-bit)

Data Range: 0x0 to 0x3

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

*Initialized Value: 0

User Watchdog Timer Fault Status

The Discrete Modules provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status Register descriptions.

Summary Status

There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Summary Status

Summary Dynamic Status
Summary Latched Status
Summary Interrupt Enable
Summary Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Function: Sets the corresponding bit when a fault is detected for BIT, overcurrent, undervoltage (VCC & VSS), overvoltage (VCC & VSS), surge suppressor fault (VCC & VSS), driver over-temperature or watchdog timer fault on that channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note

The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector

Function: Set an identifier for the interrupt.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering

Function: Sets where to direct the interrupt.

Type: unsigned binary word (32-bit)

Data Range: See table Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME	1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)	2
Direct Interrupt to PCIe Bus	5
Direct Interrupt to cPCI Bus	6

FUNCTION REGISTER MAP

Key:

Bold Italic = Configuration/Control

Bold Underline = State/Measurement/Status

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).

• Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).

Discrete Output Registers

0x2000	Output Mode Ch 1	R/W
0x2100	Output Mode Ch 2	R/W
0x2200	Output Mode Ch 3	R/W
0x2300	Output Mode Ch 4	R/W

0x2018	PWM Period Ch 1	R/W
0x2118	PWM Period Ch 2	R/W
0x2218	PWM Period Ch 3	R/W
0x2318	PWM Period Ch 4	R/W

0x201C	PWM Pulse Width Ch 1	R/W
0x211C	PWM Pulse Width Ch 2	R/W
0x221C	PWM Pulse Width Ch 3	R/W
0x222C	PWM Pulse Width Ch 4	R/W

0x1000	Drive Output High/Low/Tristate Ch 1-4	R/W

0x1004	Output Format Ch 1-4	R/W

0x1010	PWM Enable Ch 1-4	R/W

0x2020	PWM Burst Count Ch 1	R/W
0x2120	PWM Burst Count Ch 2	R/W
0x2220	PWM Burst Count Ch 3	R/W
0x2320	PWM Burst Count Ch 4	R/W

Discrete Output Control Registers

0x1008	Full Bridge Enable	R/W

0x100C	Overcurrent Reset Ch 1-4	R/W

0x2004	Current Limit Ch 1	R/W
0x2104	Current Limit Ch 2	R/W
0x2204	Current Limit Ch 3	R/W
0x2304	Current Limit Ch 4	R/W

0x1808	VCC Minimum Voltage Bank 1	R/W
0x180C	VCC Maximum Voltage Bank 1	R/W
0x1818	VSS Minimum Voltage Bank 1	R/W
0x181C	VSS Maximum Voltage Bank 1	R/W

0x1908	VCC Minimum Voltage Bank 2	R/W
0x190C	VCC Maximum Voltage Bank 2	R/W
0x1918	VSS Minimum Voltage Bank 2	R/W
0x191C	VSS Maximum Voltage Bank 2	R/W

Discrete Output Measurement Registers

0x2008	Drive Voltage (Sampled) Ch 1	R
0x2108	Drive Voltage (Sampled) Ch 2	R
0x2208	Drive Voltage (Sampled) Ch 3	R
0x2308	Drive Voltage (Sampled) Ch 4	R

0x200C	Drive Voltage (RMS) Ch 1	R
0x210C	Drive Voltage (RMS) Ch 2	R
0x220C	Drive Voltage (RMS) Ch 3	R
0x230C	Drive Voltage (RMS) Ch 4	R

0x2010	Drive Current (Sampled) Ch 1	R
0x2110	Drive Current (Sampled) Ch 2	R
0x2210	Drive Current (Sampled) Ch 3	R
0x2310	Drive Current (Sampled) Ch 4	R

0x2014	Drive Current (RMS) Ch 1	R
0x2114	Drive Current (RMS) Ch 2	R
0x2214	Drive Current (RMS) Ch 3	R
0x2314	Drive Current (RMS) Ch 4	R

0x1800	VCC Voltage Measured Bank 1	R
0x1804	VCC Current Measured Bank 1	R
0x1810	VSS Voltage Measured Bank 1	R
0x1814	VSS Current Measured Bank 1	R

0x1900	Vcc Voltage Measured Bank 2	R
0x1904	Vcc Current Measured Bank 2	R
0x1910	Vss Voltage Measured Bank 2	R
0x1914	Vss Current Measured Bank 2	R

0x1820	Drive Temperature Bank 1	R
0x1920	Drive Temperature Bank 2	R

Watchdog Timer Registers

The Discrete Module provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status Function Register Map.

Module Common Registers

Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.

Status Registers

BIT Status

0x0800	Dynamic Status	R
0x0804	Latched Status*	R/W
0x0808	Interrupt Enable	R/W
0x080C	Set Edge/Level Interrupt	R/W

Overcurrent Status

0x0810	Dynamic Status	R
0x0814	Latched Status*	R/W
0x0818	Interrupt Enable	R/W
0x081C	Set Edge/Level Interrupt	R/W

VCC Undervoltage Status

0x0820	Dynamic Status	R
0x0824	Latched Status*	R/W
0x0828	Interrupt Enable	R/W
0x082C	Set Edge/Level Interrupt	R/W

VCC Overvoltage Status

0x0830	Dynamic Status	R
0x0834	Latched Status*	R/W
0x0838	Interrupt Enable	R/W
0x083C	Set Edge/Level Interrupt	R/W

VCC Surge Suppressor Fault

0x0840	Dynamic Status	R
0x0844	Latched Status*	R/W
0x0848	Interrupt Enable	R/W
0x084C	Set Edge/Level Interrupt	R/W

VSS Undervoltage

0x0850	Dynamic Status	R
0x0854	Latched Status*	R/W
0x0858	Interrupt Enable	R/W
0x085C	Set Edge/Level Interrupt	R/W

VSS Overvoltage

0x0860	Dynamic Status	R
0x0864	Latched Status*	R/W
0x0868	Interrupt Enable	R/W
0x086C	Set Edge/Level Interrupt	R/W

VSS Surge Suppressor Fault

0x0870	Dynamic Status	R
0x0874	Latched Status*	R/W
0x0878	Interrupt Enable	R/W
0x087C	Set Edge/Level Interrupt	R/W

Driver Over-Temperature Fault

0x0880	Dynamic Status	R
0x0884	Latched Status*	R/W
0x0888	Interrupt Enable	R/W
0x088C	Set Edge/Level Interrupt	R/W

User Watchdog Timer Fault Status

The Discrete Modules provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status Function Register Map.

Summary Status

0x09A0	Dynamic Status	R
0x09A4	Latched Status*	R/W
0x09A8	Interrupt Enable	R/W
0x09AC	Set Edge/Level Interrupt	R/W

Interrupt Registers

The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.

0x0500	Module 1 Interrupt Vector 1 - BIT	R/W
0x0504 to 0x0540	Module 1 Interrupt Vector 2-17 - Reserved	R/W
0x0544	Module 1 Interrupt Vector 18 - Overcurrent	R/W
0x0548	Module 1 Interrupt Vector 19 - Reserved	R/W
0x054C	Module 1 Interrupt Vector 20 - Undervoltage	R/W
0x0550	Module 1 Interrupt Vector 21 - Overvoltage	R/W
0x0554	Module 1 Interrupt Vector 22 - Driver Over-Temperature	R/W
0x0558	Module 1 Interrupt Vector 23 -Surge Suppressor Fault	R/W
0x055C to 0x0564	Module 1 Interrupt Vector 24-26 - Reserved	R/W
0x0568	Module 1 Interrupt Vector 27 - Summary	R/W
0x056C	Module 1 Interrupt Vector 28 - User Watchdog Timer Fault	R/W
0x0570 to 0x057C	Module 1 Interrupt Vector 29-32 - Reserved	R/W

0x0600	Module 1 Interrupt Steering 1 - BIT	R/W
0x0604 to 0x0640	Module 1 Interrupt Steering 2-17 - Reserved	R/W
0x0644	Module 1 Interrupt Steering 18 - Overcurrent	R/W
0x0648	Module 1 Interrupt Steering 19 - Reserved	R/W
0x064C	Module 1 Interrupt Steering 20 - Undervoltage	R/W
0x0650	Module 1 Interrupt Steering 21 - Overvoltage	R/W
0x0654	Module 1 Interrupt Steering 22 - Driver Over-Temperature	R/W
0x0658	Module 1 Interrupt Steering 23 -Surge Suppressor Fault	R/W
0x065C to 0x0664	Module 1 Interrupt Steering 24-26 - Reserved	R/W
0x0668	Module 1 Interrupt Steering 27 - Summary	R/W
0x066C	Module 1 Interrupt Steering 28 - User Watchdog Timer Fault	R/W
0x0670 to 0x067C	Module 1 Interrupt Steering 29-32 - Reserved	R/W

0x0700	Module 2 Interrupt Vector 1 - BIT	R/W
0x0704 to 0x0740	Module 2 Interrupt Vector 2-17 - Reserved	R/W
0x0744	Module 2 Interrupt Vector 18 - Overcurrent	R/W
0x0748	Module 2 Interrupt Vector 19 - Reserved	R/W
0x074C	Module 2 Interrupt Vector 20 - Undervoltage	R/W
0x0750	Module 2 Interrupt Vector 21 - Overvoltage	R/W
0x0754	Module 2 Interrupt Vector 22 - Driver Over-Temperature	R/W
0x0758	Module 2 Interrupt Vector 23 -Surge Suppressor Fault	R/W
0x075C to 0x0764	Module 2 Interrupt Vector 24-26 - Reserved	R/W
0x0768	Module 2 Interrupt Vector 27 - Summary	R/W
0x076C	Module 2 Interrupt Vector 28 - User Watchdog Timer Fault	R/W
0x0770 to 0x077C	Module 2 Interrupt Vector 29-32 - Reserved	R/W

0x0800	Module 2 Interrupt Steering 1 - BIT	R/W
0x0804 to 0x0840	Module 2 Interrupt Steering 2-17 - Reserved	R/W
0x0844	Module 2 Interrupt Steering 18 - Overcurrent	R/W
0x0848	Module 2 Interrupt Steering 19 - Reserved	R/W
0x084C	Module 2 Interrupt Steering 20 - Undervoltage	R/W
0x0850	Module 2 Interrupt Steering 21 - Overvoltage	R/W
0x0854	Module 2 Interrupt Steering 22 - Driver Over-Temperature	R/W
0x0858	Module 2 Interrupt Steering 23 -Surge Suppressor Fault	R/W
0x085C to 0x0864	Module 2 Interrupt Steering 24-26 - Reserved	R/W
0x0868	Module 2 Interrupt Steering 27 - Summary	R/W
0x086C	Module 2 Interrupt Steering 28 - User Watchdog Timer Fault	R/W
0x0870 to 0x087C	Module 2 Interrupt Steering 29-32 - Reserved	R/W

0x0900	Module 3 Interrupt Vector 1 - BIT	R/W
0x0904 to 0x0940	Module 3 Interrupt Vector 2-17 - Reserved	R/W
0x0944	Module 3 Interrupt Vector 18 - Overcurrent	R/W
0x0948	Module 3 Interrupt Vector 19 - Reserved	R/W
0x094C	Module 3 Interrupt Vector 20 - Undervoltage	R/W
0x0950	Module 3 Interrupt Vector 21 - Overvoltage	R/W
0x0954	Module 3 Interrupt Vector 22 - Driver Over-Temperature	R/W
0x0958	Module 3 Interrupt Vector 23 -Surge Suppressor Fault	R/W
0x095C to 0x0964	Module 3 Interrupt Vector 24-26 - Reserved	R/W
0x0968	Module 3 Interrupt Vector 27 - Summary	R/W
0x096C	Module 3 Interrupt Vector 28 - User Watchdog Timer Fault	R/W
0x0970 to 0x097C	Module 3 Interrupt Vector 29-32 - Reserved	R/W

0x0A00	Module 3 Interrupt Steering 1 - BIT	R/W
0x0A04 to 0x0A40	Module 3 Interrupt Steering 2-17 - Reserved	R/W
0x0A44	Module 3 Interrupt Steering 18 - Overcurrent	R/W
0x0A48	Module 3 Interrupt Steering 19 - Reserved	R/W
0x0A4C	Module 3 Interrupt Steering 20 - Undervoltage	R/W
0x0A50	Module 3 Interrupt Steering 21 - Overvoltage	R/W
0x0A54	Module 3 Interrupt Steering 22 - Driver Over-Temperature	R/W
0x0A58	Module 3 Interrupt Steering 23 -Surge Suppressor Fault	R/W
0x0A5C to 0x0A64	Module 3 Interrupt Steering 24-26 - Reserved	R/W
0x0A68	Module 3 Interrupt Steering 27 - Summary	R/W
0x0A6C	Module 3 Interrupt Steering 28 - User Watchdog Timer Fault	R/W
0x0A70 to 0x0A7C	Module 3 Interrupt Steering 29-32 - Reserved	R/W

0x0B00	Module 4 Interrupt Vector 1 - BIT	R/W
0x0B04 to 0x0B40	Module 4 Interrupt Vector 2-17 - Reserved	R/W
0x0B44	Module 4 Interrupt Vector 18 - Overcurrent	R/W
0x0B48	Module 4 Interrupt Vector 19 - Reserved	R/W
0x0B4C	Module 4 Interrupt Vector 20 - Undervoltage	R/W
0x0B50	Module 4 Interrupt Vector 21 - Overvoltage	R/W
0x0B54	Module 4 Interrupt Vector 22 - Driver Over-Temperature	R/W
0x0B58	Module 4 Interrupt Vector 23 -Surge Suppressor Fault	R/W
0x0B5C to 0x0B64	Module 4 Interrupt Vector 24-26 - Reserved	R/W
0x0B68	Module 4 Interrupt Vector 27 - Summary	R/W
0x0B6C	Module 4 Interrupt Vector 28 - User Watchdog Timer Fault	R/W
0x0B70 to 0x0B7C	Module 4 Interrupt Vector 29-32 - Reserved	R/W

0x0C00	Module 4 Interrupt Steering 1 - BIT	R/W
0x0C04 to 0x0E40	Module 4 Interrupt Steering 2-17 - Reserved	R/W
0x0C44	Module 4 Interrupt Steering 18 - Overcurrent	R/W
0x0C48	Module 4 Interrupt Steering 19 - Reserved	R/W
0x0C4C	Module 4 Interrupt Steering 20 - Undervoltage	R/W
0x0C50	Module 4 Interrupt Steering 21 - Overvoltage	R/W
0x0C54	Module 4 Interrupt Steering 22 - Driver Over-Temperature	R/W
0x0C58	Module 4 Interrupt Steering 23 -Surge Suppressor Fault	R/W
0x0C5C to 0x0E64	Module 4 Interrupt Steering 24-26 - Reserved	R/W
0x0C68	Module 4 Interrupt Steering 27 - Summary	R/W
0x0C6C	Module 4 Interrupt Steering 28 - User Watchdog Timer Fault	R/W
0x0C70 to 0x0C7C	Module 4 Interrupt Steering 29-32 - Reserved	R/W

0x0D00	Module 5 Interrupt Vector 1 - BIT	R/W
0x0D04 to 0x0D40	Module 5 Interrupt Vector 2-17 - Reserved	R/W
0x0D44	Module 5 Interrupt Vector 18 - Overcurrent	R/W
0x0D48	Module 5 Interrupt Vector 19 - Reserved	R/W
0x0D4C	Module 5 Interrupt Vector 20 - Undervoltage	R/W
0x0D50	Module 5 Interrupt Vector 21 - Overvoltage	R/W
0x0D54	Module 5 Interrupt Vector 22 - Driver Over-Temperature	R/W
0x0D58	Module 5 Interrupt Vector 23 -Surge Suppressor Fault	R/W
0x0D5C to 0x0D64	Module 5 Interrupt Vector 24-26 - Reserved	R/W
0x0D68	Module 5 Interrupt Vector 27 - Summary	R/W
0x0D6C	Module 5 Interrupt Vector 28 - User Watchdog Timer Fault	R/W
0x0D70 to 0x0D7C	Module 5 Interrupt Vector 29-32 - Reserved	R/W

0x0E00	Module 5 Interrupt Steering 1 - BIT	R/W
0x0E04 to 0x0E40	Module 5 Interrupt Steering 2-17 - Reserved	R/W
0x0E44	Module 5 Interrupt Steering 18 - Overcurrent	R/W
0x0E48	Module 5 Interrupt Steering 19 - Reserved	R/W
0x0E4C	Module 5 Interrupt Steering 20 - Undervoltage	R/W
0x0E50	Module 5 Interrupt Steering 21 - Overvoltage	R/W
0x0E54	Module 5 Interrupt Steering 22 - Driver Over-Temperature	R/W
0x0E58	Module 5 Interrupt Steering 23 -Surge Suppressor Fault	R/W
0x0E5C to 0x0E64	Module 5 Interrupt Steering 24-26 - Reserved	R/W
0x0E68	Module 5 Interrupt Steering 27 - Summary	R/W
0x0E6C	Module 5 Interrupt Steering 28 - User Watchdog Timer Fault	R/W
0x0E70 to 0x0E7C	Module 5 Interrupt Steering 29-32 - Reserved	R/W

0x0F00	Module 6 Interrupt Vector 1 - BIT	R/W
0x0F04 to0x0F4	Module 6 Interrupt Vector 2-17 - Reserved	R/W
0x0F44	Module 6 Interrupt Vector 18 - Overcurrent	R/W
0x0F48	Module 6 Interrupt Vector 19 - Reserved	R/W
0x0F4C	Module 6 Interrupt Vector 20 - Undervoltage	R/W
0x0F50	Module 6 Interrupt Vector 21 -Overvoltage	R/W
0x0F54	Module 6 Interrupt Vector 22 - Driver Over-Temperature	R/W 0x0F58
Module 6 Interrupt Vector 23 - Surge Suppressor Fault	R/W	0x0F5C to 0x0F64
Module 6 Interrupt Vector 24-26 -Reserved	R/W	0x0F68
Module 6 Interrupt Vector 27 - Summary	R/W	0x0F6C
Module 6 Interrupt Vector 28 - User Watchdog Timer Fault	R/W	0x0F70 to0x0F7C
Module 6 Interrupt Vector 29-32 - Reserved	R/W

0x1000	Module 6 Interrupt Steering 1 - BIT	R/W
0x1004 to 0x1040	Module 6 Interrupt Steering 2-17 - Reserved	R/W
0x1044	Module 6 Interrupt Steering 18 - Overcurrent	R/W
0x1048	Module 6 Interrupt Steering 19 - Reserved	R/W
0x104C	Module 6 Interrupt Steering 20 - Undervoltage	R/W
0x1050	Module 6 Interrupt Steering 21 - Overvoltage	R/W
0x1054	Module 6 Interrupt Steering 22 - Driver Over-Temperature	R/W
0x1058	Module 6 Interrupt Steering 23 - Surge Suppressor Fault	R/W
0x105C to 0x1064	Module 6 Interrupt Steering 24-26 - Reserved	R/W
0x106	Module 6 Interrupt Steering 27 - Summary	R/W
0x106	Module 6 Interrupt Steering 28 - User Watchdog Timer Fault	R/W
0x1070 to 0x107C	Module 6 Interrupt Steering 29-32 - Reserved	R/W

APPENDIX: PIN-OUT DETAILS

Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals

Module Signal(Ref Only)	44-Pin I/O	50-Pin I/O (Mod Slot 1-J3)	50-Pin I/O (Mod Slot 2-J4)	50-Pin I/O (Mod Slot 3-J3)	50-Pin I/O (Mod Slot 3-J4)	DT3
DATIO1	2	10	1	2		CH1-DRV
DATIO2	24	35	26	27		CH1-DRV
DATIO3	3	11	2	3		CH1-DRV
DATIO4	25	36	27	28		CH1-DRV
DATIO5	5	13	4	5		VCC1
DATIO6	27	38	29	30		VSS1
DATIO7	7	14	5	6		CH2-DRV
DATIO8	29	39	30	31		CH2-DRV
DATIO9	8	15	6	7		CH2-DRV
DATIO10	30	40	31	32		CH2-DRV
DATIO11	10	10	17	8	9	VCC1
DATIO12	32	42	33	34		VSS1
DATIO13	12	18	9		17	CH3-DRV
DATIO14	34	43	34		42	CH3-DRV
DATIO15	13	19	10		18	CH3-DRV
DATIO16	35	44	35		43	CH3-DRV
DATIO17	15	21	12		20	VCC2
DATIO18	37	46	37		45	VSS2
DATIO19	17	22	13		21	CH4-DRV
DATIO20	39	47	38		46	CH4-DRV
DATIO21	18	23	14		22	CH4-DRV
DATIO22	40	48	39		47	CH4-DRV
DATIO23	20	25	16		24	VCC2
DATIO24	42	50	41		49	VSS2
DATIO25	4	12	3	4
DATIO26	26	37	28	29
DATIO27	9	16	7	8
DATIO28	31	41	32	33		ISO-GND1
DATIO29	14	20	11		19
DATIO30	36	45	36		44
DATIO31	19	24	15		23
DATIO32	41	49	40		48	ISO-GND2
DATIO33	6
DATIO34	28
DATIO35	11					EXT-SYNC+
DATIO36	33					EXT-SYNC
DATIO37	16
DATIO38	38
DATIO39	21
DATIO40	43
N/A

STATUS AND INTERRUPTS

Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.

For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.

Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.

Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).

Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.

Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).

• Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edge-triggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.

• Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Interrupt Trigger Types

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

---

Dynamic and Latched Status Registers Examples

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

		No Clearing of Latched Status	Clearing of Latched Status (Edge-Triggered)		Clearing of Latched Status(Level-Triggered)
Time	Dynamic Status	Latched Status	Action	Latched Status	Action	Latched
T0	0x0	0x0	Read Latched Register	0x0	Read Latched Register	0x0
T1	0x1	0x1	Read Latched Register	0x1		0x1
T1	0x1	0x1	Write 0x1 to Latched Register		Write 0x1 to Latched Register
T1	0x1	0x1		0x0		0x1
T2	0x0	0x1	Read Latched Register	0x0	Read Latched Register	0x1
T2	0x0	0x1	Read Latched Register	0x0	Write 0x1 to Latched Register
T2	0x0	0x1	Read Latched Register	0x0		0x0
T3	0x2	0x3	Read Latched Register	0x2	Read Latched Register	0x2
T3	0x2	0x3	Write 0x2 to Latched Register		Write 0x2 to Latched Register
T3	0x2	0x3		0x0		0x2
T4	0x2	0x3	Read Latched Register	0x1	Read Latched Register	0x3
T4	0x2	0x3	Write 0x1 to Latched Register		Write 0x3 to Latched Register
T4	0x2	0x3		0x0		0x2
T5	0xC	0xF	Read Latched Register	0xC	Read Latched Register	0xE
T5	0xC	0xF	Write 0xC to Latched Register		Write 0xE to Latched Register
T5	0xC	0xF		0x0		0xC
T6	0xC	0xF	Read Latched Register	0x0	Read Latched	0xC
T6	0xC	0xF	Read Latched Register	0x0	Write 0xC to Latched Register
T6	0xC	0xF	Read Latched Register	0x0		0xC
T7	0x4	0xF	Read Latched Register	0x0	Read Latched Register	0xC
T7	0x4	0xF	Read Latched Register	0x0	Write 0xC to Latched Register
T7	0x4	0xF	Read Latched Register	0x0		0x4
T8	0x4	0xF	Read Latched Register	0x0	Read Latched Register	0x4

Interrupt Examples

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

Time	Latched Status (Edge-Triggered - Clear Multi-Channel)		Latched Status (Edge-Triggered - Clear Single Channel) 2+		Latched Status (Level-Triggered - Clear Multi-Channel)	Action
	Latched	Action	Latched	Action	Latched	T1 (Int 1)
Interrupt Generated++``+ Read Latched Registers	0x1	Interrupt Generated++``+ Read Latched Registers	0x1	Interrupt Generated++``+ Read Latched Registers	0x1	T1 (Int 1)
Write 0x1 to Latched Register		Write 0x1 to Latched Register		Write 0x1 to Latched Register		T1 (Int 1)
	0x0		0x0	Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear until T2.	0x1	T3 (Int 2)
Interrupt Generated++``+ Read Latched Registers	0x2	Interrupt Generated++``+ Read Latched Registers	0x2	Interrupt Generated++``+ Read Latched Registers	0x2	T3 (Int 2)
Write 0x2 to Latched Register		Write 0x2 to Latched Register		Write 0x2 to Latched Register		T3 (Int 2)
	0x0		0x0	Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear until T7.	0x2	T4 (Int 3)
Interrupt Generated++``+ Read Latched Registers	0x1	Interrupt Generated++``+ Read Latched Registers	0x1	Interrupt Generated++``+ Read Latched Registers	0x3	T4 (Int 3)
Write 0x1 to Latched Register		Write 0x1 to Latched Register		Write 0x3 to Latched Register		T4 (Int 3)
	0x0		0x0	Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.	0x3	T4 (Int 3)
	0x0		0x0	Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear until T7.	0x2	T6 (Int 4)
Interrupt Generated++``+ Read Latched Registers	0xC	Interrupt Generated++``+ Read Latched Registers	0xC	Interrupt Generated++``+ Read Latched Registers	0xE	T6 (Int 4)
Write 0xC to Latched Register		Write 0x4 to Latched Register		Write 0xE to Latched Register		T6 (Int 4)
	0x0	Interrupt re-triggers++``+ Write 0x8 to Latched Register	0x8	Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.	0xE	T6 (Int 4)
	0x0		0x0	Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.	0xC	T6 (Int 4)
	0x0		0x0	Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.	0x4

REVISION HISTORY

Motherboard Manual - Status and Interrupts Revision History
Revision	Revision Date	Description
C	2021-11-30	C08896; Transition manual to docbuilder format - no technical info change.

DOCS.NAII REVISIONS

Revision Date	Description
2026-03-02	Formatting updates to document; no technical changes.

Link to original

USER WATCHDOG TIMER MODULE MANUAL

User Watchdog Timer Capability

The User Watchdog Timer (UWDT) Capability is available on the following modules:

• AC Reference Source Modules

  • AC1 - 1 Channel, 2-115 Vrms, 47 Hz - 20kHz
  • AC2 - 2 Channels, 2-28 Vrms, 47 Hz - 20kHz
  • AC3 - 1 Channel, 28-115 Vrms, 47 Hz - 2.5 kHz

• Differential Transceiver Modules

  • DF1/DF2 - 16 Channels Differential I/O

• Digital-to-Analog (D/A) Modules

  • DA1 - 12 Channels, ±10 VDC @ 25 mA, Voltage or Current Control Modes
  • DA2 - 16 Channels, ±10 VDC @ 10 mA
  • DA3 - 4 Channels, ±40 VDC @ ±100 mA, Voltage or Current Control Modes
  • DA4 - 4 Channels, ±80 VDC @ 10 mA
  • DA5 - 4 Channels, ±65 VDC or ±2 A, Voltage or Current Control Modes

• Digital-to-Synchro/Resolver (D/S) or Digital-to-L( R )VDT (D/LV) Modules

  • (Not supported)

• Discrete I/O Modules

  • DT1/DT4 - 24 Channels, Programmable for either input or output, output up to 500 mA per channel from an applied external 3 - 60 VCC source.

  • DT2/DT5 - 16 Channels, Programmable for either input voltage measurements (±80 V) or as a bi-directional current switch (up to 500 mA per channel).

  • DT3/DT6 - 4 Channels, Programmable for either input voltage measurements (±100 V) or as a bi-directional current switch (up to 3 A per channel).

• TTL/CMOS Modules

  • TL1-TL8 - 24 Channels, Programmable for either input or output.

Principle of Operation

The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.

The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:

• The application must not strobe during the Quiet time.
• The application must strobe within the Window time.
• The application must not strobe more than once in a single window time.

A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.

The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.

The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.

Figure 1. User Watchdog Timer Overview

Figure 2. User Watchdog Timer Example

Figure 3. User Watchdog Timer Failures

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

User Watchdog Timer Registers

The registers associated with the User Watchdog Timer provide the ability to specify the UWDT Quiet Time and the UWDT Window that will be monitored to ensure that EXACTLY ONE User Watchdog Timer (UWDT) Strobe is written within the window.

UWDT Quiet Time
Function:	Sets Quiet Time value (in microseconds) to use for the User Watchdog Timer Frame.
Type:	unsigned binary word (32-bit)
Data Range:	0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	LSB = 1 µsec. The application must NOT write a strobe in the time between the previous strobe and the end of the Quiet time interval. In addition, the application must write in the UWDT Window EXACTLY ONCE.
UWDT Window
Function:	Writes the window value (in microseconds) to be used for the User Watchdog Timer Frame.
Type:	unsigned binary word (32-bit)
Data Range:	0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	LSB = 1 µsec. The application must write the strobe once within the Window time after the end of the Quiet time interval. The application must write in the UWDT Window EXACTLY ONCE. This setting must be initialized to a non-zero value for operation and should allow sufficient tolerance for strobe timing by the application.
UWDT Strobe
Function:	Writes the strobe value to be use for the User Watchdog Timer Frame.
Type:	unsigned binary word (32-bit)
Data Range:	0x55AA
Read/Write:	W
Initialized Value:	0x0
Operational Settings:	At startup, the user watchdog is disabled. Write the value of 0x55AA to this register to start the user watchdog timer monitoring after initial power on or a reset. To prevent a disablement, the application must periodically write the strobe based on the user watchdog timer rules.

Status and Interrupt

The modules that are capable of User Watchdog Timer support provide status registers for the User Watchdog Timer.

User Watchdog Timer Status

The status register that contains the User Watchdog Timer Fault information is also used to indicate channel Inter-FPGA failures on modules that have communication between FPGA components. There are four registers associated with the User Watchdog Timer Fault/Inter-FPGA Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Function:	Sets the corresponding bit (D31) associated with the channel’s User Watchdog Timer Fault error.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value:	0

User Watchdog Timer Fault/Inter-FPGA Failure Dynamic Status
User Watchdog Timer Fault/Inter-FPGA Failure Latched Status
User Watchdog Timer Fault/Inter-FPGA Failure Interrupt Enable
User Watchdog Timer Fault/Inter-FPGA Failure Set Edge/Level Interrupt
Bit(s)	Status	Description
D31	User Watchdog Timer Fault Status	0 = No Fault + 1 = User Watchdog Timer Fault
D30:D0	Reserved for Inter-FPGA Failure Status	Channel bit-mapped indicating channel inter FPGA communication failure detection.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.

In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note

the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector
Function:	Set an identifier for the interrupt.
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function:	Sets where to direct the interrupt.
Type:	unsigned binary word (32-bit)
Data Range:	See table
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME	1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)	2
Direct Interrupt to PCIe Bus	5
Direct Interrupt to cPCI Bus	6

Function Register Map

KEY

Configuration/Control

Measurement/Status

USER WATCHDOG TIMER REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x01C0	UWDT Quiet Time	R/W
0x01C4	UWDT Window	R/W
0x01C8	UWDT Strobe	R/W
STATUS REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0”).
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x09B0	Dynamic Status	R
0x09B4	Latched Status*	R/W
0x09B8	Interrupt Enable	R/W
0x09BC	Set Edge/Level Interrupt	R/W
INTERRUPT REGISTERS
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x056C	Module 1 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x066C	Module 1 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x076C	Module 2 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x086C	Module 2 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x096C	Module 3 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x0A6C	Module 3 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x0B6C	Module 4 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x0C6C	Module 4 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x0D6C	Module 5 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x0E6C	Module 5 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x0F6C	Module 6 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x106C	Module 6 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W

REVISION HISTORY

Motherboard Manual - Status and Interrupts Revision History
Revision	Revision Date	Description
C	2021-11-30	C08896; Transition manual to docbuilder format - no technical info change.

DOCS.NAII REVISIONS

Revision Date	Description
2026-03-02	Formatting updates to document; no technical changes.

Link to original

MODULE COMMON REGISTERS

The registers described in this document are common to all NAI Generation 5 modules.

Module Information Registers

The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.

FPGA Version Registers

The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.

FPGA Revision
Function:	FPGA firmware revision
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Value corresponding to the revision of the board's FPGA
Operational Settings:	The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Minor Revision Number

FPGA Compile Timestamp
Function:	Compile Timestamp for the FPGA firmware.
Type:	unsigned binary word (32-bit)
Data Range:	N/A
Read/Write:	R
Initialized Value:	Value corresponding to the compile timestamp of the board's FPGA
Operational Settings:	The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

day (5-bits)

month (4-bits)

year (6-bits)

hr

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

hour (5-bits)

minutes (6-bits)

seconds (6-bits)

FPGA SerDes Revision
Function:	FPGA SerDes revision
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Value corresponding to the SerDes revision of the board's FPGA
Operational Settings:	The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Minor Revision Number

FPGA Template Revision
Function:	FPGA Template revision
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Value corresponding to the template revision of the board's FPGA
Operational Settings:	The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Minor Revision Number

FPGA Zynq Block Revision
Function:	FPGA Zynq Block revision
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Value corresponding to the Zynq block revision of the board's FPGA
Operational Settings:	The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Minor Revision Number

Bare Metal Version Registers

The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.

Bare Metal Revision
Function:	Bare Metal firmware revision
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Value corresponding to the revision of the board's Bare Metal
Operational Settings:	The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Minor Revision Number

Bare Metal Compile Time
Function:	Provides an ASCII representation of the Date/Time for the Bare Metal compile time.
Type:	24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range:	N/A
Read/Write:	R
Initialized Value:	Value corresponding to the ASCII representation of the compile time of the board's Bare Metal
Operational Settings:	The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Note

little-endian order of ASCII values

Word 1 (Ex. 0x2079614D)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Month ('y' - 0x79)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Month ('a' - 0x61)

Month ('M' - 0x4D)

Word 2 (Ex. 0x32203731)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Year ('2' - 0x32)

Space (0x20)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Day ('7' - 0x37)

Day ('1' - 0x31)

Word 3 (Ex. 0x20393130)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Year ('9' - 0x39)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Year ('1' - 0x31)

Year ('0' - 0x30)

Word 4 (Ex. 0x31207461)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Hour ('1' - 0x31)

Space (0x20)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

'a' (0x74)

't' (0x61)

Word 5 (Ex. 0x38333A35)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Minute ('8' - 0x38)

Minute ('3' - 0x33)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

':' (0x3A)

Hour ('5' - 0x35)

Word 6 (Ex. 0x0032333A)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

NULL (0x00)

Seconds ('2' - 0x32)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Seconds ('3' - 0x33)

':' (0x3A)

FSBL Version Registers

The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).

FSBL Revision
Function:	FSBL firmware revision
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Value corresponding to the revision of the board's FSBL
Operational Settings:	The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Minor Revision Number

FSBL Compile Time
Function:	Provides an ASCII representation of the Date/Time for the FSBL compile time.
Type:	24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range:	N/A
Read/Write:	R
Initialized Value:	Value corresponding to the ASCII representation of the Compile Time of the board's FSBL
Operational Settings:	The six 32-bit words provide an ASCII representation of the Date/Time.

The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Note

little-endian order of ASCII values

Word 1 (Ex. 0x2079614D)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Month ('y' - 0x79)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Month ('a' - 0x61)

Month ('M' - 0x4D)

Word 2 (Ex. 0x32203731)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Year ('2' - 0x32)

Space (0x20)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Day ('7' - 0x37)

Day ('1' - 0x31)

Word 3 (Ex. 0x20393130)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Space (0x20)

Year ('9' - 0x39)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Year ('1' - 0x31)

Year ('0' - 0x30)

Word 4 (Ex. 0x31207461)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Hour ('1' - 0x31)

Space (0x20)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

'a' (0x74)

't' (0x61)

Word 5 (Ex. 0x38333A35)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Minute ('8' - 0x38)

Minute ('3' - 0x33)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

':' (0x3A)

Hour ('5' - 0x35)

Word 6 (Ex. 0x0032333A)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

NULL (0x00)

Seconds ('2' - 0x32)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Seconds ('3' - 0x33)

':' (0x3A)

Module Serial Number Registers

The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.

Interface Board Serial Number
Function:	Unique 128-bit identifier used to identify the interface board.
Type:	16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range:	N/A
Read/Write:	R
Initialized Value:	Serial number of the interface board
Operational Settings:	This register is for information purposes only.

Functional Board Serial Number
Function:	Unique 128-bit identifier used to identify the functional board.
Type:	16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range:	N/A
Read/Write:	R
Initialized Value:	Serial number of the functional board
Operational Settings:	This register is for information purposes only.

Module Capability
Function:	Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0107
Read/Write:	R
Initialized Value:	0x0000 0107
Operational Settings:	A “1” in the bit associated with the capability indicates that it is supported.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	Flt-Pt	0	0	0	0	0	Pack	FIFO Blk	Blk

Module Memory Map Revision
Function:	Module Memory Map revision
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Value corresponding to the Module Memory Map Revision
Operational Settings:	The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major Revision Number

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Minor Revision Number

Module Measurement Registers

The registers in this section provide module temperature measurement information.

Temperature Readings Registers

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.

Interface Board Current Temperature
Function:	Measured PCB and Zynq Core temperatures on Interface Board.
Type:	signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:	0x0000 0000 to 0x0000 FFFF
Read/Write:	R
Initialized Value:	Value corresponding to the measured PCB and Zynq core temperatures based on the table below
Operational Settings:	The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

PCB Temperature

Zynq Core Temperature

Functional Board Current Temperature
Function:	Measured PCB temperature on Functional Board.
Type:	signed byte (8-bits) for PCB
Data Range:	0x0000 0000 to 0x0000 00FF
Read/Write:	R
Initialized Value:	Value corresponding to the measured PCB on the table below
Operational Settings:	The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Interface Board Maximum Temperature
Function:	Maximum PCB and Zynq Core temperatures on Interface Board since power-on.
Type:	signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:	0x0000 0000 to 0x0000 FFFF
Read/Write:	R
Initialized Value:	Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings:	The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

PCB Temperature

Zynq Core Temperature

Interface Board Minimum Temperature
Function:	Minimum PCB and Zynq Core temperatures on Interface Board since power-on.
Type:	signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:	0x0000 0000 to 0x0000 FFFF
Read/Write:	R
Initialized Value:	Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings:	The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

PCB Temperature

Zynq Core Temperature

Functional Board Maximum Temperature
Function:	Maximum PCB temperature on Functional Board since power-on.
Type:	signed byte (8-bits) for PCB
Data Range:	0x0000 0000 to 0x0000 00FF
Read/Write:	R
Initialized Value:	Value corresponding to the measured PCB on the table below
Operational Settings:	The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Functional Board Minimum Temperature
Function:	Minimum PCB temperature on Functional Board since power-on.
Type:	signed byte (8-bits) for PCB
Data Range:	0x0000 0000 to 0x0000 00FF
Read/Write:	R
Initialized Value:	Value corresponding to the measured PCB on the table below
Operational Settings:	The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	PCB Temperature

Higher Precision Temperature Readings Registers

These registers provide higher precision readings of the current Zynq and PCB temperatures.

Higher Precision Zynq Core Temperature
Function:	Higher precision measured Zynq Core temperature on Interface Board.
Type:	signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Measured Zynq Core temperature on Interface Board
Operational Settings:	The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Fractional Part of Temperature

Higher Precision Interface PCB Temperature
Function:	Higher precision measured Interface PCB temperature.
Type:	signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Measured Interface PCB temperature
Operational Settings:	The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Fractional Part of Temperature

Higher Precision Functional PCB Temperature
Function:	Higher precision measured Functional PCB temperature.
Type:	signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Measured Functional PCB temperature
Operational Settings:	The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Fractional Part of Temperature

Module Health Monitoring Registers

The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.

Module Sensor Summary Status
Function:	The corresponding sensor bit is set if the sensor has crossed any of its thresholds.
Type:	unsigned binary word (32-bits)
Data Range:	See table below
Read/Write:	R
Initialized Value:	0
Operational Settings:	This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.

Bit(s)	Sensor
D31:D6	Reserved
D5	Functional Board PCB Temperature
D4	Interface Board PCB Temperature
D3:D0	Reserved

Module Sensor Registers

The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.

Sensor Threshold Status
Function:	Reflects which threshold has been crossed
Type:	unsigned binary word (32-bits)
Data Range:	See table below
Read/Write:	R
Initialized Value:	0
Operational Settings:	The associated bit is set when the sensor reading exceed the corresponding threshold settings.

Bit(s)	Description
D31:D4	Reserved
D3	Exceeded Upper Critical Threshold
D2	Exceeded Upper Warning Threshold
D1	Exceeded Lower Critical Threshold
D0	Exceeded Lower Warning Threshold

Sensor Current Reading
Function:	Reflects current reading of temperature sensor
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Minimum Reading
Function:	Reflects minimum value of temperature sensor since power up
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Maximum Reading
Function:	Reflects maximum value of temperature sensor since power up
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Lower Warning Threshold
Function:	Reflects lower warning threshold of temperature sensor
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	Default lower warning threshold (value dependent on specific sensor)
Operational Settings:	The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.

Sensor Lower Critical Threshold
Function:	Reflects lower critical threshold of temperature sensor
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	Default lower critical threshold (value dependent on specific sensor)
Operational Settings:	The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.

Sensor Upper Warning Threshold
Function:	Reflects upper warning threshold of temperature sensor
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	Default upper warning threshold (value dependent on specific sensor)
Operational Settings:	The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.

Sensor Upper Critical Threshold
Function:	Reflects upper critical threshold of temperature sensor
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	Default upper critical threshold (value dependent on specific sensor)
Operational Settings:	The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.

FUNCTION REGISTER MAP

KEY

Configuration/Control

Measurement/Status/Board Information

MODULE INFORMATION REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x003C	FPGA Revision	R	0x0074	Bare Metal Revision	R
0x0030	FPGA Compile Timestamp	R	0x0080	Bare Metal Compile Time (Bit 0-31)	R
0x0034	FPGA SerDes Revision	R	0x0084	Bare Metal Compile Time (Bit 32-63)	R
0x0038	FPGA Template Revision	R	0x0088	Bare Metal Compile Time (Bit 64-95)	R
0x0040	FPGA Zynq Block Revision	R	0x008C	Bare Metal Compile Time (Bit 96-127)	R
			0x0090	Bare Metal Compile Time (Bit 128-159)	R
			0x0094	Bare Metal Compile Time (Bit 160-191)	R
0x007C	FSBL Revision	R
0x00B0	FSBL Compile Time (Bit 0-31)	R
0x00B4	FSBL Compile Time (Bit 32-63)	R
0x00B8	FSBL Compile Time (Bit 64-95)	R
0x00BC	FSBL Compile Time (Bit 96-127)	R
0x00C0	FSBL Compile Time (Bit 128-159)	R
0x00C4	FSBL Compile Time (Bit 160-191)	R
0x0000	Interface Board Serial Number (Bit 0-31)	R	0x0010	Functional Board Serial Number (Bit 0-31)	R
0x0034	Interface Board Serial Number (Bit 32-63)	R	0x0014	Functional Board Serial Number (Bit 32-63)	R
0x0008	Interface Board Serial Number (Bit 64-95)	R	0x0018	Functional Board Serial Number (Bit 64-95)	R
0x000C	Interface Board Serial Number (Bit 96-127)	R	0x001C	Functional Board Serial Number (Bit 96-127)	R
0x0070	Module Capability	R
0x01FC	Module Memory Map Revision	R
MODULE MEASUREMENTS REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0200	Interface Board PCB/Zynq Current Temp	R	0x0208	Functional Board PCB Current Temp	R
0x0218	Interface Board PCB/Zynq Max Temp	R	0x0228	Functional Board PCB Max Temp	R
0x0220	Interface Board PCB/Zynq Min Temp	R	0x0230	Functional Board PCB Min Temp	R
0x02C0	Higher Precision Zynq Core Temperature	R
0x02C4	Higher Precision Interface PCB Temperature	R
0x02E0	Higher Precision Functional PCB Temperature	R
MODULE HEALTH MONITORING REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x07F8	Module Sensor Summary Status	R


REVISION HISTORY

Motherboard Manual - Module Common Registers Revision History
Revision	Revision Date	Description
C	2023-08-11	ECO C10649, initial release of module common registers manual.
C1	2024-05-15	ECO C11522, removed Zynq Core/Aux/DDR Voltage register descriptions from Module Measurement Registers. Pg.16, updated Module Sensor Summary Status register to add PS references; updated Bit Table to change voltage/current bits to 'reserved'. Pg.16, updated Module/Power Supply Sensor Registers description to better describe register functionality and to add figure. Pg.17, added 'Exceeded' to threshold bit descriptions. Pg.17-18, removed voltage/current references from sensor descriptions. Pg.20, removed Zynq Core/Aux/DDR Voltage register offsets from Module Measurement Registers. Pg.20, updated Module Health Monitoring Registers offset tables.
C2	2024-07-10	ECO C11701, pg.16, updated Module Sensor Summary Status register to remove PS references;updated Bit Table to change PS temperature bits to 'reserved'. Pg.16, updated Module SensorRegisters description to remove PS references. Pg.20, updated Module Health MonitoringRegisters offset tables to remove PS temperature register offsets.

DOCS.NAII REVISIONS

Revision Date	Description
2025-11-05	Corrected register offsets for Interface Board Min Temp and Function Board Min & Max Temps.
2026-03-02	Formatting updates to document; no technical changes.

Link to original

Revision History

Module Manual - DT3 Revision History

Revision		Revision Date		Description
C		2024-01-26	ECO C11173, initial release of module manual.

Module Manual - Status and Interrupts Revision History

Revision		Revision Date		Description
C		2021-11-30 C08896;		Transition manual to docbuilder format - no technical info change.

Module Manual - User Watchdog Timer Revision History

Revision		Revision Date		Description
C		2021-11-30		C08896; Transition manual to docbuilder format - no technical info change.

Module Manual - Module Common Registers Revision History

Revision		Revision Date		Description
C		2023-08-11 ECO		C10649, initial release of module common registers manual.

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