NAI Documentation

DA2 Manual

54 min read

DA2 DATA SHEET

Click here for the DA2 Data Sheet

INTRODUCTION

As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurement and simulation, communications, Ethernet switch, and SBC functions. Our DA2 module provides sixteen independent Digital-to-Analog (D/A) output channels with a full-scale range of ±10 VDC at a maximum of ±10 mA. Linearity/accuracy is ±0.10% FS range over temperature. The DA2 provides a FIFO output buffer, which is programmable for the application. This user manual is designed to help you get the most out of our DA2 smart function module.

DA2 Overview

NAI’s DA2 modules offers several features designed to suit a variety of system requirements, including:

Sixteen (16) Channels of Digital-to-Analog I/O Interface: The DA2 provides sixteen channels of high-quality 16-bit D/A output offering a full-scale range of ±10 VDC at a maximum of ±10 mA.

Designed to meet IEC 801-2 Level 2 testing requirements: The DA2 ensures reliable performance and compliance with industry standards by meeting the testing requirements of IEC 801-2 Level 2. This capability guarantees that the module can effectively handle electromagnetic compatibility challenges, highlighting the product’s resilience in various operating environments..

Continuous Built-In Test (BIT): The module incorporates continuous BIT functionality, providing self-diagnostics and monitoring capabilities to ensure reliable operation and easy troubleshooting.

Automatic Shutdown Protection: The DA2 module utilizes an automatic shutdown protection feature to enhance operational safety by swiftly responding to potentially harmful conditions. This functionality not only safeguards the module from damage but also provides users with clear and immediate feedback by displaying the results in a status word, ensuring efficient troubleshooting and maintenance processes.

Extended D/A FIFO Buffering Capabilities: The extended D/A output FIFO buffering capabilities of the DA2 module facilitate efficient signal processing and management, ensuring smooth operation and accurate output generation. By offering a buffering mechanism, the module can handle fluctuations in data flow, reducing the risk of data loss or distortion. This feature is particularly advantageous in applications requiring precise timing or synchronization, enhancing overall system performance and reliability.

PRINCIPLE OF OPERATION

In addition to the functions and features already described, each module includes extensive background BIT/diagnostics that run in the background in normal operation without user intervention. In addition to output signal read-back (wrap) capabilities, overloaded outputs will be detected with automatic channel shutdown protection, with the results displayed in a status word. The modules also include D/A FIFO Buffering for greater control of the output voltage and signal data. The FIFO D/A buffer will accept, store and output the voltage commands, once enabled and triggered, for applications requiring simulation of waveform generation; single or periodic. The output data command word is formatted as a percentage of the full scale (FS) range selection, which allows maximum resolution and accuracy at lower voltage ranges.

Built-In Test (BIT)/Diagnostic Capability

The DA2 module supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are logically OR’d together and stored in the BIT Dynamic Status and BIT Latched Status registers.

Power-On Self-Test (POST)/Power-On BIT (PBIT)/Start-Up BIT (SBIT)

The power-on self-test is performed on each channel automatically when power is applied and report the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.

Continuous Background Built-In Test (CBIT)

The background Built-In-Test or Continuous BIT (CBIT) (“D2”) runs in the background where each channel is checked to a test accuracy of 0.2% FS. The testing is totally transparent to the user, requires no external programming, and has no effect on the operation of the module or card.

The technique used by the continuous background BIT (CBIT) test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. Note, the interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained; i.e. at a ten second interval, not a 10-millisecond interval). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state.

Initiated Built-In Test (IBIT)

The DA2 module support an off-line Initiated Built-in Test (IBIT) (“D3”).

The IBIT test uses an internal A/D that measures all D/A channels while they remain connected to the I/O and cycle through 16 signal levels from -FS to +FS. Each channel will be checked to a test accuracy of 0.2% FS. Test cycle is completed within 45 seconds (depending on update rate) and results can be read from the Status registers when IBIT bit changes from 1 to 0. This test requires no user programming and can be enabled via the bus.

D/A FIFO Buffering

The Digital-to-Analog modules include D/A FIFO Buffering for greater control of the output voltage and signal data. The D/A FIFO buffers will accept, store and output the voltage (and/or current) commands, once enabled and triggered, for applications requiring simulation of waveform generation; single or periodic. The output data command word is formatted as a percentage of the full scale (FS) range selection, which allows maximum resolution and accuracy at lower voltage ranges.

Status and Interrupts

The D/A Module provides registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

Module Common Registers

The D/A Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

Engineering Scaling Conversion

The D/A Module Data, Voltage and Current Measurement registers can be programmed to be utilized as single precision floating point values (IEEE-754) or as a 32-bit integer value.

When the Enable Floating Point Mode register is set to 1 (Floating Point Mode) the following registers are formatted as Single Precision Floating Point Value (IEEE-754):

  • Wrap Voltage (Volts)

  • Wrap Current (mA)

  • Internal Voltage (Volts)

  • DAC Value (Voltage (Volts))*

  • FIFO Buffer Data

*When the Enable Floating Point Mode register is set to 1, it is important that these registers are updated with the Single Precision Floating Point (IEEE-754) representation of the value for proper operation of the channel. Conversely, when the Enable Floating Point Mode register is set to 0, these registers must be updated with the Integer 32-bit representation of the value.

Note

When changing the Enable Floating Point Mode from Integer Mode to Floating Point Mode or vice versa, the following step should be followed to avoid faults from falsely being generated because internal registers have an incorrect binary representation of the values:

  1. Set the Enable Floating Point Mode register to the desired mode (Integer or Floating Point).

  2. Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete. Data registers will be converted to the units specified and can be read in that specified format.

  3. Initialize configuration and control registers with the values in the units specified (Integer or Floating Point).

It is very often necessary to relate D/A voltage and current to other engineering units such as PSI (Pounds per Square Inch). When the Enable Floating Point Mode register is set to 1, the values entered for the Floating Point Offset register and the Floating-Point Scale register will be used to convert the D/A data from engineering units to voltage or current values. The purpose of this is to offload the processing that is normally performed by the mission processor to convert the physical quantity to voltage or current values for the DAC Value register and the FIFO Buffer Data register. When enabled, the module will compute the D/A data as follows:

D/A Value as Volts/Current (Floating Point) =
        (D/A Value in Engineering Units (Floating Point) + Floating Point Offset) * Floating Point Scale

Note

When Enable Floating Point Mode is set to 1 (Floating Point Mode) the listed registers below are formatted as Single Precision Floating Point Value (IEEE-754) and the values specified in the Floating Point Offset register and the Float Point Scale register are applied:

  • DAC Value

  • FIFO Buffer Data – any data left in the FIFO prior to changing the Floating Point Mode will be invalid.

Watchdog Timer Capability

The Digital-to-Analog Modules provide support for Watchdog Timer capability. Refer to “Watchdog Timer Module Manual” for the Principle of Operation description.

REGISTER DESCRIPTIONS

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

D/A Output Registers

The D/A output is normally in terms of voltage. When the Enable Floating Point Mode is enabled, the register value is formatted as a Single Precision Floating Point Value (IEEE-754). In addition, the D/A output value can be specified in engineering units rather than voltage by setting the Floating Point Scale and Floating Point Offset register values to reflect the conversion algorithm.

DAC Value

Function: Sets the output voltage for the channel.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range: DAC values are dependent on Voltage Range setting for the channel

Enable Floating Point Mode: 0 (Integer Mode)

  Unipolar: 0x0000 0000 to 0x0000 FFFF

 Bipolar (2's compliment. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF

Enable Floating Point Mode: 1 (Floating Point Mode)

 Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: 0

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

D/A Control Registers

The D/A control registers provide the ability to specify the polarity and voltage range, update rate, and the enabling or disabling of the D/A outputs. The D/A channels are monitored to detect overcurrent conditions and will automatically disable the D/A output. In the event of an overcurrent condition, the D/A channel needs to be “reset” by writing to the Overcurrent Reset register.

Voltage Range

Function: Sets voltage polarity and range for each channel. The value written to the DAC Value registers will correlate to the voltage range set in this register. Note, if the Enable Floating Point Mode register is set to 1, the Floating Point Scale register must be set to the reciprocal of Voltage Range for direct voltage output.

Type: unsigned binary word (32-bit)

Data Range: See table below

Read/Write: R/W

Initialized Value: 0 (Unipolar: 0-5 V)

Operational Settings: Write to the register with a value from the table to select the range.

For example, for a ±10V bipolar range write a 0x4 to the register.

Reg ValueVoltage Range
0x0Unipolar: 0 - 5 V
0x1Unipolar: 0 - 10 V
0x2Bipolar: ± 2.5 V
0x3Bipolar: ± 5 V
0x4Bipolar: ± 10 V

Voltage Range

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
0000000000000DDD

Output Enable

Function: Enables the voltage to appear on the output.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R/W

Initialized Value: 0 (Channel outputs are disabled)

Operational Settings: Set bit to 1 to activate the output. Set bit to 0 to disable the output.

Output Enable

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9Ch8Ch7Ch6Ch5CH4Ch3Ch2Ch1

Update Rate

Function: Sets the output rate for the DAC output and FIFO Data Output

Type: unsigned binary word (32bit)

Data Range: 0x0000 09C4 to 0x0000 61A8; 400µs (2.5kHz) to 40µs (25kHz).

Read/Write: R/W

Initialized Value: 0x0000 61A8 (40µs) (25kHz)

Operational Settings: This setting is the output rate for each DAC. One update rate applies to all channels.

Overcurrent Reset

Function: Resets over loaded channels based on the current value read in the Wrap Current register.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1 Read/Write: W Initialized Value: 0

Operational Settings: Set to 1 to reset over loaded channels. Writing a 1 to this register will re-enable over loaded channels.

Overcurrent Reset

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
000000000000000D

D/A Measurement Registers

The measured voltage and current for the D/A output can be read from the Wrap Voltage, Wrap Current and Internal Voltage registers.

Wrap Voltage

Function: Wrap voltage reading from the channel’s output. Used in conjunction with BIT to verify that the output voltage is within range.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)

 Unipolar: 0x0000 0000 to 0x0003 FFFF; Bipolar: 0x0002 0000 - 0x0001 FFFF

 Bipolar (2's compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0001 7FFF

Enable Floating Point Mode: 1 (Floating Point Mode)

 Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: 0

Operational Settings:

Integer Mode: To calculate the LSB subtract the minimum voltage range from the maximum voltage range then divide by 2^16. For example, if the value in the Voltage Range register is range 0-10V then the LSB would have value (10-0)/2^16 = .153 mV. Sign bit = D17 for bipolar ranges.

Floating Point Mode: Convert the IEEE-754 Single Precision 32-bit value to a floating point value. For example, if the register value is 0x4020 0000, this is equivalent to 2.5, which represents 2.5V.

Wrap Voltage (Enable Floating Point Mode: Integer Mode)

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
DDDDDDDDDDDDDDDD

Wrap Voltage (Enable Floating Point Mode: Floating Point Mode)

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
DDDDDDDDDDDDDDDD

Wrap Current

Function: Wrap current reading from the channel’s output. Reads current values of D/A outputs being delivered per channel.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)

 Bipolar (2's compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0000 7FFF

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: 0

Operational Settings:

Integer Mode: LSB = 305 nA. Sign bit = D17.

Floating Point Mode: Convert the IEEE-754 Single Precision 32-bit value to a floating point value.

Wrap Current (Enable Floating Point Mode: Integer Mode)

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
DDDDDDDDDDDDDDDD

Wrap Current (Enable Floating Point Mode: Floating Point Mode)

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
DDDDDDDDDDDDDDDD

Internal Voltage

Function: Read the internal voltage value. The interval voltage reading is the voltage before the output switch. If the Output Enable register is configured to be disabled, the Internal Voltage register will contain the voltage reading that would be outputted.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 - 0x0003 FFFF

 Bipolar (2's compliment. 18-bit value sign extended to 32 bits): 0xFFFE 0000 to 0x0001 7FFF

Enable Floating Point Mode: 1 (Floating Point Mode)

 Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: 0

Operational Settings:

Integer Mode: To calculate the LSB subtract the minimum voltage range from the maximum voltage range then divide by 2^16. Sign bit = D17 for bipolar ranges.

Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754) value.

Internal Voltage (Enable Floating Point Mode: Integer Mode)

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
DDDDDDDDDDDDDDDD

Internal Voltage (Enable Floating Point Mode: Floating Point Mode)

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
DDDDDDDDDDDDDDDD

D/A Test Registers

Two different tests, one on-line (CBIT) and one off-line (IBIT), can be selected.

Test Enabled

Function: Sets bit to enable the associated CBIT (“D2”) or IBIT (“D3”).

Note

CBIT cannot be disabled.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 000C

Read/Write: R/W

Initialized Value: 0x4 (CBIT Test Enabled)

Operational Settings: BIT tests include an on-line CBIT and an off-line IBIT tests. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects failures.

Test Enabled

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
000000000000IBIT Test DCBIT Test 100

FIFO Registers

The FIFO registers are configurable for each channel.

Data Mode

Function: Sets the data mode of the channel. The output can be based on either the DAC Value register or the RAM Buffer.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: Write a 0 to set the data source to the DAC Value Register. Write a 1 to set the data source to the FIFO Buffer.

Data Mode

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9Ch8Ch7Ch6Ch5CH4Ch3Ch2Ch1

FIFO Buffer Data

Function: Data in the form of DAC values are written to this register one word at a time (16 bits) and will be outputted to the channel’s output once triggered. Buffer will be emptied one value at a time when triggered.

Type: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)

Data Range:

Enable Floating Point Mode: 0 (Integer Mode)

  Unipolar: 0x0000 0000 to 0x0000 FFFF

 Bipolar (2's compliment. 16-bit value sign extended to 32 bits): 0xFFFF 8000 to 0x0000 7FFF

Enable Floating Point Mode: 1 (Floating Point Mode)

  Single Precision Floating Point Value (IEEE-754)

Read/Write: W

Initialized Value: 0

Operational Settings: Data is held in FIFO until triggered. FIFO size is 1 mega words per channel (each channel has its own buffer). Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

FIFO Buffer Data (Enable Floating Point Mode: Integer Mode)

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
DDDDDDDDDDDDDDDD

FIFO Buffer Data (Enable Floating Point Mode: Floating Point Mode)

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
DDDDDDDDDDDDDDDD

FIFO Word Count

Function: Reports the number of words stored in the FIFO buffer.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R

Initialized Value: 0 (FIFO is empty)

Operational Settings: Each time a value is written to the FIFO buffer this count is incremented by 1. Once the FIFO is triggered, after each value is outputted to the DAC, this count will be decremented by 1. Watermarks and threshold values can be setup to trigger interrupts when this count crosses user defined values. The maximum number of words that can be stored in the FIFO is 1 mega words.

FIFO Thresholds

The FIFO Almost Empty, FIFO Low Watermark, FIFO High Watermark, and FIFO Almost Full sets the threshold limits that are used to set the bits in the FIFO Status register.

FIFO Almost Empty

Function: The FIFO Almost Empty is used to set the limits for the “almost empty” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R/W

Initialized Value: 0x400 (1024)

Operational Settings: When the FIFO Word Count register is less than or equal to the value stored in the FIFO Almost Empty Value register, the “almost empty” bit (D1) of the FIFO Status register will be set. When the Words in FIFO counter is greater than the value stored in the register, the “almost empty” bit (D1) of the FIFO Status register will be reset.

FIFO Low Watermark

Function: The FIFO Low Watermark (low-threshold level) is used to set the limits for the “low watermark” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R/W

Initialized Value: 0x2000 (8192)

Operational Settings: When the FIFO Word Count register is less than or equal to the value stored in the FIFO Low Watermark Value register, the “low watermark” bit (D2) of the FIFO Status register will be set. When the FIFO Word Count counter is greater than or equal to the value stored in the register, the “low watermark” bit (D2) of the FIFO Status register will be reset.

FIFO High Watermark

Function: The FIFO High Watermark (high-threshold level) is used to set the limits for the “high watermark” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R/W

Initialized Value: 0x6000 (24576)

Operational Settings: When the FIFO Word Count register is greater than or equal to the value stored in the FIFO High Watermark Value register, the “high watermark” bit (D3) of the FIFO Status register will be set. When the FIFO Word Count register is less than the value stored in the FIFO High Watermark Value, the “high watermark” bit (D3) of the FIFO Status register will be reset.

FIFO Almost Full

Function: The FIFO Almost Full is used to set the limits for the “almost full” status.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x000F FFFF

Read/Write: R/W

Initialized Value: 0x7C00 (31744)

Operational Settings: When the FIFO Word Count register is greater than or equal to the value stored in the FIFO Almost Full Value register, the “almost full” bit (D4) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the register, the “almost full” bit (D4) of the FIFO Status register will be reset

Clear FIFO

Function: Clears the FIFO buffer.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: W

Initialized Value: 0

Operational Settings: Writing a 1 will clear the FIFO buffer and reset the count in the FIFO Word Count register.

Clear FIFO

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
000000000000000D

Pattern Control

Function: Enable to output all the values written to the FIFO Buffer and then repeat.

Note

Pattern Control for the DA2 supports Loop Mode only.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: To activate FIFO Loop Mode in the Pattern Control Register, set the Data Mode register to 1. Then set the bit for the specific channel in the Pattern Control register to 1. Finally, write a 1 to the Software Trigger register. The FIFO will output all values written to the FIFO Data register and then repeat. To stop looping write a 0 to the Software Trigger register.

Pattern Control (FIFO Loop Mode)

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9Ch8Ch7Ch6Ch5CH4Ch3Ch2Ch1

Software Trigger

Function: If the memory buffer is enabled writing the trigger value to this register will start the output. Values stored in the FIFO will be output at the set update rate until the FIFO is empty.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: R/W

Initialized Value: 0

Operational Settings: To initiate output from the FIFO Buffer, the Data Mode register must be set to FIFO Mode. Then write a 1 to the Software Trigger register to begin outputting data. The 1 will clear once the FIFO empties.

Software Trigger

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
000000000000000D

Engineering Scaling Conversion Registers

The D/A Module Data, Voltage and Current Measurement registers can be programmed to be utilized as an IEEE 754 single-precision floating- point value or as a 32-bit integer value.

Enable Floating Point Mode

Function: Sets all channels for floating point mode or integer module.

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: R/W

Initialized Value: 0 (Integer mode)

Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode.

Floating Point Offset

Function: Single 32-bit register that sets the floating-point offset to add to D/A output.

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

Read/Write: R/W

Initialized Value: 0.0

Operational Settings: Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point examples.

Floating Point Scale

Function: Single 32-bit register that sets the floating-point scale to multiple to the D/A output.

Type: Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

Read/Write: R/W

Initialized Value: 0.0

Operational Settings: When changing the Voltage Range, the Floating Point Scale needs to be adjusted in order for the Wrap Voltage and Wrap Current floating point representation to be scaled correctly.

Floating Point State

Function: Indicates whether the module’s internal processing is converting the register values and internal values to the binary representation of the mode selected (Integer or Floating Point).

Type: unsigned binary word (32-bit)

Data Range: 0 to 1

Read/Write: R

Initialized Value: 0

Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

Floating Point State

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
000000000000000D

Background BIT Threshold Programming Registers

The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The Reset BIT register provides the ability to reset the BIT counter used in CBIT.

Background BIT Threshold

Type: unsigned binary word (32-bit) Data Range: 1 ms to 2^32 ms Read/Write: R/W

Initialized Value: 5 (5 ms)

Operational Settings: The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module.

Reset BIT

Function: Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: W

Initialized Value: 0

Operational Settings: Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.

Reset BIT

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9Ch8Ch7Ch6Ch5CH4Ch3Ch2Ch1

Watchdog Timer Registers

Refer to “Watchdog Timer Module Manual” for the Watchdog Timer Register Descriptions.

Module Common Registers

Refer to “Module Common Registers Module Manual” for the register descriptions.

Status and Interrupt Registers

The DA2 Module provides status registers for BIT, Overcurrent, External Power Under Voltage, Inter-FPGA Failure, and FIFO.

Channel Status Enabled

Function: Determines whether to update the status for the channels. This feature can be used to “mask” status bits of unused channels in status registers that are bitmapped by channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF (Channel Status)

Read/Write: R/W

Initialized Value: 0x0000 FFFF

Operational Settings: When the bit corresponding to a given channel in the Channel Status Enabled register is not enabled (0) the status will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status, Overcurrent Status and Summary Status).

Note

Background BIT will continue to run even if the Channel Status Enabled is set to ‘0’.

Channel Status Enabled

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9Ch8Ch7Ch6Ch5CH4Ch3Ch2Ch1

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The BIT Status register will indicate an error when the D/A conversion is outside 0.2% FS accuracy spec.

BIT Status

BIT Dynamic Status
BIT Latched Status
BIT Interrupt Enable
BIT Set Edge/Level Interrupt
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9Ch8Ch7Ch6Ch5CH4Ch3Ch2Ch1

Function: Reports the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Note

BIT Status is part of background testing and the status register may be checked or polled at any given time.

Overcurrent Status

There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Overcurrent Status

Overcurrent Dynamic Status
Overcurrent Latched Status
Overcurrent Interrupt Enable
Overcurrent Set Edge/Level Interrupt
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9Ch8Ch7Ch6Ch5CH4Ch3Ch2Ch1

Function: Reports the corresponding bit associated with the channel’s Overcurrent error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

External Power Under Voltage Status

There are four registers associated with the External Power Under Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

D0 = +12V External Power Under Voltage

D1 = -12V External Power Under Voltage

External Power Voltage Status

External Power Under Voltage Dynamic Status
External Power Under Voltage Latched Status
External Power Under Voltage Interrupt Enable
External Power Under Voltage Set Edge/Level Interrupt
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
00000000000000-12V+12V

Function: Reports the corresponding bit associated with the channel’s External Power Under Voltage error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0003

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Inter-FPGA Failure Status/Watchdog Timer Fault

Data is periodically transferred between the processing module and functional module within the FPGA. A CRC value is calculated and verified with each data transfer. In order to recover from an Inter-FPGA Failure, the module needs to be reset and re-initialized.

There are four registers associated with the Inter-FPGA Status/Watchdog Timer Fault: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

The lower 16-bits represent the Inter-FPGA Failure Status: 0 = Normal; 0xFFFF = Inter-FPGA Communication Failure. The status represents the status for all channels on the module.

Bit 31 represents the Watchdog Timer Fault: 0 = Normal; 1 = Watchdog Timer Fault.

Inter-FPGA Failure Status/Watchdog Timer Fault

Inter-FPGA Failure/Watchdog Timer Fault Dynamic Status
Inter-FPGA Failure/Watchdog Timer Fault Latched Status
Inter-FPGA Failure/Watchdog Timer Fault Interrupt Enable
Inter-FPGA Failure/Watchdog Timer Fault Set Edge/Level Interrupt
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
DDDDDDDDDDDDDDDD

Function: Sets the corresponding bit associated with the channel’s Inter-FPGA Failure and Watchdog Timer Fault error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x8000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Summary Status

There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Summary Status

Summary Status Dynamic Status
Summary Status Latched Status
Summary Status Interrupt Enable
Summary Status Set Edge/Level Interrupt
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9Ch8Ch7Ch6Ch5CH4Ch3Ch2Ch1

Function: Sets the corresponding bit when a fault is detected for BIT, Overcurrent, External Power Under Voltage or Inter-FPGA Failure on that channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 FFFF

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

FIFO Status

There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0-D5 is used to show the different conditions of the buffer.

BitDescriptionConfigurable?
D0Empty; 1 when FIFO Word Count = 0No
D1Almost Empty; 1 when FIFO Word Count ⇐ “FIFO Almost Empty” registerYes
D2Low Watermark; 1 when FIFO Word Count ⇐ “FIFO Low Watermark” registerYes
D3High Watermark; 1 when FIFO Word Count >= “FIFO High Watermark” registerYes
D4Almost Full; 1 when FIFO Word Count >= “FIFO Almost Full” registerYes
D5Full; 1 when FIFO Word Count = 1 Mega Words (0x000F FFFF)No

FIFO Status

FIFO Dynamic Status
FIFO Latched Status
FIFO Interrupt Enable
FIFO Set Edge/Level Interrupt
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
0000000000DDDDDD

Function: Sets the corresponding bit associated with the FIFO status type; there are separate registers for each channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 003F

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 1 (Empty)

Notes: Shown below is an example of interrupts generated for the High Watermark. As shown, the interrupt is generated as the FIFO Word Count crosses the High Watermark. The interrupt will not be generated a second time until the count goes below the watermark and then above it again.

Interrupt Steering and Vector

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.

In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note

the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector

Function: Set an identifier for the interrupt.

Type: unsigned binary word (32-bit) Data Range: 0 to 0xFFFF FFFF Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering

Function: Sets where to direct the interrupt.

Type: unsigned binary word (32-bit) Data Range: See table Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)2
Direct Interrupt to PCIe Bus5
Direct Interrupt to cPCI Bus6

FUNCTION REGISTER MAP

Key:

Bold Italic = Configuration/Control

Bold Underline = Measurement/Status

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a ‘1’ to a bit set to ‘1’ will set the bit to ‘0’).

**Data is available in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode.

~ Data is always in Floating Point.

D/A Output Registers

0x2004DAC Value Ch 1****R/W
0x2104DAC Value Ch 2****R/W
0x2204DAC Value Ch 3****R/W
0x2304DAC Value Ch 4****R/W
0x2404DAC Value Ch 5****R/W
0x2504DAC Value Ch 6****R/W
0x2604DAC Value Ch 7****R/W
0x2704DAC Value Ch 8****R/W
0x2804DAC Value Ch 9****R/W
0x2904DAC Value Ch 10****R/W
0x2A04DAC Value Ch 11****R/W
0x2B04DAC Value Ch 12****R/W
0x2C04DAC Value Ch 13****R/W
0x2D04DAC Value Ch 14****R/W
0x2E04DAC Value Ch 15****R/W
0x2F04DAC Value Ch 16****R/W

D/A Control Registers

0x2000Voltage Range Ch 1R/W
0x2100Voltage Range Ch 2R/W
0x2200Voltage Range Ch 3R/W
0x2300Voltage Range Ch 4R/W
0x2400Voltage Range Ch 5R/W
0x2500Voltage Range Ch 6R/W
0x2600Voltage Range Ch 7R/W
0x2700Voltage Range Ch 8R/W
0x2800Voltage Range Ch 9R/W
0x2900Voltage Range Ch 10R/W
0x2A00Voltage Range Ch 11R/W
0x2B00Voltage Range Ch 12R/W
0x2C00Voltage Range Ch 13R/W
0x2D00Voltage Range Ch 14R/W
0x2E00Voltage Range Ch 15R/W
0x2F00Voltage Range Ch 16R/W
0x100CUpdate Rate Ch 1-16R/W
0x1010Overcurrent Reset Ch 1-16R/W
0x0250Output Enable Ch 1-16R/W

D/A Measurement Registers

0x2008Wrap Voltage Ch 1****R
0x2108Wrap Voltage Ch 2****R
0x2208Wrap Voltage Ch 3****R
0x2308Wrap Voltage Ch 4****R
0x2408Wrap Voltage Ch 5****R
0x2508Wrap Voltage Ch 6****R
0x2608Wrap Voltage Ch 7****R
0x2708Wrap Voltage Ch 8****R
0x2808Wrap Voltage Ch 9****R
0x2908Wrap Voltage Ch 10****R
0x2A08Wrap Voltage Ch 11****R
0x2B08Wrap Voltage Ch 12****R
0x2C08Wrap Voltage Ch 13****R
0x2D08Wrap Voltage Ch 14****R
0x2E08Wrap Voltage Ch 15****R
0x2F08Wrap Voltage Ch 16****R
0x200CWrap Current Ch 1****R
0x210CWrap Current Ch 2****R
0x220CWrap Current Ch 3****R
0x230CWrap Current Ch 4****R
0x240CWrap Current Ch 5****R
0x250CWrap Current Ch 6****R
0x260CWrap Current Ch 7****R
0x270CWrap Current Ch 8****R
0x280CWrap Current Ch 9****R
0x290CWrap Current Ch 10****R
0x2A0CWrap Current Ch 11****R
0x2B0CWrap Current Ch 12****R
0x2C0CWrap Current Ch 13****R
0x2D0CWrap Current Ch 14****R
0x2E0CWrap Current Ch 15****R
0x2F0CWrap Current Ch 16****R
0x2044Internal Voltage Ch 1****R
0x2144Internal Voltage Ch 2****R
0x2244Internal Voltage Ch 3****R
0x2344Internal Voltage Ch 4****R
0x2444Internal Voltage Ch 5****R
0x2544Internal Voltage Ch 6****R
0x2644Internal Voltage Ch 7****R
0x2744Internal Voltage Ch 8****R
0x2844Internal Voltage Ch 9****R
0x2944Internal Voltage Ch 10****R
0x2A44Internal Voltage Ch 11****R
0x2B44Internal Voltage Ch 12****R
0x2C44Internal Voltage Ch 13****R
0x2D44Internal Voltage Ch 14****R
0x2E44Internal Voltage Ch 15****R
0x2F44Internal Voltage Ch 16****R

FIFO Registers

0x2018FIFO Buffer Data Ch 1****W
0x2118FIFO Buffer Data Ch 2****W
0x2218FIFO Buffer Data Ch 3****W
0x2318FIFO Buffer Data Ch 4****W
0x2418FIFO Buffer Data Ch 5****W
0x2518FIFO Buffer Data Ch 6****W
0x2618FIFO Buffer Data Ch 7****W
0x2718FIFO Buffer Data Ch 8****W
0x2818FIFO Buffer Data Ch 9****W
0x2918FIFO Buffer Data Ch 10****W
0x2A18FIFO Buffer Data Ch 11****W
0x2B18FIFO Buffer Data Ch 12****W
0x2C18FIFO Buffer Data Ch 13****W
0x2D18FIFO Buffer Data Ch 14****W
0x2E18FIFO Buffer Data Ch 15****W
0x2F18FIFO Buffer Data Ch 16****W
0x201CFIFO Word Count Ch 1R
0x211CFIFO Word Count Ch 2R
0x221CFIFO Word Count Ch 3R
0x231CFIFO Word Count Ch 4R
0x241CFIFO Word Count Ch 5R
0x251CFIFO Word Count Ch 6R
0x261CFIFO Word Count Ch 7R
0x271CFIFO Word Count Ch 8R
0x281CFIFO Word Count Ch 9R
0x291CFIFO Word Count Ch 10R
0x2A1CFIFO Word Count Ch 11R
0x2B1CFIFO Word Count Ch 12R
0x2C1CFIFO Word Count Ch 13R
0x2D1CFIFO Word Count Ch 14R
0x2E1CFIFO Word Count Ch 15R
0x2F1CFIFO Word Count Ch 16R
0x2010Clear FIFO Ch 1W
0x2110Clear FIFO Ch 2W
0x2210Clear FIFO Ch 3W
0x2310Clear FIFO Ch 4W
0x2410Clear FIFO Ch 5W
0x2510Clear FIFO Ch 6W
0x2610Clear FIFO Ch 7W
0x2710Clear FIFO Ch 8W
0x2810Clear FIFO Ch 9W
0x2910Clear FIFO Ch 10W
0x2A10Clear FIFO Ch 11W
0x2B10Clear FIFO Ch 12W
0x2C10Clear FIFO Ch 13W
0x2D10Clear FIFO Ch 14W
0x2E10Clear FIFO Ch 15W
0x2F10Clear FIFO Ch 16W
0x2014FIFO Software Trigger Ch 1W
0x2114FIFO Software Trigger Ch 2W
0x2214FIFO Software Trigger Ch 3W
0x2314FIFO Software Trigger Ch 4W
0x2414FIFO Software Trigger Ch 5W
0x2514FIFO Software Trigger Ch 6W
0x2614FIFO Software Trigger Ch 7W
0x2714FIFO Software Trigger Ch 8W
0x2814FIFO Software Trigger Ch 9W
0x2914FIFO Software Trigger Ch 10W
0x2A14FIFO Software Trigger Ch 11W
0x2B14FIFO Software Trigger Ch 12W
0x2C14FIFO Software Trigger Ch 13W
0x2D14FIFO Software Trigger Ch 14W
0x2E14FIFO Software Trigger Ch 15W
0x2F14FIFO Software Trigger Ch 16W
0x1004Data Mode Ch 1-16W
0x2110Pattern Control Ch 1-16W

FIFO Thresholds

0x2020FIFO Almost Empty Value Ch 1R/W
0x2120FIFO Almost Empty Value Ch 2R/W
0x2220FIFO Almost Empty Value Ch 3R/W
0x2320FIFO Almost Empty Value Ch 4R/W
0x2420FIFO Almost Empty Value Ch 5R/W
0x2520FIFO Almost Empty Value Ch 6R/W
0x2620FIFO Almost Empty Value Ch 7R/W
0x2720FIFO Almost Empty Value Ch 8R/W
0x2820FIFO Almost Empty Value Ch 9R/W
0x2920FIFO Almost Empty Value Ch 10R/W
0x2A20FIFO Almost Empty Value Ch 1R/W
0x2B20FIFO Almost Empty Value Ch 12R/W
0x2C20FIFO Almost Empty Value Ch 13R/W
0x2D20FIFO Almost Empty Value Ch 14R/W
0x2E20FIFO Almost Empty Value Ch 15R/W
0x2F20FIFO Almost Empty Value Ch 16R/W
0x2024FIFO Low Watermark Value Ch 1R/W
0x2124FIFO Low Watermark Value Ch 2R/W
0x2224FIFO Low Watermark Value Ch 3R/W
0x2324FIFO Low Watermark Value Ch 4R/W
0x2424FIFO Low Watermark Value Ch 5R/W
0x2524FIFO Low Watermark Value Ch 6R/W
0x2624FIFO Low Watermark Value Ch 7R/W
0x2724FIFO Low Watermark Value Ch 8R/W
0x2824FIFO Low Watermark Value Ch 9R/W
0x2924FIFO Low Watermark Value Ch 10R/W
0x2A24FIFO Low Watermark Value Ch 11R/W
0x2B24FIFO Low Watermark Value Ch 12R/W
0x2C24FIFO Low Watermark Value Ch 13R/W
0x2D24FIFO Low Watermark Value Ch 14R/W
0x2E24FIFO Low Watermark Value Ch 15R/W
0x2F24FIFO Low Watermark Value Ch 16R/W
0x2028FIFO High Watermark Value Ch 1R/W
0x2128FIFO High Watermark Value Ch 2R/W
0x2228FIFO High Watermark Value Ch 3R/W
0x2328FIFO High Watermark Value Ch 4R/W
0x2428FIFO High Watermark Value Ch 5R/W
0x2528FIFO High Watermark Value Ch 6R/W
0x2628FIFO High Watermark Value Ch 7R/W
0x2728FIFO High Watermark Value Ch 8R/W
0x2828FIFO High Watermark Value Ch 9R/W
0x2928FIFO High Watermark Value Ch 10R/W
0x2A28FIFO High Watermark Value Ch 11R/W
0x2B28FIFO High Watermark Value Ch 12R/W
0x2C28FIFO High Watermark Value Ch 13R/W
0x2D28FIFO High Watermark Value Ch 14R/W
0x2E28FIFO High Watermark Value Ch 15R/W
0x2F28FIFO High Watermark Value Ch 16R/W
0x202CFIFO Almost Full Value Ch 1R/W
0x212CFIFO Almost Full Value Ch 2R/W
0x222CFIFO Almost Full Value Ch 3R/W
0x232CFIFO Almost Full Value Ch 4R/W
0x242CFIFO Almost Full Value Ch 5R/W
0x252CFIFO Almost Full Value Ch 6R/W
0x262CFIFO Almost Full Value Ch 7R/W
0x272CFIFO Almost Full Value Ch 8R/W
0x282CFIFO Almost Full Value Ch 9R/W
0x292CFIFO Almost Full Value Ch 10R/W
0x2A2CFIFO Almost Full Value Ch 11R/W
0x2B2CFIFO Almost Full Value Ch 12R/W
0x2C2CFIFO Almost Full Value Ch 13R/W
0x2D2CFIFO Almost Full Value Ch 14R/W
0x2E2CFIFO Almost Full Value Ch 15R/W
0x2F2CFIFO Almost Full Value Ch 16R/W

Engineering Scaling Conversion Registers

0x02B4Enable Floating PointR/W
0x0264Floating Point StateR
0x2050Floating Point Offset Ch 1~R/W
0x2150Floating Point Offset Ch 2~R/W
0x2250Floating Point Offset Ch 3~R/W
0x2350Floating Point Offset Ch 4~R/W
0x2450Floating Point Offset Ch 5~R/W
0x2550Floating Point Offset Ch 6~R/W
0x2650Floating Point Offset Ch 7~R/W
0x2750Floating Point Offset Ch 8~R/W
0x2850Floating Point Offset Ch 9~R/W
0x2950Floating Point Offset Ch 10~R/W
0x2A50Floating Point Offset Ch 11~R/W
0x2B50Floating Point Offset Ch 12~R/W
0x2C50Floating Point Offset Ch 13~R/W
0x2D50Floating Point Offset Ch 14~R/W
0x2E50Floating Point Offset Ch 15~R/W
0x2F50Floating Point Offset Ch 16~R/W
0x2054Floating Point Scale Ch 1~R/W
0x2154Floating Point Scale Ch 2~R/W
0x2254Floating Point Scale Ch 3~R/W
0x2354Floating Point Scale Ch 4~R/W
0x2454Floating Point Scale Ch 5~R/W
0x2554Floating Point Scale Ch 6~R/W
0x2654Floating Point Scale Ch 7~R/W
0x2754Floating Point Scale Ch 8~R/W
0x2854Floating Point Scale Ch 9~R/W
0x2954Floating Point Scale Ch 10~R/W
0x2A54Floating Point Scale Ch 11~R/W
0x2B54Floating Point Scale Ch 12~R/W
0x2C54Floating Point Scale Ch 13~R/W
0x2D54Floating Point Scale Ch 14~R/W
0x2E54Floating Point Scale Ch 15~R/W
0x2F54Floating Point Scale Ch 16~R/W

Watchdog Timer Registers

The D/A Modules provide registers that support Watchdog Timer capability. Refer to “Watchdog Timer Module Manual” for the Watchdog Timer Function Register Map.

Module Common Registers

Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.

Status Registers

0x02B0Channel Status EnabledR/W

BIT Status

0x0800Dynamic StatusR
0x0804Latched Status*R/W
0x0808Interrupt EnableR/W
0x080CSet Edge/Level InterruptR/W

D/A Test Registers

0x0248Test EnabledR/W

Background BIT Threshold Registers

0x02B8Background BIT ThresholdR/W
0x02BCReset BITW
0x02ACPower-on BIT Complete++R

++After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.

Status Registers

Overcurrent Status

0x0910Dynamic StatusR
0x0914Latched Status*R/W
0x0918Interrupt EnableR/W
0x091CSet Edge/Level InterruptR/W

External Power Under Voltage Status

0x0930Dynamic StatusR
0x0934Latched Status*R/W
0x0939Interrupt EnableR/W
0x093CSet Edge/Level InterruptR/W

Watchdog Timer Fault/Inter-FPGA Failure

0x09B0Dynamic StatusR
0x09B4Latched Status*R/W
0x09B8Interrupt EnableR/W
0x09BCSet Edge/Level InterruptR/W

Summary Status

0x09A0Dynamic StatusR
0x09A4Latched Status*R/W
0x09A8Interrupt EnableR/W
0x09ACSet Edge/Level InterruptR/W

FIFO Status

Ch 1
0x0810Dynamic StatusR
0x0814Latched Status*R/W
0x0818Interrupt EnableR/W
0x081CSet Edge/Level InterruptR/W
Ch 2
0x0820Dynamic StatusR
0x0824Latched Status*R/W
0x0828Interrupt EnableR/W
0x082CSet Edge/Level InterruptR/W
Ch 3
0x0830Dynamic StatusR
0x0834Latched Status*R/W
0x0838Interrupt EnableR/W
0x083CSet Edge/Level InterruptR/W
Ch 4
0x0840Dynamic StatusR
0x0844Latched Status*R/W
0x0848Interrupt EnableR/W
0x084CSet Edge/Level InterruptR/W
Ch 5
0x0850Dynamic StatusR
0x0854Latched Status*R/W
0x0858Interrupt EnableR/W
0x085CSet Edge/Level InterruptR/W
Ch 6
0x0860Dynamic StatusR
0x0864Latched Status*R/W
0x0868Interrupt EnableR/W
0x086CSet Edge/Level InterruptR/W
Ch 7
0x0870Dynamic StatusR
0x0874Latched Status*R/W
0x0878Interrupt EnableR/W
0x087CSet Edge/Level InterruptR/W
Ch 8
0x0880Dynamic StatusR
0x0884Latched Status*R/W
0x0888Interrupt EnableR/W
0x088CSet Edge/Level InterruptR/W
Ch 9
0x0890Dynamic StatusR
0x0894Latched Status*R/W
0x0898Interrupt EnableR/W
0x089CSet Edge/Level InterruptR/W
Ch 10
0x08A0Dynamic StatusR
0x08A4Latched Status*R/W
0x08A8Interrupt EnableR/W
0x08ACSet Edge/Level InterruptR/W
Ch 11
0x08B0Dynamic StatusR
0x08B4Latched Status*R/W
0x08B8Interrupt EnableR/W
0x08BCSet Edge/Level InterruptR/W
Ch 12
0x08C0Dynamic StatusR
0x08C4Latched Status*R/W
0x08C8Interrupt EnableR/W
0x08CCSet Edge/Level InterruptR/W
Ch 13
0x08D0Dynamic StatusR
0x08D4Latched Status*R/W
0x08D8Interrupt EnableR/W
0x08DCSet Edge/Level InterruptR/W
Ch 14
0x08E0Dynamic StatusR
0x08E4Latched Status*R/W
0x08E8Interrupt EnableR/W
0x08ECSet Edge/Level InterruptR/W
Ch 15
0x08F0Dynamic StatusR
0x08F4Latched Status*R/W
0x08F8Interrupt EnableR/W
0x08FCSet Edge/Level InterruptR/W
Ch 16
0x0900Dynamic StatusR
0x0904Latched Status*R/W
0x0908Interrupt EnableR/W
0x090CSet Edge/Level InterruptR/W

Interrupt Registers

The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.

0x0500Module 1 Interrupt Vector 1 - BITR/W
0x0504Module 1 Interrupt Vector 2 - FIFO Ch 1R/W
0x0508Module 1 Interrupt Vector 3 - FIFO Ch 2R/W
0x050CModule 1 Interrupt Vector 4 - FIFO Ch 3R/W
0x0510Module 1 Interrupt Vector 5 - FIFO Ch 4R/W
0x0514Module 1 Interrupt Vector 6 - FIFO Ch 5R/W
0x0518Module 1 Interrupt Vector 7 - FIFO Ch 6R/W
0x051CModule 1 Interrupt Vector 8 - FIFO Ch 7R/W
0x0520Module 1 Interrupt Vector 9 - FIFO Ch 8R/W
0x0524Module 1 Interrupt Vector 10 - FIFO Ch 9R/W
0x0528Module 1 Interrupt Vector 11 - FIFO Ch 10R/W
0x052CModule 1 Interrupt Vector 12 - FIFO Ch 11R/W
0x0530Module 1 Interrupt Vector 13 - FIFO Ch 12R/W
0x0534Module 1 Interrupt Vector 14 - FIFO Ch 13R/W
0x0538Module 1 Interrupt Vector 15 - FIFO Ch 14R/W
0x053CModule 1 Interrupt Vector 16 - FIFO Ch 15R/W
0x0540Module 1 Interrupt Vector 17 - FIFO Ch 16R/W
0x0544Module 1 Interrupt Vector 18 - OvercurrentR/W
0x0548Module 1 Interrupt Vector 19 - ReservedR/W
0x054CModule 1 Interrupt Vector 20 - External Power Under VoltageR/W
0x0550 to 0x0564Module 1 Interrupt Vector 21-26 - ReservedR/W
0x0568Module 1 Interrupt Vector 27 - SummaryR/W
0x056CModule 1 Interrupt Vector 28 - Watchdog Timer/Inter-FPGAR/W
0x0570 to 0x057CModule 1 Interrupt Vector 29-32 - ReservedR/W
0x0600Module 1 Interrupt Steering 1 - BITR/W
0x0604Module 1 Interrupt Steering 2 - FIFO Ch 1R/W
0x0608Module 1 Interrupt Steering 3 - FIFO Ch 2R/W
0x060CModule 1 Interrupt Steering 4 - FIFO Ch 3R/W
0x0610Module 1 Interrupt Steering 5 - FIFO Ch 4R/W
0x0614Module 1 Interrupt Steering 6 - FIFO Ch 5R/W
0x0618Module 1 Interrupt Steering 7 - FIFO Ch 6R/W
0x061CModule 1 Interrupt Steering 8 - FIFO Ch 7R/W
0x0620Module 1 Interrupt Steering 9 - FIFO Ch 8R/W
0x0624Module 1 Interrupt Steering 10 - FIFO Ch 9R/W
0x0628Module 1 Interrupt Steering 11 - FIFO Ch 10R/W
0x062CModule 1 Interrupt Steering 12 - FIFO Ch 11R/W
V
0x0630Module 1 Interrupt Steering 13 - FIFO Ch 12R/W
VV
0x0634Module 1 Interrupt Steering 14 - FIFO Ch 13R/W
0x0638Module 1 Interrupt Steering 15 - FIFO Ch 14R/W
0x063CModule 1 Interrupt Steering 16 - FIFO Ch 15R/W
0x0640Module 1 Interrupt Steering 17 - FIFO Ch 16R/W
0x0644Module 1 Interrupt Steering 18 - OvercurrentR/W
0x0648Module 1 Interrupt Steering 19 - Current Range ExceededR/W
0x064CModule 1 Interrupt Steering 20 - External Power Under VoltageR/W
0x0650 to 0x0664Module 1 Interrupt Steering 21-26 - ReservedR/W
0x0668Module 1 Interrupt Steering 27 - SummaryR/W
0x066CModule 1 Interrupt Steering 28 - Watchdog Timer/Inter-FPGAR/W
0x0670 to 0x067CModule 1 Interrupt Steering 29-32 - ReservedR/W
0x0700Module 2 Interrupt Vector 1 - BITR/W
0x0704Module 2 Interrupt Vector 2 - FIFO Ch 1R/W
0x0708Module 2 Interrupt Vector 3 - FIFO Ch 2R/W
0x070CModule 2 Interrupt Vector 4 - FIFO Ch 3R/W
0x0710Module 2 Interrupt Vector 5 - FIFO Ch 4R/W
0x0714Module 2 Interrupt Vector 6 - FIFO Ch 5R/W
0x0718Module 2 Interrupt Vector 7 - FIFO Ch 6R/W
0x071CModule 2 Interrupt Vector 8 - FIFO Ch 7R/W
0x0720Module 2 Interrupt Vector 9 - FIFO Ch 8R/W
0x0724Module 2 Interrupt Vector 10 - FIFO Ch 9R/W
0x0728Module 2 Interrupt Vector 11 - FIFO Ch 10R/W
0x072CModule 2 Interrupt Vector 12 - FIFO Ch 11R/W
0x0730Module 2 Interrupt Vector 13 - FIFO Ch 12R/W
0x0734Module 2 Interrupt Vector 14 - FIFO Ch 13R/W
0x0738Module 2 Interrupt Vector 15 - FIFO Ch 14R/W
0x0738Module 2 Interrupt Vector 16 - FIFO Ch 15R/W
0x0740Module 2 Interrupt Vector 17 - FIFO Ch 16R/W
0x0744Module 2 Interrupt Vector 18 - OvercurrentR/W
0x0748Module 2 Interrupt Vector 19 - Current Range ExceededR/W
0x074CModule 2 Interrupt Vector 20 - External Power Under VoltageR/W
0x0750 to 0x0764Module 2 Interrupt Vector 21-26 - ReservedR/W
0x0768Module 2 Interrupt Vector 27 - SummaryR/W
0x076CModule 2 Interrupt Vector 28 - Watchdog Timer/Inter-FPGAR/W
0x0770 to 0x077CModule 2 Interrupt Vector 29-32 - ReservedR/W
0x0800Module 2 Interrupt Steering 1 - BITR/W
0x0804Module 2 Interrupt Steering 2 - FIFO Ch 1R/W
0x0808Module 2 Interrupt Steering 3 - FIFO Ch 2R/W
0x080CModule 2 Interrupt Steering 4 - FIFO Ch 3R/W
0x0810Module 2 Interrupt Steering 5 - FIFO Ch 4R/W
0x0814Module 2 Interrupt Steering 6 - FIFO Ch 5R/W
0x0818Module 2 Interrupt Steering 7 - FIFO Ch 6R/W
0x081CModule 2 Interrupt Steering 8 - FIFO Ch 7R/W
0x0820Module 2 Interrupt Steering 9 - FIFO Ch 8R/W
0x0824Module 2 Interrupt Steering 10 - FIFO Ch 9R/W
0x0828Module 2 Interrupt Steering 11 - FIFO Ch 10R/W
0x082CModule 2 Interrupt Steering 12 - FIFO Ch 11R/W
0x0830Module 2 Interrupt Steering 13 - FIFO Ch 12R/W
0x0834Module 2 Interrupt Steering 14 - FIFO Ch 13R/W
0x0838Module 2 Interrupt Steering 15 - FIFO Ch 14R/W
0x083CModule 2 Interrupt Steering 16 - FIFO Ch 15R/W
0x0810Module 2 Interrupt Steering 17 - FIFO Ch 16R/W
0x0844Module 2 Interrupt Steering 18 - OvercurrentR/W
0x0848Module 2 Interrupt Steering 19 - Current Range ExceededR/W
0x084CModule 2 Interrupt Steering 20 - External Power Under VoltageR/W
0x0850 to 0x0864Module 2 Interrupt Steering 21-26 - ReservedR/W
0x0868Module 2 Interrupt Steering 27 - SummaryR/W
0x086CModule 2 Interrupt Steering 28 - Watchdog Timer/Inter-FPGAR/W
0x0870 to 0x087CModule 2 Interrupt Steering 29-32 - ReservedR/W
0x0900Module 3 Interrupt Vector 1 - BITR/W
0x0904Module 3 Interrupt Vector 2 - FIFO Ch 1R/W
0x0908Module 3 Interrupt Vector 3 - FIFO Ch 2R/W
0x090CModule 3 Interrupt Vector 4 - FIFO Ch 3R/W
0x0910Module 3 Interrupt Vector 5 - FIFO Ch 4R/W
0x0914Module 3 Interrupt Vector 6 - FIFO Ch 5R/W
0x0918Module 3 Interrupt Vector 7 - FIFO Ch 6R/W
0x091CModule 3 Interrupt Vector 8 - FIFO Ch 7R/W
0x0920Module 3 Interrupt Vector 9 - FIFO Ch 8R/W
0x0924Module 3 Interrupt Vector 10 - FIFO Ch 9R/W
0x0928Module 3 Interrupt Vector 11 - FIFO Ch 10R/W
0x092CModule 3 Interrupt Vector 12 - FIFO Ch 11R/W
0x0930Module 3 Interrupt Vector 13 - FIFO Ch 12R/W
0x0934Module 3 Interrupt Vector 14 - FIFO Ch 13R/W
0x0938Module 3 Interrupt Vector 15 - FIFO Ch 14R/W
0x093CModule 3 Interrupt Vector 16 - FIFO Ch 15R/W
0x0940Module 3 Interrupt Vector 17 - FIFO Ch 16R/W
0x0944Module 3 Interrupt Vector 18 - OvercurrentR/W
0x0948Module 3 Interrupt Vector 19 - Current Range ExceededR/W
0x094CModule 3 Interrupt Vector 20 - External Power Under VoltageR/W
0x0950 to 0x0964Module 3 Interrupt Vector 21-26 - ReservedR/W
0x0968Module 3 Interrupt Vector 27 - SummaryR/W
0x096CModule 3 Interrupt Vector 28 - Watchdog Timer/Inter-FPGAR/W
0x0970 to 0x097CModule 3 Interrupt Vector 29-32 - ReservedR/W
0x0A00Module 3 Interrupt Steering 1 - BITR/W
0x0A04Module 3 Interrupt Steering 2 - FIFO Ch 1R/W
0x0A08Module 3 Interrupt Steering 3 - FIFO Ch 2R/W
0x0A0CModule 3 Interrupt Steering 4 - FIFO Ch 3R/W
0x0A10Module 3 Interrupt Steering 5 - FIFO Ch 4R/W
0x0A14Module 3 Interrupt Steering 6 - FIFO Ch 5R/W
0x0A18Module 3 Interrupt Steering 7 - FIFO Ch 6R/W
0x0A1CModule 3 Interrupt Steering 8 - FIFO Ch 7R/W
0x0A20Module 3 Interrupt Steering 9 - FIFO Ch 8R/W
0x0A24Module 3 Interrupt Steering 10 - FIFO Ch 9R/W
0x0A28Module 3 Interrupt Steering 11 - FIFO Ch 10R/W
0x0A2CModule 3 Interrupt Steering 12 - FIFO Ch 11R/W
0x0A30Module 3 Interrupt Steering 13 - FIFO Ch 12R/W
0x0A34Module 3 Interrupt Steering 14 - FIFO Ch 13R/W
0x0A38Module 3 Interrupt Steering 15 - FIFO Ch 14R/W
0x0A3CModule 3 Interrupt Steering 16 - FIFO Ch 15R/W
0x0A40Module 3 Interrupt Steering 17 - FIFO Ch 16R/W
0x0A44Module 3 Interrupt Steering 18 - OvercurrentR/W
0x0A48Module 3 Interrupt Steering 19 - Current Range ExceededR/W
0x0A4CModule 3 Interrupt Steering 20 - External Power Under VoltageR/W
0x0A50 to 0x0A64Module 3 Interrupt Steering 21-26 - ReservedR/W
0x0A68Module 3 Interrupt Steering 27 - SummaryR/W
0x0A6CModule 3 Interrupt Steering 28 - Watchdog Timer/Inter-FPGAR/W
0x0A70 to 0x0A7CModule 3 Interrupt Steering 29-32 - ReservedR/W
0x0B00Module 4 Interrupt Vector 1 - BITR/W
0x0B04Module 4 Interrupt Vector 2 - FIFO Ch 1R/W
0x0B08Module 4 Interrupt Vector 3 - FIFO Ch 2R/W
0x0B0CModule 4 Interrupt Vector 4 - FIFO Ch 3R/W
0x0B10Module 4 Interrupt Vector 5 - FIFO Ch 4R/W
0x0B14Module 4 Interrupt Vector 6 - FIFO Ch 5R/W
0x0B18Module 4 Interrupt Vector 7 - FIFO Ch 6R/W
0x0B1CModule 4 Interrupt Vector 8 - FIFO Ch 7R/W
0x0B20Module 4 Interrupt Vector 9 - FIFO Ch 8R/W
0x0B24Module 4 Interrupt Vector 10 - FIFO Ch 9R/W
0x0B28Module 4 Interrupt Vector 11 - FIFO Ch 10R/W
0x0B2CModule 4 Interrupt Vector 12 - FIFO Ch 11R/W
0x0B30Module 4 Interrupt Vector 13 - FIFO Ch 12R/W
0x0B34Module 4 Interrupt Vector 14 - FIFO Ch 13R/W
0x0B38Module 4 Interrupt Vector 15 - FIFO Ch 14R/W
0x0B3CModule 4 Interrupt Vector 16 - FIFO Ch 15R/W
0x0B40Module 4 Interrupt Vector 17 - FIFO Ch 16R/W
0x0B44Module 4 Interrupt Vector 18 - OvercurrentR/W
0x0B48Module 4 Interrupt Vector 19 - Current Range ExceededR/W
0x0B4CModule 4 Interrupt Vector 20 - External Power Under VoltageR/W
0x0B50 to 0x0B64Module 4 Interrupt Vector 21-26 - ReservedR/W
0x0B68Module 4 Interrupt Vector 27 - SummaryR/W
0x0B6CModule 4 Interrupt Vector 28 - Watchdog Timer/Inter-FPGAR/W
0x0B70 to 0x0B7CModule 4 Interrupt Vector 29-32 - ReservedR/W
0x0C00Module 4 Interrupt Steering 1 - BITR/W
0x0C04Module 4 Interrupt Steering 2 - FIFO Ch 1R/W
0x0C08Module 4 Interrupt Steering 3 - FIFO Ch 2R/W
0x0C0CModule 4 Interrupt Steering 4 - FIFO Ch 3R/W
0x0C10Module 4 Interrupt Steering 5 - FIFO Ch 4R/W
0x0C14Module 4 Interrupt Steering 6 - FIFO Ch 5R/W
0x0C18Module 4 Interrupt Steering 7 - FIFO Ch 6R/W
0x0C1CModule 4 Interrupt Steering 8 - FIFO Ch 7R/W
0x0C20Module 4 Interrupt Steering 9 - FIFO Ch 8R/W
0x0C24Module 4 Interrupt Steering 10 - FIFO Ch 9R/W
0x0C28Module 4 Interrupt Steering 11 - FIFO Ch 10R/W
0x0C2CModule 4 Interrupt Steering 12 - FIFO Ch 11R/W
0x0C30Module 4 Interrupt Steering 13 - FIFO Ch 12R/W
0x0C34Module 4 Interrupt Steering 14 - FIFO Ch 13R/W
0x0C38Module 4 Interrupt Steering 15 - FIFO Ch 14R/W
0x0C3CModule 4 Interrupt Steering 16 - FIFO Ch 15R/W
0x0C40Module 4 Interrupt Steering 17 - FIFO Ch 16R/W
0x0C44Module 4 Interrupt Steering 18 - OvercurrentR/W
0x0C48Module 4 Interrupt Steering 19 - Current Range ExceededR/W
0x0C4CModule 4 Interrupt Steering 20 – External Power Under VoltageR/W
0x0C50 to 0x0C64Module 4 Interrupt Steering 21-26 - ReservedR/W
0x0C68Module 4 Interrupt Steering 27 - SummaryR/W
0x0C6CModule 4 Interrupt Steering 28 – Watchdog Timer/Inter-FPGAR/W
0x0C70 to 0x0C7CModule 4 Interrupt Steering 29-32 - ReservedR/W
0x0D00Module 5 Interrupt Vector 1 - BITR/W
0x0D04Module 5 Interrupt Vector 2 - FIFO Ch 1R/W
0x0D08Module 5 Interrupt Vector 3 - FIFO Ch 2R/W
0x0D0CModule 5 Interrupt Vector 4 - FIFO Ch 3R/W
0x0D10Module 5 Interrupt Vector 5 - FIFO Ch 4R/W
0x0D14Module 5 Interrupt Vector 6 - FIFO Ch 5R/W
0x0D18Module 5 Interrupt Vector 7 - FIFO Ch 6R/W
0x0D1CModule 5 Interrupt Vector 8 - FIFO Ch 7R/W
0x0D20Module 5 Interrupt Vector 9 - FIFO Ch 8R/W
0x0D24Module 5 Interrupt Vector 10 - FIFO Ch 9R/W
0x0D28Module 5 Interrupt Vector 11 - FIFO Ch 10R/W
0x0D2CModule 5 Interrupt Vector 12 - FIFO Ch 11R/W
0x0D30Module 5 Interrupt Vector 13 - FIFO Ch 12R/W
0x0D34Module 5 Interrupt Vector 14 - FIFO Ch 13R/W
0x0D38Module 5 Interrupt Vector 15 - FIFO Ch 14R/W
0x0D3CModule 5 Interrupt Vector 16 - FIFO Ch 15R/W
0x0D40Module 5 Interrupt Vector 17 - FIFO Ch 16R/W
0x0D44Module 5 Interrupt Vector 18 - OvercurrentR/W
0x0D48Module 5 Interrupt Vector 19 - ReservedR/W
0x0D4CModule 5 Interrupt Vector 20 - External Power Under VoltageR/W
0x0D50 to 0x0D64Module 5 Interrupt Vector 21-26 - ReservedR/W
0x0D68Module 5 Interrupt Vector 27 - SummaryR/W
0x0D6CModule 5 Interrupt Vector 28 - Watchdog Timer/Inter-FPGAR/W
0x0D70 to 0x0D7CModule 5 Interrupt Vector 29-32 - ReservedR/W
0x0E00Module 5 Interrupt Steering 1 - BITR/W
0x0E04Module 5 Interrupt Steering 2 - FIFO Ch 1R/W
0x0E08Module 5 Interrupt Steering 3 - FIFO Ch 2R/W
0x0E0CModule 5 Interrupt Steering 4 - FIFO Ch 3R/W
0x0E10Module 5 Interrupt Steering 5 - FIFO Ch 4R/W
0x0E14Module 5 Interrupt Steering 6 - FIFO Ch 5R/W
0x0E18Module 5 Interrupt Steering 7 - FIFO Ch 6R/W
0x0E1CModule 5 Interrupt Steering 8 - FIFO Ch 7R/W
0x0E20Module 5 Interrupt Steering 9 - FIFO Ch 8R/W
0x0E24Module 5 Interrupt Steering 10 - FIFO Ch 9R/W
0x0E28Module 5 Interrupt Steering 11 - FIFO Ch 10R/W
0x0E2CModule 5 Interrupt Steering 12 - FIFO Ch 11R/W
0x0E30Module 5 Interrupt Steering 13 - FIFO Ch 12R/W
0x0E34Module 5 Interrupt Steering 14 - FIFO Ch 13R/W
0x0E38Module 5 Interrupt Steering 15 - FIFO Ch 14R/W
0x0E3CModule 5 Interrupt Steering 16 - FIFO Ch 15R/W
0x0E40Module 5 Interrupt Steering 17 - FIFO Ch 16R/W
0x0E44Module 5 Interrupt Steering 18 - OvercurrentR/W
0x0E48Module 5 Interrupt Steering 19 - ReservedR/W
0x0E4CModule 5 Interrupt Steering 20 - External Power Under VoltageR/W
0x0E50 to 0x0E64Module 5 Interrupt Steering 21-26 - ReservedR/W
0x0E68Module 5 Interrupt Steering 27 - SummaryR/W
0x0E6CModule 5 Interrupt Steering 28 - Watchdog Timer/Inter-FPGAR/W
0x0E70 to 0x0E7CModule 5 Interrupt Steering 29-32 - ReservedR/W
0x0F00Module 6 Interrupt Vector 1 - BITR/W
0x0F04Module 6 Interrupt Vector 2 - FIFO Ch 1R/W
0x0F08Module 6 Interrupt Vector 3 - FIFO Ch 2R/W
0x0F0CModule 6 Interrupt Vector 4 - FIFO Ch 3R/W
0x0F10Module 6 Interrupt Vector 5 - FIFO Ch 4R/W
0x0F14Module 6 Interrupt Vector 6 - FIFO Ch 5R/W
0x0F18Module 6 Interrupt Vector 7 - FIFO Ch 6R/W
0x0F1CModule 6 Interrupt Vector 8 - FIFO Ch 7R/W
0x0F20Module 6 Interrupt Vector 9 - FIFO Ch 8R/W
0x0F24Module 6 Interrupt Vector 10 - FIFO Ch 9R/W
0x0F28Module 6 Interrupt Vector 11 - FIFO Ch 10R/W
0x0F2CModule 6 Interrupt Vector 12 - FIFO Ch 11R/W
0x0F30Module 6 Interrupt Vector 13 - FIFO Ch 12R/W
0x0F34Module 6 Interrupt Vector 14 - FIFO Ch 13R/W
0x0F38Module 6 Interrupt Vector 15 - FIFO Ch 14R/W
0x0F3CModule 6 Interrupt Vector 16 - FIFO Ch 15R/W
0x0F40Module 6 Interrupt Vector 17 - FIFO Ch 16R/W
0x0F44Module 6 Interrupt Vector 18 - OvercurrentR/W
0x0F48Module 6 Interrupt Vector 19 - ReservedR/W
0x0F4CModule 6 Interrupt Vector 20 - External Power Under VoltageR/W
0x0F50 to 0x0F64Module 6 Interrupt Vector 21-26 - ReservedR/W
0x0F68Module 6 Interrupt Vector 27 - SummaryR/W
0x0F6CModule 6 Interrupt Vector 28 - Watchdog Timer/Inter-FPGAR/W
0x0F70 to 0x0F7CModule 6 Interrupt Vector 29-32 - ReservedR/W
0x1000Module 6 Interrupt Steering 1 - BITR/W
0x1004Module 6 Interrupt Steering 2 - FIFO Ch 1R/W
0x1008Module 6 Interrupt Steering 3 - FIFO Ch 2R/W
0x100CModule 6 Interrupt Steering 4 - FIFO Ch 3R/W
0x1010Module 6 Interrupt Steering 5 - FIFO Ch 4R/W
0x1014Module 6 Interrupt Steering 6 - FIFO Ch 5R/W
0x1018Module 6 Interrupt Steering 7 - FIFO Ch 6R/W
0x101CModule 6 Interrupt Steering 8 - FIFO Ch 7R/W
0x1020Module 6 Interrupt Steering 9 - FIFO Ch 8R/W
0x1024Module 6 Interrupt Steering 10 - FIFO Ch 9R/W
0x1028Module 6 Interrupt Steering 11 - FIFO Ch 10R/W
0x102CModule 6 Interrupt Steering 12 - FIFO Ch 11R/W
0x1030Module 6 Interrupt Steering 13 - FIFO Ch 12R/W
0x1034Module 6 Interrupt Steering 14 - FIFO Ch 13R/W
0x1038Module 6 Interrupt Steering 15 - FIFO Ch 14R/W
0x103CModule 6 Interrupt Steering 16 - FIFO Ch 15R/W
0x1040Module 6 Interrupt Steering 17 - FIFO Ch 16R/W
0x1044Module 6 Interrupt Steering 18 - OvercurrentR/W
0x1048Module 6 Interrupt Steering 19 - ReservedR/W
0x104CModule 6 Interrupt Steering 20 - External Power Under VoltageR/W
0x1050 to 0x1064Module 6 Interrupt Steering 21-26 - ReservedR/W
0x1068Module 6 Interrupt Steering 27 - SummaryR/W
0x106CModule 6 Interrupt Steering 28 - Watchdog Timer/Inter-FPGAR/W
0x1070 to 0x107CModule 6 Interrupt Steering 29-32 - ReservedR/W

APPENDIX A: INTEGER/FLOATING POINT MODE PROGRAMMING

Integer Mode Programming

The following registers should be configured as follows:

RegisterValueDescription
Voltage Range0x4±10 volts
Enable Floating Point0Disable for Floating Point Mode

Note: LSB for Bipolar ±10-volt range:

LSB = 10/0x00007FFF

10/32767=305uV

DAC Value (Integer)DAC Voltage Output
1.000 of FS = 0x0000 7FFF32767 * LSB = 10.0 volts
0.5 of FS = 0x0000 400016384 * LSB = 5.0 volts
0.0 of FS = 0x0000 00000 * LSB = 0.0 volts
-0.5 of FS = 0xFFFF C000-16384 * LSB = -5.0 volts
-1.0 of FS = 0xFFFF 8000-32768 * LSB = -10. volts

Floating Point Mode Voltage Programming

The following registers should be configured as follows:

RegisterValueDescription
Voltage Range0x4±10 volts
Enable Floating Point1Enable for Floating Point Mode
Floating Point Scale0.1Scale = 1 / (Full Range) = 1 / 10.0 = 0.1
Floating Point Offset0.0No Offset

Note: LSB for Bipolar ±10-volt range:

LSB = 10/0x00007FFF

10/32767=305uV

DAC Value (volts) (Floating Point)DAC Value (Calculated by Module)DAC Value (Integer)DAC Voltage Output
10.0(10.0 + 0.0) **0.1 = 1 (FS)FS = 0x0000 7FFF32767 ** LSB = 10.0 volts
5.0(5.0 + 0.0) **0.1 = 0.5 of FS0.5 of FS = 0x0000 400016384 ** LSB = 5.0 volts
0.0(0.0 + 0.0) **0.1 = 0.0 of FS0.0 of FS = 0x0000 00000 ** LSB = 0.0 volts
-5.0(-5.0 + 0.0) **0.1 = -0.5 of FS-0.5 of FS = 0xFFFF C000-16384 ** LSB = -5.0 volts
-10.0(-10.0 + 0.0) **0.1 = -1 (-FS)-FS = 0xFFFF 8000-32768 ** LSB = -10. volts

Floating Point Mode Engineering Units Programming

Example #1:

An application wants to associate -10 to 10 volts to -5 to 5 inches.

The following registers should be configured as follows

RegisterValueDescription
Voltage Range0x4±10 volts
Enable Floating Point1Enable for Floating Point Mode
Floating Point Scale0.2Scale = 1 / inches range = 1 / 5 = 0.2
Floating Point Offset0.0No Offset

Note: LSB for Bipolar ±10-volt range:

LSB = 10/0x00007FFF

10/32767=305uV

DAC Value (in) (Floating Point)DAC Value (Calculated by Module)DAC Value (Integer)DAC Voltage Output
5.0(5.0 + 0.0) * 0.2 = 1 (FS)FS = 0x0000 7FFF32767 * LSB = 10.0 volts
2.5(2.5 + 0.0) * 0.2 = .5 of FS0.5 of FS = 0x0000 400016384 * LSB = 5.0 volts
0.0(0.0 + 0.0) * 0.2 = 00.0 of FS = 0x0000 00000 * LSB = 0.0 volts
-2.5(-2.5 + 0.0) * 0.2 = -.5 of FS-0.5 of FS = 0xFFFF C000-16384 * LSB = -5.0 volts
-5.0(-5.0 + 0.0) * 0.2 = -1 (-FS)-FS = 0xFFFF 8000-32768 * LSB = -10. volts

Example #2:

An application wants to associate 0 to 10 volts to 0 to 50 feet with a bias of 0.5 feet (in other words 0.5 feet is equivalent to 0 volts).

The following registers should be configured as follows:

RegisterValueDescription
Voltage Range0x1Unipolar 0-10 volts
Enable Floating Point1Enable for Floating Point Mode
Floating Point Scale0.02Scale = 1 / feet range = 1 / 50 = 0.02
Floating Point Offset-0.50Bias (0.5 feet) that is equivalent to 0 volts

The following are sample outputs:

Note: LSB for Unipolar 10-volt range:

LSB = 10/0x0000FFFF

10/65535

DAC Value (ft) (Floating Point)DAC Value (Calculated by Module)DAC Value (Integer)DAC Voltage Output
50.00(50.0 - 0.50) * 0.02 = 0.99 of FS0.99 of FS = 0x0000 FD7064880 * LSB = 9.90 volts
25.00(25.00 - 0.50) * 0.02 = 0.49 of FS0.49 of FS = 0x0000 7D7032112 * LSB = 4.90 volts
5.50(5.50 - 0.50) * 0.02 = 0.10 of FS0.10 of FS = 0x0000 199A6554 * LSB = 1.00 volts
0.50(0.50 - 0.50) * 0.02 = 0.00 of FS0.00 of FS = 0x0000 00000 * LSB = 0.0 volts

APPENDIX B: REGISTER NAME CHANGES FROM PREVIOUS RELEASES

This section provides a mapping of the register names used in this document against register names used in previous releases.

Rev B - Register NamesRev A - Register Names
D/A Output Registers
DAC ValueDAC Value
D/A Control Registers
Voltage RangeVoltage Range
Output EnableEnable Output
Update RateUpdate Rate
Overcurrent ResetOvercurrent Reset
D/A Measurement Registers
Wrap VoltageWrap Voltage
Wrap CurrentWrap Current
Internal VoltageInternal Voltage
D/A Test Registers
Test EnabledTest Enable
FIFO Registers
Data ModeUse FIFO
FIFO Buffer DataFIFO Buffer Data
FIFO Word CountFIFO Word Count
FIFO Almost EmptyFIFO Empty Mark
FIFO Low WatermarkFIFO Low Mark
FIFO High WatermarkFIFO High Mark
FIFO Almost FullFIFO Full Mark
Clear FIFOFIFO Reset
Pattern ControlFIFO Loop Mode
Software TriggerSoftware Trigger
Engineering Scaling Conversion Registers
Enable Floating Point Mode
Floating Point Offset
Floating Point Scale
Floating Point State
Background BIT Threshold Programming Registers
Background BIT Threshold
Reset BIT
Status and Interrupt Registers
Channel Status Enabled
BIT Dynamic StatusBIT Dynamic Status
BIT Latched StatusBIT Latched Status
BIT Interrupt EnableBIT Interrupt Enable
BIT Set Edge/Level InterruptBIT Set Edge/Level Interrupt
Overcurrent Dynamic StatusOvercurrent Dynamic Status
Overcurrent Latched StatusOvercurrent Latched Status
Overcurrent Interrupt EnableOvercurrent Interrupt Enable
Overcurrent Set Edge/Level InterruptOvercurrent Set Edge/Level Interrupt
External Power Under Voltage Dynamic StatusExternal Power Loss Dynamic Status
External Power Under Voltage Latched StatusExternal Power Loss Latched Status
External Power Under Voltage Interrupt EnableExternal Power Loss Interrupt Enable
External Power Under Voltage Set Edge/Level InterruptExternal Power Loss Set Edge/Level Interrupt
Inter-FPGA Failure Dynamic Status
Inter-FPGA Failure Latched Status
Inter-FPGA Failure Interrupt Enable
Inter-FPGA Failure Set Edge/Level Interrupt
Summary Dynamic Status
Summary Latched Status
Summary Interrupt Enable
Summary Set Edge/Level Interrupt
FIFO Dynamic StatusFIFO Dynamic Status
FIFO Latched StatusFIFO Latched Status
FIFO Interrupt EnableFIFO Interrupt Enable
FIFO Set Edge/Level InterruptFIFO Set Edge/Level Interrupt
Interrupt Vector
Interrupt Steering

APPENDIX C: PIN-OUT DETAILS

Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals.

Module Signal (Ref Only)44-Pin I/O50-Pin I/O (Mod Slot 1-J3)50-Pin I/O (Mod Slot 2-J4)50-Pin I/O (Mod Slot 3-J3)50-Pin I/O (Mod Slot 3-J4)D/A (16 CH) (DA2)
DATIO121012OUT_CH01
DATIO224352627OUT_CH02
DATIO331123OUT_CH03
DATIO425362728OUT_CH04
DATIO551345GND-DA
DATIO627382930GND-DA
DATIO771456OUT_CH05
DATIO829393031OUT_CH06
DATIO981567OUT_CH07
DATIO1030403132OUT_CH08
DATIO11101789GND-DA
DATIO1232423334GND-DA
DATIO131218917OUT_CH09
DATIO1434433442OUT_CH10
DATIO1513191018OUT_CH11
DATIO1635443543OUT_CH12
DATIO1715211220GND-DA
DATIO1837463745GND-DA
DATIO1917221321OUT_CH13
DATIO2039473846OUT_CH14
DATIO2118231422OUT_CH15
DATIO2240483947OUT_CH16
DATIO2320251624GND-DA
DATIO2442504149GND-DA
DATIO2541234
DATIO2626372829
DATIO2791678
DATIO2831413233
DATIO2914201119EXT-SYNC+
DATIO3036453644EXT-SYNC-
DATIO3119241523
DATIO3241494048
DATIO336
DATIO3428
DATIO3511
DATIO3633
DATIO3716
DATIO3838
DATIO3921
DATIO4043
N/A

D/A HARDWARE BLOCK DIAGRAM

Figure 1. DA2 Hardware Block Diagram

FIRMWARE REVISION NOTES

This section identifies the firmware revision in which specific features were released. Prior revisions of the firmware would not support the features listed.

FeatureFPGABare Metal (BM)
Firmware RevisionRelease DateFirmware RevisionRelease Date
Power-On Self-Test (POST) / Power-on BIT (PBIT) / Start-up BIT(SBIT)2.6 and later10/08/20193.4 and later01/07/2020
Engineering Scaling Conversions2.6 and later10/08/20193.4 and later01/07/2020
Background BIT Threshold Programming2.6 and later10/08/20193.4 and later01/07/2020
Watchdog Timer Capability2.6 and later10/08/20193.4 and later01/07/2020
Channel Status Enabled and Summary Status2.6 and later10/08/20193.4 and later01/07/2020

STATUS AND INTERRUPTS

Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.

For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.

Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.

Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).

Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.

Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).

  • Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edge-triggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.

  • Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Interrupt Trigger Types

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

Dynamic and Latched Status Registers Examples

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

No Clearing of Latched StatusClearing of Latched Status (Edge-Triggered)Clearing of Latched Status(Level-Triggered)
TimeDynamic StatusLatched StatusActionLatched StatusActionLatched
T00x00x0Read Latched Register0x0Read Latched Register0x0
T10x10x1Read Latched Register0x10x1
T10x10x1Write 0x1 to Latched RegisterWrite 0x1 to Latched Register
T10x10x10x00x1
T20x00x1Read Latched Register0x0Read Latched Register0x1
T20x00x1Read Latched Register0x0Write 0x1 to Latched Register
T20x00x1Read Latched Register0x00x0
T30x20x3Read Latched Register0x2Read Latched Register0x2
T30x20x3Write 0x2 to Latched RegisterWrite 0x2 to Latched Register
T30x20x30x00x2
T40x20x3Read Latched Register0x1Read Latched Register0x3
T40x20x3Write 0x1 to Latched RegisterWrite 0x3 to Latched Register
T40x20x30x00x2
T50xC0xFRead Latched Register0xCRead Latched Register0xE
T50xC0xFWrite 0xC to Latched RegisterWrite 0xE to Latched Register
T50xC0xF0x00xC
T60xC0xFRead Latched Register0x0Read Latched0xC
T60xC0xFRead Latched Register0x0Write 0xC to Latched Register
T60xC0xFRead Latched Register0x00xC
T70x40xFRead Latched Register0x0Read Latched Register0xC
T70x40xFRead Latched Register0x0Write 0xC to Latched Register
T70x40xFRead Latched Register0x00x4
T80x40xFRead Latched Register0x0Read Latched Register0x4

Interrupt Examples

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

TimeLatched Status (Edge-Triggered - Clear Multi-Channel)Latched Status (Edge-Triggered - Clear Single Channel) 2+Latched Status (Level-Triggered - Clear Multi-Channel)Action
LatchedActionLatchedActionLatchedT1 (Int 1)
Interrupt Generated++``+
Read Latched Registers		0x1Interrupt Generated++``+
Read Latched Registers		0x1Interrupt Generated++``+
Read Latched Registers		0x1T1 (Int 1)
Write 0x1 to Latched RegisterWrite 0x1 to Latched RegisterWrite 0x1 to Latched RegisterT1 (Int 1)
0x00x0Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T2.		0x1T3 (Int 2)
Interrupt Generated++``+
Read Latched Registers		0x2Interrupt Generated++``+
Read Latched Registers		0x2Interrupt Generated++``+
Read Latched Registers		0x2T3 (Int 2)
Write 0x2 to Latched RegisterWrite 0x2 to Latched RegisterWrite 0x2 to Latched RegisterT3 (Int 2)
0x00x0Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T7.		0x2T4 (Int 3)
Interrupt Generated++``+
Read Latched Registers		0x1Interrupt Generated++``+
Read Latched Registers		0x1Interrupt Generated++``+
Read Latched Registers		0x3T4 (Int 3)
Write 0x1 to Latched RegisterWrite 0x1 to Latched RegisterWrite 0x3 to Latched RegisterT4 (Int 3)
0x00x0Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.		0x3T4 (Int 3)
0x00x0Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T7.		0x2T6 (Int 4)
Interrupt Generated++``+
Read Latched Registers		0xCInterrupt Generated++``+
Read Latched Registers		0xCInterrupt Generated++``+
Read Latched Registers		0xET6 (Int 4)
Write 0xC to Latched RegisterWrite 0x4 to Latched RegisterWrite 0xE to Latched RegisterT6 (Int 4)
0x0Interrupt re-triggers++``+
Write 0x8 to Latched Register		0x8Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.		0xET6 (Int 4)
0x00x0Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.		0xCT6 (Int 4)
0x00x0Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.		0x4

REVISION HISTORY

Motherboard Manual - Status and Interrupts Revision History
RevisionRevision DateDescription
C2021-11-30C08896; Transition manual to docbuilder format - no technical info change.

DOCS.NAII REVISIONS

Revision DateDescription
2026-03-02Formatting updates to document; no technical changes.
Link to original

USER WATCHDOG TIMER MODULE MANUAL

User Watchdog Timer Capability

The User Watchdog Timer (UWDT) Capability is available on the following modules:

  • AC Reference Source Modules

    • AC1 - 1 Channel, 2-115 Vrms, 47 Hz - 20kHz
    • AC2 - 2 Channels, 2-28 Vrms, 47 Hz - 20kHz
    • AC3 - 1 Channel, 28-115 Vrms, 47 Hz - 2.5 kHz

  • Differential Transceiver Modules

    • DF1/DF2 - 16 Channels Differential I/O

  • Digital-to-Analog (D/A) Modules

    • DA1 - 12 Channels, ±10 VDC @ 25 mA, Voltage or Current Control Modes
    • DA2 - 16 Channels, ±10 VDC @ 10 mA
    • DA3 - 4 Channels, ±40 VDC @ ±100 mA, Voltage or Current Control Modes
    • DA4 - 4 Channels, ±80 VDC @ 10 mA
    • DA5 - 4 Channels, ±65 VDC or ±2 A, Voltage or Current Control Modes

  • Digital-to-Synchro/Resolver (D/S) or Digital-to-L( R )VDT (D/LV) Modules

    • (Not supported)

  • Discrete I/O Modules

    • DT1/DT4 - 24 Channels, Programmable for either input or output, output up to 500 mA per channel from an applied external 3 - 60 VCC source.

    • DT2/DT5 - 16 Channels, Programmable for either input voltage measurements (±80 V) or as a bi-directional current switch (up to 500 mA per channel).

    • DT3/DT6 - 4 Channels, Programmable for either input voltage measurements (±100 V) or as a bi-directional current switch (up to 3 A per channel).

  • TTL/CMOS Modules

    • TL1-TL8 - 24 Channels, Programmable for either input or output.

Principle of Operation

The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.

The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:

  • The application must not strobe during the Quiet time.
  • The application must strobe within the Window time.
  • The application must not strobe more than once in a single window time.

A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.

The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.

The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.

Figure 1. User Watchdog Timer Overview

Figure 2. User Watchdog Timer Example

Figure 3. User Watchdog Timer Failures

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

User Watchdog Timer Registers

The registers associated with the User Watchdog Timer provide the ability to specify the UWDT Quiet Time and the UWDT Window that will be monitored to ensure that EXACTLY ONE User Watchdog Timer (UWDT) Strobe is written within the window.

UWDT Quiet Time
Function:Sets Quiet Time value (in microseconds) to use for the User Watchdog Timer Frame.
Type:unsigned binary word (32-bit)
Data Range:0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write:R/W
Initialized Value:0x0
Operational Settings:LSB = 1 µsec. The application must NOT write a strobe in the time between the previous strobe and the end of the Quiet time interval. In addition, the application must write in the UWDT Window EXACTLY ONCE.
UWDT Window
Function:Writes the window value (in microseconds) to be used for the User Watchdog Timer Frame.
Type:unsigned binary word (32-bit)
Data Range:0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write:R/W
Initialized Value:0x0
Operational Settings:LSB = 1 µsec. The application must write the strobe once within the Window time after the end of the Quiet time interval. The application must write in the UWDT Window EXACTLY ONCE. This setting must be initialized to a non-zero value for operation and should allow sufficient tolerance for strobe timing by the application.
UWDT Strobe
Function:Writes the strobe value to be use for the User Watchdog Timer Frame.
Type:unsigned binary word (32-bit)
Data Range:0x55AA
Read/Write:W
Initialized Value:0x0
Operational Settings:At startup, the user watchdog is disabled. Write the value of 0x55AA to this register to start the user watchdog timer monitoring after initial power on or a reset. To prevent a disablement, the application must periodically write the strobe based on the user watchdog timer rules.

Status and Interrupt

The modules that are capable of User Watchdog Timer support provide status registers for the User Watchdog Timer.

User Watchdog Timer Status

The status register that contains the User Watchdog Timer Fault information is also used to indicate channel Inter-FPGA failures on modules that have communication between FPGA components. There are four registers associated with the User Watchdog Timer Fault/Inter-FPGA Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Function:Sets the corresponding bit (D31) associated with the channel’s User Watchdog Timer Fault error.
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value:0
User Watchdog Timer Fault/Inter-FPGA Failure Dynamic Status
User Watchdog Timer Fault/Inter-FPGA Failure Latched Status
User Watchdog Timer Fault/Inter-FPGA Failure Interrupt Enable
User Watchdog Timer Fault/Inter-FPGA Failure Set Edge/Level Interrupt
Bit(s)StatusDescription
D31User Watchdog Timer Fault Status0 = No Fault + 1 = User Watchdog Timer Fault
D30:D0Reserved for Inter-FPGA Failure StatusChannel bit-mapped indicating channel inter FPGA communication failure detection.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.

In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note

the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector
Function:Set an identifier for the interrupt.
Type:unsigned binary word (32-bit)
Data Range:0 to 0xFFFF FFFF
Read/Write:R/W
Initialized Value:0
Operational Settings:When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function:Sets where to direct the interrupt.
Type:unsigned binary word (32-bit)
Data Range:See table
Read/Write:R/W
Initialized Value:0
Operational Settings:When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME1
Direct Interrupt to ARM Processor (via SerDes)
(Custom App on ARM or NAI Ethernet Listener App)		2
Direct Interrupt to PCIe Bus5
Direct Interrupt to cPCI Bus6

Function Register Map

KEY

Configuration/Control
Measurement/Status
USER WATCHDOG TIMER REGISTERS
OFFSETREGISTER NAMEACCESSOFFSETREGISTER NAMEACCESS
0x01C0UWDT Quiet TimeR/W
0x01C4UWDT WindowR/W
0x01C8UWDT StrobeR/W
STATUS REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0”).
OFFSETREGISTER NAMEACCESSOFFSETREGISTER NAMEACCESS
0x09B0Dynamic StatusR
0x09B4Latched Status*R/W
0x09B8Interrupt EnableR/W
0x09BCSet Edge/Level InterruptR/W
INTERRUPT REGISTERS
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.
OFFSETREGISTER NAMEACCESSOFFSETREGISTER NAMEACCESS
0x056CModule 1 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W0x066CModule 1 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W
0x076CModule 2 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W0x086CModule 2 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W
0x096CModule 3 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W0x0A6CModule 3 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W
0x0B6CModule 4 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W0x0C6CModule 4 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W
0x0D6CModule 5 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W0x0E6CModule 5 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W
0x0F6CModule 6 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W0x106CModule 6 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA FailureR/W

REVISION HISTORY

Motherboard Manual - Status and Interrupts Revision History
RevisionRevision DateDescription
C2021-11-30C08896; Transition manual to docbuilder format - no technical info change.

DOCS.NAII REVISIONS

Revision DateDescription
2026-03-02Formatting updates to document; no technical changes.
Link to original

MODULE COMMON REGISTERS

The registers described in this document are common to all NAI Generation 5 modules.

Module Information Registers

The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.

FPGA Version Registers

The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.

FPGA Revision
Function:FPGA firmware revision
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R
Initialized Value:Value corresponding to the revision of the board's FPGA
Operational Settings:The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Major Revision Number
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Minor Revision Number
FPGA Compile Timestamp
Function:Compile Timestamp for the FPGA firmware.
Type:unsigned binary word (32-bit)
Data Range:N/A
Read/Write:R
Initialized Value:Value corresponding to the compile timestamp of the board's FPGA
Operational Settings:The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
day (5-bits)month (4-bits)year (6-bits)hr
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
hour (5-bits)minutes (6-bits)seconds (6-bits)
FPGA SerDes Revision
Function:FPGA SerDes revision
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R
Initialized Value:Value corresponding to the SerDes revision of the board's FPGA
Operational Settings:The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Major Revision Number
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Minor Revision Number
FPGA Template Revision
Function:FPGA Template revision
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R
Initialized Value:Value corresponding to the template revision of the board's FPGA
Operational Settings:The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Major Revision Number
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Minor Revision Number
FPGA Zynq Block Revision
Function:FPGA Zynq Block revision
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R
Initialized Value:Value corresponding to the Zynq block revision of the board's FPGA
Operational Settings:The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Major Revision Number
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Minor Revision Number

Bare Metal Version Registers

The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.

Bare Metal Revision
Function:Bare Metal firmware revision
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R
Initialized Value:Value corresponding to the revision of the board's Bare Metal
Operational Settings:The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Major Revision Number
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Minor Revision Number
Bare Metal Compile Time
Function:Provides an ASCII representation of the Date/Time for the Bare Metal compile time.
Type:24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range:N/A
Read/Write:R
Initialized Value:Value corresponding to the ASCII representation of the compile time of the board's Bare Metal
Operational Settings:The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Note

little-endian order of ASCII values

Word 1 (Ex. 0x2079614D)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Space (0x20)Month ('y' - 0x79)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Month ('a' - 0x61)Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Year ('2' - 0x32)Space (0x20)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Day ('7' - 0x37)Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Space (0x20)Year ('9' - 0x39)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Year ('1' - 0x31)Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Hour ('1' - 0x31)Space (0x20)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
'a' (0x74)'t' (0x61)
Word 5 (Ex. 0x38333A35)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Minute ('8' - 0x38)Minute ('3' - 0x33)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
':' (0x3A)Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
NULL (0x00)Seconds ('2' - 0x32)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Seconds ('3' - 0x33)':' (0x3A)

FSBL Version Registers

The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).

FSBL Revision
Function:FSBL firmware revision
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R
Initialized Value:Value corresponding to the revision of the board's FSBL
Operational Settings:The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Major Revision Number
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Minor Revision Number
FSBL Compile Time
Function:Provides an ASCII representation of the Date/Time for the FSBL compile time.
Type:24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range:N/A
Read/Write:R
Initialized Value:Value corresponding to the ASCII representation of the Compile Time of the board's FSBL
Operational Settings:The six 32-bit words provide an ASCII representation of the Date/Time.

The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Note

little-endian order of ASCII values

Word 1 (Ex. 0x2079614D)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Space (0x20)Month ('y' - 0x79)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Month ('a' - 0x61)Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Year ('2' - 0x32)Space (0x20)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Day ('7' - 0x37)Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Space (0x20)Year ('9' - 0x39)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Year ('1' - 0x31)Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Hour ('1' - 0x31)Space (0x20)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
'a' (0x74)'t' (0x61)
Word 5 (Ex. 0x38333A35)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Minute ('8' - 0x38)Minute ('3' - 0x33)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
':' (0x3A)Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
NULL (0x00)Seconds ('2' - 0x32)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Seconds ('3' - 0x33)':' (0x3A)

Module Serial Number Registers

The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.

Interface Board Serial Number
Function:Unique 128-bit identifier used to identify the interface board.
Type:16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range:N/A
Read/Write:R
Initialized Value:Serial number of the interface board
Operational Settings:This register is for information purposes only.
Functional Board Serial Number
Function:Unique 128-bit identifier used to identify the functional board.
Type:16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range:N/A
Read/Write:R
Initialized Value:Serial number of the functional board
Operational Settings:This register is for information purposes only.
Module Capability
Function:Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0x0000 0107
Read/Write:R
Initialized Value:0x0000 0107
Operational Settings:A “1” in the bit associated with the capability indicates that it is supported.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
0000000Flt-Pt00000PackFIFO BlkBlk
Module Memory Map Revision
Function:Module Memory Map revision
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R
Initialized Value:Value corresponding to the Module Memory Map Revision
Operational Settings:The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Major Revision Number
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Minor Revision Number

Module Measurement Registers

The registers in this section provide module temperature measurement information.

Temperature Readings Registers

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.

Interface Board Current Temperature
Function:Measured PCB and Zynq Core temperatures on Interface Board.
Type:signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:0x0000 0000 to 0x0000 FFFF
Read/Write:R
Initialized Value:Value corresponding to the measured PCB and Zynq core temperatures based on the table below
Operational Settings:The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
PCB TemperatureZynq Core Temperature
Functional Board Current Temperature
Function:Measured PCB temperature on Functional Board.
Type:signed byte (8-bits) for PCB
Data Range:0x0000 0000 to 0x0000 00FF
Read/Write:R
Initialized Value:Value corresponding to the measured PCB on the table below
Operational Settings:The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
00000000PCB Temperature
Interface Board Maximum Temperature
Function:Maximum PCB and Zynq Core temperatures on Interface Board since power-on.
Type:signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:0x0000 0000 to 0x0000 FFFF
Read/Write:R
Initialized Value:Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings:The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
PCB TemperatureZynq Core Temperature
Interface Board Minimum Temperature
Function:Minimum PCB and Zynq Core temperatures on Interface Board since power-on.
Type:signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:0x0000 0000 to 0x0000 FFFF
Read/Write:R
Initialized Value:Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings:The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
PCB TemperatureZynq Core Temperature
Functional Board Maximum Temperature
Function:Maximum PCB temperature on Functional Board since power-on.
Type:signed byte (8-bits) for PCB
Data Range:0x0000 0000 to 0x0000 00FF
Read/Write:R
Initialized Value:Value corresponding to the measured PCB on the table below
Operational Settings:The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
00000000PCB Temperature
Functional Board Minimum Temperature
Function:Minimum PCB temperature on Functional Board since power-on.
Type:signed byte (8-bits) for PCB
Data Range:0x0000 0000 to 0x0000 00FF
Read/Write:R
Initialized Value:Value corresponding to the measured PCB on the table below
Operational Settings:The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
0000000000000000
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
00000000PCB Temperature

Higher Precision Temperature Readings Registers

These registers provide higher precision readings of the current Zynq and PCB temperatures.

Higher Precision Zynq Core Temperature
Function:Higher precision measured Zynq Core temperature on Interface Board.
Type:signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R
Initialized Value:Measured Zynq Core temperature on Interface Board
Operational Settings:The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Signed Integer Part of Temperature
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Fractional Part of Temperature
Higher Precision Interface PCB Temperature
Function:Higher precision measured Interface PCB temperature.
Type:signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R
Initialized Value:Measured Interface PCB temperature
Operational Settings:The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Signed Integer Part of Temperature
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Fractional Part of Temperature
Higher Precision Functional PCB Temperature
Function:Higher precision measured Functional PCB temperature.
Type:signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R
Initialized Value:Measured Functional PCB temperature
Operational Settings:The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Signed Integer Part of Temperature
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Fractional Part of Temperature

Module Health Monitoring Registers

The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.

Module Sensor Summary Status
Function:The corresponding sensor bit is set if the sensor has crossed any of its thresholds.
Type:unsigned binary word (32-bits)
Data Range:See table below
Read/Write:R
Initialized Value:0
Operational Settings:This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.
Bit(s)Sensor
D31:D6Reserved
D5Functional Board PCB Temperature
D4Interface Board PCB Temperature
D3:D0Reserved

Module Sensor Registers

The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.

Sensor Threshold Status
Function:Reflects which threshold has been crossed
Type:unsigned binary word (32-bits)
Data Range:See table below
Read/Write:R
Initialized Value:0
Operational Settings:The associated bit is set when the sensor reading exceed the corresponding threshold settings.
Bit(s)Description
D31:D4Reserved
D3Exceeded Upper Critical Threshold
D2Exceeded Upper Warning Threshold
D1Exceeded Lower Critical Threshold
D0Exceeded Lower Warning Threshold
Sensor Current Reading
Function:Reflects current reading of temperature sensor
Type:Single Precision Floating Point Value (IEEE-754)
Data Range:Single Precision Floating Point Value (IEEE-754)
Read/Write:R
Initialized Value:N/A
Operational Settings:The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Minimum Reading
Function:Reflects minimum value of temperature sensor since power up
Type:Single Precision Floating Point Value (IEEE-754)
Data Range:Single Precision Floating Point Value (IEEE-754)
Read/Write:R
Initialized Value:N/A
Operational Settings:The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Maximum Reading
Function:Reflects maximum value of temperature sensor since power up
Type:Single Precision Floating Point Value (IEEE-754)
Data Range:Single Precision Floating Point Value (IEEE-754)
Read/Write:R
Initialized Value:N/A
Operational Settings:The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Lower Warning Threshold
Function:Reflects lower warning threshold of temperature sensor
Type:Single Precision Floating Point Value (IEEE-754)
Data Range:Single Precision Floating Point Value (IEEE-754)
Read/Write:R/W
Initialized Value:Default lower warning threshold (value dependent on specific sensor)
Operational Settings:The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.
Sensor Lower Critical Threshold
Function:Reflects lower critical threshold of temperature sensor
Type:Single Precision Floating Point Value (IEEE-754)
Data Range:Single Precision Floating Point Value (IEEE-754)
Read/Write:R/W
Initialized Value:Default lower critical threshold (value dependent on specific sensor)
Operational Settings:The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.
Sensor Upper Warning Threshold
Function:Reflects upper warning threshold of temperature sensor
Type:Single Precision Floating Point Value (IEEE-754)
Data Range:Single Precision Floating Point Value (IEEE-754)
Read/Write:R/W
Initialized Value:Default upper warning threshold (value dependent on specific sensor)
Operational Settings:The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.
Sensor Upper Critical Threshold
Function:Reflects upper critical threshold of temperature sensor
Type:Single Precision Floating Point Value (IEEE-754)
Data Range:Single Precision Floating Point Value (IEEE-754)
Read/Write:R/W
Initialized Value:Default upper critical threshold (value dependent on specific sensor)
Operational Settings:The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.

FUNCTION REGISTER MAP

KEY

Configuration/Control
Measurement/Status/Board Information
MODULE INFORMATION REGISTERS
OFFSETREGISTER NAMEACCESSOFFSETREGISTER NAMEACCESS
0x003CFPGA RevisionR0x0074Bare Metal RevisionR
0x0030FPGA Compile TimestampR0x0080Bare Metal Compile Time (Bit 0-31)R
0x0034FPGA SerDes RevisionR0x0084Bare Metal Compile Time (Bit 32-63)R
0x0038FPGA Template RevisionR0x0088Bare Metal Compile Time (Bit 64-95)R
0x0040FPGA Zynq Block RevisionR0x008CBare Metal Compile Time (Bit 96-127)R
0x0090Bare Metal Compile Time (Bit 128-159)R
0x0094Bare Metal Compile Time (Bit 160-191)R
0x007CFSBL RevisionR
0x00B0FSBL Compile Time (Bit 0-31)R
0x00B4FSBL Compile Time (Bit 32-63)R
0x00B8FSBL Compile Time (Bit 64-95)R
0x00BCFSBL Compile Time (Bit 96-127)R
0x00C0FSBL Compile Time (Bit 128-159)R
0x00C4FSBL Compile Time (Bit 160-191)R
0x0000Interface Board Serial Number (Bit 0-31)R0x0010Functional Board Serial Number (Bit 0-31)R
0x0034Interface Board Serial Number (Bit 32-63)R0x0014Functional Board Serial Number (Bit 32-63)R
0x0008Interface Board Serial Number (Bit 64-95)R0x0018Functional Board Serial Number (Bit 64-95)R
0x000CInterface Board Serial Number (Bit 96-127)R0x001CFunctional Board Serial Number (Bit 96-127)R
0x0070Module CapabilityR
0x01FCModule Memory Map RevisionR
MODULE MEASUREMENTS REGISTERS
OFFSETREGISTER NAMEACCESSOFFSETREGISTER NAMEACCESS
0x0200Interface Board PCB/Zynq Current TempR0x0208Functional Board PCB Current TempR
0x0218Interface Board PCB/Zynq Max TempR0x0228Functional Board PCB Max TempR
0x0220Interface Board PCB/Zynq Min TempR0x0230Functional Board PCB Min TempR
0x02C0Higher Precision Zynq Core TemperatureR
0x02C4Higher Precision Interface PCB TemperatureR
0x02E0Higher Precision Functional PCB TemperatureR
MODULE HEALTH MONITORING REGISTERS
OFFSETREGISTER NAMEACCESSOFFSETREGISTER NAMEACCESS
0x07F8Module Sensor Summary StatusR
![](/_shared/images/Module_Sensor_Registers_Memory_Map.png)

REVISION HISTORY

Motherboard Manual - Module Common Registers Revision History
RevisionRevision DateDescription
C2023-08-11ECO C10649, initial release of module common registers manual.
C12024-05-15ECO C11522, removed Zynq Core/Aux/DDR Voltage register descriptions from Module Measurement Registers. Pg.16, updated Module Sensor Summary Status register to add PS references; updated Bit Table to change voltage/current bits to 'reserved'. Pg.16, updated Module/Power Supply Sensor Registers description to better describe register functionality and to add figure. Pg.17, added 'Exceeded' to threshold bit descriptions. Pg.17-18, removed voltage/current references from sensor descriptions. Pg.20, removed Zynq Core/Aux/DDR Voltage register offsets from Module Measurement Registers. Pg.20, updated Module Health Monitoring Registers offset tables.
C22024-07-10ECO C11701, pg.16, updated Module Sensor Summary Status register to remove PS references;updated Bit Table to change PS temperature bits to 'reserved'. Pg.16, updated Module SensorRegisters description to remove PS references. Pg.20, updated Module Health MonitoringRegisters offset tables to remove PS temperature register offsets.

DOCS.NAII REVISIONS

Revision DateDescription
2025-11-05Corrected register offsets for Interface Board Min Temp and Function Board Min & Max Temps.
2026-03-02Formatting updates to document; no technical changes.
Link to original

Revision History

Module Manual - DA2 Revision History

RevisionRevision DateDescription
C2023-06-13ECO C11340, Transitioned manual to docbuilder format. Pg.6, replaced Specifications section with Data Sheet. Pg.8, updated Introduction/replaced Features with Overview. Pg.9/20/30, added module common registers. Pg.23, removed Summary Events Table. Pg.44, added Pin-OutDetails.

Module Manual - Status and Interrupts Revision History

RevisionRevision DateDescription
C2021-11-30C08896; Transition manual to docbuilder format - no technical info change.

Module Manual - User Watchdog Timer Revision History

RevisionRevision DateDescription
C2023-08-11ECO C10649, initial release of module common registers manual.

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