DATA SHEET
Click here for the CMH data sheet
INTRODUCTION
As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurements and simulation, communications, Ethernet switch, and SBC functions. Our CMH combination module offers users the functionality of two COSA® smart function modules in one physical module. Based on NAI’s SC3 and DF1 modules, the CMH module provides five asynchronous (ASYNC) and six Digital I/O channels in a single smart function module. This user manual is designed to help you get the most out of our CMH smart function module.
CMH Overview
NAI’s CMH module offers a range of features designed to suit a variety of system requirements, including:
Serial Communications (SC3 Module-Type) Features
Five Communication Channels: The SC3 function offers five high-speed, programmable communication channels supporting RS232, RS-422, and RS-485 protocols. One channel (CH1) provides RS-232 ASYNC with hardware flow control (TX/RX/CTS/RTS). Four channels (CH2-CH5) provide RS-422/485 ASYNC with TX±/RX± differential signaling.
Data Transfer Efficiency: For asynchronous communications, data transfers occur within just two baud clocks, ensuring rapid data exchange.
Digital Noise Filtering: The SC3 function features digital noise filtering on receivers, enhancing signal quality and reliability.
Receiver Control: Users can selectively enable or disable specific receivers, providing fine-grained control over the communication channels.
Interrupt-Driven Operation: The SC3 function can operate in an Interrupt-Driven environment, delivering notifications of all events to the system. When flow control mode is selected, the module handles operations automatically with minimal system intervention, streamlining the communication process.
Buffer Capacity: The module boasts 1MBx16 receive and transmit buffers, ensuring ample storage for data transfer.
Built-in Test: The SC3 function comes with a built-in test feature, simplifying diagnostics and maintenance.
Digital I/O (DF1 Module-Type) Features
Six Programmable I/O channels: The DF1 function features six programmable I/O channels. Each differential channel can be programmed for input or output, and each input channel has a selectable internal resistor of 120 ohms across its inputs.
Programmable Slew Rate: The slew rate of each channel can be programmed as fast or slow, with a slow slew rate being desirable for sensitive EMI-radiated transmission line applications.
Programmable debounce circuitry: The debounce circuits for each channel offer a programmable time delay, which eliminates false signals resulting from contact bounce commonly experienced with mechanical relays and switches. All inputs are continuously scanned.
Continuous background Built-in-Test (BIT): The DF1 function features Continuous Background Built-in-Test (BIT) status, which provides real-time channel health to ensure reliable operation in mission-critical systems. This feature runs in the background and is transparent in normal operations. When the channels are programmed as inputs, a redundant, read-back circuit continually scans each channel to verify the input. Similarly, when the channels are programmed as outputs, the read-back circuit is compared with the commanded output logic. This ensures that the data communication remains reliable and consistent.
SERIAL COMMUNICATIONS FUNCTION
The serial communications function is similar to the standard SC3 function module (SC3 may be used as a reference/guide within the context of this document).
Principle of Operation
Channel 1 of the SC3 function is always configured for RS-232 Asynchronous Serial Communication with hardware flow control. Channels 2 through 5 of the SC3 function can be individually software configured for RS-422 or RS-485 Asynchronous Serial Communications. The architecture avoids latency problems because all data transfer is done in hardware and not in software. Any incoming data, no matter how many channels are active, in whatever mode, can be immediately extracted. FPGA design simplifies programming and usage.
Configuration
Before the user can write to any configuration register, certain steps must be followed to ensure the module accepts the user specified configuration. The steps are as follows:
-
Write a 0 to the Enable Channel bit of the Tx-Rx Configuration register to tell the hardware that we are about to change the configuration.
-
Wait for the Channel Configured status of the Realtime Channel Status registers to read a 0.
-
Write all desired configuration registers.
-
Set the Enable Channel bit of the Tx-Rx Configuration register to 1 to notify the hardware that it can read all the configuration registers.
-
Wait for the Channel Configured status in the Realtime Channel Status register to read a 1 before proceeding to send/receive data.
Hardware Flow Control
Channel 1 of the SC3 function is configured to operate in hardware flow control mode. This enables the channel’s transmitter and receiver to be used with the Request to Send (RTS) and Clear to Send (CTS) signals.
Gap Timeout Status
The Gap Timeout Occurred status gets set when there’s data in a channel’s receive buffer but there’s no activity on a channel’s receiver for approximately three byte-times. To use the Gap Timeout feature, set the Enable Gap Timeout bit in the Tx-Rx Configuration register to a 1. When receiving asynchronous data, monitor the Gap Timeout status bit of the Channel Status register to know if a timeout occurred. The status is cleared after all the data in the receive buffer is read or cleared.
Serial Built-In Test/Diagnostic Capability
The SC3 function supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are logically ORed together and stored in the BIT Dynamic Status and BIT Latched Status registers.
Power-on Self-Test (POST)/Power-on BIT (PBIT)/Start-up BIT (SBIT)
The power-on self-test is performed on each channel automatically when power is applied and report the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.
Continuous Background Built-In Test
The background Built-In-Test (BIT) or Continuous BIT (CBIT) runs in the background for each enabled channel. It monitors the transmit and receive lines using dedicated hardware to detect any differences in the levels. The technique used by the automatic background BIT test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the threshold value, the specific channel’s fault bit in the BIT status register will be set, the internal threshold can be scaled via the Background BIT Threshold register.
Note
the interval at which BIT is performed is dependent and differs between module types.
The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained; i.e. at a ten second interval, not a 10-millisecond interval). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state. Results of the Continuous BIT are stored in the BIT Dynamic Status and BIT Latched Status register.
Initiated Built-In Test
The Initiated Built-In-Test (IBIT) is an internal loopback available for each channel of the SC3 module. The test is initiated by setting the bit for the associated channel in the Test Enabled register or (for legacy applications) setting the Initiate BIT bit of the Tx-Rx-Configuration register to a 1. Prior to initiating the test, the user must disable the channel, and its respective pair, by writing a 0 to the Enable Channel bit of the channel’s Tx-Rx-Configuration register. BIT will not run if the channel is enabled. After the user disables the channel and initiates BIT, they must wait a minimum of 5 msec then check to see if the bit for the associated channel in the Test Enabled register or (for legacy application) Initiate BIT bit of the Tx-Rx-Configuration register reads a 0. When the SC3 clears the bit, it means that the test has completed, and its results can be checked. If the bit has not cleared after 10ms, the test has timed out and not run. In the event this should occur, the user should verify that the channel, and its pair, has been disabled. The results of the IBIT is stored in the BIT Dynamic Status and BIT Latched Status registers, a 0 indicates that the channel has passed and a 1 indicates that it failed.
Receiver Enable/Disable
A Receiver Enable/Disable function allows the user to turn selected receivers ON/OFF. When a receiver is disabled, no data will be placed in the buffer.
Serial Data Transmit Enhancement
An additional asynchronous mode to support “Immediate Transmit” operation has been incorporated. This mode immediately transmits serial data anytime the transmit buffer is not empty. There is no requirement to set the Tx Initiate bit before each transmission, which simplifies system traffic and overhead, since only the actual data byte being transmitted needs be sent to the transmit buffer. Each channel has its own configurable Transmit and Receive buffer. The upper byte of each received word provides status information for that word.
Multi-Drop Link Mode (RS485)
The transmitter and receivers of up to 32 channels can be tied together in either Half or Full-Duplex mode. While in Multi-Drop Link Mode, the transmit line for each channel will automatically tri-state. When data in the transmit buffer is initiated, the transmitter will be taken out of tri-state and send the data. Once transmission is completed, the transmit line is automatically changed back to tri-state mode.
To program the serial channel for Multi-Drop mode, the interface level must be set to RS485, and the Tristate Transmit Line bit in the Channel Control register must be set to a 1.
Communication Module Factory Defaults: Registers and Delays
| Address Recognition: | Off |
|---|---|
| Baud Rate: | 9600 |
| CTS/RTS: | Disabled |
| Protocol: | 0 |
| Interface Levels: | 5 (Tri-state mode) |
| Termination Character: | 0x0003h |
| Interrupt Level: | 0 |
| Interrupt Vector: | 0x00 |
| Mode: | Asynchronous |
| Number of Data Bits: | 8 |
| Parity: | Disabled |
| Receivers: | Disabled |
| Transmit Buffer Word Count: | 0 |
| Receive Buffer Word Count: | 0 |
| Receive Buffer, Almost Full: | 0xFFF9B |
| Stop Bits: | 1 |
| Transmit Buffer, Almost Empty: | 0x0064 |
| Tx-Rx Configuration: | 0 |
| Channel Control: | 0 |
| Data Configuration: | 0x0108 |
| Preamble: | 0 |
| Receive Buffer High Watermark: | 0xFFF9B |
| Receive Buffer Low Watermark: | 0x0800h |
| XON: | 0x0011h |
| XOFF: | 0x0013h |
| XON/XOFF: | Disabled |
| Time Out Value: | 0x9C40 |
A write to the following registers takes place immediately:
-
Transmit Data
-
Channel Control
-
Channel Interrupt Enable
-
Channel Interrupt Edge/Level
-
Summary Interrupt Enable
-
Summary Edge/Level
-
Interrupt Vector
-
Interrupt Steering
For all other registers, channel configuration protocol must be followed.
Status and Interrupts
The SC3 Serial Communications function provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.
Module Common Registers
The SC3 Serial Communications function includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.
Register Descriptions
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.
Receive Registers
Serial data received are placed in the Receive FIFO Buffer register. The Receive FIFO Buffer Word Count provide the count of the number of elements in the Receive FIFO Buffer. The Receive FIFO Buffer Almost Full, Receive FIFO Buffer High Watermark and Receive FIFO Buffer Low Watermark registers provide the ability to specify the thresholds for the associated status in the Channel FIFO Status register.
Receive FIFO Buffer
| Function: | Received data is placed in this buffer. |
|---|---|
| Type: | unsigned binary word (32-bit). |
| Data Range: | 0x 0000 0000 to 0x 0000 FFFF |
| Read/Write: | R |
| Initialized Value: | Not Applicable (NA) |
| Operational Settings: Data is received is based on Protocol. |
Note
BOF is defined as the first data message received after a frame opens (dependent on channel configuration).
Note
EOF is defined as the last message received (dependent on channel configuration).
Note
Receive FIFO Buffer is a self-clearing register. Performing a register read of the Receive FIFO marks the current location as ‘read’. This moves the pointer to the next unread location and decrements the Receive FIFO Buffer Word Count register count by one.
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| PE | FE/BOF | 0 | 0 | 0 | EOF/ER0 | P/EOF | D | D | D | D | D | D | D | D | D |
| PE | = Parity Error | A 1 indicates the calculated parity does not match the received parity bit. |
|---|---|---|
| FE | = Framing Error | A 1 indicates a framing error was detected. |
| BOF | = Beginning of Frame | A 1 indicates first character of frame. Useful to identify multiple frames in large buffer. |
| EOF | = End of Frame | A 1 indicates an ETx character was received. Termination Character Detection must be turned on. |
| P | = Parity Bit | This bit carries the parity bit of the last received character. |
| ER0 | = Last Frame Status | 000 = Good Frame, 111 = CRC Error |
Receive FIFO Buffer Word Count
| Function: | Contains the number of words in the Receive FIFO Buffer waiting to be read back. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0 to 0x0010 0000 (Buffer Size) |
| Read/Write: | R |
| Initialized Value: | 0 |
| Operational Settings: | Reads Integers |
Receive FIFO Buffer Almost Full
| Function: | Specifies the maximum size, in bytes, of the receive buffer before the Receive FIFO Almost Full Status bit D0 in the FIFO Status register is flagged (High True). |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0 to 0x0010 0000 (Buffer Size) |
| Read/Write: | R/W |
| Initialized Value: | 1048475 (0x000F FF9B) |
| Operational Settings: | If the interrupt is enabled (see Interrupt Enable register), a System interrupt will be generated. |
Receive FIFO Buffer High Watermark
| Function: | Defines the Receive Buffer High Watermark value. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | Low Watermark < High Watermark < 0xFFF9B |
| Read/Write: | R/W |
| Initialized Value: | 1048475 (0x000F FF9B) |
| Operational Settings: | When Receive FIFO Buffer size equals the High Watermark value, the High Watermark bit in both the FIFO Status and Channel Status registers is set to a 1 and: * If RTS/CTS is enabled, RTS goes inactive. The Watermark registers are used for RTS/CTS flow control. The Receive Buffer High Watermark register value controls when the RTS signal would be negated when using hardware flow control. There is also a High Watermark Reached interrupt enable/disable bit in the Channel Interrupt Enable register and a High Watermark Reached bit in the Channel Interrupt Status register. When the High Watermark is reached, an interrupt request will be generated, when the interrupt enable/disable bit is enabled. |
Receive FIFO Buffer Low Watermark
| Function: | Defines the Receive Buffer Low Watermark value. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | Low Watermark < High Watermark < 0xFFF9B |
| Read/Write: | R/W |
| Initialized Value: | 2048 (0x0800) |
| Operational Settings: | When Receive FIFO Buffer size equals the Low Watermark value, the Low Watermark bit in both the FIFO Status and Channel Status registers is set to a 1 and: * If RTS/CTS is enabled, RTS goes inactive. The Watermark registers are used for RTS/CTS flow control. The Receive Buffer Low Watermark register value controls when the RTS signal would be negated when using hardware flow control. There is also a Low Watermark Reached interrupt enable/disable bit in the Channel Interrupt Enable register and a Low Watermark Reached bit in the Channel Interrupt Status register. When the Low Watermark is reached, an interrupt request will be generated, when the interrupt enable/disable bit is enabled. |
Transmit Registers
Serial data to be transmitted are placed in the Transmit FIFO Buffer register. The Transmit FIFO Buffer Word Count provides the count of the number of elements in the Transmit FIFO Buffer. The Receive FIFO Buffer Almost Empty register provide the ability to specify the threshold for the associated status in the Channel FIFO Status register.
Transmit FIFO Buffer
| Function: | Data to be transmitted is placed in this buffer prior to transmission. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0x 0000 0000 to 0x 0000 01FF |
| Read/Write: | W |
| Initialized Value: | Not Applicable (NA) |
| Operational Settings: | Data words are 8-bit and occupy the register’s lowest significant bits (LSBs), or low byte. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | D | D | D | D | D | D | D | D | D |
Transmit FIFO Buffer Word Count
| Function: | Contains the number of words in the Transmit FIFO Buffer waiting to be transmitted. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0 to 0x0010 0000 (Buffer Size) |
| Read/Write: | R |
| Initialized Value: | 0 |
Transmit FIFO Buffer Almost Empty
| Function: | Specifies the minimum size, in bytes, of the transmit buffer before the Transmit Buffer Almost Empty Status bit D1 in the FIFO Status register is flagged (High True). |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0 to 0x0010 0000 (Buffer Size) |
| Read/Write: | R/W |
| Initialized Value: | 100 (0x64) |
| Operational Settings: | If the interrupt is enabled (see Interrupt Enable register), a System interrupt will be generated. |
Configuration Registers
SC3 configurations includes setting the Interface Levels, Baud Rate, Tx-Rx Configuration and if applicable, the Termination Character registers. Additional registers need to be configured specifically for Async or Sync modes.
Interface Levels
| Function: | Configures the interface level (RS-232, RS-422, RS-485, Loopback, Tri-State, FPGA Loop-Back) for the associated channel. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | See table |
| Read/Write: | R/W |
| Initialized Value: | 5 (Tri-State) |
| Operational Settings: | Loopback selection connects the channel’s transmit and receive line internally. To implement, user must send data and look at Receive FIFO to verify that the sent data. Loopback is usually used for testing. |
Note
Channels are programmed for loop back. For example, Channel 1 loops back to Channel 1, Channel 2 loops back to Channel 2, etc.
| Bit(s) | Interface | Description |
|---|---|---|
| D31:D8 | Reserved | Set Reserved bits to 0. |
| D7 | Disable termination resistor | Disables termination resistor in-between the differential pairs of the transmitter and the receiver. Useful for RS485 Multi-Drop. |
| D6:D3 | Reserved | Set Reserved bits to 0. |
| D2:D0 | Interface Level | These bits set the interface level: (0:0:0) RS232 (0:1:0) RS422 (0:1:1) RS485 (1:0:0) Loopback (1:0:1) Tri-State |
Baud Rate
| Function: | Sets the baud rate for communications. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 300 bps to 1.5 Mbps Async |
| Read/Write: | R/W |
| Initialized Value: | 9600 bps |
Tx-Rx Configuration
| Function: | Sets the transmit/receive configuration for the associated channel. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | See table |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | BIT - Set Enable Channel bit, D24 low (0) to clear the selected channel. The BIT Status register reports the channel status. |
| Bit(s) | Name | Description |
|---|---|---|
| D31:D27 | Reserved | Set Reserved bits to 0. |
| D26 | Invert RTS | 0 = Normal + 1 = Invert. NOTE: applicable to Channel 1 only; Channels 2-5 are set to Reserved (0) |
| D25 | Invert CTS | 0 = Normal + 1 = Invert. NOTE: applicable to Channel 1 only; Channels 2-5 are set to Reserved (0) |
| D24 | Enable Channel | 0 = Disable + 1 = Enable. |
| D23:D21 | Reserved | Set Reserved bits to 0. |
| D20 | Enable Gap Timeout | 0 = Ignore gap timeout + 1 = Set Gap Timeout Occurred status when there is no activity on the receiver’s bus for more than 3-byte times. |
| D19:D16 | Reserved | Set Reserved bits to 0. |
| D15 | Timeout Detection | Turns on timeout detection |
| D14:D13 | Reserved | Set Reserved bits to 0. |
| D12 | Termination Character Detection | 0 = Ignore termination character + 1 = Set Rx Complete/ETx Received status bit when termination character is received. |
| D11:D0 | Reserved | Set Reserved bits to 0. |
Termination Character
| Function: | Contains the termination character used for termination detection. |
|---|---|
| Type: | unsigned character (usually a member of the ASCII data set) |
| Data Range: | 0x00 to 0xFF |
| Read/Write: | R/W |
| Initialized Value: | 0x03 |
| Operational Settings: | The receive data stream is monitored for the occurrence of the termination character. When this character is detected, the Rx COMPLETE / ETx RECEIVED bit is set in the Channel Status register, an interrupt is generated, if enabled. |
Data Configuration
| Function: | Channel data configuration. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | See table |
| Read/Write: | R/W |
| Initialized Value: | 0x108 |
| Operational Settings: | Sets up the Serial channel configuration. |
| Bit(s) | Name | Description |
|---|---|---|
| D31:D10 | Reserved | Set Reserved bits to 0. |
| D9:D8 | Stop Bits | The following sets the number of stop bits: (0:1) 1 Stop bit + (1:0) 2 Stop bits |
| D7 | Reserved | Set Reserved bits to 0. |
| D6:D4 | Parity | The following sets the Parity: (0:0:0) No Parity (0:0:1) Space Parity (0:1:0) Reserved (0:1:1) Odd Parity (1:0:0) Reserved (1:0:1) Even Parity (1:1:1) Mark Parity |
| D3:D0 | Number of Data Bits | Actual number of data bits between 5 and 9. |
Time Out Value
| Function: | Determines the timeout period. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0 to 0xFFFF |
| Read/Write: | R/W |
| Initialized Value: | 0x9C40 (1 second) |
| Operational Settings: | If there is no receive line activity for the configured period of time, a timeout is indicated in the Interrupt Status register (bit D10). LSB is 25µs. |
Control Register
The Channel Control register provides control of the serial channel.
Channel Control
| Function: | Channel control configuration. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | See table. |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | Real time control of the Serial channel. |
| Bit(s) | Name | Description |
|---|---|---|
| D31:D19 | Reserved | Set Reserved bits to 0. |
| D18 | Enable Receiver | |
| D17 | Tx Always | Transmit data as soon as data is buffered. |
| D16 | Tx Initiate | Transmit data in Tx buffer. (The data bit is cleared when all data from the Tx Buffer is transmitted) |
| D15 | Clear Tx FIFO | Clear all data in the Tx FIFO. The data bit is self-clearing. |
| D14 | Clear Rx FIFO | Clear all data in the Rx FIFO. The data bit is self-clearing. |
| D13 | Reset Channel FIFOs & UART | Clear both FIFOs and reset channel. Bit is NOT self-clearing. |
| D12:D11 | Reserved | Set Reserved bits to 0. |
| D10 | Set/Release Break | 0 = Break not set + 1 = Pull transmitter low |
| D9 | Reserved | Set Reserved bits to 0. |
| D8 | Tristate Transmit Line | Tristate the transmit line after transmitting, for use with RS485 Multi-Drop mode. |
| D7:D1 | Reserved | Set Reserved bits to 0. |
| D0 | RTS | Request to Send for HW flow control. |
Serial Test Registers
The serial module provides the ability to run an initiated test (IBIT). Writing a 1 to the bit associated with the channel in the Test Enabled register.
Test Enabled
| Function: | Set the bit corresponding to the channel you want to run Initiated Built-In-Test. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0 to 0x0000 001F |
| Read/Write: | R/W |
| Initialized Value: | 0x0 |
| Operational Settings: | Set bit to 1 for channel to run an Initiated BIT test. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects failures. Bit is self-clearing. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Background BIT Threshold Programming Registers
The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The Reset BIT register provides the ability to reset the BIT counter used in CBIT.
Background BIT Threshold
| Function: | Sets background BIT Threshold value to use for all channels for BIT failure indication. This value is a scalar for the internal BIT counter, refer to Continuous Background Built-In Test. To filter out momentary or intermittent anomalies in background BIT errors, this value can be increased to allow the error to “come and go” before the BIT status is flagged. |
|---|---|
| Data Range: | 0x1 to 0xFFFF |
| Read/Write: | R/W |
| Initialized Value: | 5 |
Reset BIT
| Function: | Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0 to 0x0000 001F |
| Read/Write: | W |
| Initialized Value: | 0 |
| Operational Settings: | Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Module Common Registers
Refer to “Module Common Registers Module Manual” for the register descriptions.
Status and Interrupt Registers
The SC3 Module provides status registers for BIT, Channel, Summary and Channel FIFO.
BIT Status
There are four registers associated with the BIT Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.
| Function: | Sets the corresponding bit associated with the channel’s BIT error. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0x0000 0000 to 0x003F 001F |
| Read/Write: | R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) |
| Initialized Value: | 0 |
Note
BIT Status is a shared register between the SC3 and DF1 functions. Bits D04:D0 are dedicated to the SC3 functions and bits D21:D16 are dedicated to the DF1 function.
| BIT Dynamic Status Register | |||||||||||||||
| BIT Latched Status Register | |||||||||||||||
| BIT Interrupt Enable Register | |||||||||||||||
| BIT Set Edge/Level Interrupt Register | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 DF1 | Ch5 DF1 | Ch4 DF1 | Ch3 DF1 | Ch2 DF1 | Ch1 DF1 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch5 SC3 | Ch4 SC3 | Ch3 SC3 | Ch2 SC3 | Ch1 SC3 |
Power-on BIT Complete
After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.
| Function: | Indication if Power-on BIT has completed. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0x0000 0000 to 0x0000 0001 |
| Read/Write: | R |
| Initialized Value: | 0 |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PBIT Complete |
Channel Status
| Function: | Sets the corresponding bit associated with each event type. There are separate registers for each channel. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | See table. |
| Read/Write: | R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt) Initialized Value: 0 |
| Channel Dynamic Status Register | |||
| Channel Latched Status Register | |||
| Channel Interrupt Enable Register | |||
| Channel Set Edge/Level Interrupt Register | |||
| Bit(s) | Name | Configurable | Description |
| D31 | Channel Configured | No | Module is configured and ready to operate. |
| D30 | Built-in-Self Test Passed | No | Indicates the status of the last ran IBIT test. |
| D29:D18 | Reserved | No | Set Reserved bits to 0. |
| D17 | Gap Timeout Occurred | Yes | Rx FIFO has data in it, but there hasn't been activity on the bus in 3-byte times. |
| D16 | Reserved | No | Set Reserved bits to 0. |
| D15 | CTS/GPI1 | No | Binary value of general-purpose input 1 or CTS. NOTE: applicable to Channel 1 only; Channels 2-5 are set to Reserved (0) |
| D14 | CTS Low Detect (fall) | No | CTS falling edge detected. NOTE: applicable to Channel 1 only; Channels 2-5 are set to Reserved (0) |
| D13 | CTS High Detect (rise) | No | CTS rising edge detected. NOTE: applicable to Channel 1 only; Channels 2-5 are set to Reserved (0) |
| D12 | Reserved | No | Set Reserved bits to 0. |
| D11 | Break/Abort | No | Break recognized. |
| D10 | Timeout Occurred | Yes | No receive line activity within timeout value. |
| D9 | Tx Complete | No | While transmitting, Tx FIFO count reaches zero. |
| D8 | Tx FIFO Almost Empty | Yes | Transmit FIFO Almost Empty Threshold reached. |
| D7 | Low Watermark Reached | Yes | Rx Buffer Low Watermark Threshold reached. |
| D6 | High Watermark Reached | Yes | Rx Buffer High Watermark Threshold reached. |
| D5 | Rx Overrun | No | Data was received while the Rx FIFO was full. |
| D4 | Rx Data Available | No | Receive FIFO count is greater than zero. |
| D3 | Rx Complete/ET x Received | No | Termination character received (Only if termination detection is turned on.) |
| D2 | Reserved | No | Set Reserved bits to 0. |
| D1 | Rx FIFO Almost Full | Yes | Receive FIFO Almost Full Threshold |
| D0 | Parity Error | No | Parity bit did not match. |
Note
For the Latched Channel Status register, the interrupts are cleared when a 1 is written to the specific bit.
Channel FIFO Status
| Function: | Describes current FIFO Status. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | See Table |
| Read/Write: | R |
| Initialized Value: | 0 |
| Operational Settings: | See Rx Almost Full, Tx Almost Empty, Rx High Watermark and Rx Low Watermark specific registers for function description and programming. |
| Bit(s) | Name | Configurable? | Description |
|---|---|---|---|
| D5 | Tx FIFO Full | No | Tx FIFO has reached maximum buffer size. |
| D4 | Rx FIFO Empty | No | Rx FIFO count is zero. |
| D3 | Low Watermark Reached | Yes | Rx Buffer Low Watermark Threshold reached. |
| D2 | High Watermark Reached | Yes | Rx Buffer High Watermark Threshold reached. |
| D1 | Tx FIFO Almost Empty | Yes | Tx FIFO Almost Empty Threshold reached. |
| D0 | Rx FIFO Almost Full | Yes | Rx FIFO Almost Full Threshold reached |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D | D | D | D | D | D |
Summary Status
| Function: | Sets the corresponding bit associated with the channel that has data available to receive in its Receive FIFO Buffer. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0x0000 0000 to 0x0000 001F |
| Read/Write: | R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt) |
| Initialized Value: | 0 |
| Summary Dynamic Status Register | |||||||||||||||
| Summary Latched Status Register | |||||||||||||||
| Summary Interrupt Enable Register | |||||||||||||||
| Summary Set Edge/Level Interrupt Register | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.
In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
Interrupt Vector
| Function: | Set an identifier for the interrupt. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | When an interrupt occurs, this value is reported as part of the interrupt mechanism. |
Interrupt Steering
| Function: | Sets where to direct the interrupt. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Data Range: | See table Read/Write: R/W |
| Initialized Value: | 0 |
| Operational Settings: | When an interrupt occurs, the interrupt is sent as specified: |
| Direct Interrupt to VME | 1 |
|---|---|
| Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) | 2 |
| Direct Interrupt to PCIe Bus | 5 |
| Direct Interrupt to cPCI Bus | 6 |
Function Register Map
Key:
| Regular Italic | = Incoming Data |
|---|---|
| Regular Underline | = Outgoing Data |
| Bold Italic | = Configuration/Control |
| Bold Underline | = Status |
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
Receive Registers
Base Address: 0x4000 0000
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1004 | Receive FIFO Buffer Ch 1 | R |
| 0x1084 | Receive FIFO Buffer Ch 2 | R |
| 0x1104 | Receive FIFO Buffer Ch 3 | R |
| 0x1184 | Receive FIFO Buffer Ch 4 | R |
| 0x1204 | Receive FIFO Buffer Ch 5 | R |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x100C | Receive FIFO Buffer Word Count Ch 1 | R |
| 0x108C | Receive FIFO Buffer Word Count Ch 2 | R |
| 0x110C | Receive FIFO Buffer Word Count Ch 3 | R |
| 0x118C | Receive FIFO Buffer Word Count Ch 4 | R |
| 0x120C | Receive FIFO Buffer Word Count Ch 5 | R |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1034 | Receive FIFO Buffer Almost Full Ch 1 | R/W |
| 0x10B4 | Receive FIFO Buffer Almost Full Ch 2 | R/W |
| 0x1134 | Receive FIFO Buffer Almost Full Ch 3 | R/W |
| 0x11B4 | Receive FIFO Buffer Almost Full Ch 4 | R/W |
| 0x1234 | Receive FIFO Buffer Almost Full Ch 5 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1038 | Receive FIFO Buffer High Watermark Ch 1 | R/W |
| 0x10B8 | Receive FIFO Buffer High Watermark Ch 2 | R/W |
| 0x1138 | Receive FIFO Buffer High Watermark Ch 3 | R/W |
| 0x11B8 | Receive FIFO Buffer High Watermark Ch 4 | R/W |
| 0x1238 | Receive FIFO Buffer High Watermark Ch 5 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x103C | Receive FIFO Buffer Low Watermark Ch 1 | R/W |
| 0x10BC | Receive FIFO Buffer Low Watermark Ch 2 | R/W |
| 0x113C | Receive FIFO Buffer Low Watermark Ch 3 | R/W |
| 0x11BC | Receive FIFO Buffer Low Watermark Ch 4 | R/W |
| 0x123C | Receive FIFO Buffer Low Watermark Ch 5 | R/W |
Transmit Registers
Base Address: 0x4000 0000
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1000 | Transmit FIFO Buffer Ch 1 | W |
| 0x1080 | Transmit FIFO Buffer Ch 2 | W |
| 0x1100 | Transmit FIFO Buffer Ch 3 | W |
| 0x1180 | Transmit FIFO Buffer Ch 4 | W |
| 0x1200 | Transmit FIFO Buffer Ch 5 | W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1008 | Transmit FIFO Buffer Word Count Ch 1 | R |
| 0x1088 | Transmit FIFO Buffer Word Count Ch 2 | R |
| 0x1108 | Transmit FIFO Buffer Word Count Ch 3 | R |
| 0x1188 | Transmit FIFO Buffer Word Count Ch 4 | R |
| 0x1208 | Transmit FIFO Buffer Word Count Ch 5 | R |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1030 | Transmit FIFO Buffer Almost Empty Ch 1 | R/W |
| 0x10B0 | Transmit FIFO Buffer Almost Empty Ch 2 | R/W |
| 0x1130 | Transmit FIFO Buffer Almost Empty Ch 3 | R/W |
| 0x11B0 | Transmit FIFO Buffer Almost Empty Ch 4 | R/W |
| 0x1230 | Transmit FIFO Buffer Almost Empty Ch 5 | R/W |
Configuration Registers
Base Address: 0x4000 0000
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1018 | Interface Levels Ch 1 | R/W |
| 0x1098 | Interface Levels Ch 2 | R/W |
| 0x1118 | Interface Levels Ch 3 | R/W |
| 0x1198 | Interface Levels Ch 4 | R/W |
| 0x1218 | Interface Levels Ch 5 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1028 | Baud Rate Ch 1 | R/W |
| 0x10A8 | Baud Rate Ch 2 | R/W |
| 0x1128 | Baud Rate Ch 3 | R/W |
| 0x11A8 | Baud Rate Ch 4 | R/W |
| 0x1228 | Baud Rate Ch 5 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x101C | Tx-Rx Configuration Ch 1 | R/W |
| 0x109C | Tx-Rx Configuration Ch 2 | R/W |
| 0x111C | Tx-Rx Configuration Ch 3 | R/W |
| 0x119C | Tx-Rx Configuration Ch 4 | R/W |
| 0x121C | Tx-Rx Configuration Ch 5 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1050 | Termination Character Ch 1 | R/W |
| 0x10D0 | Termination Character Ch 2 | R/W |
| 0x1150 | Termination Character Ch 3 | R/W |
| 0x11D0 | Termination Character Ch 4 | R/W |
| 0x1250 | Termination Character Ch 5 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1024 | Data Configuration Ch 1 | R/W |
| 0x10A4 | Data Configuration Ch 2 | R/W |
| 0x1124 | Data Configuration Ch 3 | R/W |
| 0x11A4 | Data Configuration Ch 4 | R/W |
| 0x1224 | Data Configuration Ch 5 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1054 | Time Out Value Ch 1 | R/W |
| 0x10D4 | Time Out Value Ch 2 | R/W |
| 0x1154 | Time Out Value Ch 3 | R/W |
| 0x11D4 | Time Out Value Ch 4 | R/W |
| 0x1254 | Time Out Value Ch 5 | R/W |
Control Registers
Base Address: 0x4000 0000
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1020 | Channel Control Ch 1 | R/W |
| 0x10A0 | Channel Control Ch 2 | R/W |
| 0x1120 | Channel Control Ch 3 | R/W |
| 0x11A0 | Channel Control Ch 4 | R/W |
| 0x1220 | Channel Control Ch 5 | R/W |
Module Common Registers
Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.
BIT
Base Address: 0x4000 0800
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0800 | Dynamic Status | R |
| 0x0804 | Latched Status* | R/W |
| 0x0808 | Interrupt Enable | R/W |
| 0x080C | Set Edge/Level Interrupt | R/W |
Base Address: 0x4000 0000
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0248 | Test Enabled | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x02B8 | Background BIT Threshold | R/W |
| 0x02BC | Reset BIT | W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x02AC | Power-on BIT Complete++ | R |
++After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.
Channel Status
Base Address: 0x4000 0800
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0810 | Channel Dynamic Status Ch 1 | R |
| 0x0814 | Channel Latched Status Ch 1* | R/W |
| 0x0818 | Channel Interrupt Enable Ch 1 | R/W |
| 0x081C | Channel Set Edge/Level Interrupt Ch 1 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0820 | Channel Dynamic Status Ch 2 | R |
| 0x0824 | Channel Latched Status Ch 2* | R/W |
| 0x0828 | Channel Interrupt Enable Ch 2 | R/W |
| 0x082C | Channel Set Edge/Level Interrupt Ch 2 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0830 | Channel Dynamic Status Ch 3 | R |
| 0x0834 | Channel Latched Status Ch 3* | R/W |
| 0x0838 | Channel Interrupt Enable Ch 3 | R/W |
| 0x083C | Channel Set Edge/Level Interrupt Ch 3 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0840 | Channel Dynamic Status Ch 4 | R |
| 0x0844 | Channel Latched Status Ch 4* | R/W |
| 0x0848 | Channel Interrupt Enable Ch 4 | R/W |
| 0x084C | Channel Set Edge/Level Interrupt Ch 4 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0850 | Channel Dynamic Status Ch 5 | R |
| 0x0854 | Channel Latched Status Ch 5* | R/W |
| 0x0858 | Channel Interrupt Enable Ch 5 | R/W |
| 0x085C | Channel Set Edge/Level Interrupt Ch 5 | R/W |
FIFO Status
Base Address: 0x4000 0000
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1058 | FIFO Status Ch 1 | R |
| 0x10D8 | FIFO Status Ch 2 | R |
| 0x1158 | FIFO Status Ch 3 | R |
| 0x11D8 | FIFO Status Ch 4 | R |
| 0x1258 | FIFO Status Ch 5 | R |
Summary Status
Base Address: 0x4000 0800
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x09A0 | Summary Dynamic Status | R |
| 0x09A4 | Summary Latched Status* | R/W |
| 0x09A8 | Summary Interrupt Enable | R/W |
| 0x09AC | Summary Set Edge/Level Interrupt | R/W |
Interrupt Registers
The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0500 | Module 1 Interrupt Vector 1 - BIT | R/W |
| 0x0504 | Module 1 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0508 | Module 1 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x050C | Module 1 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0510 | Module 1 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0514 | Module 1 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0518 | Module 1 Interrupt Vector 7 - Reserved | R/W |
| 0x051C | Module 1 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0520 | Module 1 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0522 | Module 1 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0524 to 0x0564 | Module 1 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0568 | Module 1 Interrupt Vector 27 - Summary Status | R/W |
| 0x056C | Module 1 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0570 to 0x057C | Module 1 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0600 | Module 1 Interrupt Steering 1 - BIT | R/W |
| 0x0604 | Module 1 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x0608 | Module 1 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x060C | Module 1 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x0610 | Module 1 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x0614 | Module 1 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x0618 | Module 1 Interrupt Steering 7 - Reserved | R/W |
| 0x061C | Module 1 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x0620 | Module 1 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x0622 | Module 1 Interrupt Steering 10 – Overcurrent | R/W |
| 0x0624 to 0x0664 | Module 1 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x0668 | Module 1 Interrupt Steering 27 - Summary Status | R/W |
| 0x066C | Module 1 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x0670 to 0x067C | Module 1 Interrupt Steering 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0700 | Module 2 Interrupt Vector 1 - BIT | R/W |
| 0x0704 | Module 2 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0708 | Module 2 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x070C | Module 2 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0710 | Module 2 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0714 | Module 2 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0718 | Module 2 Interrupt Vector 7 - Reserved | R/W |
| 0x071C | Module 2 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0720 | Module 2 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0722 | Module 2 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0724 to 0x0764 | Module 2 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0768 | Module 2 Interrupt Vector 27 - Summary Status | R/W |
| 0x076C | Module 2 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0770 to 0x077C | Module 2 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0800 | Module 2 Interrupt Steering 1 - BIT | R/W |
| 0x0804 | Module 2 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x0808 | Module 2 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x080C | Module 2 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x0810 | Module 2 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x0814 | Module 2 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x0818 | Module 2 Interrupt Steering 7 - Reserved | R/W |
| 0x081C | Module 2 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x0820 | Module 2 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x0822 | Module 2 Interrupt Steering 10 – Overcurrent | R/W |
| 0x0824 to 0x0864 | Module 2 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x0868 | Module 2 Interrupt Steering 27 - Summary Status | R/W |
| 0x086C | Module 2 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x0870 to 0x087C | Module 2 Interrupt Steering 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0900 | Module 3 Interrupt Vector 1 - BIT | R/W |
| 0x0904 | Module 3 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0908 | Module 3 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x090C | Module 3 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0910 | Module 3 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0914 | Module 3 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0918 | Module 3 Interrupt Vector 7 - Reserved | R/W |
| 0x091C | Module 3 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0920 | Module 3 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0922 | Module 3 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0924 to 0x0964 | Module 3 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0968 | Module 3 Interrupt Vector 27 - Summary Status | R/W |
| 0x096C | Module 3 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0970 to 0x097C | Module 3 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0A00 | Module 3 Interrupt Steering 1 - BIT | R/W |
| 0x0A04 | Module 3 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x0A08 | Module 3 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x0A0C | Module 3 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x0A10 | Module 3 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x0A14 | Module 3 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x0A18 | Module 3 Interrupt Steering 7 - Reserved | R/W |
| 0x0A1C | Module 3 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x0A20 | Module 3 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x0A22 | Module 3 Interrupt Steering 10 – Overcurrent | R/W |
| 0x0A24 to 0x0A64 | Module 3 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x0A68 | Module 3 Interrupt Steering 27 - Summary Status | R/W |
| 0x0A6C | Module 3 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x0A70 to 0x0A7C | Module 3 Interrupt Steering 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0B00 | Module 4 Interrupt Vector 1 - BIT | R/W |
| 0x0B04 | Module 4 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0B08 | Module 4 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x0B0C | Module 4 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0B10 | Module 4 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0B14 | Module 4 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0B18 | Module 4 Interrupt Vector 7 - Reserved | R/W |
| 0x0B1C | Module 4 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0B20 | Module 4 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0B22 | Module 4 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0B24 to 0x0B64 | Module 4 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0B68 | Module 4 Interrupt Vector 27 - Summary Status | R/W |
| 0x0B6C | Module 4 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0B70 to 0x0B7C | Module 4 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0C00 | Module 4 Interrupt Steering 1 - BIT | R/W |
| 0x0C04 | Module 4 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x0C08 | Module 4 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x0C0C | Module 4 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x0C10 | Module 4 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x0C14 | Module 4 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x0C18 | Module 4 Interrupt Steering 7 - Reserved | R/W |
| 0x0C1C | Module 4 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x0C20 | Module 4 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x0C22 | Module 4 Interrupt Steering 10 – Overcurrent | R/W |
| 0x0C24 to 0x0C64 | Module 4 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x0C68 | Module 4 Interrupt Steering 27 - Summary Status | R/W |
| 0x0C6C | Module 4 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x0C70 to 0x0C7C | Module 4 Interrupt Steering 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0D00 | Module 5 Interrupt Vector 1 - BIT | R/W |
| 0x0D04 | Module 5 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0D08 | Module 5 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x0D0C | Module 5 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0D10 | Module 5 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0D14 | Module 5 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0D18 | Module 5 Interrupt Vector 7 - Reserved | R/W |
| 0x0D1C | Module 5 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0D20 | Module 5 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0D22 | Module 5 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0D24 to 0x0D64 | Module 5 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0D68 | Module 5 Interrupt Vector 27 - Summary Status | R/W |
| 0x0D6C | Module 5 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0D70 to 0x0D7C | Module 5 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0E00 | Module 5 Interrupt Steering 1 - BIT | R/W |
| 0x0E04 | Module 5 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x0E08 | Module 5 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x0E0C | Module 5 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x0E10 | Module 5 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x0E14 | Module 5 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x0E18 | Module 5 Interrupt Steering 7 - Reserved | R/W |
| 0x0E1C | Module 5 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x0E20 | Module 5 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x0E22 | Module 5 Interrupt Steering 10 – Overcurrent | R/W |
| 0x0E24 to 0x0E64 | Module 5 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x0E68 | Module 5 Interrupt Steering 27 - Summary Status | R/W |
| 0x0E6C | Module 5 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x0E70 to 0x0E7C | Module 5 Interrupt Steering 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0F00 | Module 6 Interrupt Vector 1 - BIT | R/W |
| 0x0F04 | Module 6 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0F08 | Module 6 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x0F0C | Module 6 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0F10 | Module 6 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0F14 | Module 6 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0F18 | Module 6 Interrupt Vector 7 - Reserved | R/W |
| 0x0F1C | Module 6 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0F20 | Module 6 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0F22 | Module 6 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0F24 to 0x0F64 | Module 6 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0F68 | Module 6 Interrupt Vector 27 - Summary Status | R/W |
| 0x0F6C | Module 6 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0F70 to 0x0F7C | Module 6 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1000 | Module 6 Interrupt Steering 1 - BIT | R/W |
| 0x1004 | Module 6 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x1008 | Module 6 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x100C | Module 6 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x1010 | Module 6 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x1014 | Module 6 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x1018 | Module 6 Interrupt Steering 7 - Reserved | R/W |
| 0x101C | Module 6 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x1020 | Module 6 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x1022 | Module 6 Interrupt Steering 10 – Overcurrent | R/W |
| 0x01024 to 0x1064 | Module 6 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x1068 | Module 6 Interrupt Steering 27 - Summary Status | R/W |
| 0x106C | Module 6 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x1070 to 0x107C | Module 6 Interrupt Steering 29 to 32 - Reserved | R/W |
DIGITAL I/O - DIFFERENTIAL TRANSCEIVER FUNCTION
The digital I/O - differential transceiver function is similar to the standard DF1 function module (DF1 may be used as a reference/guide within the context of this document).
Principle of Operation
DF1 channels 1 through 6 may be set as inputs or outputs. When programmed as inputs, status and/or interrupts are enabled for each channel to indicate transition on rising edge or transition on falling edge or both as well as BIT fault. Each channel has a selectable internal 120-ohm internal resistor across its inputs.
When programmed as outputs, if an overcurrent condition is detected, the channel will be reset to input mode. All outputs are continually scanned “real-time”, for present status. Debounce circuits for each channel offer a selectable time delay to eliminate false signals resulting from contact bounce commonly experienced with mechanical relays and switches.
Each channel can also be programmed for fast or slow slew rates (slow slew rate may be desirable for certain sensitive EMI radiated transmission line applications).
Debounce Programming
The Debounce Time register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Once a signal level is a logic voltage level period longer than the Debounce Time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed Debounce Time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state.
Automatic Background Built-In Test (BIT)/Diagnostic Capability
The function contains automatic background BIT testing that verifies channel processing (data read or write logic), tests for overcurrent conditions and provides status for threshold signal transitioning.
Any failure triggers an Interrupt (if enabled) with the results available in status registers. The testing is totally transparent to the user, requires no external programming and has no effect on the operation of this card. It can be enabled or disabled via the bus (see further details in register description), and continually checks that each channel is functional. This capability is accomplished by an additional test comparator that is incorporated into each module. The test comparator checks each channel and is compared against the operational channel. Depending upon the configuration, the Input data read or Output logic written of the operational channel and test comparator must agree or a fault is indicated with the results available in the associated status register. Low-toHigh and High-to-Low logic transitions are indicated.
There is no independent overcurrent detection. Instead, the BIT detection circuitry is used to infer an overcurrent condition if the output state setting doesn’t match the readback value seen by the input circuitry. For example, a shorted output, causing the read state to be opposite from the expected value would trigger this. If the fault persists beyond the BIT interval stabilization time, the overcurrent protection will kick in and reset the drive output by returning the transceiver to input mode. To reset this condition, a reset command needs to be issued to the Overcurrent Reset register, which will restore drive output and allow the latched status to be reset. This is separate from the reset for the Overcurrent Interrupt Enable register on this module. It is recommended that a reset command is done whenever status is cleared to avoid a non-apparent output reset condition.
Status and Interrupts
The DF1 function provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.
User Watchdog Timer Capability
The DF1 function provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the Principle of Operation description.
Module Common Registers
The DF1 function provide module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.
Register Descriptions
The register descriptions provide the register name, Register Offset, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.
Input/Output Registers
I/O Format
| Function: | Sets channels as inputs or outputs. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | Write 0 for input (default), 1 for output. Power-on default or reset is configured for input. Bit-mapped per channel. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Read I/O
| Function: | Reads High (1) or Low (0) inputs or outputs as defined by internal channel threshold values. Bit-mapped per channel. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Read/Write: | R |
| Initialized Value: | N/A |
| Operational Settings: | N/A |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Write Outputs
| Function: | Sets data outputs High (1) or Low (0). Bit-mapped per channel. |
|---|---|
| Type: | binary word (32-bit) |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | Write 1 for High output; write 0 for Low. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Input/Output Control Registers
Debounce Time
| Function: | When the Input/Output Format register is programmed for Input mode, the input signal will have the debounce filtering applied based on this programmed value. This is selectable for each channel. |
|---|---|
| Type: | binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | The Debounce Time register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Enter required debounce time into appropriate channel registers. LSB weight is 8 ns/bit (register may be programmed from 0 (debounce filter inactive) through a maximum of 34.36s (full scale w/ 8 ns resolution). Once a signal level is a logic voltage level period longer than the debounce time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed debounce time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state. Enter a value of 0 to disable debounce filtering. Debounce defaults to 0x0000 upon reset. |
Slew Rate
| Function: | Enables user selection of Normal Mode or a reduced (Slow Mode) slew rate to soften the driver output edges to control high-frequency EMI emissions. |
|---|---|
| Type: | signed binary word (32-bit) |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | Write 1 for Normal Mode or 0 for Slow Mode. With Slow Mode selected, the data rate is limited to about 250 kbps. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Termination
| Function: | Enables 120 Ω termination. |
|---|---|
| Type: | signed binary word (32-bit) |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | Write 1 for 120 Ω termination. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Overcurrent Reset
| Function: | Resets disabled channels in Overcurrent Latched Status register following an overcurrent condition. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | 1 is written to reset disabled channels. Processor will write a 0 back to the Overcurrent Reset register when reset process is complete. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
User Watchdog Timer Programming Registers
Refer to “User Watchdog Timer Module Manual” for the register descriptions.
Module Common Registers
Refer to “Module Common Registers Module Manual” for the register descriptions.
General Purpose Status Functions
BIT Error Interrupt Interval
| Function: | Sets up a threshold requirement of “successive” events to accumulate before a BIT Error is generated. Accumulated successive fault detections add +2 to the count and no-fault detections subtract 1 from the count to filter BIT errors prior to an actual interrupt generation. Once the count exceeds this register’s value, a BIT error is generated. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R/W |
| Initialized Value: | 0x3 |
| Operational Settings: | Write a threshold to filter BIT errors prior to generating a BIT Error. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| D | D | D | D | D | D | D | D | D | D | D | D | D | D | D | D |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| D | D | D | D | D | D | D | D | D | D | D | D | D | D | D | D |
Invert BIT Signal
| Function: | Sets the corresponding bit for each channel to generate a BIT error. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | To internally generate a BIT error when testing the function’s BIT logic, set the channel’s corresponding BIT to 1. This will confirm whether or not the BIT logic is functioning correctly. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
BIT Count Error Clear
| Function: | Clears the BIT error. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | Write a 1 to clear BIT errors. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Module Common Registers
Refer to “Module Common Registers Module Manual” for the register descriptions.
Status and Interrupt Registers
The DF Digital I/O function provides status registers for BIT, Low-to-High Transition, High-to-Low Transition, and Overcurrent.
BIT Status
There are four registers associated with the BIT Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.
| Function: | Sets the corresponding bit associated with the channel’s BIT error. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0x0000 0000 to 0x003F 001F |
| Read/Write: | R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) |
| Initialized Value: | 0 |
Note
BIT Status is a shared register between the SC3 and DF1 functions. Bits D04:D0 are dedicated to the SC3 functions and bits D21:D16 are dedicated to the DF1 function.
| BIT Dynamic Status Register | |||||||||||||||
| BIT Latched Status Register | |||||||||||||||
| BIT Interrupt Enable Register | |||||||||||||||
| BIT Set Edge/Level Interrupt Register | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 DF1 | Ch5 DF1 | Ch4 DF1 | Ch3 DF1 | Ch2 DF1 | Ch1 DF1 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch5 SC3 | Ch4 SC3 | Ch3 SC3 | Ch2 SC3 | Ch1 SC3 |
Low-to-High Transition Status
There are four registers associated with the Low-to-High Transition Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.
| Function: | Sets the corresponding bit associated with the channel’s Low-to-High Transition event. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0x0000 0000 to 0x0000 003F |
| Read/Write: | R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) |
| Initialized Value: | 0 |
| Low-to-High Transition Dynamic Status Register | |||||||||||||||
| Low-to-High Transition Latched Status Register | |||||||||||||||
| Low-to-High Transition Interrupt Enable Register | |||||||||||||||
| Low-to-High Transition Set Edge/Level Interrupt Register | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Note
Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 40 ns.
Note
Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 100 ns.
Note
Transition status follows the value read by the I/O Format register.
High-to-Low Transition Status
There are four registers associated with the High-to-Low Transition Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.
| Function: | Sets the corresponding bit associated with the channel’s High-to-Low Transition event. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0x0000 0000 to 0x0000 003F |
| Read/Write: | R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) |
| Initialized Value: | 0 |
| High-to-Low Transition Dynamic Status Register | |||||||||||||||
| High-to-Low Transition Latched Status Register | |||||||||||||||
| High-to-Low Transition Interrupt Enable Register | |||||||||||||||
| High-to-Low Transition Set Edge/Level Interrupt Register | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Note
Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 40 ns.
Note
Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 100 ns.
Note
Transition status follows the value read by the I/O Format register.
Overcurrent Status
There are four registers associated with the Overcurrent Transition Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.
| Function: | Sets the corresponding bit associated with the channel’s Overcurrent Error. |
|---|---|
| Type: | unsigned binary word (32-bits) |
| Data Range: | 0x0000 0000 to 0x0000 003F |
| Read/Write: | R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt) |
| Initialized Value: | 0 |
| Overcurrent Dynamic Status Register | |||||||||||||||
| Overcurrent Latched Status Register | |||||||||||||||
| Overcurrent Interrupt Enable Register | |||||||||||||||
| Overcurrent Set Edge/Level Interrupt Register | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 |
Note
Status is indicated (associated channel(s) bit set to 1) within 80 ns.
Note
Channel(s) shut down by overcurrent sensed can be reset by writing to the Overcurrent Reset register.
User Watchdog Timer Fault Status
The DF1 function provides registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status register descriptions.
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
Interrupt Vector
| Function: | Set an identifier for the interrupt. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | When an interrupt occurs, this value is reported as part of the interrupt mechanism. |
Interrupt Steering
| Function: | Sets where to direct the interrupt. |
|---|---|
| Type: | unsigned binary word (32-bit) |
| Data Range: | See table Read/Write: R/W |
| Initialized Value: | 0 |
| Operational Settings: | When an interrupt occurs, the interrupt is sent as specified: |
| Direct Interrupt to VME | 1 |
|---|---|
| Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) | 2 |
| Direct Interrupt to PCIe Bus | 5 |
| Direct Interrupt to cPCI Bus | 6 |
Function Register Map
Key:
| Bold Italic | = Configuration/Control |
|---|---|
| Bold Underline | = Status |
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
Input/Output Registers
Base Address: 0x4010 0000
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1038 | Input/Output Format | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1000 | Read I/O | R |
| 0x1024 | Write Outputs | R/W |
Input/Output Control Registers
Base Address: 0x4010 0000
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x208C | Debounce Time Ch.1 | R/W |
| 0x210C | Debounce Time Ch.2 | R/W |
| 0x218C | Debounce Time Ch.3 | R/W |
| 0x220C | Debounce Time Ch.4 | R/W |
| 0x228C | Debounce Time Ch.5 | R/W |
| 0x230C | Debounce Time Ch.6 | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1008 | Slew Rate | R/W |
| 0x100C | Termination | R/W |
| 0x1100 | Overcurrent Reset | R/W |
User Watchdog Timer Programming Registers
Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Status Function Register Map.
Module Common Registers
Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.
Status Registers
Base Address: 0x4000 0800
BIT Registers
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0800 | Dynamic Status | R |
| 0x0804 | Latched Status* | R/W |
| 0x0808 | Interrupt Enable | R/W |
| 0x080C | Set Edge/Level Interrupt | R/W |
Base Address: 0x4010 0000
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1014 | BIT Count Error Clear | R/W |
| 0x1018 | Invert BIT Signal | R/W |
| 0x101C | BIT Error Interrupt Interval | R/W |
Status Registers
Base Address: 0x4000 0800
Low-to-High Transition
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0870 | Dynamic Status | R |
| 0x0874 | Latched Status* | R/W |
| 0x0878 | Interrupt Enable | R/W |
| 0x087C | Set Edge/Level Interrupt | R/W |
High-to-Low Transition
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0880 | Dynamic Status | R |
| 0x0884 | Latched Status* | R/W |
| 0x0888 | Interrupt Enable | R/W |
| 0x088C | Set Edge/Level Interrupt | R/W |
Overcurrent
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0890 | Dynamic Status | R |
| 0x0894 | Latched Status* | R/W |
| 0x0898 | Interrupt Enable | R/W |
| 0x089C | Set Edge/Level Interrupt | R/W |
User Watchdog Timer Registers
The DF1 function provides registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status Function Register Map.
Interrupt Registers
The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0500 | Module 1 Interrupt Vector 1 - BIT | R/W |
| 0x0504 | Module 1 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0508 | Module 1 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x050C | Module 1 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0510 | Module 1 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0514 | Module 1 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0518 | Module 1 Interrupt Vector 7 - Reserved | R/W |
| 0x051C | Module 1 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0520 | Module 1 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0522 | Module 1 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0524 to 0x0564 | Module 1 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0568 | Module 1 Interrupt Vector 27 - Summary Status | R/W |
| 0x056C | Module 1 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0570 to 0x057C | Module 1 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0600 | Module 1 Interrupt Steering 1 - BIT | R/W |
| 0x0604 | Module 1 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x0608 | Module 1 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x060C | Module 1 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x0610 | Module 1 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x0614 | Module 1 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x0618 | Module 1 Interrupt Steering 7 - Reserved | R/W |
| 0x061C | Module 1 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x0620 | Module 1 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x0622 | Module 1 Interrupt Steering 10 – Overcurrent | R/W |
| 0x0624 to 0x0664 | Module 1 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x0668 | Module 1 Interrupt Steering 27 - Summary Status | R/W |
| 0x066C | Module 1 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x0670 to 0x067C | Module 1 Interrupt Steering 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0700 | Module 2 Interrupt Vector 1 - BIT | R/W |
| 0x0704 | Module 2 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0708 | Module 2 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x070C | Module 2 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0710 | Module 2 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0714 | Module 2 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0718 | Module 2 Interrupt Vector 7 - Reserved | R/W |
| 0x071C | Module 2 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0720 | Module 2 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0722 | Module 2 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0724 to 0x0764 | Module 2 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0768 | Module 2 Interrupt Vector 27 - Summary Status | R/W |
| 0x076C | Module 2 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0770 to 0x077C | Module 2 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0800 | Module 2 Interrupt Steering 1 - BIT | R/W |
| 0x0804 | Module 2 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x0808 | Module 2 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x080C | Module 2 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x0810 | Module 2 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x0814 | Module 2 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x0818 | Module 2 Interrupt Steering 7 - Reserved | R/W |
| 0x081C | Module 2 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x0820 | Module 2 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x0822 | Module 2 Interrupt Steering 10 – Overcurrent | R/W |
| 0x0824 to 0x0864 | Module 2 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x0868 | Module 2 Interrupt Steering 27 - Summary Status | R/W |
| 0x086C | Module 2 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x0870 to 0x087C | Module 2 Interrupt Steering 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0900 | Module 3 Interrupt Vector 1 - BIT | R/W |
| 0x0904 | Module 3 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0908 | Module 3 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x090C | Module 3 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0910 | Module 3 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0914 | Module 3 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0918 | Module 3 Interrupt Vector 7 - Reserved | R/W |
| 0x091C | Module 3 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0920 | Module 3 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0922 | Module 3 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0924 to 0x0964 | Module 3 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0968 | Module 3 Interrupt Vector 27 - Summary Status | R/W |
| 0x096C | Module 3 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0970 to 0x097C | Module 3 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0A00 | Module 3 Interrupt Steering 1 - BIT | R/W |
| 0x0A04 | Module 3 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x0A08 | Module 3 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x0A0C | Module 3 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x0A10 | Module 3 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x0A14 | Module 3 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x0A18 | Module 3 Interrupt Steering 7 - Reserved | R/W |
| 0x0A1C | Module 3 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x0A20 | Module 3 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x0A22 | Module 3 Interrupt Steering 10 – Overcurrent | R/W |
| 0x0A24 to 0x0A64 | Module 3 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x0A68 | Module 3 Interrupt Steering 27 - Summary Status | R/W |
| 0x0A6C | Module 3 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x0A70 to 0x0A7C | Module 3 Interrupt Steering 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0B00 | Module 4 Interrupt Vector 1 - BIT | R/W |
| 0x0B04 | Module 4 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0B08 | Module 4 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x0B0C | Module 4 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0B10 | Module 4 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0B14 | Module 4 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0B18 | Module 4 Interrupt Vector 7 - Reserved | R/W |
| 0x0B1C | Module 4 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0B20 | Module 4 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0B22 | Module 4 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0B24 to 0x0B64 | Module 4 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0B68 | Module 4 Interrupt Vector 27 - Summary Status | R/W |
| 0x0B6C | Module 4 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0B70 to 0x0B7C | Module 4 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0C00 | Module 4 Interrupt Steering 1 - BIT | R/W |
| 0x0C04 | Module 4 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x0C08 | Module 4 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x0C0C | Module 4 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x0C10 | Module 4 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x0C14 | Module 4 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x0C18 | Module 4 Interrupt Steering 7 - Reserved | R/W |
| 0x0C1C | Module 4 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x0C20 | Module 4 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x0C22 | Module 4 Interrupt Steering 10 – Overcurrent | R/W |
| 0x0C24 to 0x0C64 | Module 4 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x0C68 | Module 4 Interrupt Steering 27 - Summary Status | R/W |
| 0x0C6C | Module 4 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x0C70 to 0x0C7C | Module 4 Interrupt Steering 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0D00 | Module 5 Interrupt Vector 1 - BIT | R/W |
| 0x0D04 | Module 5 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0D08 | Module 5 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x0D0C | Module 5 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0D10 | Module 5 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0D14 | Module 5 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0D18 | Module 5 Interrupt Vector 7 - Reserved | R/W |
| 0x0D1C | Module 5 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0D20 | Module 5 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0D22 | Module 5 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0D24 to 0x0D64 | Module 5 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0D68 | Module 5 Interrupt Vector 27 - Summary Status | R/W |
| 0x0D6C | Module 5 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0D70 to 0x0D7C | Module 5 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0E00 | Module 5 Interrupt Steering 1 - BIT | R/W |
| 0x0E04 | Module 5 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x0E08 | Module 5 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x0E0C | Module 5 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x0E10 | Module 5 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x0E14 | Module 5 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x0E18 | Module 5 Interrupt Steering 7 - Reserved | R/W |
| 0x0E1C | Module 5 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x0E20 | Module 5 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x0E22 | Module 5 Interrupt Steering 10 – Overcurrent | R/W |
| 0x0E24 to 0x0E64 | Module 5 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x0E68 | Module 5 Interrupt Steering 27 - Summary Status | R/W |
| 0x0E6C | Module 5 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x0E70 to 0x0E7C | Module 5 Interrupt Steering 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x0F00 | Module 6 Interrupt Vector 1 - BIT | R/W |
| 0x0F04 | Module 6 Interrupt Vector 2 - Serial Channel Status Ch 1 | R/W |
| 0x0F08 | Module 6 Interrupt Vector 3 - Serial Channel Status Ch 2 | R/W |
| 0x0F0C | Module 6 Interrupt Vector 4 - Serial Channel Status Ch 3 | R/W |
| 0x0F10 | Module 6 Interrupt Vector 5 - Serial Channel Status Ch 4 | R/W |
| 0x0F14 | Module 6 Interrupt Vector 6 - Serial Channel Status Ch 5 | R/W |
| 0x0F18 | Module 6 Interrupt Vector 7 - Reserved | R/W |
| 0x0F1C | Module 6 Interrupt Vector 8 - Low-High Transition | R/W |
| 0x0F20 | Module 6 Interrupt Vector 9 – High-Low Transition | R/W |
| 0x0F22 | Module 6 Interrupt Vector 10 – Overcurrent | R/W |
| 0x0F24 to 0x0F64 | Module 6 Interrupt Vector 11 to 26 - Reserved | R/W |
| 0x0F68 | Module 6 Interrupt Vector 27 - Summary Status | R/W |
| 0x0F6C | Module 6 Interrupt Vector 28 - User Watchdog Timer Fault | R/W |
| 0x0F70 to 0x0F7C | Module 6 Interrupt Vector 29 to 32 - Reserved | R/W |
| Addr (Hex) | Name | Read/Write |
|---|---|---|
| 0x1000 | Module 6 Interrupt Steering 1 - BIT | R/W |
| 0x1004 | Module 6 Interrupt Steering 2 - Serial Channel Status Ch 1 | R/W |
| 0x1008 | Module 6 Interrupt Steering 3 - Serial Channel Status Ch 2 | R/W |
| 0x100C | Module 6 Interrupt Steering 4 - Serial Channel Status Ch 3 | R/W |
| 0x1010 | Module 6 Interrupt Steering 5 - Serial Channel Status Ch 4 | R/W |
| 0x1014 | Module 6 Interrupt Steering 6 - Serial Channel Status Ch 5 | R/W |
| 0x1018 | Module 6 Interrupt Steering 7 - Reserved | R/W |
| 0x101C | Module 6 Interrupt Steering 8 - Low-High Transition | R/W |
| 0x1020 | Module 6 Interrupt Steering 9 – High-Low Transition | R/W |
| 0x1022 | Module 6 Interrupt Steering 10 – Overcurrent | R/W |
| 0x01024 to 0x1064 | Module 6 Interrupt Steering 11 to 26 - Reserved | R/W |
| 0x1068 | Module 6 Interrupt Steering 27 - Summary Status | R/W |
| 0x106C | Module 6 Interrupt Steering 28 - User Watchdog Timer Fault | R/W |
| 0x1070 to 0x107C | Module 6 Interrupt Steering 29 to 32 - Reserved | R/W |
PINOUT DETAILS
Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals.
| Module Signal (Ref Only) | 44-Pin I/O | 50-Pin I/O (Mod Slot 1-J3) | 50-Pin I/O (Mod Slot 2-J4) | 50-Pin I/O (Mod Slot 3-J3) | 50-Pin I/O (Mod Slot 3-J4) | 5 CH RS (CH1 - RS232 HW Flow; CH2-CH5 - RS422/485) & 6 CH DF + (CMH) |
|---|---|---|---|---|---|---|
| DATIO1 | 2 | 10 | 1 | 2 | RXD-CH1 | |
| DATIO2 | 24 | 35 | 26 | 27 | CTS-CH1 | |
| DATIO3 | 3 | 11 | 2 | 3 | TXD-CH1 | |
| DATIO4 | 25 | 36 | 27 | 28 | RTS-CH1 | |
| DATIO5 | 5 | 13 | 4 | 5 | RXDLO-CH2 | |
| DATIO6 | 27 | 38 | 29 | 30 | RXDHI-CH2 | |
| DATIO7 | 7 | 14 | 5 | 6 | TXDLO-CH2 | |
| DATIO8 | 29 | 39 | 30 | 31 | TXDHI-CH2 | |
| DATIO9 | 8 | 15 | 6 | 7 | RXDLO-CH3 | |
| DATIO10 | 30 | 40 | 31 | 32 | RXDHI-CH3 | |
| DATIO11 | 10 | 17 | 8 | 9 | TXDLO-CH3 | |
| DATIO12 | 32 | 42 | 33 | 34 | TXDHI-CH3 | |
| DATIO13 | 12 | 18 | 9 | 17 | RXDLO-CH5 | |
| DATIO14 | 34 | 43 | 34 | 42 | RXDHI-CH5 | |
| DATIO15 | 13 | 19 | 10 | 18 | TXDLO-CH5 | |
| DATIO16 | 35 | 44 | 35 | 43 | TXDHI-CH5 | |
| DATIO17 | 15 | 21 | 12 | 20 | IOLO-CH5 | |
| DATIO18 | 37 | 46 | 37 | 45 | IOHI-CH5 | |
| DATIO19 | 17 | 22 | 13 | 21 | IOLO-CH6 | |
| DATIO20 | 39 | 47 | 38 | 46 | IOHI-CH6 | |
| DATIO21 | 18 | 23 | 14 | 22 | IOLO-CH1 | |
| DATIO22 | 40 | 48 | 39 | 47 | IOHI-CH1 | |
| DATIO23 | 20 | 25 | 16 | 24 | IOLO-CH2 | |
| DATIO24 | 42 | 50 | 41 | 49 | IOHI-CH2 | |
| DATIO25 | 4 | 12 | 3 | 4 | RXDLO-CH4 | |
| DATIO26 | 26 | 37 | 28 | 29 | RXDHI-CH4 | |
| DATIO27 | 9 | 16 | 7 | 8 | TXDLO-CH4 | |
| DATIO28 | 31 | 41 | 32 | 33 | TXDHI-CH4 | |
| DATIO29 | 14 | 20 | 11 | 19 | IOLO-CH4 | |
| DATIO30 | 36 | 45 | 36 | 44 | IOHI-CH4 | |
| DATIO31 | 19 | 24 | 15 | 23 | IOLO-CH3 | |
| DATIO32 | 41 | 49 | 40 | 48 | IOHI-CH3 | |
| DATIO33 | 6 | |||||
| DATIO34 | 28 | |||||
| DATIO35 | 11 | |||||
| DATIO36 | 33 | |||||
| DATIO37 | 16 | |||||
| DATIO38 | 38 | |||||
| DATIO39 | 21 | |||||
| DATIO40 | 43 | |||||
| N/A |
REVISION HISTORY
| Revision Date | Description |
|---|---|
| 2025-10-06 | Initial release of CMH manual. |
STATUS AND INTERRUPTS
Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.
For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.
Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.
Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).
Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.
Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).
Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edge-triggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Interrupt Trigger Types
In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.
Example 1: Fault detection
This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.
Example 2: Threshold detection
This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.
Dynamic and Latched Status Registers Examples
The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.
Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States
No Clearing of Latched Status Clearing of Latched Status (Edge-Triggered) Clearing of Latched Status(Level-Triggered) Time Dynamic Status Latched Status Action Latched Status Action Latched T0 0x0 0x0 Read Latched Register 0x0 Read Latched Register 0x0 T1 0x1 0x1 Read Latched Register 0x1 0x1 T1 0x1 0x1 Write 0x1 to Latched Register Write 0x1 to Latched Register T1 0x1 0x1 0x0 0x1 T2 0x0 0x1 Read Latched Register 0x0 Read Latched Register 0x1 T2 0x0 0x1 Read Latched Register 0x0 Write 0x1 to Latched Register T2 0x0 0x1 Read Latched Register 0x0 0x0 T3 0x2 0x3 Read Latched Register 0x2 Read Latched Register 0x2 T3 0x2 0x3 Write 0x2 to Latched Register Write 0x2 to Latched Register T3 0x2 0x3 0x0 0x2 T4 0x2 0x3 Read Latched Register 0x1 Read Latched Register 0x3 T4 0x2 0x3 Write 0x1 to Latched Register Write 0x3 to Latched Register T4 0x2 0x3 0x0 0x2 T5 0xC 0xF Read Latched Register 0xC Read Latched Register 0xE T5 0xC 0xF Write 0xC to Latched Register Write 0xE to Latched Register T5 0xC 0xF 0x0 0xC T6 0xC 0xF Read Latched Register 0x0 Read Latched 0xC T6 0xC 0xF Read Latched Register 0x0 Write 0xC to Latched Register T6 0xC 0xF Read Latched Register 0x0 0xC T7 0x4 0xF Read Latched Register 0x0 Read Latched Register 0xC T7 0x4 0xF Read Latched Register 0x0 Write 0xC to Latched Register T7 0x4 0xF Read Latched Register 0x0 0x4 T8 0x4 0xF Read Latched Register 0x0 Read Latched Register 0x4 Interrupt Examples
The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.
Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled
Time Latched Status (Edge-Triggered - Clear Multi-Channel) Latched Status (Edge-Triggered - Clear Single Channel) 2+ Latched Status (Level-Triggered - Clear Multi-Channel) Action Latched Action Latched Action Latched T1 (Int 1) Interrupt Generated++``+
Read Latched Registers0x1 Interrupt Generated++``+
Read Latched Registers0x1 Interrupt Generated++``+
Read Latched Registers0x1 T1 (Int 1) Write 0x1 to Latched Register Write 0x1 to Latched Register Write 0x1 to Latched Register T1 (Int 1) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T2.0x1 T3 (Int 2) Interrupt Generated++``+
Read Latched Registers0x2 Interrupt Generated++``+
Read Latched Registers0x2 Interrupt Generated++``+
Read Latched Registers0x2 T3 (Int 2) Write 0x2 to Latched Register Write 0x2 to Latched Register Write 0x2 to Latched Register T3 (Int 2) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T7.0x2 T4 (Int 3) Interrupt Generated++``+
Read Latched Registers0x1 Interrupt Generated++``+
Read Latched Registers0x1 Interrupt Generated++``+
Read Latched Registers0x3 T4 (Int 3) Write 0x1 to Latched Register Write 0x1 to Latched Register Write 0x3 to Latched Register T4 (Int 3) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.0x3 T4 (Int 3) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T7.0x2 T6 (Int 4) Interrupt Generated++``+
Read Latched Registers0xC Interrupt Generated++``+
Read Latched Registers0xC Interrupt Generated++``+
Read Latched Registers0xE T6 (Int 4) Write 0xC to Latched Register Write 0x4 to Latched Register Write 0xE to Latched Register T6 (Int 4) 0x0 Interrupt re-triggers++``+
Write 0x8 to Latched Register0x8 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.0xE T6 (Int 4) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.0xC T6 (Int 4) 0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.0x4 REVISION HISTORY
Motherboard Manual - Status and Interrupts Revision History Revision Revision Date Description C 2021-11-30 C08896; Transition manual to docbuilder format - no technical info change. DOCS.NAII REVISIONS
Link to original
Revision Date Description 2026-03-02 Formatting updates to document; no technical changes.
USER WATCHDOG TIMER MODULE MANUAL
User Watchdog Timer Capability
The User Watchdog Timer (UWDT) Capability is available on the following modules:
AC Reference Source Modules
- AC1 - 1 Channel, 2-115 Vrms, 47 Hz - 20kHz
- AC2 - 2 Channels, 2-28 Vrms, 47 Hz - 20kHz
- AC3 - 1 Channel, 28-115 Vrms, 47 Hz - 2.5 kHz
Differential Transceiver Modules
- DF1/DF2 - 16 Channels Differential I/O
Digital-to-Analog (D/A) Modules
- DA1 - 12 Channels, ±10 VDC @ 25 mA, Voltage or Current Control Modes
- DA2 - 16 Channels, ±10 VDC @ 10 mA
- DA3 - 4 Channels, ±40 VDC @ ±100 mA, Voltage or Current Control Modes
- DA4 - 4 Channels, ±80 VDC @ 10 mA
- DA5 - 4 Channels, ±65 VDC or ±2 A, Voltage or Current Control Modes
Digital-to-Synchro/Resolver (D/S) or Digital-to-L( R )VDT (D/LV) Modules
- (Not supported)
Discrete I/O Modules
DT1/DT4 - 24 Channels, Programmable for either input or output, output up to 500 mA per channel from an applied external 3 - 60 VCC source.
DT2/DT5 - 16 Channels, Programmable for either input voltage measurements (±80 V) or as a bi-directional current switch (up to 500 mA per channel).
DT3/DT6 - 4 Channels, Programmable for either input voltage measurements (±100 V) or as a bi-directional current switch (up to 3 A per channel).
TTL/CMOS Modules
- TL1-TL8 - 24 Channels, Programmable for either input or output.
Principle of Operation
The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.
The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:
- The application must not strobe during the Quiet time.
- The application must strobe within the Window time.
- The application must not strobe more than once in a single window time.
A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.
The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.
The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.
Figure 1. User Watchdog Timer Overview
Figure 2. User Watchdog Timer Example
Figure 3. User Watchdog Timer Failures
Register Descriptions
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.
User Watchdog Timer Registers
The registers associated with the User Watchdog Timer provide the ability to specify the UWDT Quiet Time and the UWDT Window that will be monitored to ensure that EXACTLY ONE User Watchdog Timer (UWDT) Strobe is written within the window.
UWDT Quiet Time Function: Sets Quiet Time value (in microseconds) to use for the User Watchdog Timer Frame. Type: unsigned binary word (32-bit) Data Range: 0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF) Read/Write: R/W Initialized Value: 0x0 Operational Settings: LSB = 1 µsec. The application must NOT write a strobe in the time between the previous strobe and the end of the Quiet time interval. In addition, the application must write in the UWDT Window EXACTLY ONCE. UWDT Window Function: Writes the window value (in microseconds) to be used for the User Watchdog Timer Frame. Type: unsigned binary word (32-bit) Data Range: 0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF) Read/Write: R/W Initialized Value: 0x0 Operational Settings: LSB = 1 µsec. The application must write the strobe once within the Window time after the end of the Quiet time interval. The application must write in the UWDT Window EXACTLY ONCE. This setting must be initialized to a non-zero value for operation and should allow sufficient tolerance for strobe timing by the application. UWDT Strobe Function: Writes the strobe value to be use for the User Watchdog Timer Frame. Type: unsigned binary word (32-bit) Data Range: 0x55AA Read/Write: W Initialized Value: 0x0 Operational Settings: At startup, the user watchdog is disabled. Write the value of 0x55AA to this register to start the user watchdog timer monitoring after initial power on or a reset. To prevent a disablement, the application must periodically write the strobe based on the user watchdog timer rules. Status and Interrupt
The modules that are capable of User Watchdog Timer support provide status registers for the User Watchdog Timer.
User Watchdog Timer Status
The status register that contains the User Watchdog Timer Fault information is also used to indicate channel Inter-FPGA failures on modules that have communication between FPGA components. There are four registers associated with the User Watchdog Timer Fault/Inter-FPGA Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.
Function: Sets the corresponding bit (D31) associated with the channel’s User Watchdog Timer Fault error. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt) Initialized Value: 0
User Watchdog Timer Fault/Inter-FPGA Failure Dynamic Status User Watchdog Timer Fault/Inter-FPGA Failure Latched Status User Watchdog Timer Fault/Inter-FPGA Failure Interrupt Enable User Watchdog Timer Fault/Inter-FPGA Failure Set Edge/Level Interrupt Bit(s) Status Description D31 User Watchdog Timer Fault Status 0 = No Fault + 1 = User Watchdog Timer Fault D30:D0 Reserved for Inter-FPGA Failure Status Channel bit-mapped indicating channel inter FPGA communication failure detection. Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.
In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
Interrupt Vector Function: Set an identifier for the interrupt. Type: unsigned binary word (32-bit) Data Range: 0 to 0xFFFF FFFF Read/Write: R/W Initialized Value: 0 Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism. Interrupt Steering Function: Sets where to direct the interrupt. Type: unsigned binary word (32-bit) Data Range: See table Read/Write: R/W Initialized Value: 0 Operational Settings: When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME 1 Direct Interrupt to ARM Processor (via SerDes)
(Custom App on ARM or NAI Ethernet Listener App)2 Direct Interrupt to PCIe Bus 5 Direct Interrupt to cPCI Bus 6 Function Register Map
KEY
Configuration/Control Measurement/Status
USER WATCHDOG TIMER REGISTERS OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS 0x01C0 UWDT Quiet Time R/W 0x01C4 UWDT Window R/W 0x01C8 UWDT Strobe R/W STATUS REGISTERS *When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0”). OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS 0x09B0 Dynamic Status R 0x09B4 Latched Status* R/W 0x09B8 Interrupt Enable R/W 0x09BC Set Edge/Level Interrupt R/W INTERRUPT REGISTERS The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses. OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS 0x056C Module 1 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x066C Module 1 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x076C Module 2 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x086C Module 2 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x096C Module 3 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x0A6C Module 3 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x0B6C Module 4 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x0C6C Module 4 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x0D6C Module 5 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x0E6C Module 5 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x0F6C Module 6 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x106C Module 6 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W REVISION HISTORY
Motherboard Manual - Status and Interrupts Revision History Revision Revision Date Description C 2021-11-30 C08896; Transition manual to docbuilder format - no technical info change. DOCS.NAII REVISIONS
Link to original
Revision Date Description 2026-03-02 Formatting updates to document; no technical changes.
MODULE COMMON REGISTERS
The registers described in this document are common to all NAI Generation 5 modules.
Module Information Registers
The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.
FPGA Version Registers
The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.
FPGA Revision Function: FPGA firmware revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the revision of the board's FPGA Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number
FPGA Compile Timestamp Function: Compile Timestamp for the FPGA firmware. Type: unsigned binary word (32-bit) Data Range: N/A Read/Write: R Initialized Value: Value corresponding to the compile timestamp of the board's FPGA Operational Settings: The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 day (5-bits) month (4-bits) year (6-bits) hr D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 hour (5-bits) minutes (6-bits) seconds (6-bits)
FPGA SerDes Revision Function: FPGA SerDes revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the SerDes revision of the board's FPGA Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number
FPGA Template Revision Function: FPGA Template revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the template revision of the board's FPGA Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number
FPGA Zynq Block Revision Function: FPGA Zynq Block revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the Zynq block revision of the board's FPGA Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number Bare Metal Version Registers
The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.
Bare Metal Revision Function: Bare Metal firmware revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the revision of the board's Bare Metal Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number
Bare Metal Compile Time Function: Provides an ASCII representation of the Date/Time for the Bare Metal compile time. Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit) Data Range: N/A Read/Write: R Initialized Value: Value corresponding to the ASCII representation of the compile time of the board's Bare Metal Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32 Note
little-endian order of ASCII values
Word 1 (Ex. 0x2079614D) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Space (0x20) Month ('y' - 0x79) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Month ('a' - 0x61) Month ('M' - 0x4D) Word 2 (Ex. 0x32203731) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Year ('2' - 0x32) Space (0x20) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Day ('7' - 0x37) Day ('1' - 0x31) Word 3 (Ex. 0x20393130) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Space (0x20) Year ('9' - 0x39) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Year ('1' - 0x31) Year ('0' - 0x30) Word 4 (Ex. 0x31207461) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Hour ('1' - 0x31) Space (0x20) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 'a' (0x74) 't' (0x61) Word 5 (Ex. 0x38333A35) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Minute ('8' - 0x38) Minute ('3' - 0x33) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ':' (0x3A) Hour ('5' - 0x35) Word 6 (Ex. 0x0032333A) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 NULL (0x00) Seconds ('2' - 0x32) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Seconds ('3' - 0x33) ':' (0x3A) FSBL Version Registers
The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).
FSBL Revision Function: FSBL firmware revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the revision of the board's FSBL Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number
FSBL Compile Time Function: Provides an ASCII representation of the Date/Time for the FSBL compile time. Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit) Data Range: N/A Read/Write: R Initialized Value: Value corresponding to the ASCII representation of the Compile Time of the board's FSBL Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32
Note
little-endian order of ASCII values
Word 1 (Ex. 0x2079614D) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Space (0x20) Month ('y' - 0x79) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Month ('a' - 0x61) Month ('M' - 0x4D) Word 2 (Ex. 0x32203731) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Year ('2' - 0x32) Space (0x20) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Day ('7' - 0x37) Day ('1' - 0x31) Word 3 (Ex. 0x20393130) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Space (0x20) Year ('9' - 0x39) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Year ('1' - 0x31) Year ('0' - 0x30) Word 4 (Ex. 0x31207461) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Hour ('1' - 0x31) Space (0x20) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 'a' (0x74) 't' (0x61) Word 5 (Ex. 0x38333A35) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Minute ('8' - 0x38) Minute ('3' - 0x33) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ':' (0x3A) Hour ('5' - 0x35) Word 6 (Ex. 0x0032333A) D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 NULL (0x00) Seconds ('2' - 0x32) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Seconds ('3' - 0x33) ':' (0x3A) Module Serial Number Registers
The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.
Interface Board Serial Number Function: Unique 128-bit identifier used to identify the interface board. Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit) Data Range: N/A Read/Write: R Initialized Value: Serial number of the interface board Operational Settings: This register is for information purposes only.
Functional Board Serial Number Function: Unique 128-bit identifier used to identify the functional board. Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit) Data Range: N/A Read/Write: R Initialized Value: Serial number of the functional board Operational Settings: This register is for information purposes only.
Module Capability Function: Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface. Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0x0000 0107 Read/Write: R Initialized Value: 0x0000 0107 Operational Settings: A “1” in the bit associated with the capability indicates that it is supported.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 Flt-Pt 0 0 0 0 0 Pack FIFO Blk Blk
Module Memory Map Revision Function: Module Memory Map revision Type: unsigned binary word (32-bit) Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Value corresponding to the Module Memory Map Revision Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Major Revision Number D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Minor Revision Number Module Measurement Registers
The registers in this section provide module temperature measurement information.
Temperature Readings Registers
The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.
Interface Board Current Temperature Function: Measured PCB and Zynq Core temperatures on Interface Board. Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R Initialized Value: Value corresponding to the measured PCB and Zynq core temperatures based on the table below Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PCB Temperature Zynq Core Temperature
Functional Board Current Temperature Function: Measured PCB temperature on Functional Board. Type: signed byte (8-bits) for PCB Data Range: 0x0000 0000 to 0x0000 00FF Read/Write: R Initialized Value: Value corresponding to the measured PCB on the table below Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 PCB Temperature
Interface Board Maximum Temperature Function: Maximum PCB and Zynq Core temperatures on Interface Board since power-on. Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R Initialized Value: Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PCB Temperature Zynq Core Temperature
Interface Board Minimum Temperature Function: Minimum PCB and Zynq Core temperatures on Interface Board since power-on. Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures Data Range: 0x0000 0000 to 0x0000 FFFF Read/Write: R Initialized Value: Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PCB Temperature Zynq Core Temperature
Functional Board Maximum Temperature Function: Maximum PCB temperature on Functional Board since power-on. Type: signed byte (8-bits) for PCB Data Range: 0x0000 0000 to 0x0000 00FF Read/Write: R Initialized Value: Value corresponding to the measured PCB on the table below Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 PCB Temperature
Functional Board Minimum Temperature Function: Minimum PCB temperature on Functional Board since power-on. Type: signed byte (8-bits) for PCB Data Range: 0x0000 0000 to 0x0000 00FF Read/Write: R Initialized Value: Value corresponding to the measured PCB on the table below Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 PCB Temperature Higher Precision Temperature Readings Registers
These registers provide higher precision readings of the current Zynq and PCB temperatures.
Higher Precision Zynq Core Temperature Function: Higher precision measured Zynq Core temperature on Interface Board. Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Measured Zynq Core temperature on Interface Board Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Signed Integer Part of Temperature D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Fractional Part of Temperature
Higher Precision Interface PCB Temperature Function: Higher precision measured Interface PCB temperature. Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Measured Interface PCB temperature Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Signed Integer Part of Temperature D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Fractional Part of Temperature
Higher Precision Functional PCB Temperature Function: Higher precision measured Functional PCB temperature. Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part Data Range: 0x0000 0000 to 0xFFFF FFFF Read/Write: R Initialized Value: Measured Functional PCB temperature Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Signed Integer Part of Temperature D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Fractional Part of Temperature Module Health Monitoring Registers
The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.
Module Sensor Summary Status Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds. Type: unsigned binary word (32-bits) Data Range: See table below Read/Write: R Initialized Value: 0 Operational Settings: This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.
Bit(s) Sensor D31:D6 Reserved D5 Functional Board PCB Temperature D4 Interface Board PCB Temperature D3:D0 Reserved Module Sensor Registers
The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.
Sensor Threshold Status Function: Reflects which threshold has been crossed Type: unsigned binary word (32-bits) Data Range: See table below Read/Write: R Initialized Value: 0 Operational Settings: The associated bit is set when the sensor reading exceed the corresponding threshold settings.
Bit(s) Description D31:D4 Reserved D3 Exceeded Upper Critical Threshold D2 Exceeded Upper Warning Threshold D1 Exceeded Lower Critical Threshold D0 Exceeded Lower Warning Threshold
Sensor Current Reading Function: Reflects current reading of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R Initialized Value: N/A Operational Settings: The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Minimum Reading Function: Reflects minimum value of temperature sensor since power up Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R Initialized Value: N/A Operational Settings: The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Maximum Reading Function: Reflects maximum value of temperature sensor since power up Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R Initialized Value: N/A Operational Settings: The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Lower Warning Threshold Function: Reflects lower warning threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default lower warning threshold (value dependent on specific sensor) Operational Settings: The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.
Sensor Lower Critical Threshold Function: Reflects lower critical threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default lower critical threshold (value dependent on specific sensor) Operational Settings: The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.
Sensor Upper Warning Threshold Function: Reflects upper warning threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default upper warning threshold (value dependent on specific sensor) Operational Settings: The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.
Sensor Upper Critical Threshold Function: Reflects upper critical threshold of temperature sensor Type: Single Precision Floating Point Value (IEEE-754) Data Range: Single Precision Floating Point Value (IEEE-754) Read/Write: R/W Initialized Value: Default upper critical threshold (value dependent on specific sensor) Operational Settings: The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius. FUNCTION REGISTER MAP
KEY
Configuration/Control Measurement/Status/Board Information
MODULE INFORMATION REGISTERS OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS 0x003C FPGA Revision R 0x0074 Bare Metal Revision R 0x0030 FPGA Compile Timestamp R 0x0080 Bare Metal Compile Time (Bit 0-31) R 0x0034 FPGA SerDes Revision R 0x0084 Bare Metal Compile Time (Bit 32-63) R 0x0038 FPGA Template Revision R 0x0088 Bare Metal Compile Time (Bit 64-95) R 0x0040 FPGA Zynq Block Revision R 0x008C Bare Metal Compile Time (Bit 96-127) R 0x0090 Bare Metal Compile Time (Bit 128-159) R 0x0094 Bare Metal Compile Time (Bit 160-191) R 0x007C FSBL Revision R 0x00B0 FSBL Compile Time (Bit 0-31) R 0x00B4 FSBL Compile Time (Bit 32-63) R 0x00B8 FSBL Compile Time (Bit 64-95) R 0x00BC FSBL Compile Time (Bit 96-127) R 0x00C0 FSBL Compile Time (Bit 128-159) R 0x00C4 FSBL Compile Time (Bit 160-191) R 0x0000 Interface Board Serial Number (Bit 0-31) R 0x0010 Functional Board Serial Number (Bit 0-31) R 0x0034 Interface Board Serial Number (Bit 32-63) R 0x0014 Functional Board Serial Number (Bit 32-63) R 0x0008 Interface Board Serial Number (Bit 64-95) R 0x0018 Functional Board Serial Number (Bit 64-95) R 0x000C Interface Board Serial Number (Bit 96-127) R 0x001C Functional Board Serial Number (Bit 96-127) R 0x0070 Module Capability R 0x01FC Module Memory Map Revision R MODULE MEASUREMENTS REGISTERS OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS 0x0200 Interface Board PCB/Zynq Current Temp R 0x0208 Functional Board PCB Current Temp R 0x0218 Interface Board PCB/Zynq Max Temp R 0x0228 Functional Board PCB Max Temp R 0x0220 Interface Board PCB/Zynq Min Temp R 0x0230 Functional Board PCB Min Temp R 0x02C0 Higher Precision Zynq Core Temperature R 0x02C4 Higher Precision Interface PCB Temperature R 0x02E0 Higher Precision Functional PCB Temperature R MODULE HEALTH MONITORING REGISTERS OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS 0x07F8 Module Sensor Summary Status R  REVISION HISTORY
Motherboard Manual - Module Common Registers Revision History Revision Revision Date Description C 2023-08-11 ECO C10649, initial release of module common registers manual. C1 2024-05-15 ECO C11522, removed Zynq Core/Aux/DDR Voltage register descriptions from Module Measurement Registers. Pg.16, updated Module Sensor Summary Status register to add PS references; updated Bit Table to change voltage/current bits to 'reserved'. Pg.16, updated Module/Power Supply Sensor Registers description to better describe register functionality and to add figure. Pg.17, added 'Exceeded' to threshold bit descriptions. Pg.17-18, removed voltage/current references from sensor descriptions. Pg.20, removed Zynq Core/Aux/DDR Voltage register offsets from Module Measurement Registers. Pg.20, updated Module Health Monitoring Registers offset tables. C2 2024-07-10 ECO C11701, pg.16, updated Module Sensor Summary Status register to remove PS references;updated Bit Table to change PS temperature bits to 'reserved'. Pg.16, updated Module SensorRegisters description to remove PS references. Pg.20, updated Module Health MonitoringRegisters offset tables to remove PS temperature register offsets. DOCS.NAII REVISIONS
Link to original
Revision Date Description 2025-11-05 Corrected register offsets for Interface Board Min Temp and Function Board Min & Max Temps. 2026-03-02 Formatting updates to document; no technical changes.
NAI Cares
North Atlantic Industries (NAI) is a leading independent supplier of Embedded I/O Boards, Single Board Computers, Rugged Power Supplies, Embedded Systems and Motion Simulation and Measurement Instruments for the Military, Aerospace and Industrial Industries. We accelerate our clients’ time-to-mission with a unique approach based on a Configurable Open Systems Architecture™ (COSA®) that delivers the best of both worlds: custom solutions from standard COTS components.
We have built a reputation by listening to our customers, understanding their needs, and designing, testing and delivering board and system-level products for their most demanding air, land and sea requirements. If you have any applications or questions regarding the use of our products, please contact us for an expedient solution.
Please visit us at: www.naii.com or select one of the following for immediate assistance:
Documentation
FAQ
Application Notes
http://www.naii.com/applicationnotes
Calibration and Repairs
http://www.naii.com/calibrationrepairs
Call Us
(631) 567-1100
Link to original