AC Manual

INTRODUCTION

This module manual provides information about the North Atlantic Industries, Inc. (NAI) AC Reference Functions (AC1, AC2, and AC3). The AC modules are compatible with all NAI Generation 5 motherboards.

AC Reference modules provide an AC reference voltage or an AC signal source for multifunction Input/Output (I/O) and Single Board Computer (SBC) systems. Each module covers a specific voltage range:

Module ID	General Description
AC1	2 Channels AC Reference; CH-1: 2-28 Vrms, 47 Hz-20 kHz, 6 VA / 500 mA max. CH-2: 28 -115 Vrms, 47 Hz -2.5 kHz, 6 VA / 52 mA max. Note: Advanced Specification. Contact Factory for further information.
AC2	2 Channels AC Reference 2 to 28 Vrms, 47 Hz to 20 kHz, 6 VA / 500 mA max.
AC3	2 Channels AC Reference 28 to 115 Vrms, 47 Hz to 2.5 kHz, 6 VA / 52 mA max.

FEATURES

High accuracy reference or source AC voltages
Variety of Vrms ranges
Overcurrent protection
All channels have continuous background Built-In-Test (BIT).

SPECIFICATION

Module ID	General Description
AC1	2 Channels AC Reference; CH-1: 2-28 Vrms, 47 Hz-20 kHz, CH2: 28 -115 Vrms, 47 Hz -2.5 kHz Note: Advanced Specification. Contact Factory for further information.
AC2	2 Channels AC Reference (2 to 28 Vrms, 47 Hz to 20 kHz)
AC3	2 Channels AC Reference (28 to 115 Vrms, 47 Hz to 2.5 kHz)

Voltage Output:

AC1	2 Vrms to 115 Vrms, programmable with a resolution of 0.01V 2.0 to 28.0 Vrms; 47 Hz to 20 kHz frequency range 28.0 to 115.0 Vrms; 47 Hz to 2.5 kHz frequency range
AC2	2 Vrms to 28 Vrms, programmable with a resolution of 0.01 V
AC3	28 Vrms to 115 Vrms, programmable with a resolution of 0.01 V

Accuracy (No Load):

AC1	±1% of setting < 15 kHz; ±3% of setting ≥ 15 kHz
AC2	±1.5% of setting < 15 kHz; ±3% of setting ≥ 15 kHz
AC3	±1% of setting

Regulation:

AC1	±1% No Load to Full Load (using sense lines)
AC2	±1.5% No Load to Full Load (using sense lines)
AC3	±0.5% No Load to Full Load (using sense lines)

Output Drive:

AC1	6 VA maximum or 500 mA, 2V-28 V ; 50 mA maximum, 28 V-115 V
AC2	6 VA maximum or 500 mA
AC3	6 VA maximum or 52 mA maximum

Protection:

AC1-AC3	Output overcurrent shutdown with manual reset

Frequency:

AC1	47 Hz to 20 kHz programmable with 0.01 Hz steps
AC2	47 Hz to 20 kHz programmable with 0.01 Hz steps
AC3	47 Hz to 2.5 kHz programmable with 0.01 Hz steps

Freq. Accuracy:

AC1-AC3	±0.1% of programmed frequency or ±1 Hz (whichever is greater)

THD:

AC1	< 3% (47 Hz – 15 kHz), < 5% (15 kHz – 20 kHz)
AC2	< 3% (47 Hz – 15 kHz), < 5% (15 kHz – 20 kHz)
AC3	< 5%

Power:

AC1-AC3	5 VDC @ 350 mA ±12 VDC @ 230 mA (Quiescent, no load) Note: Add ±12 VDC @ 100 mA for every 1 VA Load

Ground:

AC1-AC3	Isolated from system ground

Weight:

AC1-AC3	1.5 oz. (43g)

Specifications are subject to change without notice.

Specifications

Module ID	General Description
AC1	2 Channels AC Reference; CH-1: 2-28 Vrms, 47 Hz-20 kHz, CH2: 28 -115 Vrms, 47 Hz -2.5 kHz Note: Advanced Specification. Contact Factory for further information.
AC2	2 Channels AC Reference (2 to 28 Vrms, 47 Hz to 20 kHz)
AC3	2 Channels AC Reference (28 to 115 Vrms, 47 Hz to 2.5 kHz)

PRINCIPLE OF OPERATION

The AC Reference module is typically used to provide an AC signal source for synchro, resolver LVDT and RVDT devices. All synchro, resolver, LVDT and RVDT measurement and simulation systems use transformers (either true transformers or galvanic solid-state transformers), whose main primary-to-secondary coupling is varied by physically changing (or, in simulation, commanding) the relative orientation of the two windings. For operation, the primary winding of theses transformers is excited by an alternating current, by which electromagnetic induction causes currents to flow in the secondary windings fixed at certain characteristic electrical angles, for example: a synchro has three secondary winding legs, each at 120 E-degrees apart to each other on the stator. While most of NAI’s modules provide an onboard reference module as an option, when a secondary source is required, the AC reference modules can be used to provide an AC signal source.

The AC Reference module provides a constant voltage and a high accuracy reference over 2 channels of operation. The 2-channel, isolated AC output is voltage and frequency programmable for its full-range Continuous accuracy monitoring is performed to verify the voltage and frequency outputs. Overcurrent protection is provided via a sensing circuit that continuously samples the current. The module will be shut down the reference channel when the overcurrent condition is detected.

The following is the suggested sequence of initialization:

Reference Frequency for each channel
Reference Voltage for each channel
Power-on module

Built-In Test (BIT)/Diagnostic Capability

Automatic background BIT testing is provided. Each channel is checked for correct voltage, current and frequency. Any failure triggers an interrupt, if enabled, with the results available in the status registers. The testing is totally transparent to the user and has no effect on the operation of this module.

Auto Gain Control and Voltage Out-of-Spec Detection

If the voltage is within the module’s voltage specification for the set value, the firmware will adjust the voltage to meet the set value. If the voltage is outside the specification range, the AGC will stop and the voltage out-of-spec bit will be set in the status register. A BIT error will also be generated. Note, when the voltage out-of-spec is detected, the channel is not disabled.

Frequency Out-of-Spec Detection

The frequency is measured using a clock from a different source than the 100 MHz clock generating the sine wave reference. If the output frequency is outside the module’s specification of the set value, the frequency out-of-spec bit will be set in the status register. A BIT error will also be generated. Note, when the frequency out-of-spec is detected, the channel is not disabled.

Overcurrent Detection

There are two current limits which are used to detect overcurrent.

A programmable current limit can be specified. When the output RMS current exceeds this user defined threshold, the overcurrent bit will be set in the status register. Note, when the overcurrent of the user defined threshold is detected, the channel is disabled.
A hard-current (AC module dependent) limit. When the output RMS current exceeds the maximum rated current, determined by the output voltage setpoint, the channel automatically disables the channel. Writing a “1” to the channel’s Reset Overcurrent register reenables the channel. AC module current limits are as follows:

a. AC1: TBD b. AC2: 550 mA (2 Vrms - 12 Vrms) or 6.6 VA (12 Vrms - 28 Vrms). c. AC3: 55 mA (28 Vrms - 115 Vrms)

Background BIT Threshold Programming

The technique used by the continuous background BIT (CBIT) test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. Note, the interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go” before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained; i.e. at a ten second interval, not a 10-millisecond interval). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state.

Status and Interrupts

The AC Reference Module provides registers that indicate faults or events. Refer to “User Watchdog Timer Module Manual” for the Principle of Operation description.

Module Common Registers

The AC Reference Module includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

Unit Conversions

The AC Reference Module registers can be programmed to be utilized as single precision floating point values (IEEE-754) or as 32-bit integer values. When using floating point values, the hardware handles the float-to-fixed conversion (and vise-versa) so your mission computer’s CPU is not burden with the task.

When Enable Floating Point Mode is set to 1 (Floating Point Mode) the following registers are formatted as Single Precision Floating Point Value (IEEE-754):

Voltage Reading (Volts)
Current Reading (mA)
Frequency Reading (Hz)
Reference Frequency (Hz)*
Reference Voltage (V)*
Current Limit (mA)*

*When the Enable Floating Point Mode register is set to 1, it is important that these registers are updated with the Single Precision Floating Point (IEEE-754) representation of the value for proper operation of the channel. Conversely, when the Enable Floating Point Mode register is set to 0, these registers must be updated with the Integer 32-bit representation of the value.

Note

When changing the Enable Floating Point Mode from Integer Mode to Floating Point Mode or vice versa, the following step should be followed to avoid faults from falsely being generated because data registers (such as Thresholds) or internal registers may have the incorrect binary representation of the values:

Set the Enable Floating Point Mode register to the desired mode (Integer = 0 or Floating Point = 1).
Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete. Data registers will be converted to the units specified and can be read in that specified format.
Initialize configuration and control registers with the values in the units specified (Integer or Floating Point).

User Watchdog Timer Capability

The AC Reference Module provides User Watchdog Timer Capability. Refer to “User Watchdog Timer Module Manual” for the Principle of Operation description.

REGISTER DESCRIPTIONS

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Reference Command Registers

The frequency and voltage for the reference channel are set by writing to the Reference Frequency and Reference Voltage registers.

Reference Frequency

Function: Programs reference frequency for each channel.

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: AC1:47 to 10kHz, AC2: 47 to 20kHz, AC3: 47 to 2.5kHz

 Enable Floating Point Mode: 0 (Integer Mode) **AC1**: 0x0000 125C to 0x000F

4240; AC2: 0x0000 125C to 0x001E 8480; AC3: 0x0000 125C to 0x0003 D090

 Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: 47 Hz

Operational Settings:

Integer Mode: LSB is 0.01 Hz. For example: to program 400 Hz, 400 / 0.01 = 40000. (binary equivalent for 40000 is 0x0000 9C40).

Floating Point Mode: Set value as Single Precision Floating Point Value (IEEE-754). For example, to program 400 Hz, enter 400 as Single Precision Floating Point Value (IEEE-754) (binary equivalent 400 is 0x43C8 0000).

Reference Frequency (Enable Floating Point Mode: Integer Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Reference Frequency (Enable Floating Point Mode: Floating Point Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Reference Voltage

Function: Program Reference Voltage for each channel.

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: AC1: 2.0 to 115Vrms; AC2: 2.0 to 28.0Vrms; AC3: 28.0 to 115Vrms

 Enable Floating Point Mode: 0 (Integer Mode) **AC1**: 0x0000 00C8 to 0x0000

2CEC; AC2: 0x0000 00C8 to 0x0000 0AF0; AC3: 0x0000 0AF0 to 0x0000 2CEC

 Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: 2 V

Operational Settings:

Integer Mode: LSB is 0.01 VRMS. For example: to program 26.1 VRMS, 26.1 / 0.01 = 2610 (binary equivalent for 2610 is 0x0000 0A32).

Floating Point Mode: Set Single Precision Floating Point Value (IEEE-754) for reference frequency. For example, to program 26.1 V, enter 26.1 as Single Precision Floating Point Value (IEEE-754) (binary equivalent for 26.1 is 0x41D0 CCCD).

Reference Voltage (Enable Integer Mode: Integer Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

Reference Voltage (Enable Floating Point Mode: Floating Point Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Reference Reading Registers

The measured voltage, current and frequency for the reference channel can be read from the Voltage Reading, Current Reading and Frequency Reading registers.

_Voltage Reading _

Function: Read Voltage for each channel.

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

 Enable Floating Point Mode: 0 (Integer Mode) 0x0000 0000 to 0x0000 0AF0

 Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings:

Integer Mode: LSB is 0.01 VRMS. If the register value is 2610 (binary equivalent for this value is 0x0000 0A32), conversion to the voltage value is 2610 * 0.01 = 26.1 V.

Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754). For example, the binary equivalent for 0x41D0 CCCD is 26.1 which represent 26.1 V.

Voltage Reading (Enable Floating Point Mode: Integer Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

Voltage Reading (Enable Floating Point Mode: Floating Point Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Current Reading

Function: Read Current for each channel

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

 Enable Floating Point Mode: 0 (Integer Mode) (Actual current * 100)

 Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings:

Integer Mode: LSB is .01 mA. If the register value is 10 (binary equivalent for this value is 0x0000 000A), conversion to the current value is 10 * .01 = .10 mA.

Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754). For example, the binary equivalent for 0x4120 0000 is 10.0 which represent 10 mA.

Current Reading (Enable Floating Point Mode: Integer Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

Current Reading (Enable Floating Point Mode: Floating Point Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Frequency Reading

Function: Read Frequency for each channel

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

 Enable Floating Point Mode: 0 (Integer Mode) (Actual Frequency * 100)

 Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R

Initialized Value: N/A

Operational Settings:

Integer Mode: LSB is 0.01 Hz. If the register value is 40000 (binary equivalent for this value is 0x0000 9C40), conversion to the hertz value is 40000 * 0.01 = 400 Hz.

Floating Point Mode: Read as Single Precision Floating Point Value (IEEE-754). For example, the binary equivalent for 0x43C8 0000 is 400 which represent 400 Hz.

Frequency Reading (Enable Floating Point Mode: Integer Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Frequency Reading (Enable Floating Point Mode: Floating Point Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Reference Control Registers

The registers specified in this section provide current limit, enable and overcurrent reset control for each reference channel.

Current Limit

Function: Set the Current Limit for each channel

Type: unsigned binary word (32-bit) or Single Precision Floating Point Value (IEEE-754)

Data Range: N/A

 Enable Floating Point Mode: 0 (Integer Mode) (Current limit to the nearest milliamp)

 Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)

Read/Write: R/W

Initialized Value: N/A

Operational Settings: Set the current limit for the channel in mA

Integer Mode: LSB is 1.0 mA. For example: to program 100 mA, 100 x 1.0= 100 (binary equivalent for this value is 0x0000 0064).

Floating Point Mode: Set as Single Precision Floating Point Value (IEEE-754) for reference frequency. For example, to program 100 mA, enter 100.0 as Single Precision Floating Point Value (IEEE-754) (binary equivalent for 100.0 is 0x42C8 0000).

Current Limit (Enable Floating Point Mode: Integer Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

Current Limit (Enable Floating Point Mode: Floating Point Mode)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

_Channel Enable _

Function: Enable for each channel

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: R/W

Initialized Value: 0

Operational Settings: Writing a 1 to this register turns on the channel. Writing a 0 to this register turns off the channel.

Channel Enable

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Reset Overcurrent

Function: Reset overcurrent for each channel

Type: unsigned binary word (32-bit)

Data Range: 0 or 1

Read/Write: R/W

Initialized Value: 0

Operational Settings: The Reset Overcurrent register will be set to 0. To re-enable the overcurrent protection circuit, write a 1 to the Reset Overcurrent register. The firmware will write a 0 when the overcurrent reset is complete

Reset Overcurrent

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Background BIT Threshold Programming Registers

The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The Reset BIT register provides the ability to reset the BIT counter used in CBIT.

Background BIT Threshold

Function: Sets BIT Threshold value (in milliseconds) to use for all channels for BIT failure indication.

Type: unsigned binary word (32-bit)

Data Range: 1 ms to TBD

Read/Write: R/W

Initialized Value: TBD

Operational Settings: The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module.

Reset BIT

Function: Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0003

Read/Write: W

Initialized Value: 0

Operational Settings: Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.

Reset BIT

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Ch2	Ch1

Unit Conversion Programming Registers

The Enable Floating Point register provides the ability to set the Frequency, Voltage and Current values as floating point values and read the Voltage, Current and Frequency readings as floating point values. The purpose for this feature is to offload the processing that is normally performed by the mission processor to convert the integer values to floating point values.

Enable Floating Point Mode

Function: Sets all channels for floating point mode or integer module.

Type: unsigned binary word (32-bit)

Data Range: 0 to 1

Read/Write: R/W

Initialized Value: 0

Operational Settings: Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode. Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

Enable Floating Point Mode

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Floating Point State

Function: Indicates whether the module’s internal processing is converting the register values and internal values to the binary representation of the mode selected (Integer or Floating Point).

Type: unsigned binary word (32-bit)

Data Range: 0 to 1

Read/Write: R

Initialized Value: 0

Operational Settings: Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register’s value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

Floating Point State

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

User Watchdog Timer Registers

Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Register Descriptions.

Module Common Registers

Refer to “Module Common Registers Module Manual” for the register descriptions.

Status and Interrupt Registers

The AC Modules provide BIT, Reference Channel, User Watchdog Time Fault and Summary status registers.

Channel Status Enabled

Function: Determines whether to update the status for the channels. This feature can be used to “mask” status bits of unused channels in status registers that are bitmapped by channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0FFF (Channel Status)

Read/Write: R/W

Initialized Value: 0x0000 0FFF

Operational Settings: When the bit corresponding to a given channel in the Channel Status Enabled register is not enabled (0) the status will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status and Summary Status).

Note

Background BIT will continue to run even if the Channel Status Enabled is set to ‘0’.

Channel Status Enabled

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Ch2	Ch1

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The BIT Status register will indicate an error when the voltage read is not within the error of the set value.

BIT Status

BIT Dynamic Status
BIT Latched Status
BIT Interrupt Enable BIT
Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Ch2	Ch1

Function: Sets the corresponding bit associated with the channel’s BIT error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0003

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Reference Channel Status

There are four registers associated with the Reference Channel Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The Reference Channel Status register will indicate an error for the conditions shown in the table below:

Bit	Description
D0	Overcurrent
D1	Voltage out-of-spec
D2	Frequency out-of-spec

Reference Channel Status

Reference Channel Dynamic Status
Reference Channel Latched Status
Reference Channel Interrupt Enable
Reference Channel Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	D	D	D

Function: Sets the corresponding bits associated with a channel’s Overcurrent, Voltage or Frequency out-of-specification error.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0007

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

User Watchdog Timer Fault

Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Fault Status and Interrupt Descriptions.

Summary Status

There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Summary Status

Summary Status Dynamic Status
Summary Status Latched Status
Summary Status Interrupt Enable
Summary Status Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Ch2	Ch1

Function: Sets the corresponding bit when a fault is detected for BIT or any error condition that is set in the Reference Channel Status (Overcurrent, Voltage out-of-spec, and Frequency out-of-spec) on that channel.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0x0000 0003

Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)

Initialized Value: 0

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note

The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector

Function: Set an identifier for the interrupt.

Type: unsigned binary word (32-bit)

Data Range: 0x0000 0000 to 0xFFFF FFFF

Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering*

Function: Sets where to direct the interrupt.

Type: unsigned binary word (32-bit)

Data Range: See table Read/Write: R/W

Initialized Value: 0

Operational Settings: When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME	1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)	2
Direct Interrupt to PCIe Bus	5
Direct Interrupt to cPCI Bus	6

FUNCTION REGISTER MAP

Key:

Bold Italic = Configuration/Control

Bold Underline = Measurement/Status

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0”).

Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).

Reference Command Registers

0x1000	Reference Frequency Ch 1****	R/W
0x1100	Reference Frequency Ch 2****	R/W

0x1004	Reference Voltage Ch 1****	R/W
0x1104	Reference Voltage Ch 2****	R/W

=== Reference Reading Registers

0x1008	Voltage Reading Ch 1****	R
0x1108	Voltage Reading Ch 2****	R

0x100C	Current Reading Ch 1****	R
0x110C	Current Reading Ch 2****	R

0x101C	Frequency Reading Ch 1****	R
0x111C	Frequency Reading Ch 2****	R

Reference Control Registers

0x1018	Current Limit Ch 1****	R/W
0x1118	Current Limit Ch 2****	R/W

0x1010	*Channel Enable Ch 1*	R/W
0x1110	*Channel Enable Ch 2*	R/W

0x1014	*Reset Overcurrent Ch 1*	W
0x1114	*Reset Overcurrent Ch 2*	W

Unit Conversion Programming Registers

0x02B4	*Enable Floating Point*	R/W
0x0264	Floating Point State	R

User Watchdog Timer Registers

The AC Reference Modules provide registers that support User Watchdog Timer capability. Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Function Register Map.

Module Common Registers

Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.

Status Registers

0x02B0	*Channel Status Enabled*	R/W BIT Registers

BIT Status

0x0800	Dynamic Status	R
0x0804	Latched Status*	R/W
0x0808	*Interrupt Enable*	R/W
0x080C	*Set Edge/Level Interrupt*	R/W

0x02B8	*Background BIT Threshold*	R/W
0x02BC	*Reset BIT*	W

Status Registers

Reference Channel Status

Ch 1
0x0810	Dynamic Status	R
0x0814	Latched Status*	R/W
0x0818	*Interrupt Enable*	R/W
0x081C	*Set Edge/Level Interrupt*	R/W
Ch 2
0x0820	Dynamic Status	R
0x0824	Latched Status*	R/W
0x0828	*Interrupt Enable*	R/W
0x082C	*Set Edge/Level Interrupt*	R/W

User Watchdog Timer Fault

Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Status Function Register Map.

Summary Status

0x09A0	Dynamic Status	R
0x09A4	Latched Status*	R/W
0x09A8	*Interrupt Enable*	R/W
0x09AC	*Set Edge/Level Interrupt*	R/W

Interrupt Registers

The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.

0x0500	*Module 1 Interrupt Vector 1 - BIT*	R/W
0x0504	*Module 1 Interrupt Vector 2 - Ref Status Ch 1*	R/W
0x0508	*Module 1 Interrupt Vector 3 - Ref Status Ch 2*	R/W
0x050C to 0x0564	*Module 1 Interrupt Vector 4 to 26 - Reserved*	R/W
0x0568	*Module 1 Interrupt Vector 27 - Summary*	R/W
0x056C	*Module 1 Interrupt Vector 28 - User Watchdog Timer*	R/W
0x0570 to 0x057C	*Module 1 Interrupt Vector 29 to 32 - Reserved*	R/W

0x0600	*Module 1 Interrupt Steering 1 - BIT*	R/W
0x0604	*Module 1 Interrupt Steering 2 - Ref Status Ch 1*	R/W
0x0608	*Module 1 Interrupt Steering 3 - Ref Status Ch 2*	R/W
0x060C to 0x0664	*Module 1 Interrupt Steering 4 to 26 - Reserved*	R/W
0x0668	*Module 1 Interrupt Steering 27 - Summary*	R/W
0x066C	*Module 1 Interrupt Steering 28 - User Watchdog Timer*	R/W
0x0670 to 0x067C	*Module 1 Interrupt Steering 29 to 32 - Reserved*	R/W

0x0700	*Module 2 Interrupt Vector 1 - BIT*	R/W
0x0704	*Module 2 Interrupt Vector 2 - Ref Status Ch 1*	R/W
0x0708	*Module 2 Interrupt Vector 3 - Ref Status Ch 2*	R/W
0x070C to 0x0764	*Module 2 Interrupt Vector 4 to 26 - Reserved*	R/W
0x0768	*Module 2 Interrupt Vector 27 - Summary*	R/W
0x076C	*Module 2 Interrupt Vector 28 - User Watchdog Timer*	R/W
0x0770 to 0x077C	*Module 2 Interrupt Vector 29 to 32 - Reserved*	R/W

0x0800	*Module 2 Interrupt Steering 1 - BIT*	R/W
0x0804	*Module 2 Interrupt Steering 2 - Ref Status Ch 1*	R/W
0x0808	*Module 2 Interrupt Steering 3 - Ref Status Ch 2*	R/W
0x080C to 0x0864	*Module 2 Interrupt Steering 4 to 26 - Reserved*	R/W
0x0868	*Module 2 Interrupt Steering 27 - Summary*	R/W
0x086C	*Module 2 Interrupt Steering 28 - User Watchdog Timer*	R/W
0x0870 to 0x087C	*Module 2 Interrupt Steering 29 to 32 - Reserved*	R/W

0x0900	*Module 3 Interrupt Vector 1 - BIT*	R/W
0x0904	*Module 3 Interrupt Vector 2 - Ref Status Ch 1*	R/W
0x0908	*Module 3 Interrupt Vector 3 - Ref Status Ch 2*	R/W
0x090C to 0x0964	*Module 3 Interrupt Vector 4 to 26 - Reserved*	R/W
0x0968	*Module 3 Interrupt Vector 27 - Summary*	R/W
0x096C	*Module 3 Interrupt Vector 28 - User Watchdog Timer*	R/W
0x0970 to 0x097C	*Module 3 Interrupt Vector 29 to 32 - Reserved*	R/W

0x0A00	*Module 3 Interrupt Steering 1 - BIT*	R/W
0x0A04	*Module 3 Interrupt Steering 2 - Ref Status Ch 1*	R/W
0x0A08	*Module 3 Interrupt Steering 3 - Ref Status Ch 2*	R/W
0x0A0C to 0x0A64	*Module 3 Interrupt Steering 4 to 26 - Reserved*	R/W
0x0A68	*Module 3 Interrupt Steering 27 - Summary*	R/W
0x0A6C	*Module 3 Interrupt Steering 28 - User Watchdog Timer*	R/W
0x0A70 to 0x0A7C	*Module 3 Interrupt Steering 29 to 32 - Reserved*	R/W

0x0B00	*Module 4 Interrupt Vector 1 - BIT*	R/W
0x0B04	*Module 4 Interrupt Vector 2 - Ref Status Ch 1*	R/W
0x0B08	*Module 4 Interrupt Vector 3 - Ref Status Ch 2*	R/W
0x0B0C to 0x0B64	*Module 4 Interrupt Vector 4 to 26 - Reserved*	R/W
0x0B68	*Module 4 Interrupt Vector 27 - Summary*	R/W
0x0B6C	*Module 4 Interrupt Vector 28 - User Watchdog Timer*	R/W
0x0B70 to 0x0B7C	*Module 4 Interrupt Vector 29 to 32 - Reserved*	R/W

0x0C00	*Module 4 Interrupt Steering 1 - BIT*	R/W
0x0C04	*Module 4 Interrupt Steering 2 - Ref Status Ch 1*	R/W
0x0C08	*Module 4 Interrupt Steering 3 - Ref Status Ch 2*	R/W
0x0C0C to 0x0C64	*Module 4 Interrupt Steering 4 to 26 - Reserved*	R/W
0x0C68	*Module 4 Interrupt Steering 27 - Summary*	R/W
0x0C6C	*Module 4 Interrupt Steering 28 - User Watchdog Timer*	R/W
0x0C70 to 0x0C7C	*Module 4 Interrupt Steering 29 to 32 - Reserved*	R/W

0x0D00	*Module 5 Interrupt Vector 1 - BIT*	R/W
0x0D04	*Module 5 Interrupt Vector 2 - Ref Status Ch 1*	R/W
0x0D08	*Module 5 Interrupt Vector 3 - Ref Status Ch 2*	R/W
0x0D0C to 0x0D64	*Module 5 Interrupt Vector 4 to 26 - Reserved*	R/W
0x0D68	*Module 5 Interrupt Vector 27 - Summary*	R/W
0x0D6C	*Module 5 Interrupt Vector 28 - User Watchdog Timer*	R/W
0x0D70 to 0x0D7C	*Module 5 Interrupt Vector 29 to 32 - Reserved*	R/W

0x0E00	*Module 5 Interrupt Steering 1 - BIT*	R/W
0x0E04	*Module 5 Interrupt Steering 2 - Ref Status Ch 1*	R/W
0x0E08	*Module 5 Interrupt Steering 3 - Ref Status Ch 2*	R/W
0x0E0C to 0x0E64	*Module 5 Interrupt Steering 4 to 26 - Reserved*	R/W
0x0E68	*Module 5 Interrupt Steering 27 - Summary*	R/W
0x0E6C	*Module 5 Interrupt Steering 28 - User Watchdog Timer*	R/W
0x0E70 to 0x0E7C	*Module 5 Interrupt Steering 29 to 32 - Reserved*	R/W

0x0F00	*Module 6 Interrupt Vector 1 - BIT*	R/W
0x0F04	*Module 6 Interrupt Vector 2 - Ref Status Ch 1*	R/W
0x0F08	*Module 6 Interrupt Vector 3 - Ref Status Ch 2*	R/W
0x0F0C to 0x0F64	*Module 6 Interrupt Vector 4 to 26 - Reserved*	R/W
0x0F68	*Module 6 Interrupt Vector 27 - Summary*	R/W
0x0F6C	*Module 6 Interrupt Vector 28 - User Watchdog Timer*	R/W
0x0F70 to 0x0F7C	*Module 6 Interrupt Vector 29 to 32 - Reserved*	R/W

0x1000	*Module 6 Interrupt Steering 1 - BIT*	R/W
0x1004	*Module 6 Interrupt Steering 2 - Ref Status Ch 1*	R/W
0x1008	*Module 6 Interrupt Steering 3 - Ref Status Ch 2*	R/W
0x100C to 0x1064	*Module 6 Interrupt Steering 4 to 26 - Reserved*	R/W
0x1068	*Module 6 Interrupt Steering 27 - Summary*	R/W
0x106C	*Module 6 Interrupt Steering 28 - User Watchdog Timer*	R/W
0x1070 to 0x107C	*Module 6 Interrupt Steering 29 to 32 - Reserved*	R/W

APPENDIX A: REGISTER NAME CHANGES FROM PREVIOUS RELEASE

This section provides a mapping of the register names used in this document against register names used in previous releases.

Rev B - Register Names	Rev A - Register Names
Reference Command Registers
Reference Frequency	Reference Frequency
Reference Voltage	Reference Voltage
Reference Reading Registers
Voltage Reading	Read Voltage
Current Reading	Read Current
Frequency Reading
Reference Control Registers
Current Limit
Channel Enable	Channel Enable
Reset Overcurrent	Reset Overcurrent
Unit Conversion Programming Registers
Enable Floating Point Mode
Floating Point State
Background BIT Threshold Programming Registers
Background BIT Threshold
Reset BIT
User Watchdog Timer Registers
Refer to “User Watchdog Timer Module Manual”
Status and Interrupt Registers
Channel Status Enabled
BIT Dynamic Status	BIT Dynamic Status
BIT Latched Status	BIT Latched Status
BIT Interrupt Enable	BIT Interrupt Enable
BIT Edge/Level Interrupt	BIT Edge/Level Select
Reference Channel Dynamic Status	Dynamic Interrupt Status
Reference Channel Latched Status	Latched Interrupt Status
Reference Channel Interrupt Enable
Reference Channel Edge/Level Interrupt	Set Edge/Level Interrupt
User Watchdog Timer Fault Dynamic Status
User Watchdog Timer Fault Latched Status
User Watchdog Timer Fault Interrupt Enable
User Watchdog Timer Fault Edge/Level Interrupt
Summary Dynamic Status
Summary Latched Status
Summary Interrupt Enable
Summary Set Edge/Level Interrupt

APPENDIX B: PIN-OUT DETAILS

Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard Operational Manuals.

Module Signal (Ref Only)	44-Pin I/O	50-Pin I/O (Mod Slot 1-J3)	50-Pin I/O (Mod Slot 2-J4)	50-Pin I/O (Mod Slot 3-J3)	50-Pin I/O (Mod Slot 3-J4)	AC Ref (AC1-3)
DATIO1	2	10	1	2		RHI-SNS-CH1
DATIO2	24	35	26	27		RLO-SNS-CH1
DATIO3	3	11	2	3		N/C
DATIO4	25	36	27	28		N/C
DATIO5	5	13	4	5		RHI-OUT-CH1
DATIO6	27	38	29	30		RLO-OUT-CH1
DATIO7	7	14	5	6		N/C
DATIO8	29	39	30	31		N/C
DATIO9	8	15	6	7		N/C
DATIO10	30	40	31	32		N/C
DATIO11	10	17	8	9		N/C
DATIO12	32	42	33	34		N/C
DATIO13	12	18	9		17	N/C
DATIO14	34	43	34		42	N/C
DATIO15	13	19	10		18	N/C
DATIO16	35	44	35		43	N/C
DATIO17	15	21	12		20	N/C
DATIO18	37	46	37		45	N/C
DATIO19	17	22	13		21	RHI-SNS-CH2
DATIO20	39	47	38		46	RLO-SNS-CH2
DATIO21	23	14		22	18	N/C
DATIO22	40	48	39		47	N/C
DATIO23	20	25	16		24	RHI-OUT-CH2
DATIO24	42	50	41		49	RLO-OUT-CH2
DATIO25	4	12	3	4		N/C
DATIO26	26	37	28	29		N/C
DATIO27	9	16	7	8		N/C
DATIO28	31	41	32	33		N/C
DATIO29	14	20	11		19	N/C
DATIO30	36	45	36		44	N/C
DATIO31	19	24	15		23	N/C
DATIO32	41	49	40		48	N/C
DATIO33	6
DATIO34	28
DATIO35	11
DATIO36	33
DATIO37	16
DATIO38	38
DATIO39	21
DATIO40	43
N/A

AC REFERENCE MODULE HARDWARE BLOCK DIAGRAM

AC REFERENCE MODULE PROCESSING BLOCK DIAGRAM

FIRMWARE REVISION NOTES

This section identifies lists the firmware revision in which specific features were released. Prior revisions of the firmware would not support the features listed.

Feature	FPGA		Bare Metal (BM)
	Firmware Revision	Release Date	Firmware Revision	Release Date
Unit Conversions	3.00006	1/17/2020 11:01:38 AM	1.6	Jan 09 2020 at 15:29:59
Background BIT Threshold Programming	3.00006	1/17/2020 11:01:38 AM	1.6	Jan 09 2020 at 15:29:59
User Watchdog Timer Capability	3.00006	1/17/2020 11:01:38 AM	1.6	Jan 09 2020 at 15:29:59
Channel Status Enabled	3.00006	1/17/2020 11:01:38 AM	1.6	Jan 09 2020 at 15:29:59
Summary Status	3.00006	1/17/2020 11:01:38 AM	1.6	Jan 09 2020 at 15:29:59

STATUS AND INTERRUPTS

Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.

For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.

Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.

Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).

Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.

Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).

Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edge-triggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.

Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Interrupt Trigger Types

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

Dynamic and Latched Status Registers Examples

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

No Clearing of Latched Status Clearing of Latched Status (Edge-Triggered) Clearing of Latched Status(Level-Triggered)
Time Dynamic Status Latched Status Action Latched Status Action Latched
T0 0x0 0x0 Read Latched Register 0x0 Read Latched Register 0x0
T1 0x1 0x1 Read Latched Register 0x1 0x1
T1 0x1 0x1 Write 0x1 to Latched Register Write 0x1 to Latched Register
T1 0x1 0x1 0x0 0x1
T2 0x0 0x1 Read Latched Register 0x0 Read Latched Register 0x1
T2 0x0 0x1 Read Latched Register 0x0 Write 0x1 to Latched Register
T2 0x0 0x1 Read Latched Register 0x0 0x0
T3 0x2 0x3 Read Latched Register 0x2 Read Latched Register 0x2
T3 0x2 0x3 Write 0x2 to Latched Register Write 0x2 to Latched Register
T3 0x2 0x3 0x0 0x2
T4 0x2 0x3 Read Latched Register 0x1 Read Latched Register 0x3
T4 0x2 0x3 Write 0x1 to Latched Register Write 0x3 to Latched Register
T4 0x2 0x3 0x0 0x2
T5 0xC 0xF Read Latched Register 0xC Read Latched Register 0xE
T5 0xC 0xF Write 0xC to Latched Register Write 0xE to Latched Register
T5 0xC 0xF 0x0 0xC
T6 0xC 0xF Read Latched Register 0x0 Read Latched 0xC
T6 0xC 0xF Read Latched Register 0x0 Write 0xC to Latched Register
T6 0xC 0xF Read Latched Register 0x0 0xC
T7 0x4 0xF Read Latched Register 0x0 Read Latched Register 0xC
T7 0x4 0xF Read Latched Register 0x0 Write 0xC to Latched Register
T7 0x4 0xF Read Latched Register 0x0 0x4
T8 0x4 0xF Read Latched Register 0x0 Read Latched Register 0x4

Interrupt Examples

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

Time Latched Status (Edge-Triggered - Clear Multi-Channel) Latched Status (Edge-Triggered - Clear Single Channel) 2+ Latched Status (Level-Triggered - Clear Multi-Channel) Action
Latched Action Latched Action Latched T1 (Int 1)
Interrupt Generated++``+
Read Latched Registers 0x1 Interrupt Generated++``+
Read Latched Registers 0x1 Interrupt Generated++``+
Read Latched Registers 0x1 T1 (Int 1)
Write 0x1 to Latched Register Write 0x1 to Latched Register Write 0x1 to Latched Register T1 (Int 1)
0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T2. 0x1 T3 (Int 2)
Interrupt Generated++``+
Read Latched Registers 0x2 Interrupt Generated++``+
Read Latched Registers 0x2 Interrupt Generated++``+
Read Latched Registers 0x2 T3 (Int 2)
Write 0x2 to Latched Register Write 0x2 to Latched Register Write 0x2 to Latched Register T3 (Int 2)
0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T7. 0x2 T4 (Int 3)
Interrupt Generated++``+
Read Latched Registers 0x1 Interrupt Generated++``+
Read Latched Registers 0x1 Interrupt Generated++``+
Read Latched Registers 0x3 T4 (Int 3)
Write 0x1 to Latched Register Write 0x1 to Latched Register Write 0x3 to Latched Register T4 (Int 3)
0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5. 0x3 T4 (Int 3)
0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear until T7. 0x2 T6 (Int 4)
Interrupt Generated++``+
Read Latched Registers 0xC Interrupt Generated++``+
Read Latched Registers 0xC Interrupt Generated++``+
Read Latched Registers 0xE T6 (Int 4)
Write 0xC to Latched Register Write 0x4 to Latched Register Write 0xE to Latched Register T6 (Int 4)
0x0 Interrupt re-triggers++``+
Write 0x8 to Latched Register 0x8 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7. 0xE T6 (Int 4)
0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8. 0xC T6 (Int 4)
0x0 0x0 Interrupt re-triggers++``+
Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always. 0x4

REVISION HISTORY

Motherboard Manual - Status and Interrupts Revision History
Revision Revision Date Description
C 2021-11-30 C08896; Transition manual to docbuilder format - no technical info change.

DOCS.NAII REVISIONS

Revision Date Description
2026-03-02 Formatting updates to document; no technical changes.
Link to original

USER WATCHDOG TIMER MODULE MANUAL

User Watchdog Timer Capability

The User Watchdog Timer (UWDT) Capability is available on the following modules:

AC Reference Source Modules

AC1 - 1 Channel, 2-115 Vrms, 47 Hz - 20kHz

AC2 - 2 Channels, 2-28 Vrms, 47 Hz - 20kHz

AC3 - 1 Channel, 28-115 Vrms, 47 Hz - 2.5 kHz

Differential Transceiver Modules

DF1/DF2 - 16 Channels Differential I/O

Digital-to-Analog (D/A) Modules

DA1 - 12 Channels, ±10 VDC @ 25 mA, Voltage or Current Control Modes

DA2 - 16 Channels, ±10 VDC @ 10 mA

DA3 - 4 Channels, ±40 VDC @ ±100 mA, Voltage or Current Control Modes

DA4 - 4 Channels, ±80 VDC @ 10 mA

DA5 - 4 Channels, ±65 VDC or ±2 A, Voltage or Current Control Modes

Digital-to-Synchro/Resolver (D/S) or Digital-to-L( R )VDT (D/LV) Modules

(Not supported)

Discrete I/O Modules

DT1/DT4 - 24 Channels, Programmable for either input or output, output up to 500 mA per channel from an applied external 3 - 60 VCC source.

DT2/DT5 - 16 Channels, Programmable for either input voltage measurements (±80 V) or as a bi-directional current switch (up to 500 mA per channel).

DT3/DT6 - 4 Channels, Programmable for either input voltage measurements (±100 V) or as a bi-directional current switch (up to 3 A per channel).

TTL/CMOS Modules

TL1-TL8 - 24 Channels, Programmable for either input or output.

Principle of Operation

The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.

The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:

The application must not strobe during the Quiet time.

The application must strobe within the Window time.

The application must not strobe more than once in a single window time.

A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.

The Figure 1 and Figure 2 provides an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.

The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.

Figure 1. User Watchdog Timer Overview

Figure 2. User Watchdog Timer Example

Figure 3. User Watchdog Timer Failures

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

User Watchdog Timer Registers

The registers associated with the User Watchdog Timer provide the ability to specify the UWDT Quiet Time and the UWDT Window that will be monitored to ensure that EXACTLY ONE User Watchdog Timer (UWDT) Strobe is written within the window.

UWDT Quiet Time
Function: Sets Quiet Time value (in microseconds) to use for the User Watchdog Timer Frame.
Type: unsigned binary word (32-bit)
Data Range: 0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write: R/W
Initialized Value: 0x0
Operational Settings: LSB = 1 µsec. The application must NOT write a strobe in the time between the previous strobe and the end of the Quiet time interval. In addition, the application must write in the UWDT Window EXACTLY ONCE.
UWDT Window
Function: Writes the window value (in microseconds) to be used for the User Watchdog Timer Frame.
Type: unsigned binary word (32-bit)
Data Range: 0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write: R/W
Initialized Value: 0x0
Operational Settings: LSB = 1 µsec. The application must write the strobe once within the Window time after the end of the Quiet time interval. The application must write in the UWDT Window EXACTLY ONCE. This setting must be initialized to a non-zero value for operation and should allow sufficient tolerance for strobe timing by the application.
UWDT Strobe
Function: Writes the strobe value to be use for the User Watchdog Timer Frame.
Type: unsigned binary word (32-bit)
Data Range: 0x55AA
Read/Write: W
Initialized Value: 0x0
Operational Settings: At startup, the user watchdog is disabled. Write the value of 0x55AA to this register to start the user watchdog timer monitoring after initial power on or a reset. To prevent a disablement, the application must periodically write the strobe based on the user watchdog timer rules.

Status and Interrupt

The modules that are capable of User Watchdog Timer support provide status registers for the User Watchdog Timer.

User Watchdog Timer Status

The status register that contains the User Watchdog Timer Fault information is also used to indicate channel Inter-FPGA failures on modules that have communication between FPGA components. There are four registers associated with the User Watchdog Timer Fault/Inter-FPGA Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Function: Sets the corresponding bit (D31) associated with the channel’s User Watchdog Timer Fault error.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value: 0

User Watchdog Timer Fault/Inter-FPGA Failure Dynamic Status
User Watchdog Timer Fault/Inter-FPGA Failure Latched Status
User Watchdog Timer Fault/Inter-FPGA Failure Interrupt Enable
User Watchdog Timer Fault/Inter-FPGA Failure Set Edge/Level Interrupt
Bit(s) Status Description
D31 User Watchdog Timer Fault Status 0 = No Fault + 1 = User Watchdog Timer Fault
D30:D0 Reserved for Inter-FPGA Failure Status Channel bit-mapped indicating channel inter FPGA communication failure detection.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.

In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note

the Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector
Function: Set an identifier for the interrupt.
Type: unsigned binary word (32-bit)
Data Range: 0 to 0xFFFF FFFF
Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function: Sets where to direct the interrupt.
Type: unsigned binary word (32-bit)
Data Range: See table
Read/Write: R/W
Initialized Value: 0
Operational Settings: When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME 1
Direct Interrupt to ARM Processor (via SerDes)
(Custom App on ARM or NAI Ethernet Listener App) 2
Direct Interrupt to PCIe Bus 5
Direct Interrupt to cPCI Bus 6

Function Register Map

KEY

Configuration/Control
Measurement/Status

USER WATCHDOG TIMER REGISTERS
OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS
0x01C0 UWDT Quiet Time R/W
0x01C4 UWDT Window R/W
0x01C8 UWDT Strobe R/W
STATUS REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0”).
OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS
0x09B0 Dynamic Status R
0x09B4 Latched Status* R/W
0x09B8 Interrupt Enable R/W
0x09BC Set Edge/Level Interrupt R/W
INTERRUPT REGISTERS
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.
OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS
0x056C Module 1 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x066C Module 1 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W
0x076C Module 2 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x086C Module 2 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W
0x096C Module 3 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x0A6C Module 3 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W
0x0B6C Module 4 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x0C6C Module 4 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W
0x0D6C Module 5 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x0E6C Module 5 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W
0x0F6C Module 6 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W 0x106C Module 6 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure R/W

REVISION HISTORY

Motherboard Manual - Status and Interrupts Revision History
Revision Revision Date Description
C 2021-11-30 C08896; Transition manual to docbuilder format - no technical info change.

DOCS.NAII REVISIONS

Revision Date Description
2026-03-02 Formatting updates to document; no technical changes.
Link to original

MODULE COMMON REGISTERS

The registers described in this document are common to all NAI Generation 5 modules.

Module Information Registers

The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.

FPGA Version Registers

The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.

FPGA Revision
Function: FPGA firmware revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the revision of the board's FPGA
Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Major Revision Number
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Minor Revision Number

FPGA Compile Timestamp
Function: Compile Timestamp for the FPGA firmware.
Type: unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Value corresponding to the compile timestamp of the board's FPGA
Operational Settings: The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
day (5-bits) month (4-bits) year (6-bits) hr
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
hour (5-bits) minutes (6-bits) seconds (6-bits)

FPGA SerDes Revision
Function: FPGA SerDes revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the SerDes revision of the board's FPGA
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Major Revision Number
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Minor Revision Number

FPGA Template Revision
Function: FPGA Template revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the template revision of the board's FPGA
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Major Revision Number
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Minor Revision Number

FPGA Zynq Block Revision
Function: FPGA Zynq Block revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Zynq block revision of the board's FPGA
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Major Revision Number
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Minor Revision Number

Bare Metal Version Registers

The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.

Bare Metal Revision
Function: Bare Metal firmware revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the revision of the board's Bare Metal
Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Major Revision Number
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Minor Revision Number

Bare Metal Compile Time
Function: Provides an ASCII representation of the Date/Time for the Bare Metal compile time.
Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Value corresponding to the ASCII representation of the compile time of the board's Bare Metal
Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Note

little-endian order of ASCII values

Word 1 (Ex. 0x2079614D)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Space (0x20) Month ('y' - 0x79)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Month ('a' - 0x61) Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Year ('2' - 0x32) Space (0x20)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Day ('7' - 0x37) Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Space (0x20) Year ('9' - 0x39)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Year ('1' - 0x31) Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Hour ('1' - 0x31) Space (0x20)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
'a' (0x74) 't' (0x61)
Word 5 (Ex. 0x38333A35)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Minute ('8' - 0x38) Minute ('3' - 0x33)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
':' (0x3A) Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
NULL (0x00) Seconds ('2' - 0x32)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Seconds ('3' - 0x33) ':' (0x3A)

FSBL Version Registers

The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).

FSBL Revision
Function: FSBL firmware revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the revision of the board's FSBL
Operational Settings: The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Major Revision Number
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Minor Revision Number

FSBL Compile Time
Function: Provides an ASCII representation of the Date/Time for the FSBL compile time.
Type: 24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Value corresponding to the ASCII representation of the Compile Time of the board's FSBL
Operational Settings: The six 32-bit words provide an ASCII representation of the Date/Time.

The hexadecimal values in the field below represent: May 17 2019 at 15:38:32

Note

little-endian order of ASCII values

Word 1 (Ex. 0x2079614D)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Space (0x20) Month ('y' - 0x79)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Month ('a' - 0x61) Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Year ('2' - 0x32) Space (0x20)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Day ('7' - 0x37) Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Space (0x20) Year ('9' - 0x39)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Year ('1' - 0x31) Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Hour ('1' - 0x31) Space (0x20)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
'a' (0x74) 't' (0x61)
Word 5 (Ex. 0x38333A35)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Minute ('8' - 0x38) Minute ('3' - 0x33)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
':' (0x3A) Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
NULL (0x00) Seconds ('2' - 0x32)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Seconds ('3' - 0x33) ':' (0x3A)

Module Serial Number Registers

The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.

Interface Board Serial Number
Function: Unique 128-bit identifier used to identify the interface board.
Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Serial number of the interface board
Operational Settings: This register is for information purposes only.

Functional Board Serial Number
Function: Unique 128-bit identifier used to identify the functional board.
Type: 16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range: N/A
Read/Write: R
Initialized Value: Serial number of the functional board
Operational Settings: This register is for information purposes only.

Module Capability
Function: Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0x0000 0107
Read/Write: R
Initialized Value: 0x0000 0107
Operational Settings: A “1” in the bit associated with the capability indicates that it is supported.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 Flt-Pt 0 0 0 0 0 Pack FIFO Blk Blk

Module Memory Map Revision
Function: Module Memory Map revision
Type: unsigned binary word (32-bit)
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Value corresponding to the Module Memory Map Revision
Operational Settings: The upper 16-bits are the major revision and the lower 16-bits are the minor revision.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Major Revision Number
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Minor Revision Number

Module Measurement Registers

The registers in this section provide module temperature measurement information.

Temperature Readings Registers

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.

Interface Board Current Temperature
Function: Measured PCB and Zynq Core temperatures on Interface Board.
Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB and Zynq core temperatures based on the table below
Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PCB Temperature Zynq Core Temperature

Functional Board Current Temperature
Function: Measured PCB temperature on Functional Board.
Type: signed byte (8-bits) for PCB
Data Range: 0x0000 0000 to 0x0000 00FF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB on the table below
Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 PCB Temperature

Interface Board Maximum Temperature
Function: Maximum PCB and Zynq Core temperatures on Interface Board since power-on.
Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PCB Temperature Zynq Core Temperature

Interface Board Minimum Temperature
Function: Minimum PCB and Zynq Core temperatures on Interface Board since power-on.
Type: signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range: 0x0000 0000 to 0x0000 FFFF
Read/Write: R
Initialized Value: Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings: The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PCB Temperature Zynq Core Temperature

Functional Board Maximum Temperature
Function: Maximum PCB temperature on Functional Board since power-on.
Type: signed byte (8-bits) for PCB
Data Range: 0x0000 0000 to 0x0000 00FF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB on the table below
Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 PCB Temperature

Functional Board Minimum Temperature
Function: Minimum PCB temperature on Functional Board since power-on.
Type: signed byte (8-bits) for PCB
Data Range: 0x0000 0000 to 0x0000 00FF
Read/Write: R
Initialized Value: Value corresponding to the measured PCB on the table below
Operational Settings: The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 PCB Temperature

Higher Precision Temperature Readings Registers

These registers provide higher precision readings of the current Zynq and PCB temperatures.

Higher Precision Zynq Core Temperature
Function: Higher precision measured Zynq Core temperature on Interface Board.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Zynq Core temperature on Interface Board
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Signed Integer Part of Temperature
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Fractional Part of Temperature

Higher Precision Interface PCB Temperature
Function: Higher precision measured Interface PCB temperature.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Interface PCB temperature
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Signed Integer Part of Temperature
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Fractional Part of Temperature

Higher Precision Functional PCB Temperature
Function: Higher precision measured Functional PCB temperature.
Type: signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range: 0x0000 0000 to 0xFFFF FFFF
Read/Write: R
Initialized Value: Measured Functional PCB temperature
Operational Settings: The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
Signed Integer Part of Temperature
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Fractional Part of Temperature

Module Health Monitoring Registers

The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.

Module Sensor Summary Status
Function: The corresponding sensor bit is set if the sensor has crossed any of its thresholds.
Type: unsigned binary word (32-bits)
Data Range: See table below
Read/Write: R
Initialized Value: 0
Operational Settings: This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.

Bit(s) Sensor
D31:D6 Reserved
D5 Functional Board PCB Temperature
D4 Interface Board PCB Temperature
D3:D0 Reserved

Module Sensor Registers

The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.

Sensor Threshold Status
Function: Reflects which threshold has been crossed
Type: unsigned binary word (32-bits)
Data Range: See table below
Read/Write: R
Initialized Value: 0
Operational Settings: The associated bit is set when the sensor reading exceed the corresponding threshold settings.

Bit(s) Description
D31:D4 Reserved
D3 Exceeded Upper Critical Threshold
D2 Exceeded Upper Warning Threshold
D1 Exceeded Lower Critical Threshold
D0 Exceeded Lower Warning Threshold

Sensor Current Reading
Function: Reflects current reading of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Minimum Reading
Function: Reflects minimum value of temperature sensor since power up
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Maximum Reading
Function: Reflects maximum value of temperature sensor since power up
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R
Initialized Value: N/A
Operational Settings: The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Lower Warning Threshold
Function: Reflects lower warning threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default lower warning threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.

Sensor Lower Critical Threshold
Function: Reflects lower critical threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default lower critical threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.

Sensor Upper Warning Threshold
Function: Reflects upper warning threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default upper warning threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.

Sensor Upper Critical Threshold
Function: Reflects upper critical threshold of temperature sensor
Type: Single Precision Floating Point Value (IEEE-754)
Data Range: Single Precision Floating Point Value (IEEE-754)
Read/Write: R/W
Initialized Value: Default upper critical threshold (value dependent on specific sensor)
Operational Settings: The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.

FUNCTION REGISTER MAP

KEY

Configuration/Control
Measurement/Status/Board Information

MODULE INFORMATION REGISTERS
OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS
0x003C FPGA Revision R 0x0074 Bare Metal Revision R
0x0030 FPGA Compile Timestamp R 0x0080 Bare Metal Compile Time (Bit 0-31) R
0x0034 FPGA SerDes Revision R 0x0084 Bare Metal Compile Time (Bit 32-63) R
0x0038 FPGA Template Revision R 0x0088 Bare Metal Compile Time (Bit 64-95) R
0x0040 FPGA Zynq Block Revision R 0x008C Bare Metal Compile Time (Bit 96-127) R
0x0090 Bare Metal Compile Time (Bit 128-159) R
0x0094 Bare Metal Compile Time (Bit 160-191) R
0x007C FSBL Revision R
0x00B0 FSBL Compile Time (Bit 0-31) R
0x00B4 FSBL Compile Time (Bit 32-63) R
0x00B8 FSBL Compile Time (Bit 64-95) R
0x00BC FSBL Compile Time (Bit 96-127) R
0x00C0 FSBL Compile Time (Bit 128-159) R
0x00C4 FSBL Compile Time (Bit 160-191) R
0x0000 Interface Board Serial Number (Bit 0-31) R 0x0010 Functional Board Serial Number (Bit 0-31) R
0x0034 Interface Board Serial Number (Bit 32-63) R 0x0014 Functional Board Serial Number (Bit 32-63) R
0x0008 Interface Board Serial Number (Bit 64-95) R 0x0018 Functional Board Serial Number (Bit 64-95) R
0x000C Interface Board Serial Number (Bit 96-127) R 0x001C Functional Board Serial Number (Bit 96-127) R
0x0070 Module Capability R
0x01FC Module Memory Map Revision R
MODULE MEASUREMENTS REGISTERS
OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS
0x0200 Interface Board PCB/Zynq Current Temp R 0x0208 Functional Board PCB Current Temp R
0x0218 Interface Board PCB/Zynq Max Temp R 0x0228 Functional Board PCB Max Temp R
0x0220 Interface Board PCB/Zynq Min Temp R 0x0230 Functional Board PCB Min Temp R
0x02C0 Higher Precision Zynq Core Temperature R
0x02C4 Higher Precision Interface PCB Temperature R
0x02E0 Higher Precision Functional PCB Temperature R
MODULE HEALTH MONITORING REGISTERS
OFFSET REGISTER NAME ACCESS OFFSET REGISTER NAME ACCESS
0x07F8 Module Sensor Summary Status R
![](/_shared/images/Module_Sensor_Registers_Memory_Map.png)

REVISION HISTORY

Motherboard Manual - Module Common Registers Revision History
Revision Revision Date Description
C 2023-08-11 ECO C10649, initial release of module common registers manual.
C1 2024-05-15 ECO C11522, removed Zynq Core/Aux/DDR Voltage register descriptions from Module Measurement Registers. Pg.16, updated Module Sensor Summary Status register to add PS references; updated Bit Table to change voltage/current bits to 'reserved'. Pg.16, updated Module/Power Supply Sensor Registers description to better describe register functionality and to add figure. Pg.17, added 'Exceeded' to threshold bit descriptions. Pg.17-18, removed voltage/current references from sensor descriptions. Pg.20, removed Zynq Core/Aux/DDR Voltage register offsets from Module Measurement Registers. Pg.20, updated Module Health Monitoring Registers offset tables.
C2 2024-07-10 ECO C11701, pg.16, updated Module Sensor Summary Status register to remove PS references;updated Bit Table to change PS temperature bits to 'reserved'. Pg.16, updated Module SensorRegisters description to remove PS references. Pg.20, updated Module Health MonitoringRegisters offset tables to remove PS temperature register offsets.

DOCS.NAII REVISIONS

Revision Date Description
2025-11-05 Corrected register offsets for Interface Board Min Temp and Function Board Min & Max Temps.
2026-03-02 Formatting updates to document; no technical changes.
Link to original

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Link to original

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
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D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
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D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
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D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
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D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

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D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
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D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
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D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

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D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
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D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

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NAI Documentation

Explorer

INTRODUCTION

FEATURES

SPECIFICATION

Voltage Output:

Accuracy (No Load):

Regulation:

Output Drive:

Protection:

Frequency:

Freq. Accuracy:

THD:

Power:

Ground:

Weight:

Specifications

PRINCIPLE OF OPERATION

Built-In Test (BIT)/Diagnostic Capability

Auto Gain Control and Voltage Out-of-Spec Detection

Frequency Out-of-Spec Detection

Overcurrent Detection

Background BIT Threshold Programming

Status and Interrupts

Module Common Registers

Unit Conversions

User Watchdog Timer Capability

REGISTER DESCRIPTIONS

Reference Command Registers

Reference Frequency

Reference Frequency (Enable Floating Point Mode: Integer Mode)

Reference Frequency (Enable Floating Point Mode: Floating Point Mode)

Reference Voltage

Reference Voltage (Enable Integer Mode: Integer Mode)

Reference Voltage (Enable Floating Point Mode: Floating Point Mode)

Reference Reading Registers

_Voltage Reading _

Voltage Reading (Enable Floating Point Mode: Integer Mode)

Voltage Reading (Enable Floating Point Mode: Floating Point Mode)

Current Reading

Current Reading (Enable Floating Point Mode: Integer Mode)

Current Reading (Enable Floating Point Mode: Floating Point Mode)

Frequency Reading

Frequency Reading (Enable Floating Point Mode: Integer Mode)

Frequency Reading (Enable Floating Point Mode: Floating Point Mode)

Reference Control Registers

Current Limit

Current Limit (Enable Floating Point Mode: Integer Mode)

Current Limit (Enable Floating Point Mode: Floating Point Mode)

_Channel Enable _

Channel Enable

Reset Overcurrent

Reset Overcurrent

Background BIT Threshold Programming Registers

Background BIT Threshold

Reset BIT

Reset BIT

Unit Conversion Programming Registers

Enable Floating Point Mode

Enable Floating Point Mode

Floating Point State

Floating Point State

User Watchdog Timer Registers

Module Common Registers

Status and Interrupt Registers

Channel Status Enabled

Channel Status Enabled

BIT Status

BIT Status

Reference Channel Status

Reference Channel Status

User Watchdog Timer Fault

Summary Status

Summary Status

Interrupt Vector and Steering

Interrupt Vector

Interrupt Steering*

FUNCTION REGISTER MAP

Reference Command Registers

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D