As a leading manufacturer of smart function modules, NAI offers over 100 different modules that cover a wide range of I/O, measurements and
simulation, communications, Ethernet switch, and SBC functions. Our serial communications smart function modules provide high-speed,
programmable RS-232/RS-422/RS-485, isolated or non-isolated, communication channels. Each channel has one transmit and one receive signal
pair (±) as applicable. This user manual is designed to help you get the most out of our serial communications smart function module.
For a brief description of the module and complete list of specifications, click here for the SC3 data sheet.
Note
Manual revision B2 marked the introduction of the SC3 product update to include the additional synchronous (SYNC) mode functionality.
The SC3 SYNC mode and function capability is available for products identified with DOM > 1/2020, Mod-HW ≥ Rev. B and FPGA/Firmware ≥
Rev. 00001.00003.
SC3 Overview
NAI’s SC3 module offers a range of features designed to suit a variety of system requirements, including:
Eight Communication Channels: The SC3 module offers eight high-speed, programmable communication channels supporting RS232, RS-422, and RS-485 protocols. These channels can be configured as eight asynchronous (async) channels or four synchronous (sync) channels. In Sync Mode, the
module can set up clock signals (clk) on the companion pair channels (CH1-CH4 clk companion channels are CH5-CH8)
General Purpose Input/Output (GPIO): The SC3 module includes General Purpose Input/Output (GPIO) functionality, enhancing its versatility.
Data Transfer Efficiency: For asynchronous communications, data transfers occur within just two baud clocks, ensuring rapid data exchange. Synchronous
communications achieve efficient data transfers in as little as 15 baud clocks.
Digital Noise Filtering: The SC3 module features digital noise filtering on receivers, enhancing signal quality and reliability.
Receiver Control: Users can selectively enable or disable specific receivers, providing fine-grained control over the communication channels.
Interrupt-Driven Operation: The SC3 module can operate in an Interrupt-Driven environment, delivering notifications of all events to the system. When flow control mode is selected, the module handles operations automatically with minimal system intervention, streamlining the communication process.
Buffer Capacity: The module boasts 1MBx16 receive and transmit buffers, ensuring ample storage for data transfer.
Built-in Test: The SC3 module comes with a built-in test feature, simplifying diagnostics and maintenance.
PRINCIPLE OF OPERATION
Each channel of the module can be individually software configured for RS-232C, RS-422 or RS-485 Asynchronous/Synchronous Serial
Communications or GPIO. See table below for more specific pinouts between modes. The architecture avoids latency problems because all data
transfer is done in hardware and not in software. Any incoming data, no matter how many channels are active, in whatever mode, can be
immediately extracted. FPGA design simplifies programming and usage.
-
RS232
RS232 GPIO
RS232 HW Flow
RS422/485
RS422/485 GPIO
RS422/485 HW Flow
RS422/485 Sync
RxDLo - 1
RXD - 1
GPI2 - 1
RXD - 1
RXDLO - 1
GPI-LO - 1
RXDLO - 1
RXDLO - 1
RxDHi - 1
n/a
GPI1 - 1
CTS - 1
RXDHI - 1
GPI-HI - 1
RXDHI - 1
RXDHI - 1
TxDLo -1
TXD - 1
GPO2 - 1
TXD - 1
TXDLO - 1
GPO-LO - 1
TXDLO - 1
TXDLO - 1
TxDHi - 1
n/a
GPO1 - 1
RTS - 1
TXDHI - 1
GPO-HI - 1
TXDHI - 1
TXDHI - 1
...
RxDLo - 5
RXD - 5
GPI2 - 5
RXD - 5
RXDLO - 5
GPI-LO - 5
CTSLO - 1
CLKINLO - 1
RxDHi - 5
n/a
GPI2 - 5
CTS - 5
RXDHI - 5
GPI-HI - 5
CTSHI - 1
CLKINHI - 1
TxDLo - 5
TXD - 5
GPO2 - 5
TXD - 5
TXDLO - 5
GPO-LO - 5
RTSLO - 1
CLKOUTLO - 1
TxDHi - 5
n/a
GPO5 - 5
RTS - 5
TXDHI - 5
GPO-HI - 5
RTSHI - 1
CLKOUTHI - 1
...
Configuration
Before the user can write to any configuration register, certain steps must be followed to ensure the module accepts the user specified
configuration. The steps are as follows:
Write a 0 to the Enable Channel bit of the Tx-Rx Configuration register to tell the hardware that we are about to change the configuration.
Wait for the Channel Configured status of the Realtime Channel Status registers to read a 0.
Write all desired configuration registers.
Set the Enable Channel bit of the Tx-Rx Configuration register to 1 to notify the hardware that it can read all the configuration registers.
Wait for the Channel Configured status in the Realtime Channel Status register to read a 1 before proceeding to send/receive data.
Async/Sync Modes
All eight channels can be configured in asynchronous mode or the first four channels can be configured for synchronous modes. Mixing
asynchronous and synchronous modes is also possible.
Sync Mode Channel Pairs
The user can configure any of the first four channel sof the SC3 to operate in any of the following synchronous modes: HDLC, Mono-Synchronous
or Bi-Synchronous. When any of these channels are configured for a synchronous mode, the channel will need to pair with another channel to
make sue of its transmitter and receiver to handle clock input and output signals. Channel pairs are as follows: 1&5, 2&6, 3&7, 4&8.
Hardware Flow Control
The user can configure any of the first four channel sof the SC3 to operate in hardware flow control mode by setting the RTS/CTS Flow Control bit
of the Tx-Rx Configuration register to a 1. When a channel is configured in this mode, the channel pair’s transmitter and receiver will be used for
the Request to Send (RTS) and Clear to Send (CTS) signals. The channels pairs are the same as in sync mode.
GPIO Mode
The SC3 is configured for GPIO mode via the Interface Levels register. Setting the GPIO bit to 1, sets a channel to GPIO mode. It is also
necessary to choose either RS-232 or RS-422 to determine the GPIO signal level.
Note
As shown in the table on page 7, single ended RS-232 provides GPI 1, GPI 2, GPO1 and GPO 2. RS-422 provides GPI 1 and GPO 1 only.
To set an output (GPO) channel to a high state, set the Channel Control register RTS/GPO 1 or GPO 2 bits, to 1. The default is 0 (low). Inputs
(GPI) are monitored by the Dynamic Status register, bits CTS/GPI 1 and GPI 2, which provide real-time status monitoring of the GPI inputs. The
Latched Status register, bits CTS/GPI 1 and GPI 2, latch when an input is received and are cleared when a 1 is written to the register. The
Interrupt Enable register bits CTS/GPI 1 and GPI 2 when set to a 1, will create an interrupt. To invert the GPI/GPO inputs and outputs, set the Tx-Rx Configuration register bits Invert CTS (GPI) and Invert RTS (GPO), to 1. See the Register Descriptions for more information.
Gap Timeout Status
The Gap Timeout Occurred status gets set when there’s data in a channel’s receive buffer but there’s no activity on a channel’s receiver for
approximately three byte-times. To use the Gap Timeout feature, set the Enable Gap Timeout bit in the Tx-Rx Configuration register to a 1. When
receiving asynchronous data, monitor the Gap Timeout status bit of the Channel Status register to know if a timeout occurred. The status is
cleared after all the data in the receive buffer is read or cleared.
Serial Built-In Test/Diagnostic Capability
The SC3 module supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are logically
ORed together and stored in the BIT Dynamic Status and BIT Latched Status registers.
Power-on Self-Test (POST)/Power-on BIT (PBIT)/Start-up BIT (SBIT)
The power-on self-test is performed on each channel automatically when power is applied and report the results in the BIT Status register when
complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before
reading the BIT Dynamic Status and BIT Latched Status registers.
Continuous Background Built-In Test
The background Built-In-Test (BIT) or Continuous BIT (CBIT) runs in the background for each enabled channel. It monitors the transmit and
receive lines using dedicated hardware to detect any differences in the levels. When in synchronous mode the clock lines are monitored for a
clock presence. The technique used by the automatic background BIT test consists of an “add-2, subtract-1” counting scheme. The BIT counter is
incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0.
When the BIT counter exceeds the threshold value, the specific channel’s fault bit in the BIT status register will be set, the internal threshold can
be scaled via the Background BIT Threshold register. Note, the interval at which BIT is performed is dependent and differs between module types.
The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT
fault status or indication is flagged (e.g. BIT faults would register when sustained; i.e. at a ten second interval, not a 10-millisecond interval). This
prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on
errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates”
between a pass and fail state. Results of the Continuous BIT are stored in the BIT Dynamic Status and BIT Latched Status register.
Initiated Built-In Test
The Initiated Built-In-Test (IBIT) is an internal loopback available for each channel of the SC3 module. The test is initiated by setting the bit for the
associated channel in the Test Enabled register or (for legacy applications) setting the Initiate BIT bit of the Tx-Rx-Configuration register to a 1.
Prior to initiating the test, the user must disable the channel, and its respective pair, by writing a 0 to the Enable Channel bit of the channel’s Tx-Rx Configuration register. BIT will not run if the channel is enabled. After the user disables the channel and initiates BIT, they must wait a
minimum of 5 msec then check to see if the bit for the associated channel in the Test Enabled register or (for legacy application) Initiate BIT bit of
the Tx-Rx-Configuration register reads a 0. When the SC3 clears the bit, it means that the test has completed, and its results can be checked. If
the bit has not cleared after 10ms, the test has timed out and not run. In the event this should occur, the user should verify that the channel, and
its pair, has been disabled. The results of the IBIT is stored in the BIT Dynamic Status and BIT Latched Status registers, a 0 indicates that the
channel has passed and a 1 indicates that it failed.
Receiver Enable/Disable
A Receiver Enable/Disable function allows the user to turn selected receivers ON/OFF. When a receiver is disabled, no data will be placed in the
buffer.
Serial Data Transmit Enhancement
An additional asynchronous mode to support “Immediate Transmit” operation has been incorporated. This mode immediately transmits serial data
anytime the transmit buffer is not empty. There is no requirement to set the Tx Initiate bit before each transmission, which simplifies system traffic and overhead, since only the actual data byte being transmitted needs be sent to the transmit buffer. Each channel has its own configurable
Transmit and Receive buffer. The upper byte of each received word provides status information for that word.
Multi-Drop Link Mode (RS485)
The transmitter and receivers of up to 32 channels can be tied together in either Half or Full-Duplex mode. While in Multi-Drop Link Mode, the
transmit line for each channel will automatically tri-state. When data in the transmit buffer is initiated, the transmitter will be taken out of tri-state and send the data. Once transmission is completed, the transmit line is automatically changed back to tri-state mode.
To program the serial channel for Multi-Drop mode, the interface level must be set to RS485, and the Tristate Transmit Line bit in the Channel
Control register must be set to a 1.
Communication Module Factory Defaults: Registers and Delays
Address Recognition:
Off
Baud Rate:
9600
CTS/RTS:
Disabled
Protocol:
0, Asynchronous
Interface Levels:
5 (Tri-state mode)
Termination Character:
0x0003h
Interrupt Level:
0
Interrupt Vector:
0x00
Mode:
Asynchronous
Number of Data Bits:
8
Parity:
Disabled
Receivers:
Disabled
Transmit Buffer Word Count:
0
Receive Buffer Word Count:
0
Receive Buffer, Almost Full:
0xFFF9B
Stop Bits:
1
Transmit Buffer, Almost Empty:
0x0064
Tx-Rx Configuration:
0
Channel Control:
0
Data Configuration:
0x0108
Preamble:
0
Receive Buffer High Watermark:
0xFFF9B
Receive Buffer Low Watermark:
0x0800h
XON:
0x0011h
XOFF:
0x0013h
XON/XOFF:
Disabled
Time Out Value:
0x9C40
A write to the following registers takes place immediately:
Transmit Data
Channel Control
Channel Interrupt Enable
Channel Interrupt Edge/Level
Summary Interrupt Enable
Summary Edge/Level
Interrupt Vector
Interrupt Steering
For all other registers, channel configuration protocol must be followed.
Status and Interrupts
The SC3 Serial Communications Function Module provide registers that indicate faults or events. Refer to “Status and Interrupts Module Manual”
for the Principle of Operation description.
Module Common Registers
The SC3 Serial Communications Function Module includes module common registers that provide access to module-level bare metal/FPGA
revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers
Module Manual” for the detailed information.
REGISTER DESCRIPTIONS
The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function
and, in most cases, a data table.
Receive Registers
Serial data received are placed in the Receive FIFO Buffer register. The Receive FIFO Buffer Word Count provide the count of the number of elements in the Receive FIFO Buffer. The Receive FIFO Buffer Almost Full, Receive FIFO Buffer High Watermark and Receive FIFO Buffer Low Watermark registers provide the ability to specify the thresholds for the associated status in the Channel FIFO Status register.
Receive FIFO Buffer
Function:
Received data is placed in this buffer.
Type:
unsigned binary word (32-bit).
Data Range:
0x 0000 0000 to 0x 0000 FFFF
Read/Write:
R
Initialized Value:
N/A
Operational Settings:
Data is received is based on Protocol.
Note
Receive FIFO Buffer is a self-clearing register. Performing a register read of the Receive FIFO marks the current location as ‘read’. This moves the pointer to the next unread location and decrements the Receive FIFO Buffer Word Count register count by one.
Asynchronous/Asynchronous-GPI
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PE
FE
0
0
0
EOF
P
D
D
D
D
D
D
D
D
D
Bi-Synchronous/Mono-Synchronous
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
EOF
0
D
D
D
D
D
D
D
D
HDLC
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
BOF
0
ER1
ER1
ER0
EOF
0
D
D
D
D
D
D
D
D
Asynchronous/Asynchronous-GPI
PE
= Parity Error
A 1 indicates the calculated parity does not match the received parity bit.
FE
= Framing Error
A 1 indicates a framing error was detected.
EOF
= End of Frame
A 1 indicates an ETx character was received. Termination Character Detection must be turned on.
P
= Parity Bit
This bit carries the parity bit of the last received character.
Bi-Synchronous/Mono-Synchronous
EOF
= End of Frame
A 1 indicates the End of Frame. Useful to identify multiple frames in large buffer.
HDLC
BOF
= Beginning of Frame
A 1 indicates first character of frame. Useful to identify multiple frames in large buffer.
EOF
= End of Frame
A 1 indicates End of Frame. Useful to identify multiple frames in large buffer.
ER2:ER0
= Last Frame Status
000 = Good Frame, 111 = CRC Error
Receive FIFO Buffer Word Count
Function:
Contains the number of words in the Receive FIFO Buffer waiting to be read back.
Type:
unsigned binary word (32-bits)
Data Range:
0 to 0x0010 0000 (Buffer Size)
Read/Write:
R
Initialized Value:
0
Operational Settings:
Reads Integers.
Receive FIFO Buffer Almost Full
Function:
Specifies the maximum size, in bytes, of the receive buffer before the Receive FIFO Almost Full Status bit D0 in the FIFO Status register is flagged (High True).
Type:
unsigned binary word (32-bits)
Data Range:
0 to 0x0010 0000 (Buffer Size)
Read/Write:
R/W
Initialized Value:
1048475 (0x000F FF9B)
Operational Settings:
If the interrupt is enabled (see Interrupt Enable register), a System interrupt will be generated.
Receive FIFO Buffer High Watermark
Function:
Defines the Receive Buffer High Watermark value.
Type:
unsigned binary word (32-bits)
Data Range:
Low Watermark < High Watermark < 0xFFF9B
Read/Write:
R/W
Initialized Value:
1048475 (0xFFF9B)
Operational Settings:
When Receive FIFO Buffer size equals the High Watermark value, the High Watermark bit in both the FIFO Status and Channel Status registers is set to a 1 and: If XON/XOFF is enabled, XOFF is sent, and/or If RTS/CTS is enabled, RTS goes inactive. The Watermark registers are used for XON/XOFF and/or RTS/CTS flow control. The Receive Buffer High Watermark register value controls when the XOFF character is sent when using software flow control and controls when the RTS signal would be negated when using hardware flow control. For software flow control operation, the XOFF character would be sent once when the number of bytes in the Receive FIFO Buffer equals the value in the Receive Buffer High Watermark register. Once the XOFF has been sent, it cannot be sent again until the XON character has been sent. The valid state transitions to sending the XOFF character can be either no previous XON/XOFF character sent or a previous XON character sent. There is also a High Watermark Reached interrupt enable/disable bit in the Channel Interrupt Enable register and a High Watermark Reached bit in the Channel Interrupt Status Register. When the High Watermark is reached, an interrupt request will be generated, when the interrupt enable/disable bit is enabled.
Receive FIFO Buffer Low Watermark
Function:
Defines the Receive Buffer Low Watermark value.
Type:
unsigned binary word (32-bits)
Data Range:
0 < Low Watermark < High Watermark < 0xFFF9B
Read/Write:
R/W
Initialized Value:
2048 (0x0800)
Operational Settings:
When Receive Buffer size equals the Low Watermark value, the Low Watermark bit in both the FIFO Status and Channel Status registers is set to a 1 and: If XON/XOFF is enabled, XON is sent, and/or If RTS/CTS is enabled, RTS goes active. The Watermark registers are used for XON/XOFF and/or RTS/CTS flow control. The Receive Buffer Low Watermark register value controls when the XON character is sent when using software flow control and controls when the RTS signal would be asserted when using hardware flow control. For software flow control operation, the XON character would be sent once when the number of bytes in the Receive FIFO Buffer equals the value in the Receive Buffer Low Watermark register AND an XOFF character has been sent prior to this XON character. The valid state transition to sending the XON character can only be from the state of a previous XOFF character that has been sent. There is a Low Watermark Reached interrupt enable/disable bit in the Channel Interrupt Enable register and a Low Watermark Reached bit in the Channel Interrupt Status Register. When the Low Watermark is reached, an interrupt request will be generated, when the interrupt enable/disable bit is enabled.
Transmit Registers
Serial data to be transmitted are placed in the Transmit FIFO Buffer register. The Transmit FIFO Buffer Word Count provides the count of the number of elements in the Transmit FIFO Buffer. The Receive FIFO Buffer Almost Empty register provide the ability to specify the threshold for the associated status in the Channel FIFO Status register.
Transmit FIFO Buffer
Function:
Data to be transmitted is placed in this buffer prior to transmission.
Type:
unsigned binary word (32-bits)
Data Range:
0x 0000 0000 to 0x 0000 01FF
Read/Write:
W
Initialized Value:
Not Applicable (NA)
Operational Settings:
Data words are 8-bit and occupy the register's lowest significant bits (LSBs), or low byte.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
D1
D
D
D
D
D
D
D
D
Note 1: Data only in Asynchronous mode when data bits are set to 9.
Transmit FIFO Buffer Word Count
Function:
Contains the number of words in the Transmit FIFO Buffer waiting to be transmitted.
Type:
unsigned binary word (32-bits)
Data Range:
0 to 0x0010 0000 (Buffer Size)
Read/Write:
R
Initialized Value:
0
Transmit FIFO Buffer Almost Empty
Function:
Specifies the minimum size, in bytes, of the transmit buffer before the Transmit Buffer Almost Empty Status bit D1 in the FIFO Status register is flagged (High True).
Type:
unsigned binary word (32-bits)
Data Range:
0 to 0x0010 0000 (Buffer Size)
Read/Write:
R/W
Initialized Value:
100 (0x64)
Operational Settings:
If the interrupt is enabled (see Interrupt Enable register), a System interrupt will be generated.
Configuration Registers
SC3 configurations includes setting the Interface Levels, Baud Rate,
Protocol, Tx-Rx Configuration and if applicable, the Termination Character
registers. Additional registers need to be configured specifically for Async or Sync
modes.
Interface Levels
Function:
Configures the interface level (RS-232, RS-422, RS-485, Loopback, Tri-State, FPGA Loop-Back, GPIO) for the associated channel.
Type:
unsigned binary word (32-bits)
Data Range:
See table
Read/Write:
R/W
Initialized Value:
5 (Tri-State)
Operational Settings:
Loopback selection connects the channel's transmit and receive line internally. To implement, user must send data and look at Receive FIFO to verify that the sent data. Loopback is usually used for testing. Notes: Channels are programmed for loop back in pairs. For example, if channel 1 is programmed for loop back, then channel 2 will be also. This includes channels 3 and 4, 5 and 6 and 7 and 8.
Bit(s)
Interface
Description
D31:D15
Reserved
Set Reserved bits to 0.
D14
GPIO
Needs to be ORed with either RS232 or RS422.
D13:D8
Reserved
Set Reserved bits to 0.
D7
Disable termination resistor
Disables termination resistor in-between the differential pairs of the transmitter and the receiver. Useful for RS485 Multi-Drop.
D6:D3
Reserved
Set Reserved bits to 0.
D2:D0
Interface Level
These bits set the interface level: (0:0:0) RS232 ` (0:1:0) RS422 ` (0:1:1) RS485 ` (1:0:0) Loopback ` (1:0:1) Tri-State
Baud Rate
Function:
Sets the baud rate for communications.
Type:
unsigned binary word (32-bits)
Data Range:
300 bps to 10 Mbps Sync (1.5 Mbps Async)
Read/Write:
R/W
Initialized Value:
9600 bps
Protocol
Function:
Configures the associated channel for either asynchronous, mono-synchronous, bi-synchronous, HDLC mode or mixed asynchronous and GPIO modes.
Async-GPO: This mode can transmit general purpose signals on the channels transmitter while being able to receive async serial data on the receiver. Async-GPI: This mode can transmit async serial data on the channels transmitter while being able to receive general purpose signals on the receiver.
Tx-Rx Configuration
Function:
Sets the transmit/receive configuration for the associated channel.
Type:
unsigned binary word (32-bits)
Data Range:
See table
Read/Write:
R/W
Initialized Value:
0
Operational Settings:
BIT - Set Enable Channel bit, D24 low (0) to clear the selected channel. Set Initiate BIT bit D27 high (1) to initiate BIT. After 5 msec, a 0 should be read, which indicates that the BIT test is complete. The BIT Status register reports the channel status.
Bit(s)
Name
Description
D31:D28
Reserved
Set Reserved bits to 0.
D27
Initiate BIT
Write a 1 to start built-in-test. The channel running BIT needs to be disabled, as well as it's channel pair. For common module functionality see the Test Enabled register.
D26
Invert RTS/GPO
0 = Normal + 1 = Invert.
D25
Invert CTS/GPI
0 = Normal + 1 = Invert.
D24
Enable Channel
0 = Disable + 1 = Enable.
D23
Rx Suppression
0 = Receiver Always On + 1 = Receiver Off During Transmission (RS485 only)
D22
Reserved
Set Reserved bits to 0.
D21
Idle Flag
Idle Flag (0x7E) Transmission
D20
Enable Gap Timeout
0 = Ignore gap timeout + 1 = Set Gap Timeout Occurred status when there is no activity on the receiver's bus for more than 3-byte times.
D19
Append CRC
0 = No CRC + 1 = Append CRC to Tx Data, Expect CRC with Rx data
0 = Ignore termination character + 1 = Set Rx Complete/ETx Received status bit when termination character is received.
D11
Sync char as data
0 = Stripped + 1 = Keep in data
D10:D8
Reserved
Set Reserved bits to 0.
D7
Address Length
0 = 8 bits + 1 = 16 bits
D6:D4
Address Transmission/Recognition (HLDC only): 0x0 - Addressing Off ` 0x1 - Rx Address Recognition only ` 0x2 - Tx Address Transmission only + 0x4 - Addressing On
Addressing Off: Don't send address, receive data from any address. ` Rx Address Recognition: Expect address on Rx, but don't send address. ` Tx Address Transmission: Send address, but don't expect it. + Addressing On: Send and expect address.
D3-D1
Reserved
Set Reserved bits to 0.
D0
RTS/CTS Flow Control
Turns on Hardware Flow Control
Termination Character
Function:
Contains the termination character used for termination detection.
Type:
unsigned character (usually a member of the ASCII data set)
Data Range:
0x00 to 0xFF
Read/Write:
R/W
Initialized Value:
0x03
Operational Settings:
When using the Asynchronous or Mono/Bi-Synchronous modes, the receive data stream is monitored for the occurrence of the termination character. When this character is detected, the Rx COMPLETE / ETx RECEIVED bit is set in the Channel Status register, an interrupt is generated, if enabled.
Async Only Configuration
In Async mode, additional configurations include setting the Data Configuration, Time Out Value, XOFF Character and XON Character registers.
Data Configuration
Function:
Channel data configuration.
Type:
unsigned binary word (32-bits)
Data Range:
See table
Read/Write:
R/W
Initialized Value:
0x108
Operational Settings:
Sets up the Serial channel configuration.
Bit(s)
Name
Description
D31:D15
Reserved
Set Reserved bits to 0.
D14:D12
Encoding
The following sets the Data Encoding: (0:0:0) No Encoding (NRZ) ` (1:1:0) Manchester (GE Thomas) ` (1:1:1) Manchester (IEEE 802.3)
D11:D10
Reserved
Set Reserved bits to 0.
D9:D8
Stop Bits
The following sets the number of stop bits: (0:1) 1 Stop bit + (1:0) 2 Stop bits
D7
Reserved
Set Reserved bits to 0.
D6:D4
Parity
The following sets the Parity: (0:0:0) No Parity ` (0:0:1) Space Parity ` (0:1:0) Reserved ` (0:1:1) Odd Parity ` (1:0:0) Reserved ` (1:0:1) Even Parity ` (1:1:1) Mark Parity +
D3:D0
Number of Data Bits
Actual number of data bits between 5 and 9. For Asynchronous Protocol only.
Time Out Value
Function:
Determines the timeout period.
Type:
unsigned binary word (32-bits)
Data Range:
0 to 0xFFFF
Read/Write:
R/W
Initialized Value:
0x9C40 (1 second)
Operational Settings:
If there is no receive line activity for the configured period of time, a timeout is indicated in the Interrupt Status register, bit D10. LSB is 25µs. Modes Affected: Async.
XON Character
Function:
Specifies the XON character for asynchronous flow control mode.
Type:
unsigned binary word 32-bits (usually a member of the ASCII data set)
Data Range:
0x00 to 0xFF
Read/Write:
R/W
Initialized Value:
0x11
Modes Affected:
Async
Operational Settings:
When software flow control is enabled, this value is sent as the XON character.
XOFF Character
Function:
Specifies the XOFF character for asynchronous software flow control mode.
Type:
unsigned binary word 32-bits (usually a member of the ASCII data set)
Data Range:
0x00 to 0xFF
Read/Write:
R/W
Initialized Value:
0x13
Modes Affected:
Async
Operational Settings:
When software flow control is enabled, this value is sent as the XOFF character.
Sync Only Configuration
In Sync mode, additional configurations include setting the Clock Mode, HDLC
Rx Address/Sync Character and HDLC Tx Address/Sync Character registers.
Clock Mode
Function:
Configures clock for internal (driven) or external (received) transmit/receive clocks
Type:
unsigned binary word (32-bits)
Data Range:
See table.
Read/Write:
R/W
Initialized Value:
0
Operational Settings:
Applicable only for Mono/bi-synchronous or HDLC as set by Protocol register.
Mode dependent for HDLC and Synchronous modes. See Operational Settings.
Type:
unsigned binary word (32-bits)
Data Range:
0x0000 to 0xFFFF
Read/Write:
R/W
Initialized Value:
0xA5
Operational Settings:
HDLC Mode: This value is compared to the address of the received message and if it's equal, the message is stored in the receive buffer. Mono/Bi-Synchronous Mode: this value is considered the “Sync Character” and is used for communication synchronization. The receiver searches incoming data for the Sync Character. Once found, communication is synchronized, and additional data is valid. When in Bi-Synchronous, low byte is sent before high byte. HDLC Rx Address/Sync Character Register
HDLC
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
8-bit address when Address Length bit in Tx-Rx Configuration register is 0.
16-bit address when Address Length bit in Tx-Rx Configuration register is 1.
Mono-Synchronous
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
8-bit synchronization character
Bi-Synchronous
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Second 8-bit synchronization character
First 8-bit synchronization character
HDLC Tx Address/Sync Character
Function:
Mode dependent for HDLC and Synchronous modes. See Operational Settings.
Type:
unsigned binary word (32-bits)
Data Range:
0x0000 to 0xFFFF
Read/Write:
R/W
Initialized Value:
0xA5
Operational Settings:
If using HDLC Mode: this value is compared to the address of the received message and if it's equal, the message is stored in the receive buffer. Mono/Bi-Synchronous Mode: this value is considered the “Sync Character” and is used for communication synchronization. The receiver searches incoming data for the Sync Character. Once found, communication is synchronized, and additional data is valid. When in Bi-Synchronous, low byte is sent before high byte.
Preamble
Function:
Determines the number of preambles and the preamble pattern sent during a preamble transmission.
Type:
unsigned binary word (32-bits)
Data Range:
0x0000 to 0xF0FF
Read/Write:
R/W
Initialized Value:
0
Operational Settings:
In HDLC Mode: zero-bit insertion is disabled during preamble transmission.
Bit(s)
Name
Description
D31:D16
Reserved
Set Reserved bits to 0.
D15:D12
Number of Preambles
The number of Preamble Patterns to be sent.
D11:D8
Reserved
Set Reserved bits to 0.
D7:D0
Preamble Pattern
Actual data byte to be sent.
Control Register
The Channel Control register provides control of the serial channel.
Channel Control
Function:
Channel control configuration.
Type:
unsigned binary word (32-bits)
Data Range:
See table.
Read/Write:
R/W
Initialized Value:
0
Operational Settings:
Real time control of the Serial channel.
Bit(s)
Name
Description
D31:D19
Reserved
Set Reserved bits to 0.
D18
Enable Receiver
D17
Tx Always (Async Only)
Transmit data as soon as data is buffered.
D16
Tx Initiate
Transmit data in Tx buffer. (The data bit is cleared when all data from the Tx Buffer is transmitted)
D15
Clear Tx FIFO
Clear all data in the Tx FIFO. The data bit is self-clearing.
D14
Clear Rx FIFO
Clear all data in the Rx FIFO. The data bit is self-clearing.
D13
Reset Channel FIFOs & UART
Clear both FIFOs and reset channel. Bit is not self-clearing.
D12:D11
Reserved
Set Reserved bits to 0.
D10
Set/Release Break
0 = Break not set + 1 = Pull transmitter low
D9
Reserved
Set Reserved bits to 0.
D8
Tristate Transmit Line
Tristate the transmit line after transmitting, for use with RS485 Multi-Drop mode.
D7:D2
Reserved
Set Reserved bits to 0.
D1
GPO 2
General purpose output two control.
D0
RTS/GPO*
General purpose output one control.
Note
*RTS/CTS as GPO when RTS/CTS Flow Control disabled.
Serial Test Registers
The serial module provides the ability to run an initiated test (IBIT).
Writing a 1 to the bit associated with the channel in the Test Enabled
register.
Note
This register has the same effect as writing a 1 to the Initiate BIT
bit of the Tx-Rx Configuration register for legacy applications.
Test Enabled
Function:
Set the bit corresponding to the channel you want to run Initiated Built-In-Test.
Type:
unsigned binary word (32-bit)
Data Range:
0 to 0x0000 00FF
Read/Write:
R/W
Initialized Value:
0x0
Operational Settings:
Set bit to 1 for channel to run an Initiated BIT test. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects failures. Bit is self-clearing.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Ch8
Ch7
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
Background BIT Threshold Programming Registers
The Background BIT Threshold register provides the ability to specify the
minimum time before the BIT fault is reported in the BIT Status registers.
The Reset BIT register provides the ability to reset the BIT counter used in
CBIT.
Background BIT Threshold
Function:
Sets background BIT Threshold value to use for all channels for BIT failure indication. This value is a scalar for the internal BIT counter, refer to Continuous Background Built-In Test. To filter out momentary or intermittent anomalies in background BIT errors, this value can be increased to allow the error to “come and go” before the BIT status is flagged.
Data Range:
0x1 to 0xFFFF
Read/Write:
R/W
Initialized Value:
5
Reset BIT
Function:
Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.
Type:
unsigned binary word (32-bit)
Data Range:
0 to 0x0000 00FF
Read/Write:
W
Initialized Value:
0
Operational Settings:
Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Ch8
Ch7
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
Module Common Registers
Refer to “Module Common Registers Module Manual” for the register
descriptions.
Status and Interrupt Registers
The SC3 Module provides status registers for BIT, Channel, Summary and
Channel FIFO.
BIT Status
There are four registers associated with the BIT Status: Dynamic Status,
Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.
BIT Status
Function:
Sets the corresponding bit associated with the channel's BIT error.
Type:
unsigned binary word (32-bits)
Data Range:
0x0000 0000 to 0x0000 00FF
Read/Write:
R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:
0
BIT Dynamic Status
BIT Latched Status
BIT Interrupt Enable
BIT Set Edge/Level Interrupt
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Ch8
Ch7
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
Power-on BIT (PBIT) Complete
Function:
Indication if Power-on BIT has completed.
Type:
unsigned binary word (32-bits)
Data Range:
0x0000 0000 to 0x0000 0001
Read/Write:
R
Initialized Value:
0
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PBIT Complete
Channel Status
Function:
Sets the corresponding bit associated with each event type. There are separate registers for each channel.
Type:
unsigned binary word (32-bits)
Data Range:
See table.
Read/Write:
R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value:
0
Channel Dynamic Status
Channel Latched Status
Channel Interrupt Enable
Channel Set Edge/Level Interrupt
Bit(s)
Name
Configurable
Description
D31
Channel Configured
No
Module is configured and ready to operate.
D30
Built-in-Self Test Passed
No
Indicates the status of the last ran IBIT test.
D29:D18
Reserved
No
Set Reserved bits to 0.
D17
Gap Timeout Occurred
Yes
Rx FIFO has data in it, but there hasn't been activity on the bus in 3-byte times.
D16
GPI 2
No
Binary value of general-purpose input 2.
D15
CTS/GPI1
No
Binary value of general-purpose input 1 or CTS.
D14
CTS Low Detect (fall)
No
CTS falling edge detected.
D13
CTS High Detect (rise)
No
CTS rising edge detected.
D12
Reserved
No
Set Reserved bits to 0.
D11
Break/Abort
No
Break recognized.
D10
Timeout Occurred
Yes
No receive line activity within timeout value.
D9
Tx Complete
No
While transmitting, Tx FIFO count reaches zero.
D8
Tx FIFO Almost Empty
Yes
Transmit FIFO Almost Empty Threshold reached.
D7
Low Watermark Reached
Yes
Rx Buffer Low Watermark Threshold reached.
D6
High Watermark Reached
Yes
Rx Buffer High Watermark Threshold reached.
D5
Rx Overrun
No
Data was received while the Rx FIFO was full.
D4
Rx Data Available
No
Receive FIFO count is greater than zero.
D3
Rx Complete/ET x Received
No
Async: Termination character received (Only if termination detection is turned on.) ` HDLC: End of frame flag detected. ` Mono/Bi-Sync: Termination character received.
D2
CRC Error (Sync & HDLC)
No
CRC calculation did not match.
D1
Rx FIFO Almost Full
Yes
Receive FIFO Almost Full Threshold
D0
Parity Error
No
Parity bit did not match.
Note
For the Latched Channel Status register, the interrupts are cleared when a 1 is written to the specific bit.
Channel FIFO Status
Function:
Describes current FIFO Status.
Type:
unsigned binary word (32-bits)
Data Range:
See Table
Read/Write:
R
Initialized Value:
0
Operational Settings:
See Rx Almost Full, Tx Almost Empty, Rx High Watermark and Rx Low Watermark specific registers for function description and programming.
Bit(s)
Name
Configurable?
Description
D5
Tx FIFO Full
No
Tx FIFO has reached maximum buffer size.
D4
Rx FIFO Empty
No
Rx FIFO count is zero.
D3
Low Watermark Reached
Yes
Rx Buffer Low Watermark Threshold reached.
D2
High Watermark Reached
Yes
Rx Buffer High Watermark Threshold reached.
D1
Tx FIFO Almost Empty
Yes
Tx FIFO Almost Empty Threshold reached.
D0
Rx FIFO Almost Full
Yes
Rx FIFO Almost Full Threshold reached
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
D
D
D
D
D
D
Summary Status
Function:
Sets the corresponding bit associated with the channel that has data available to receive in its Receive FIFO Buffer.
Type:
unsigned binary word (32-bits)
Data Range:
0x0000 0000 to 0x0000 00FF
Read/Write:
R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value:
0
Summary Dynamic Status
Summary Latched Status
Summary Interrupt Enable
Summary Set Edge/Level Interrupt
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Ch8
Ch7
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism.
In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
Interrupt Vector
Function:
Set an identifier for the interrupt.
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R/W
Initialized Value:
0
Operational Settings:
When an interrupt occurs, this value is reported as part of the interrupt mechanism.
Interrupt Steering
Function:
Sets where to direct the interrupt.
Type:
unsigned binary word (32-bit)
Data Range:
See table
Read/Write:
R/W
Initialized Value:
0
Operational Settings:
When an interrupt occurs, the interrupt is sent as specified:
Direct Interrupt to VME
1
Direct Interrupt to ARM Processor (via SerDes) + (Custom App on ARM or NAI Ethernet Listener App)
2
Direct Interrupt to PCIe Bus
5
Direct Interrupt to cPCI Bus
6
FUNCTION REGISTER MAP
KEY
Incoming Data
Outgoing Data
Configuration/Control
Status
RECEIVE REGISTERS
NOTE: Base Address - 0x4000 0000
OFFSET
REGISTER NAME
ACCESS
OFFSET
REGISTER NAME
ACCESS
0x1004
Receive FIFO Buffer Ch 1
R
0x100C
Receive FIFO Buffer Word Count Ch 1
R
0x1084
Receive FIFO Buffer Ch 2
R
0x108C
Receive FIFO Buffer Word Count Ch 2
R
0x1104
Receive FIFO Buffer Ch 3
R
0x110C
Receive FIFO Buffer Word Count Ch 3
R
0x1184
Receive FIFO Buffer Ch 4
R
0x118C
Receive FIFO Buffer Word Count Ch 4
R
0x1204
Receive FIFO Buffer Ch 5
R
0x120C
Receive FIFO Buffer Word Count Ch 5
R
0x1284
Receive FIFO Buffer Ch 6
R
0x128C
Receive FIFO Buffer Word Count Ch 6
R
0x1304
Receive FIFO Buffer Ch 7
R
0x130C
Receive FIFO Buffer Word Count Ch 7
R
0x1384
Receive FIFO Buffer Ch 8
R
0x138C
Receive FIFO Buffer Word Count Ch 8
R
0x1034
Receive FIFO Buffer Almost Full Ch 1
R/W
0x1038
Receive FIFO Buffer High Watermark Ch 1
R/W
0x10B4
Receive FIFO Buffer Almost Full Ch 2
R/W
0x10B8
Receive FIFO Buffer High Watermark Ch 2
R/W
0x1134
Receive FIFO Buffer Almost Full Ch 3
R/W
0x1138
Receive FIFO Buffer High Watermark Ch 3
R/W
0x11B4
Receive FIFO Buffer Almost Full Ch 4
R/W
0x11B8
Receive FIFO Buffer High Watermark Ch 4
R/W
0x1234
Receive FIFO Buffer Almost Full Ch 5
R/W
0x1238
Receive FIFO Buffer High Watermark Ch 5
R/W
0x12B4
Receive FIFO Buffer Almost Full Ch 6
R/W
0x12B8
Receive FIFO Buffer High Watermark Ch 6
R/W
0x1334
Receive FIFO Buffer Almost Full Ch 7
R/W
0x1338
Receive FIFO Buffer High Watermark Ch 7
R/W
0x13B4
Receive FIFO Buffer Almost Full Ch 8
R/W
0x13B8
Receive FIFO Buffer High Watermark Ch 8
R/W
0x103C
Receive FIFO Buffer Low Watermark Ch 1
R/W
0x10BC
Receive FIFO Buffer Low Watermark Ch 2
R/W
0x113C
Receive FIFO Buffer Low Watermark Ch 3
R/W
0x11BC
Receive FIFO Buffer Low Watermark Ch 4
R/W
0x123C
Receive FIFO Buffer Low Watermark Ch 5
R/W
0x12BC
Receive FIFO Buffer Low Watermark Ch 6
R/W
0x133C
Receive FIFO Buffer Low Watermark Ch 7
R/W
0x13BC
Receive FIFO Buffer Low Watermark Ch 8
R/W
TRANSMIT REGISTERS
NOTE: Base Address - 0x4000 0000
OFFSET
REGISTER NAME
ACCESS
OFFSET
REGISTER NAME
ACCESS
0x1000
Transmit FIFO Buffer Ch 1
W
0x1008
Transmit FIFO Buffer Word Count Ch 1
R
0x1080
Transmit FIFO Buffer Ch 2
W
0x1088
Transmit FIFO Buffer Word Count Ch 2
R
0x1100
Transmit FIFO Buffer Ch 3
W
0x1108
Transmit FIFO Buffer Word Count Ch 3
R
0x1180
Transmit FIFO Buffer Ch 4
W
0x1188
Transmit FIFO Buffer Word Count Ch 4
R
0x1200
Transmit FIFO Buffer Ch 5
W
0x1208
Transmit FIFO Buffer Word Count Ch 5
R
0x1280
Transmit FIFO Buffer Ch 6
W
0x1288
Transmit FIFO Buffer Word Count Ch 6
R
0x1300
Transmit FIFO Buffer Ch 7
W
0x1308
Transmit FIFO Buffer Word Count Ch 7
R
0x1380
Transmit FIFO Buffer Ch 8
W
0x1388
Transmit FIFO Buffer Word Count Ch 8
R
0x1030
Transmit FIFO Buffer Almost Empty Ch 1
R/W
0x10B0
Transmit FIFO Buffer Almost Empty Ch 2
R/W
0x1130
Transmit FIFO Buffer Almost Empty Ch 3
R/W
0x11B0
Transmit FIFO Buffer Almost Empty Ch 4
R/W
0x1230
Transmit FIFO Buffer Almost Empty Ch 5
R/W
0x12B0
Transmit FIFO Buffer Almost Empty Ch 6
R/W
0x1330
Transmit FIFO Buffer Almost Empty Ch 7
R/W
0x13B0
Transmit FIFO Buffer Almost Empty Ch 8
R/W
CONFIGURATION REGISTERS
NOTE: Base Address - 0x4000 0000
OFFSET
REGISTER NAME
ACCESS
OFFSET
REGISTER NAME
ACCESS
0x1018
Interface Levels Ch 1
R/W
0x1028
Baud Rate Ch 1
R/W
0x1098
Interface Levels Ch 2
R/W
0x10A8
Baud Rate Ch 2
R/W
0x1118
Interface Levels Ch 3
R/W
0x1128
Baud Rate Ch 3
R/W
0x1198
Interface Levels Ch 4
R/W
0x11A8
Baud Rate Ch 4
R/W
0x1218
Interface Levels Ch 5
R/W
0x1228
Baud Rate Ch 5
R/W
0x1298
Interface Levels Ch 6
R/W
0x12A8
Baud Rate Ch 6
R/W
0x1318
Interface Levels Ch 7
R/W
0x1328
Baud Rate Ch 7
R/W
0x1398
Interface Levels Ch 8
R/W
0x13A8
Baud Rate Ch 8
R/W
0x1010
Protocol Ch 1
R/W
0x101C
Tx-Rx Configuration Ch 1
R/W
0x1090
Protocol Ch 2
R/W
0x109C
Tx-Rx Configuration Ch 2
R/W
0x1110
Protocol Ch 3
R/W
0x111C
Tx-Rx Configuration Ch 3
R/W
0x1190
Protocol Ch 4
R/W
0x119C
Tx-Rx Configuration Ch 4
R/W
0x1210
Protocol Ch 5
R/W
0x121C
Tx-Rx Configuration Ch 5
R/W
0x1290
Protocol Ch 6
R/W
0x129C
Tx-Rx Configuration Ch 6
R/W
0x1310
Protocol Ch 7
R/W
0x131C
Tx-Rx Configuration Ch 7
R/W
0x1390
Protocol Ch 8
R/W
0x139C
Tx-Rx Configuration Ch 8
R/W
0x1050
Termination Character Ch 1
R/W
0x10D0
Termination Character Ch 2
R/W
0x1150
Termination Character Ch 3
R/W
0x11D0
Termination Character Ch 4
R/W
0x1250
Termination Character Ch 5
R/W
0x12D0
Termination Character Ch 6
R/W
0x1350
Termination Character Ch 7
R/W
0x13D0
Termination Character Ch 8
R/W
ASYNC ONLY CONFIGURATION REGISTERS
NOTE: Base Address - 0x4000 0000
0x1024
Data Configuration Ch 1
R/W
0x1054
Time Out Value Ch 1
R/W
0x10A4
Data Configuration Ch 2
R/W
0x10D4
Time Out Value Ch 2
R/W
0x1124
Data Configuration Ch 3
R/W
0x1154
Time Out Value Ch 3
R/W
0x11A4
Data Configuration Ch 4
R/W
0x11D4
Time Out Value Ch 4
R/W
0x1224
Data Configuration Ch 5
R/W
0x1254
Time Out Value Ch 5
R/W
0x12A4
Data Configuration Ch 6
R/W
0x12D4
Time Out Value Ch 6
R/W
0x1324
Data Configuration Ch 7
R/W
0x1354
Time Out Value Ch 7
R/W
0x13A4
Data Configuration Ch 8
R/W
0x13D4
Time Out Value Ch 8
R/W
0x1048
XON Character Ch 1
R/W
0x104C
XOFF Character Ch 1
R/W
0x10C8
XON Character Ch 2
R/W
0x10CC
XOFF Character Ch 2
R/W
0x1148
XON Character Ch 3
R/W
0x114C
XOFF Character Ch 3
R/W
0x11C8
XON Character Ch 4
R/W
0x11CC
XOFF Character Ch 4
R/W
0x1248
XON Character Ch 5
R/W
0x124C
XOFF Character Ch 5
R/W
0x12C8
XON Character Ch 6
R/W
0x12CC
XOFF Character Ch 6
R/W
0x1348
XON Character Ch 7
R/W
0x134C
XOFF Character Ch 7
R/W
0x13C8
XON Character Ch 8
R/W
0x13CC
XOFF Character Ch 8
R/W
SYNC ONLY CONFIGURATION REGISTERS
NOTE: Base Address - 0x4000 0000
0x1014
Clock Mode Ch 1
R/W
0x1040
HDLC Rx Address/Sync Character Ch 1
R/W
0x1094
Clock Mode Ch 2
R/W
0x10C0
HDLC Rx Address/Sync Character Ch 2
R/W
0x1114
Clock Mode Ch 3
R/W
0x1140
HDLC Rx Address/Sync Character Ch 3
R/W
0x1194
Clock Mode Ch 4
R/W
0x11C0
HDLC Rx Address/Sync Character Ch 4
R/W
0x1044
HDLC Tx Address/Sync Character Ch 1
R/W
0x102C
Preamble Ch 1
R/W
0x10C4
HDLC Tx Address/Sync Character Ch 2
R/W
0x10AC
Preamble Ch 2
R/W
0x1144
HDLC Tx Address/Sync Character Ch 3
R/W
0x112C
Preamble Ch 3
R/W
0x11C4
HDLC Tx Address/Sync Character Ch 4
R/W
0x11AC
Preamble Ch 4
R/W
CONTROL REGISTERS
NOTE: Base Address - 0x4000 0000
OFFSET
REGISTER NAME
ACCESS
OFFSET
REGISTER NAME
ACCESS
0x1020
Channel Control Ch 1
R/W
0x10A0
Channel Control Ch 2
R/W
0x1120
Channel Control Ch 3
R/W
0x11A0
Channel Control Ch 4
R/W
0x1220
Channel Control Ch 5
R/W
0x12A0
Channel Control Ch 6
R/W
0x1320
Channel Control Ch 7
R/W
0x13A0
Channel Control Ch 8
R/W
MODULE COMMON REGISTERS
Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.
++``+ STATUS REGISTERS*
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x4000 0000
OFFSET
REGISTER NAME
ACCESS
OFFSET
REGISTER NAME
ACCESS
0x02B0
Channel Status Enabled
R/W
0x0800
BIT Dynamic Status
R
0x0804
BIT Latched Status*
R/W
0x0808
BIT Interrupt Enable
R/W
0x080C
BIT Set Edge/Level Interrupt
R/W
0x02A8
Test Enabled
R/W
0x02AC
Power-on BIT Complete++
R/W
NOTE: ++After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.
0x02B8
Background BIT Threshold
R/W
0x02BC
Reset BIT
W
Channel 1 Status
Channel 2 Status
0x0810
Dynamic Status
R
0x0820
Dynamic Status
R
0x0814
Latched Status*
R/W
0x0824
Latched Status*
R/W
0x0818
Interrupt Enable
R/W
0x0828
Interrupt Enable
R/W
0x081C
Set Edge/Level Interrupt
R/W
0x082C
Set Edge/Level Interrupt
R/W
Channel 3 Status
Channel 4 Status
0x0830
Dynamic Status
R
0x0840
Dynamic Status
R
0x0834
Latched Status*
R/W
0x0844
Latched Status*
R/W
0x0838
Interrupt Enable
R/W
0x0848
Interrupt Enable
R/W
0x083C
Set Edge/Level Interrupt
R/W
0x084C
Set Edge/Level Interrupt
R/W
Channel 5 Status
Channel 6 Status
0x0850
Dynamic Status
R
0x0860
Dynamic Status
R
0x0854
Latched Status*
R/W
0x0864
Latched Status*
R/W
0x0858
Interrupt Enable
R/W
0x0868
Interrupt Enable
R/W
0x085C
Set Edge/Level Interrupt
R/W
0x086C
Set Edge/Level Interrupt
R/W
Channel 7 Status
Channel 8 Status
0x0870
Dynamic Status
R
0x0880
Dynamic Status
R
0x0874
Latched Status*
R/W
0x0884
Latched Status*
R/W
0x0878
Interrupt Enable
R/W
0x0888
Interrupt Enable
R/W
0x087C
Set Edge/Level Interrupt
R/W
0x088C
Set Edge/Level Interrupt
R/W
FIFO Status
Summary Status
0x1058
Channel 1 FIFO Status
R
0x09A0
Dynamic Status
R
0x10D8
Channel 2 FIFO Status
R/W
0x09A4
Latched Status*
R/W
0x1158
Channel 3 FIFO Status
R/W
0x09A8
Interrupt Enable
R/W
0x11D8
Channel 4 FIFO Status
R/W
0x09AC
Set Edge/Level Interrupt
R/W
0x1258
Channel 5 FIFO Status
R/W
0x12D8
Channel 6 FIFO Status
R/W
0x1358
Channel 7 FIFO Status
R/W
0x13D8
Channel 8 FIFO Status
R/W
INTERRUPT REGISTERS
The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.
OFFSET
REGISTER NAME
ACCESS
OFFSET
REGISTER NAME
ACCESS
0x0500
Module 1 Interrupt Vector 1 - BIT
R/W
0x0600
Module 1 Interrupt Steering 1 - BIT
R/W
0x0504
Module 1 Interrupt Vector 2 - Channel Status Ch 1
R/W
0x0604
Module 1 Interrupt Steering 2 - Channel Status Ch 1
R/W
0x0508
Module 1 Interrupt Vector 3 - Channel Status Ch 2
R/W
0x0608
Module 1 Interrupt Steering 3 - Channel Status Ch 2
R/W
0x050C
Module 1 Interrupt Vector 4 - Channel Status Ch 3
R/W
0x060C
Module 1 Interrupt Steering 4 - Channel Status Ch 3
R/W
0x0510
Module 1 Interrupt Vector 5 - Channel Status Ch 4
R/W
0x0610
Module 1 Interrupt Steering 5 - Channel Status Ch 4
R/W
0x0514
Module 1 Interrupt Vector 6 - Channel Status Ch 5
R/W
0x0614
Module 1 Interrupt Steering 6 - Channel Status Ch 5
R/W
0x0518
Module 1 Interrupt Vector 7 - Channel Status Ch 6
R/W
0x0618
Module 1 Interrupt Steering 7 - Channel Status Ch 6
R/W
0x051C
Module 1 Interrupt Vector 8 - Channel Status Ch 7
R/W
0x061C
Module 1 Interrupt Steering 8 - Channel Status Ch 7
R/W
0x0520
Module 1 Interrupt Vector 9 - Channel Status Ch 8
R/W
0x0620
Module 1 Interrupt Steering 9 - Channel Status Ch 8
R/W
0x0524 to 0x0564
Module 1 Interrupt Vector 10 to 26 - Reserved
R/W
0x0624 to 0x0664
Module 1 Interrupt Steering 10 to 26 - Reserved
R/W
0x0568
Module 1 Interrupt Vector 27 - Summary Status
R/W
0x0668
Module 1 Interrupt Steering 27 - Summary Status
R/W
0x056C to 0x057C
Module 1 Interrupt Vector 28 to 32 - Reserved
R/W
0x066C to 0x067C
Module 1 Interrupt Steering 28 to 32 - Reserved
R/W
0x0700
Module 2 Interrupt Vector 1 - BIT
R/W
0x0800
Module 2 Interrupt Steering 1 - BIT
R/W
0x0704
Module 2 Interrupt Vector 2 - Channel Status Ch 1
R/W
0x0804
Module 2 Interrupt Steering 2 - Channel Status Ch 1
R/W
0x0708
Module 2 Interrupt Vector 3 - Channel Status Ch 2
R/W
0x0808
Module 2 Interrupt Steering 3 - Channel Status Ch 2
R/W
0x070C
Module 2 Interrupt Vector 4 - Channel Status Ch 3
R/W
0x080C
Module 2 Interrupt Steering 4 - Channel Status Ch 3
R/W
0x0710
Module 2 Interrupt Vector 5 - Channel Status Ch 4
R/W
0x0810
Module 2 Interrupt Steering 5 - Channel Status Ch 4
R/W
0x0714
Module 2 Interrupt Vector 6 - Channel Status Ch 5
R/W
0x0814
Module 2 Interrupt Steering 6 - Channel Status Ch 5
R/W
0x0718
Module 2 Interrupt Vector 7 - Channel Status Ch 6
R/W
0x0818
Module 2 Interrupt Steering 7 - Channel Status Ch 6
R/W
0x071C
Module 2 Interrupt Vector 8 - Channel Status Ch 7
R/W
0x081C
Module 2 Interrupt Steering 8 - Channel Status Ch 7
R/W
0x0720
Module 2 Interrupt Vector 9 - Channel Status Ch 8
R/W
0x0820
Module 2 Interrupt Steering 9 - Channel Status Ch 8
R/W
0x0724 to 0x0764
Module 2 Interrupt Vector 10 to 26 - Reserved
R/W
0x0824 to 0x0864
Module 2 Interrupt Steering 10 to 26 - Reserved
R/W
0x0768
Module 2 Interrupt Vector 27 - Summary Status
R/W
0x0868
Module 2 Interrupt Steering 27 - Summary Status
R/W
0x076C to 0x077C
Module 2 Interrupt Vector 28 to 32 - Reserved
R/W
0x086C to 0x087C
Module 2 Interrupt Steering 28 to 32 - Reserved
R/W
0x0900
Module 3 Interrupt Vector 1 - BIT
R/W
0x0A00
Module 3 Interrupt Steering 1 - BIT
R/W
0x0904
Module 3 Interrupt Vector 2 - Channel Status Ch 1
R/W
0x0A04
Module 3 Interrupt Steering 2 - Channel Status Ch 1
R/W
0x0908
Module 3 Interrupt Vector 3 - Channel Status Ch 2
R/W
0x0A08
Module 3 Interrupt Steering 3 - Channel Status Ch 2
R/W
0x090C
Module 3 Interrupt Vector 4 - Channel Status Ch 3
R/W
0x0A0C
Module 3 Interrupt Steering 4 - Channel Status Ch 3
R/W
0x0910
Module 3 Interrupt Vector 5 - Channel Status Ch 4
R/W
0x0A10
Module 3 Interrupt Steering 5 - Channel Status Ch 4
R/W
0x0914
Module 3 Interrupt Vector 6 - Channel Status Ch 5
R/W
0x0A14
Module 3 Interrupt Steering 6 - Channel Status Ch 5
R/W
0x0918
Module 3 Interrupt Vector 7 - Channel Status Ch 6
R/W
0x0A18
Module 3 Interrupt Steering 7 - Channel Status Ch 6
R/W
0x091C
Module 3 Interrupt Vector 8 - Channel Status Ch 7
R/W
0x0A1C
Module 3 Interrupt Steering 8 - Channel Status Ch 7
R/W
0x0920
Module 3 Interrupt Vector 9 - Channel Status Ch 8
R/W
0x0A20
Module 3 Interrupt Steering 9 - Channel Status Ch 8
R/W
0x0924 to 0x0964
Module 3 Interrupt Vector 10 to 26 - Reserved
R/W
0x0A24 to 0x0A64
Module 3 Interrupt Steering 10 to 26 - Reserved
R/W
0x0968
Module 3 Interrupt Vector 27 - Summary Status
R/W
0x0A68
Module 3 Interrupt Steering 27 - Summary Status
R/W
0x096C to 0x097C
Module 3 Interrupt Vector 28 to 32 - Reserved
R/W
0x0A6C to 0x0A7C
Module 3 Interrupt Steering 28 to 32 - Reserved
R/W
0x0B00
Module 4 Interrupt Vector 1 - BIT
R/W
0x0C00
Module 4 Interrupt Steering 1 - BIT
R/W
0x0B04
Module 4 Interrupt Vector 2 - Channel Status Ch 1
R/W
0x0C04
Module 4 Interrupt Steering 2 - Channel Status Ch 1
R/W
0x0B08
Module 4 Interrupt Vector 3 - Channel Status Ch 2
R/W
0x0C08
Module 4 Interrupt Steering 3 - Channel Status Ch 2
R/W
0x0B0C
Module 4 Interrupt Vector 4 - Channel Status Ch 3
R/W
0x0C0C
Module 4 Interrupt Steering 4 - Channel Status Ch 3
R/W
0x0B10
Module 4 Interrupt Vector 5 - Channel Status Ch 4
R/W
0x0C10
Module 4 Interrupt Steering 5 - Channel Status Ch 4
R/W
0x0B14
Module 4 Interrupt Vector 6 - Channel Status Ch 5
R/W
0x0C14
Module 4 Interrupt Steering 6 - Channel Status Ch 5
R/W
0x0B18
Module 4 Interrupt Vector 7 - Channel Status Ch 6
R/W
0x0C18
Module 4 Interrupt Steering 7 - Channel Status Ch 6
R/W
0x0B1C
Module 4 Interrupt Vector 8 - Channel Status Ch 7
R/W
0x0C1C
Module 4 Interrupt Steering 8 - Channel Status Ch 7
R/W
0x0B20
Module 4 Interrupt Vector 9 - Channel Status Ch 8
R/W
0x0C20
Module 4 Interrupt Steering 9 - Channel Status Ch 8
R/W
0x0B24 to 0x0B64
Module 4 Interrupt Vector 10 to 26 - Reserved
R/W
0x0C24 to 0x0C64
Module 4 Interrupt Steering 10 to 26 - Reserved
R/W
0x0B68
Module 4 Interrupt Vector 27 - Summary Status
R/W
0x0C68
Module 4 Interrupt Steering 27 - Summary Status
R/W
0x0B6C to 0x0B7C
Module 4 Interrupt Vector 28 to 32 - Reserved
R/W
0x0C6C to 0x0C7C
Module 4 Interrupt Steering 28 to 32 - Reserved
R/W
0x0D00
Module 5 Interrupt Vector 1 - BIT
R/W
0x0E00
Module 5 Interrupt Steering 1 - BIT
R/W
0x0D04
Module 5 Interrupt Vector 2 - Channel Status Ch 1
R/W
0x0E04
Module 5 Interrupt Steering 2 - Channel Status Ch 1
R/W
0x0D08
Module 5 Interrupt Vector 3 - Channel Status Ch 2
R/W
0x0E08
Module 5 Interrupt Steering 3 - Channel Status Ch 2
R/W
0x0D0C
Module 5 Interrupt Vector 4 - Channel Status Ch 3
R/W
0x0E0C
Module 5 Interrupt Steering 4 - Channel Status Ch 3
R/W
0x0D10
Module 5 Interrupt Vector 5 - Channel Status Ch 4
R/W
0x0E10
Module 5 Interrupt Steering 5 - Channel Status Ch 4
R/W
0x0D14
Module 5 Interrupt Vector 6 - Channel Status Ch 5
R/W
0x0E14
Module 5 Interrupt Steering 6 - Channel Status Ch 5
R/W
0x0D18
Module 5 Interrupt Vector 7 - Channel Status Ch 6
R/W
0x0E18
Module 5 Interrupt Steering 7 - Channel Status Ch 6
R/W
0x0D1C
Module 5 Interrupt Vector 8 - Channel Status Ch 7
R/W
0x0E1C
Module 5 Interrupt Steering 8 - Channel Status Ch 7
R/W
0x0D20
Module 5 Interrupt Vector 9 - Channel Status Ch 8
R/W
0x0E20
Module 5 Interrupt Steering 9 - Channel Status Ch 8
R/W
0x0D24 to 0x0D64
Module 5 Interrupt Vector 10 to 26 - Reserved
R/W
0x0E24 to 0x0E64
Module 5 Interrupt Steering 10 to 26 - Reserved
R/W
0x0D68
Module 5 Interrupt Vector 27 - Summary Status
R/W
0x0E68
Module 5 Interrupt Steering 27 - Summary Status
R/W
0x0D6C to 0x0D7C
Module 5 Interrupt Vector 28 to 32 - Reserved
R/W
0x0E6C to 0x0E7C
Module 5 Interrupt Steering 28 to 32 - Reserved
R/W
0x0F00
Module 6 Interrupt Vector 1 - BIT
R/W
0x1000
Module 6 Interrupt Steering 1 - BIT
R/W
0x0F04
Module 6 Interrupt Vector 2 - Channel Status Ch 1
R/W
0x1004
Module 6 Interrupt Steering 2 - Channel Status Ch 1
R/W
0x0F08
Module 6 Interrupt Vector 3 - Channel Status Ch 2
R/W
0x1008
Module 6 Interrupt Steering 3 - Channel Status Ch 2
R/W
0x0F0C
Module 6 Interrupt Vector 4 - Channel Status Ch 3
R/W
0x100C
Module 6 Interrupt Steering 4 - Channel Status Ch 3
R/W
0x0F10
Module 6 Interrupt Vector 5 - Channel Status Ch 4
R/W
0x1010
Module 6 Interrupt Steering 5 - Channel Status Ch 4
R/W
0x0F14
Module 6 Interrupt Vector 6 - Channel Status Ch 5
R/W
0x1014
Module 6 Interrupt Steering 6 - Channel Status Ch 5
R/W
0x0F18
Module 6 Interrupt Vector 7 - Channel Status Ch 6
R/W
0x1018
Module 6 Interrupt Steering 7 - Channel Status Ch 6
R/W
0x0F1C
Module 6 Interrupt Vector 8 - Channel Status Ch 7
R/W
0x101C
Module 6 Interrupt Steering 8 - Channel Status Ch 7
R/W
0x0F20
Module 6 Interrupt Vector 9 - Channel Status Ch 8
R/W
0x1020
Module 6 Interrupt Steering 9 - Channel Status Ch 8
R/W
0x0F24 to 0x0F64
Module 6 Interrupt Vector 10 to 26 - Reserved
R/W
0x1024 to 0x1064
Module 6 Interrupt Steering 10 to 26 - Reserved
R/W
0x0F68
Module 6 Interrupt Vector 27 - Summary Status
R/W
0x1068
Module 6 Interrupt Steering 27 - Summary Status
R/W
0x0F6C to 0x0F7C
Module 6 Interrupt Vector 28 to 32 - Reserved
R/W
0x106C to 0x107C
Module 6 Interrupt Steering 28 to 32 - Reserved
R/W
APPENDIX A: REGISTER NAME CHANGE
This section provides a mapping of the register names used in this document against register names used in previous releases.
Rev B - Register Names
Rev A - Register Names
Receive Registers
Receive FIFO Buffer
Receive Buffer
Receive FIFO Buffer Word Count
Number of Words Rx Buffer
Receive FIFO Buffer Almost Full
Rx Buffer Almost Full
Receive FIFO Buffer High Watermark
Rx Buffer High Watermark
Receive FIFO Buffer Low Watermark
Rx Buffer Low Watermark
Transmit Registers
Transmit FIFO Buffer
Transmit Buffer
Transmit FIFO Buffer Word Count
Number of Words Tx Buffer
Transmit FIFO Buffer Almost Empty
Tx Buffer Almost Empty
Configuration Registers
Interface Levels
Interface Levels
Baud Rate
Baud Rate
Protocol
Protocol
Tx-Rx Configuration
Tx-Rx Configuration
Termination Character
Termination Character
Data Configuration
Data Configuration
Time Out Value
Time Out Value
XOFF Character
XOFF Character
XON Character
XON Character
Clock Mode
HDLC Rx Address/Sync Character
HDLC Tx Address/Sync Character
Control Registers
Channel Control
Channel Control
Serial Test Registers
Test Enabled
Background BIT Threshold Programming Registers
Background BIT Threshold
Reset BIT
Status and Interrupt Registers
BIT Dynamic Status
BIT Dynamic Status
BIT Latched Status
BIT Latched Status
BIT Interrupt Enable
BIT Interrupt Enable
BIT Set Edge/Level Interrupt
BIT Set Edge/Level Interrupt
Channel Dynamic Status
Dynamic Status
Channel Latched Status
Latched Status
Channel Interrupt Enable
Interrupt Enable
Channel Set Edge/Level Interrupt
Set Edge/Level Interrupt
Channel FIFO Status
FIFO Status
Summary Dynamic Status
Summary Latched Status
Summary Interrupt Enable
Summary Set Edge/Level Interrupt
Interrupt Vector
Interrupt Steering
APPENDIX B: PIN-OUT DETAILS
Pin-out details (for reference) are shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Motherboard
Operational Manuals.
Note
Due to number of pinout configurations, SC3 module pinout table has be broken into two tables for clarity.
Module Signal (Ref Only)
44-Pin I/O
50-Pin I/O (Mod Slot 1-J3)
50-Pin I/O (Mod Slot 2-J4)
50-Pin I/O (Mod Slot 3-J3)
50-Pin I/O (Mod Slot 3-J4)
8 CH-Serial Comms RS422/485 ASYNC mode (SC3)
4 CH-Serial Comms RS422/485 SYNC mode (SC3)**
4 CH-Serial Comms RS422/485 ASYNC w/HW Flow Control mode (SC3)**
8 CH-Serial Comms RS422/485 GPIO mode (SC3)
DATIO1
2
10
1
2
RXDLO-CH1
RXDLO-CH1
RXDLO-CH1
GPI-LO-CH1
DATIO2
24
35
26
27
RXDHI-CH1
RXDHI-CH1
RXDHI-CH1
GPI-HI-CH1
DATIO3
3
11
2
3
TXDLO-CH1
TXDLO-CH1
TXDLO-CH1
GPO-LO-CH1
DATIO4
25
36
27
28
TXDHI-CH1
TXDHI-CH1
TXDHI-CH1
GPO-HI-CH1
DATIO5
5
13
4
5
RXDLO-CH2
RXDLO-CH2
RXDLO-CH2
GPI-LO-CH2
DATIO6
27
38
29
30
RXDHI-CH2
RXDHI-CH2
RXDHI-CH2
GPI-HI-CH2
DATIO7
7
14
5
6
TXDLO-CH2
TXDLO-CH2
TXDLO-CH2
GPO-LO-CH2
DATIO8
29
39
30
31
TXDHI-CH2
TXDHI-CH2
TXDHI-CH2
GPO-HI-CH2
DATIO9
8
15
6
7
RXDLO-CH3
RXDLO-CH3
RXDLO-CH3
GPI-LO-CH3
DATIO10
30
40
31
32
RXDHI-CH3
RXDHI-CH3
RXDHI-CH3
GPI-HI-CH3
DATIO11
10
17
8
9
TXDLO-CH3
TXDLO-CH3
TXDLO-CH3
GPO-LO-CH3
DATIO12
32
42
33
34
TXDHI-CH3
TXDHI-CH3
TXDHI-CH3
GPO-HI-CH3
DATIO13
12
18
9
17
RXDLO-CH5
CLKIN-LO-CH1
CTS-LO-CH1
GPI-LO-CH5
DATIO14
34
43
34
42
RXDHI-CH5
CLKIN-HI-CH1
CTS-HI-CH1
GPI-HI-CH5
DATIO15
13
19
10
18
TXDLO-CH5
CLKOUT-LO-CH1
RTS-LO-CH1
GPO-LO-CH5
DATIO16
35
44
35
43
TXDHI-CH5
CLKOUT-HI-CH1
RTS-HI-CH1
GPO-HI-CH5
DATIO17
15
21
12
20
RXDLO-CH6
CLKIN-LO-CH2
CTS-LO-CH2
GPI-LO-CH6
DATIO18
37
46
37
45
RXDHI-CH6
CLKIN-HI-CH2
CTS-HI-CH2
GPI-HI-CH6
DATIO19
17
22
13
21
TXDLO-CH6
CLKOUT-LO-CH2
RTS-LO-CH2
GPO-LO-CH6
DATIO20
39
47
38
46
TXDHI-CH6
CLKOUT-HI-CH2
RTS-HI-CH2
GPO-HI-CH6
DATIO21
18
23
14
22
RXDLO-CH7
CLKIN-LO-CH3
CTS-LO-CH3
GPI-LO-CH7
DATIO22
40
48
39
47
RXDHI-CH7
CLKIN-HI-CH3
CTS-HI-CH3
GPI-HI-CH7
DATIO23
20
25
16
24
TXDLO-CH7
CLKOUT-LO-CH3
RTS-LO-CH3
GPO-LO-CH7
DATIO24
42
50
41
49
TXDHI-CH7
CLKOUT-HI-CH3
RTS-HI-CH3
GPO-HI-CH7
DATIO25
4
12
3
4
RXDLO-CH4
RXDLO-CH4
RXDLO-CH4
GPI-LO-CH4
DATIO26
26
37
28
29
RXDHI-CH4
RXDHI-CH4
RXDHI-CH4
GPI-HI-CH4
DATIO27
9
16
7
8
TXDLO-CH4
TXDLO-CH4
TXDLO-CH4
GPO-LO-CH4
DATIO28
31
41
32
33
TXDHI-CH4
TXDHI-CH4
TXDHI-CH4
GPO-HI-CH4
DATIO29
14
20
11
19
RXDLO-CH8
CLKIN-LO-CH4
CTS-LO-CH4
GPI-LO-CH8
DATIO30
36
45
36
44
RXDHI-CH8
CLKIN-HI-CH4
CTS-HI-CH4
GPI-HI-CH8
DATIO31
19
24
15
23
TXDLO-CH8
CLKOUT-LO-CH4
RTS-LO-CH4
GPO-LO-CH8
DATIO32
41
49
40
48
TXDHI-CH8
CLKOUT-HI-CH4
RTS-HI-CH4
GPO-HI-CH8
DATIO33
6
DATIO34
28
DATIO35
11
DATIO36
33
DATIO37
16
DATIO38
38
DATIO39
21
DATIO40
43
N/A
Module Signal (Ref Only)
44-Pin I/O
50-Pin I/O (Mod Slot 1-J3)
50-Pin I/O (Mod Slot 2-J4)
50-Pin I/O (Mod Slot 3-J3)
50-Pin I/O (Mod Slot 3-J4)
4 CH-Serial Comms RS232 w/ ASYNC w/HW Flow Control (SC3)
8 CH-Serial Comms RS232 ASYNC (SC3)
4 CH-Serial Comms RS232 SYNC (SC3)
8 CH-Serial Comms RS-232 GPIO (SC3)
DATIO1
2
10
1
2
RxD-CH1
RxD-CH1
RxD-CH1
GPI2-CH1
DATIO2
24
35
26
27
-
-
-
GPI1-CH1
DATIO3
3
11
2
3
TxD-CH1
TxD-CH1
TxD-CH1
GPO2-CH1
DATIO4
25
36
27
28
-
-
-
GPO1-CH1
DATIO5
5
13
4
5
RxD-CH2
RxD-CH2
RxD-CH2
GPI2-CH2
DATIO6
27
38
29
30
-
-
-
GPI1-CH2
DATIO7
7
14
5
6
TxD-CH2
TxD-CH2
TxD-CH2
GPO2-CH2
DATIO8
29
39
30
31
-
-
-
GPO1-CH2
DATIO9
8
15
6
7
RxD-CH3
RxD-CH3
RxD-CH3
GPI2-CH3
DATIO10
30
40
31
32
-
-
-
GPI1-CH3
DATIO11
10
17
8
9
TxD-CH3
TxD-CH3
TxD-CH3
GPO2-CH3
DATIO12
32
42
33
34
-
-
-
GPO1-CH3
DATIO13
12
18
9
17
-
RxD-CH5
-
GPI2-CH5
DATIO14
34
43
34
42
CTS-CH1
-
CLKIN-CH1
GPI1-CH5
DATIO15
13
19
10
18
-
TxD-CH5
-
GPO2-CH5
DATIO16
35
44
35
43
RTS-CH1
-
CLKOUT-CH1
GPO1-CH5
DATIO17
15
21
12
20
-
RxD-CH6
-
GPI2-CH6
DATIO18
37
46
37
45
CTS-CH2
-
CLKIN-CH2
GPI1-CH6
DATIO19
17
22
13
21
-
TxD-CH6
-
GPO2-CH6
DATIO20
39
47
38
46
RTS-CH2
-
CLKOUT-CH2
GPO1-CH6
DATIO21
18
23
14
22
-
RxD-CH7
-
GPI2-CH7
DATIO22
40
48
39
47
CTS-CH3
-
CLKIN-CH3
GPI1-CH7
DATIO23
20
25
16
24
-
TxD-CH7
-
GPO2-CH7
DATIO24
42
50
41
49
RTS-CH3
-
CLKOUT-CH3
GPO1-CH7
DATIO25
4
12
3
4
RxD-CH4
RxD-CH4
RxD-CH4
GPI2-CH4
DATIO26
26
37
28
29
-
-
-
GPI1-CH4
DATIO27
9
16
7
8
TxD-CH4
TxD-CH4
TxD-CH4
GPO2-CH4
DATIO28
31
41
32
33
-
-
-
GPO1-CH4
DATIO29
14
20
11
19
-
RxD-CH8
-
GPI2-CH8
DATIO30
36
45
36
44
CTS-CH4
-
CLKIN-CH4
GPI1-CH8
DATIO31
19
24
15
23
-
TxD-CH8
-
GPO2-CH8
DATIO32
41
49
40
48
RTS-CH4
-
CLKOUT-CH4
GPO1-CH8
DATIO33
6
DATIO34
28
DATIO35
11
DATIO36
33
DATIO37
16
DATIO38
38
DATIO39
21
DATIO40
43
N/A
Notes
**
SC3 sync mode available for products identified with DOM > 1/2020, Mod-HW ≥ Rev. B and FPGA/Firmware ≥ Rev. 00001.00003.
(General)
SC1, SC3. SC7 signals are referenced to system (SYS) GND (RTN).
SC3 HARDWARE BLOCK DIAGRAM
SC3 PROCESSING BLOCK DIAGRAM
FIRMWARE REVISION NOTES
For reference only - contact factory for additional clarifications. This section identifies the firmware revision in which specific features were
released. Prior revisions of the firmware would not support the features listed.
Feature
Firmware Revision
Release Date
Gap Timeout
0.00012
4/6/2018
Sync Mode
1.00003
7/24/2019
Background BIT Threshold Programming
1.00003
7/24/2019
Summary Status
1.00003
7/24/2019
REVISION HISTORY
Motherboard Manual - SC3 Revision History
Revision
Revision Date
Description
C
2022-10-05
ECO C09709, transition to docbuilder format. Pg.15, changed bit D6 to 'Reserved'; changed description to 'Set Reserved bits to 0'. Pg.15, changed D2:D0 description (1:0:0) to 'Reserved'. Pg.39, added Appendix B: Pin-Out Details.
C1
2023-03-21
ECO C10200, pg.15, changed D2:D0 description (1:0:0) to 'Loopback'.
Updated module pinout table to add module I/O pinouts for 44- & 50-pin connectors.
2025-03-28
Converted single pinout table to two tables for clarity/quality due to number of pinout options; added ‘ASYNC’ to 4CH 422/485 Flow Control Column Heading; added ‘ASYNC’ to RS232 Flow Control Column Heading; changed ‘8 CH’ to ‘4 CH’; updated pinouts in pinout column to address change in number of channels; removed ‘w/NO HW Flow’ and ‘GPIO’ from 8 CH RS232 ASYNC column heading; removed GPIO pinouts from pinout column; added ‘4 CH Serial Comms RS232 SYNC’ pinout column
2025-04-08
Updated pin-out table (revised RS-232 4-CH mode RTS/CTS & CLK-OUT/CLK-IN pins (moved from high lines to low lines)).
2025-05-07
Added note about how reading RX FIFO with register read function removes data from FIFO.
2026-04-08
Formatting updates throughout manual (non-technical changes).
STATUS AND INTERRUPTS
Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.
For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.
Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.
Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).
Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.
Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).
Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edge-triggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.
Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Interrupt Trigger Types
In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.
Example 1: Fault detection
This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.
Example 2: Threshold detection
This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.
Dynamic and Latched Status Registers Examples
The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.
Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States
No Clearing of Latched Status
Clearing of Latched Status (Edge-Triggered)
Clearing of Latched Status(Level-Triggered)
Time
Dynamic Status
Latched Status
Action
Latched Status
Action
Latched
T0
0x0
0x0
Read Latched Register
0x0
Read Latched Register
0x0
T1
0x1
0x1
Read Latched Register
0x1
0x1
T1
0x1
0x1
Write 0x1 to Latched Register
Write 0x1 to Latched Register
T1
0x1
0x1
0x0
0x1
T2
0x0
0x1
Read Latched Register
0x0
Read Latched Register
0x1
T2
0x0
0x1
Read Latched Register
0x0
Write 0x1 to Latched Register
T2
0x0
0x1
Read Latched Register
0x0
0x0
T3
0x2
0x3
Read Latched Register
0x2
Read Latched Register
0x2
T3
0x2
0x3
Write 0x2 to Latched Register
Write 0x2 to Latched Register
T3
0x2
0x3
0x0
0x2
T4
0x2
0x3
Read Latched Register
0x1
Read Latched Register
0x3
T4
0x2
0x3
Write 0x1 to Latched Register
Write 0x3 to Latched Register
T4
0x2
0x3
0x0
0x2
T5
0xC
0xF
Read Latched Register
0xC
Read Latched Register
0xE
T5
0xC
0xF
Write 0xC to Latched Register
Write 0xE to Latched Register
T5
0xC
0xF
0x0
0xC
T6
0xC
0xF
Read Latched Register
0x0
Read Latched
0xC
T6
0xC
0xF
Read Latched Register
0x0
Write 0xC to Latched Register
T6
0xC
0xF
Read Latched Register
0x0
0xC
T7
0x4
0xF
Read Latched Register
0x0
Read Latched Register
0xC
T7
0x4
0xF
Read Latched Register
0x0
Write 0xC to Latched Register
T7
0x4
0xF
Read Latched Register
0x0
0x4
T8
0x4
0xF
Read Latched Register
0x0
Read Latched Register
0x4
Interrupt Examples
The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.
Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled
Time
Latched Status (Edge-Triggered - Clear Multi-Channel)
Latched Status (Edge-Triggered - Clear Single Channel) 2+
Latched Status (Level-Triggered - Clear Multi-Channel)
Action
Latched
Action
Latched
Action
Latched
T1 (Int 1)
Interrupt Generated++``+ Read Latched Registers
0x1
Interrupt Generated++``+ Read Latched Registers
0x1
Interrupt Generated++``+ Read Latched Registers
0x1
T1 (Int 1)
Write 0x1 to Latched Register
Write 0x1 to Latched Register
Write 0x1 to Latched Register
T1 (Int 1)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear until T2.
0x1
T3 (Int 2)
Interrupt Generated++``+ Read Latched Registers
0x2
Interrupt Generated++``+ Read Latched Registers
0x2
Interrupt Generated++``+ Read Latched Registers
0x2
T3 (Int 2)
Write 0x2 to Latched Register
Write 0x2 to Latched Register
Write 0x2 to Latched Register
T3 (Int 2)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear until T7.
0x2
T4 (Int 3)
Interrupt Generated++``+ Read Latched Registers
0x1
Interrupt Generated++``+ Read Latched Registers
0x1
Interrupt Generated++``+ Read Latched Registers
0x3
T4 (Int 3)
Write 0x1 to Latched Register
Write 0x1 to Latched Register
Write 0x3 to Latched Register
T4 (Int 3)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.
0x3
T4 (Int 3)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear until T7.
0x2
T6 (Int 4)
Interrupt Generated++``+ Read Latched Registers
0xC
Interrupt Generated++``+ Read Latched Registers
0xC
Interrupt Generated++``+ Read Latched Registers
0xE
T6 (Int 4)
Write 0xC to Latched Register
Write 0x4 to Latched Register
Write 0xE to Latched Register
T6 (Int 4)
0x0
Interrupt re-triggers++``+ Write 0x8 to Latched Register
0x8
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.
0xE
T6 (Int 4)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.
0xC
T6 (Int 4)
0x0
0x0
Interrupt re-triggers++``+ Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.
0x4
REVISION HISTORY
Motherboard Manual - Status and Interrupts Revision History
Revision
Revision Date
Description
C
2021-11-30
C08896; Transition manual to docbuilder format - no technical info change.
DOCS.NAII REVISIONS
Revision Date
Description
2026-03-02
Formatting updates to document; no technical changes.
The registers described in this document are common to all NAI Generation 5 modules.
Module Information Registers
The registers in this section provide module information such as firmware revisions, capabilities and unique serial number information.
FPGA Version Registers
The FPGA firmware version registers include registers that contain the Revision, Compile Timestamp, SerDes Revision, Template Revision and Zynq Block Revision information.
FPGA Revision
Function:
FPGA firmware revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the revision of the board's FPGA
Operational Settings:
The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
FPGA Compile Timestamp
Function:
Compile Timestamp for the FPGA firmware.
Type:
unsigned binary word (32-bit)
Data Range:
N/A
Read/Write:
R
Initialized Value:
Value corresponding to the compile timestamp of the board's FPGA
Operational Settings:
The 32-bit value represents the Day, Month, Year, Hour, Minutes and Seconds as formatted in the table:
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
day (5-bits)
month (4-bits)
year (6-bits)
hr
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
hour (5-bits)
minutes (6-bits)
seconds (6-bits)
FPGA SerDes Revision
Function:
FPGA SerDes revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the SerDes revision of the board's FPGA
Operational Settings:
The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
FPGA Template Revision
Function:
FPGA Template revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the template revision of the board's FPGA
Operational Settings:
The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
FPGA Zynq Block Revision
Function:
FPGA Zynq Block revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the Zynq block revision of the board's FPGA
Operational Settings:
The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
Bare Metal Version Registers
The Bare Metal firmware version registers include registers that contain the Revision and Compile Time information.
Bare Metal Revision
Function:
Bare Metal firmware revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the revision of the board's Bare Metal
Operational Settings:
The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
Bare Metal Compile Time
Function:
Provides an ASCII representation of the Date/Time for the Bare Metal compile time.
Type:
24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range:
N/A
Read/Write:
R
Initialized Value:
Value corresponding to the ASCII representation of the compile time of the board's Bare Metal
Operational Settings:
The six 32-bit words provide an ASCII representation of the Date/Time. The hexadecimal values in the field below represent: May 17 2019 at 15:38:32
Note
little-endian order of ASCII values
Word 1 (Ex. 0x2079614D)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Space (0x20)
Month ('y' - 0x79)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Month ('a' - 0x61)
Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Year ('2' - 0x32)
Space (0x20)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Day ('7' - 0x37)
Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Space (0x20)
Year ('9' - 0x39)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Year ('1' - 0x31)
Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Hour ('1' - 0x31)
Space (0x20)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
'a' (0x74)
't' (0x61)
Word 5 (Ex. 0x38333A35)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Minute ('8' - 0x38)
Minute ('3' - 0x33)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
':' (0x3A)
Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
NULL (0x00)
Seconds ('2' - 0x32)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Seconds ('3' - 0x33)
':' (0x3A)
FSBL Version Registers
The FSBL version registers include registers that contain the Revision and Compile Time information for the First Stage Boot Loader (FSBL).
FSBL Revision
Function:
FSBL firmware revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the revision of the board's FSBL
Operational Settings:
The upper 16-bits are the major revision, and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
FSBL Compile Time
Function:
Provides an ASCII representation of the Date/Time for the FSBL compile time.
Type:
24-character ASCII string - Six (6) unsigned binary word (32-bit)
Data Range:
N/A
Read/Write:
R
Initialized Value:
Value corresponding to the ASCII representation of the Compile Time of the board's FSBL
Operational Settings:
The six 32-bit words provide an ASCII representation of the Date/Time.
The hexadecimal values in the field below represent: May 17 2019 at 15:38:32
Note
little-endian order of ASCII values
Word 1 (Ex. 0x2079614D)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Space (0x20)
Month ('y' - 0x79)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Month ('a' - 0x61)
Month ('M' - 0x4D)
Word 2 (Ex. 0x32203731)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Year ('2' - 0x32)
Space (0x20)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Day ('7' - 0x37)
Day ('1' - 0x31)
Word 3 (Ex. 0x20393130)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Space (0x20)
Year ('9' - 0x39)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Year ('1' - 0x31)
Year ('0' - 0x30)
Word 4 (Ex. 0x31207461)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Hour ('1' - 0x31)
Space (0x20)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
'a' (0x74)
't' (0x61)
Word 5 (Ex. 0x38333A35)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Minute ('8' - 0x38)
Minute ('3' - 0x33)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
':' (0x3A)
Hour ('5' - 0x35)
Word 6 (Ex. 0x0032333A)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
NULL (0x00)
Seconds ('2' - 0x32)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Seconds ('3' - 0x33)
':' (0x3A)
Module Serial Number Registers
The Module Serial Number registers include registers that contain the Serial Numbers for the Interface Board and the Functional Board of the module.
Interface Board Serial Number
Function:
Unique 128-bit identifier used to identify the interface board.
Type:
16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range:
N/A
Read/Write:
R
Initialized Value:
Serial number of the interface board
Operational Settings:
This register is for information purposes only.
Functional Board Serial Number
Function:
Unique 128-bit identifier used to identify the functional board.
Type:
16-character ASCII string - Four (4) unsigned binary words (32-bit)
Data Range:
N/A
Read/Write:
R
Initialized Value:
Serial number of the functional board
Operational Settings:
This register is for information purposes only.
Module Capability
Function:
Provides indication for whether or not the module can support the following: SerDes block reads, SerDes FIFO block reads, SerDes packing (combining two 16-bit values into one 32-bit value) and floating point representation. The purpose for block access and packing is to improve the performance of accessing larger amounts of data over the SerDes interface.
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0x0000 0107
Read/Write:
R
Initialized Value:
0x0000 0107
Operational Settings:
A “1” in the bit associated with the capability indicates that it is supported.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
Flt-Pt
0
0
0
0
0
Pack
FIFO Blk
Blk
Module Memory Map Revision
Function:
Module Memory Map revision
Type:
unsigned binary word (32-bit)
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the Module Memory Map Revision
Operational Settings:
The upper 16-bits are the major revision and the lower 16-bits are the minor revision.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Major Revision Number
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Minor Revision Number
Module Measurement Registers
The registers in this section provide module temperature measurement information.
Temperature Readings Registers
The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) Zynq and PCB temperatures.
Interface Board Current Temperature
Function:
Measured PCB and Zynq Core temperatures on Interface Board.
Type:
signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:
0x0000 0000 to 0x0000 FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the measured PCB and Zynq core temperatures based on the table below
Operational Settings:
The upper 16-bits are not used, and the lower 16-bits are the PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 202C, this represents PCB Temperature = 32° Celsius and Zynq Temperature = 44° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PCB Temperature
Zynq Core Temperature
Functional Board Current Temperature
Function:
Measured PCB temperature on Functional Board.
Type:
signed byte (8-bits) for PCB
Data Range:
0x0000 0000 to 0x0000 00FF
Read/Write:
R
Initialized Value:
Value corresponding to the measured PCB on the table below
Operational Settings:
The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0019, this represents PCB Temperature = 25° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
PCB Temperature
Interface Board Maximum Temperature
Function:
Maximum PCB and Zynq Core temperatures on Interface Board since power-on.
Type:
signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:
0x0000 0000 to 0x0000 FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the maximum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings:
The upper 16-bits are not used, and the lower 16-bits are the maximum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 5569, this represents maximum PCB Temperature = 85° Celsius and maximum Zynq Temperature = 105° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PCB Temperature
Zynq Core Temperature
Interface Board Minimum Temperature
Function:
Minimum PCB and Zynq Core temperatures on Interface Board since power-on.
Type:
signed byte (8-bits) for PCB and signed byte (8-bits) for Zynq core temperatures
Data Range:
0x0000 0000 to 0x0000 FFFF
Read/Write:
R
Initialized Value:
Value corresponding to the minimum measured PCB and Zynq core temperatures since power-on based on the table below
Operational Settings:
The upper 16-bits are not used, and the lower 16-bits are the minimum PCB and Zynq Core Temperatures. For example, if the register contains the value 0x0000 D8E7, this represents minimum PCB Temperature = -40° Celsius and minimum Zynq Temperature = -25° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PCB Temperature
Zynq Core Temperature
Functional Board Maximum Temperature
Function:
Maximum PCB temperature on Functional Board since power-on.
Type:
signed byte (8-bits) for PCB
Data Range:
0x0000 0000 to 0x0000 00FF
Read/Write:
R
Initialized Value:
Value corresponding to the measured PCB on the table below
Operational Settings:
The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 0055, this represents PCB Temperature = 85° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
PCB Temperature
Functional Board Minimum Temperature
Function:
Minimum PCB temperature on Functional Board since power-on.
Type:
signed byte (8-bits) for PCB
Data Range:
0x0000 0000 to 0x0000 00FF
Read/Write:
R
Initialized Value:
Value corresponding to the measured PCB on the table below
Operational Settings:
The upper 24-bits are not used, and the lower 8-bits are the PCB Temperature. For example, if the register contains the value 0x0000 00D8, this represents PCB Temperature = -40° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
PCB Temperature
Higher Precision Temperature Readings Registers
These registers provide higher precision readings of the current Zynq and PCB temperatures.
Higher Precision Zynq Core Temperature
Function:
Higher precision measured Zynq Core temperature on Interface Board.
Type:
signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Measured Zynq Core temperature on Interface Board
Operational Settings:
The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 0271, this represents Zynq Core Temperature = 43.625° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.
signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Measured Interface PCB temperature
Operational Settings:
The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x0020 007D, this represents Interface PCB Temperature = 32.125° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.
signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:
0x0000 0000 to 0xFFFF FFFF
Read/Write:
R
Initialized Value:
Measured Functional PCB temperature
Operational Settings:
The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/100 of degree Celsius. For example, if the register contains the value 0x0018 004B, this represents Functional PCB Temperature = 24.75° Celsius, and value 0xFFD9 0019 represents -39.25° Celsius.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Signed Integer Part of Temperature
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Fractional Part of Temperature
Module Health Monitoring Registers
The registers in this section provide module temperature measurement information. If the temperature measurements reaches the Lower Critical or Upper Critical conditions, the module will automatically reset itself to prevent damage to the hardware.
Module Sensor Summary Status
Function:
The corresponding sensor bit is set if the sensor has crossed any of its thresholds.
Type:
unsigned binary word (32-bits)
Data Range:
See table below
Read/Write:
R
Initialized Value:
0
Operational Settings:
This register provides a summary for module sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.
Bit(s)
Sensor
D31:D6
Reserved
D5
Functional Board PCB Temperature
D4
Interface Board PCB Temperature
D3:D0
Reserved
Module Sensor Registers
The registers listed in this section apply to each module sensor listed for the Module Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring module temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Interface Board PCB Temperature sensor as an example.
Sensor Threshold Status
Function:
Reflects which threshold has been crossed
Type:
unsigned binary word (32-bits)
Data Range:
See table below
Read/Write:
R
Initialized Value:
0
Operational Settings:
The associated bit is set when the sensor reading exceed the corresponding threshold settings.
Bit(s)
Description
D31:D4
Reserved
D3
Exceeded Upper Critical Threshold
D2
Exceeded Upper Warning Threshold
D1
Exceeded Lower Critical Threshold
D0
Exceeded Lower Warning Threshold
Sensor Current Reading
Function:
Reflects current reading of temperature sensor
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R
Initialized Value:
N/A
Operational Settings:
The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Minimum Reading
Function:
Reflects minimum value of temperature sensor since power up
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R
Initialized Value:
N/A
Operational Settings:
The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Maximum Reading
Function:
Reflects maximum value of temperature sensor since power up
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R
Initialized Value:
N/A
Operational Settings:
The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.
Sensor Lower Warning Threshold
Function:
Reflects lower warning threshold of temperature sensor
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R/W
Initialized Value:
Default lower warning threshold (value dependent on specific sensor)
Operational Settings:
The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.
Sensor Lower Critical Threshold
Function:
Reflects lower critical threshold of temperature sensor
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R/W
Initialized Value:
Default lower critical threshold (value dependent on specific sensor)
Operational Settings:
The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.
Sensor Upper Warning Threshold
Function:
Reflects upper warning threshold of temperature sensor
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R/W
Initialized Value:
Default upper warning threshold (value dependent on specific sensor)
Operational Settings:
The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.
Sensor Upper Critical Threshold
Function:
Reflects upper critical threshold of temperature sensor
Type:
Single Precision Floating Point Value (IEEE-754)
Data Range:
Single Precision Floating Point Value (IEEE-754)
Read/Write:
R/W
Initialized Value:
Default upper critical threshold (value dependent on specific sensor)
Operational Settings:
The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.
Motherboard Manual - Module Common Registers Revision History
Revision
Revision Date
Description
C
2023-08-11
ECO C10649, initial release of module common registers manual.
C1
2024-05-15
ECO C11522, removed Zynq Core/Aux/DDR Voltage register descriptions from Module Measurement Registers. Pg.16, updated Module Sensor Summary Status register to add PS references; updated Bit Table to change voltage/current bits to 'reserved'. Pg.16, updated Module/Power Supply Sensor Registers description to better describe register functionality and to add figure. Pg.17, added 'Exceeded' to threshold bit descriptions. Pg.17-18, removed voltage/current references from sensor descriptions. Pg.20, removed Zynq Core/Aux/DDR Voltage register offsets from Module Measurement Registers. Pg.20, updated Module Health Monitoring Registers offset tables.
C2
2024-07-10
ECO C11701, pg.16, updated Module Sensor Summary Status register to remove PS references;updated Bit Table to change PS temperature bits to 'reserved'. Pg.16, updated Module SensorRegisters description to remove PS references. Pg.20, updated Module Health MonitoringRegisters offset tables to remove PS temperature register offsets.
DOCS.NAII REVISIONS
Revision Date
Description
2025-11-05
Corrected register offsets for Interface Board Min Temp and Function Board Min & Max Temps.
2026-03-02
Formatting updates to document; no technical changes.
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Figure 1. Example of Module’s Channel-Mapped Dynamic and Latched Status States
Figure 2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled
