NAI Documentation

THRESHOLD AND SATURATION CAPABILITY

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THRESHOLD AND SATURATION CAPABILITY

The Threshold and Saturation Capability is available on the following modules:

  • Analog-to-Digital (A/D) Modules

    • AD1 - 12 Channels Analog-to-Digital (Voltage Input Only) (±10 to ±1.25 VDC FSR)

    • AD2 - 12 Channels Analog-to-Digital (Voltage Input Only) (±100 to ±12.5 VDC FSR)

    • AD3 - 12 Channels Analog-to-Digital (Current Input Only) (±25 mA FSR)

    • AD4 - 16 Channels Analog-to-Digital (±10.0 to ±1.25 VDC or ±25 mA FSR)

    • AD5 - 16 Channels Analog-to-Digital (±50.0 to ±6.25 VDC FSR)

    • AD6 - 16 Channels Analog-to-Digital (±100 to ±12.5 VDC FSR)

    • ADE - 16 Channels Analog-to-Digital (Voltage Input Only) (±10 to ±0.625 VDC FSR)

    • ADF - 16 Channels Analog-to-Digital (Voltage Input Only) (±100 to ±6.25 VDC FSR)

PRINCIPLE OF OPERATION

The AD modules provide the ability to monitor the acquired data and set a status when the specific thresholds are reached.

Threshold Detect

There are two thresholds that can be independently programmed on the A/D modules. These thresholds are used to monitor the acquired data and set a status when the specified thresholds are reached. A configurable hysteresis may also be set to determine when the Threshold Detect registers are cleared. The threshold detection can be configured as a FIFO trigger to capture data based on a specified event. Refer to Figure 1 and Figure 2 for illustrations for Threshold Detect Programming.

Figure 1. Threshold Programming with Hysteresis

Figure 2. Threshold Programming with No Hysteresis

Saturation Programming

A low and high saturation setting that can be independently programmed on the A/D modules. These saturation values are used to monitor the acquired data and set a status when the specified saturation is reached as well as setting the A/D reading to the saturation value. Saturation programming can be used to prevent the A/D reading from exceeding the saturation value. Refer to Figure 3 for illustrations of Saturation Programming

Figure 3. Saturation Programming

REGISTER DESCRIPTIONS

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

Threshold Detect Programming Registers

There are two threshold and hysteresis registers that can be independently programmed on the A/D modules.

Threshold Detect Level

The Threshold Detect Level registers sets the first and second threshold level values.

Threshold Detect Level 1
Function:Sets the first threshold level value
Type:signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:Voltage Threshold Level values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) `      Unipolar: (AD4-AD6, ADE-ADF) 0x0000 0000 to 0x0000 FFFF `                      (AD1-AD3): 0x0000 0000 to 0x00FF FFFF `      Bipolar (2's complement. 24-bit value sign extended to 32 bits): `                      (AD4-AD6, ADE-ADF) 0xFFFF 8000 to 0x0000 7FFF; `                      (AD1-AD3): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:R/W
Initialized Value:90% of full scale (bipolar)
Threshold Detect Level 2
Function:Sets the second threshold level value.
Type:signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:Voltage Threshold Level values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) `      Unipolar: (AD4-AD6, ADE-ADF) 0x0000 0000 to 0x0000 FFFF `                      (AD1-AD3): 0x0000 0000 to 0x00FF FFFF `      Bipolar (2's complement. 24-bit value sign extended to 32 bits): `                      (AD4-AD6, ADE-ADF) 0xFFFF 8000 to 0x0000 7FFF; `                      (AD1-AD3): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:R/W
Initialized Value:-90% of full scale (bipolar)

Threshold Detect Hysteresis

The Threshold Detect Hysteresis registers sets the first and second threshold hysteresis values. Note, the hysteresis value must be a positive value.

Threshold Detect Hysteresis 1
Function:Sets the first threshold hysteresis value. This value must be positive.
Type:signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:Voltage Threshold Hysteresis values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) `      Unipolar: (AD4-AD6, ADE-ADF) 0x0000 0000 to 0x0000 FFFF `                      (AD1-AD3): 0x0000 0000 to 0x00FF FFFF `      Bipolar (2's complement. 24-bit value sign extended to 32 bits): `                      (AD4-AD6, ADE-ADF) 0xFFFF 8000 to 0x0000 7FFF; `                      (AD1-AD3): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:R/W
Initialized Value:0
Threshold Detect Hysteresis 2
Function:Sets the second threshold hysteresis value. This value must be positive.
Type:signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:Voltage Threshold Hysteresis values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) `      Unipolar: (AD4-AD6, ADE-ADF) 0x0000 0000 to 0x0000 FFFF `                      (AD1-AD3): 0x0000 0000 to 0x00FF FFFF `      Bipolar (2's complement. 24-bit value sign extended to 32 bits): `                      (AD4-AD6, ADE-ADF) 0xFFFF 8000 to 0x0000 7FFF; `                      (AD1-AD3): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:R/W
Initialized Value:0

Threshold Detect Control

Threshold Detect Control
Function:Sets up detect control for the two thresholds for each channel.
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R/W
Initialized Value:0
Operational Settings:Set bit to 0 to detect above the threshold level. Set bit to 1 to detect below the threshold level.
AD1-AD3
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
00000000Ch12Ch11Ch10Ch9
T2T1T2T1T2T1T2T1
DDDDDDDD
AD4-AD6 and ADE-ADF
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9
T2T1T2T1T2T1T2T1T2T1T2T1T2T1T2T1
DDDDDDDDDDDDDDDD
All A/D Modules
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch8Ch7Ch6Ch5Ch4Ch3Ch2Ch1
T2T1T2T1T2T1T2T1T2T1T2T1T2T1T2T1
DDDDDDDDDDDDDDDD

Saturation Programming Registers

A low and high saturation setting that can be independently programmed on the A/D modules.

Saturation Value

The Low Saturation Value registers sets value to report as A/D reading and sets the Saturation Status bit when the A/D data is below the low saturation value. The High Saturation Value registers sets value to report as A/D reading and sets the Saturation Status bit when the A/D data is above the high saturation value.

Low Saturation
Function:Sets the low saturation value.
Type:signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:Saturation Voltage values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) `      Unipolar: (AD4-AD6, ADE-ADF) 0x0000 0000 to 0x0000 FFFF `                      (AD1-AD3): 0x0000 0000 to 0x00FF FFFF `      Bipolar (2's complement. 24-bit value sign extended to 32 bits): `                      (AD4-AD6, ADE-ADF) 0xFFFF 8000 to 0x0000 7FFF; `                      (AD1-AD3): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:R/W
Initialized Value:0
High Saturation
Function:Sets the high saturation value.
Type:signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:Saturation Voltage values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) `      Unipolar: (AD4-AD6, ADE-ADF) 0x0000 0000 to 0x0000 FFFF `                      (AD1-AD3): 0x0000 0000 to 0x00FF FFFF `      Bipolar (2's complement. 24-bit value sign extended to 32 bits): `                      (AD4-AD6, ADE-ADF) 0xFFFF 8000 to 0x0000 7FFF; `                      (AD1-AD3): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:R/W
Initialized Value:0
Saturation Control
Function:Sets up saturation control for the two saturation levels for each channel.
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0xFFFF FFFF
Read/Write:R/W
Initialized Value:0
Operational Settings:Set bits to 1 to enable Saturation Control. Set bits to 0 to disable Saturation Control. Each channel control consists of two bits: Low Saturation Control ("Even' bits (B0, B2, B4,...)) and High Saturation Control ("Odd' bits (B1, B3, B5,...)).
AD1-AD3
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
00000000Ch12Ch11Ch10Ch9
HighLowHighLowHighLowHighLow
DDDDDDDD
AD4-AD6 and ADE-ADF
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9
HighLowHighLowHighLowHighLowHighLowHighLowHighLowHighLow
DDDDDDDDDDDDDDDD
All A/D Modules
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch8Ch7Ch6Ch5Ch4Ch3Ch2Ch1
HighLowHighLowHighLowHighLowHighLowHighLowHighLowHighLow
DDDDDDDDDDDDDDDD

Status and Interrupt

The A/D Module provides status registers for Threshold Detect and Saturation.

Threshold Detect Status

There are four registers associated with the Threshold Detect Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

0 = Normal; 1 = Outside of threshold range. The status is created based on the values set in the Threshold Detect 1 and Threshold Detect 2 registers. Bits D0 and D1 represent if channel 1 is outside the threshold for Threshold Detect 1 and Threshold Detect 2 respectively, Bits D2 and D3 represent if channel 2 is outside the threshold for Threshold Detect 1 and Threshold Detect 2 respectively, etc. This pattern continues for all channels.

Threshold Detect Status
Function:Sets the corresponding bit associated with the channel's Threshold Detect error.
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0x00FF FFFF
Read/Write:R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:0
Threshold Detect Dynamic Status
Threshold Detect Latched Status
Threshold Detect Interrupt Enable
Threshold Detect Set Edge/Level Interrupt
AD1-AD3
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
00000000Ch12Ch11Ch10Ch9
T2T1T2T1T2T1T2T1
DDDDDDDD
AD4-AD6 and ADE-ADF
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9
T2T1T2T1T2T1T2T1T2T1T2T1T2T1T2T1
DDDDDDDDDDDDDDDD
All A/D Modules
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch8Ch7Ch6Ch5Ch4Ch3Ch2Ch1
T2T1T2T1T2T1T2T1T2T1T2T1T2T1T2T1
DDDDDDDDDDDDDDDD

Saturation Status

There are four registers associated with the Saturation Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

0 = Normal; 1 = Outside of saturation range. The status is created based on the values set in the Low Saturation and High Saturation registers. Bits D0 and D1 represent if channel 1 is outside the voltage for Low Saturation and High Saturation respectively, Bits D2 and D3 represent if channel 2 is outside the voltage for Low Saturation and High Saturation respectively, etc. This pattern continues for all channels.

Saturation Status
Function:Sets the corresponding bit associated with the channel's Saturation error.
Type:unsigned binary word (32-bit)
Data Range:0x0000 0000 to 0x00FF FFFF
Read/Write:R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:0
Saturation Dynamic Status
Saturation Latched Status
Saturation Interrupt Enable
Saturation Set Edge/Level Interrupt
AD1-AD3
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
00000000Ch12Ch11Ch10Ch9
HighLowHighLowHighLowHighLow
DDDDDDDD
AD4-AD6 and ADE-ADF
D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16
Ch16Ch15Ch14Ch13Ch12Ch11Ch10Ch9
HighLowHighLowHighLowHighLowHighLowHighLowHighLowHighLow
DDDDDDDDDDDDDDDD
All A/D Modules
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Ch8Ch7Ch6Ch5Ch4Ch3Ch2Ch1
HighLowHighLowHighLowHighLowHighLowHighLowHighLowHighLow
DDDDDDDDDDDDDDDD

FUNCTION REGISTER MAP

KEY

Configuration/Control
State/Measurement/Status
THRESHOLD DETECT PROGRAMMING REGISTERS
**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).
NOTE: Base Address - 0x4000 0000
OFFSETREGISTER NAMEACCESSOFFSETREGISTER NAMEACCESS
All A/D Modules
0x1980Threshold Detect Level 1 Ch 1**R/W0x1A00Threshold Detect Level 1 Hysteresis Ch 1**R/W
0x1984Threshold Detect Level 1 Ch 2**R/W0x1A04Threshold Detect Level 1 Hysteresis Ch 2**R/W
0x1988Threshold Detect Level 1 Ch 3**R/W0x1A08Threshold Detect Level 1 Hysteresis Ch 3**R/W
0x198CThreshold Detect Level 1 Ch 4**R/W0x1A0CThreshold Detect Level 1 Hysteresis Ch 4**R/W
0x1990Threshold Detect Level 1 Ch 5**R/W0x1A10Threshold Detect Level 1 Hysteresis Ch 5**R/W
0x1994Threshold Detect Level 1 Ch 6**R/W0x1A14Threshold Detect Level 1 Hysteresis Ch 6**R/W
0x1998Threshold Detect Level 1 Ch 7**R/W0x1A18Threshold Detect Level 1 Hysteresis Ch 7**R/W
0x199CThreshold Detect Level 1 Ch 8**R/W0x1A1CThreshold Detect Level 1 Hysteresis Ch 8**R/W
0x19A0Threshold Detect Level 1 Ch 9**R/W0x1A20Threshold Detect Level 1 Hysteresis Ch 9**R/W
0x19A4Threshold Detect Level 1 Ch 10**R/W0x1A24Threshold Detect Level 1 Hysteresis Ch 10**R/W
0x19A8Threshold Detect Level 1 Ch 11**R/W0x1A28Threshold Detect Level 1 Hysteresis Ch 11**R/W
0x19ACThreshold Detect Level 1 Ch 12**R/W0x1A2CThreshold Detect Level 1 Hysteresis Ch 12**R/W
AD4-AD6, ADE-ADF
0x19B0Threshold Detect Level 1 Ch 13**R/W0x1A30Threshold Detect Level 1 Hysteresis Ch 13**R/W
0x19B4Threshold Detect Level 1 Ch 14**R/W0x1A34Threshold Detect Level 1 Hysteresis Ch 14**R/W
0x19B8Threshold Detect Level 1 Ch 15**R/W0x1A38Threshold Detect Level 1 Hysteresis Ch 15**R/W
0x19BCThreshold Detect Level 1 Ch 16**R/W0x1A3CThreshold Detect Level 1 Hysteresis Ch 16**R/W
All A/D Modules
0x1A80Threshold Detect Level 2 Ch 1**R/W0x1B00Threshold Detect Level 2 Hysteresis Ch 1**R/W
0x1A84Threshold Detect Level 2 Ch 2**R/W0x1B04Threshold Detect Level 2 Hysteresis Ch 2**R/W
0x1A88Threshold Detect Level 2 Ch 3**R/W0x1B08Threshold Detect Level 2 Hysteresis Ch 3**R/W
0x1A8CThreshold Detect Level 2 Ch 4**R/W0x1B0CThreshold Detect Level 2 Hysteresis Ch 4**R/W
0x1A90Threshold Detect Level 2 Ch 5**R/W0x1B10Threshold Detect Level 2 Hysteresis Ch 5**R/W
0x1A94Threshold Detect Level 2 Ch 6**R/W0x1B14Threshold Detect Level 2 Hysteresis Ch 6**R/W
0x1A98Threshold Detect Level 2 Ch 7**R/W0x1B18Threshold Detect Level 2 Hysteresis Ch 7**R/W
0x1A9CThreshold Detect Level 2 Ch 8**R/W0x1B1CThreshold Detect Level 2 Hysteresis Ch 8**R/W
0x1AA0Threshold Detect Level 2 Ch 9**R/W0x1B20Threshold Detect Level 2 Hysteresis Ch 9**R/W
0x1AA4Threshold Detect Level 2 Ch 10**R/W0x1B24Threshold Detect Level 2 Hysteresis Ch 10**R/W
0x1AA8Threshold Detect Level 2 Ch 11**R/W0x1B28Threshold Detect Level 2 Hysteresis Ch 11**R/W
0x1AACThreshold Detect Level 2 Ch 12**R/W0x1B2CThreshold Detect Level 2 Hysteresis Ch 12**R/W
AD4-AD6, ADE-ADF
0x1AB0Threshold Detect Level 2 Ch 13**R/W0x1B30Threshold Detect Level 2 Hysteresis Ch 13**R/W
0x1AB4Threshold Detect Level 2 Ch 14**R/W0x1B34Threshold Detect Level 2 Hysteresis Ch 14**R/W
0x1AB8Threshold Detect Level 2 Ch 15**R/W0x1B38Threshold Detect Level 2 Hysteresis Ch 15**R/W
0x1ABCThreshold Detect Level 2 Ch 16**R/W0x1B3CThreshold Detect Level 2 Hysteresis Ch 16**R/W
0x1C80Threshold Detect ControlR/W
SATURATION PROGRAMMING REGISTERS
**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).
NOTE: Base Address - 0x4000 0000
OFFSETREGISTER NAMEACCESSOFFSETREGISTER NAMEACCESS
All A/D Modules
0x1B80Low Saturation Value Ch 1**R/W0x1C00High Saturation Value Ch 1**R/W
0x1B84Low Saturation Value Ch 2**R/W0x1C04High Saturation Value Ch 2**R/W
0x1B88Low Saturation Value Ch 3**R/W0x1C08High Saturation Value Ch 3**R/W
0x1B8CLow Saturation Value Ch 4**R/W0x1C0CHigh Saturation Value Ch 4**R/W
0x1B90Low Saturation Value Ch 5**R/W0x1C10High Saturation Value Ch 5**R/W
0x1B94Low Saturation Value Ch 6**R/W0x1C14High Saturation Value Ch 6**R/W
0x1B98Low Saturation Value Ch 7**R/W0x1C18High Saturation Value Ch 7**R/W
0x1B9CLow Saturation Value Ch 8**R/W0x1C1CHigh Saturation Value Ch 8**R/W
0x1BA0Low Saturation Value Ch 9**R/W0x1C20High Saturation Value Ch 9**R/W
0x1BA4Low Saturation Value Ch 10**R/W0x1C24High Saturation Value Ch 10**R/W
0x1BA8Low Saturation Value Ch 11**R/W0x1C28High Saturation Value Ch 11**R/W
0x1BACLow Saturation Value Ch 12**R/W0x1C2CHigh Saturation Value Ch 12**R/W
AD4-AD6, ADE-ADF
0x1BB0Low Saturation Value Ch 13**R/W0x1C30High Saturation Value Ch 13**R/W
0x1BB4Low Saturation Value Ch 14**R/W0x1C34High Saturation Value Ch 14**R/W
0x1BB8Low Saturation Value Ch 15**R/W0x1C38High Saturation Value Ch 15**R/W
0x1BBCLow Saturation Value Ch 16**R/W0x1C3CHigh Saturation Value Ch 16**R/W
0x1C90Saturation ControlR/W
STATUS REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x4000 0000
OFFSETREGISTER NAMEACCESSOFFSETREGISTER NAMEACCESS
ThresholdSaturation
0x0940Dynamic StatusR0x0960Dynamic StatusR
0x0944Latched Status*R/W0x0964Latched Status*R/W
0x0948Interrupt EnableR/W0x0968Interrupt EnableR/W
0x094CSet Edge/Level InterruptR/W0x096CSet Edge/Level InterruptR/W
INTERRUPT REGISTERS
The Interrupt Vector and Interrupt Steering registers are located on the Motherboard Memory Space and do not require any Module Address Offsets. These registers are accessed using the absolute addresses listed in the table below.
OFFSETREGISTER NAMEACCESSOFFSETREGISTER NAMEACCESS
0x0550Module 1 Interrupt Vector 21 - Threshold StatusR/W0x0650Module 1 Interrupt Steering 21 - Threshold StatusR/W
0x0558Module 1 Interrupt Vector 23 - Saturation StatusR/W0x0658Module 1 Interrupt Steering 23 - Saturation StatusR/W
0x0750Module 2 Interrupt Vector 21 - Threshold StatusR/W0x0850Module 2 Interrupt Steering 21 - Threshold StatusR/W
0x0758Module 2 Interrupt Vector 23 - Saturation StatusR/W0x0858Module 2 Interrupt Steering 23 - Saturation StatusR/W
0x0950Module 3 Interrupt Vector 21 - Threshold StatusR/W0x0A50Module 3 Interrupt Steering 21 - Threshold StatusR/W
0x0958Module 3 Interrupt Vector 23 - Saturation StatusR/W0x0A58Module 3 Interrupt Steering 23 - Saturation StatusR/W
0x0B50Module 4 Interrupt Vector 21 - Threshold StatusR/W0x0C50Module 4 Interrupt Steering 21 - Threshold StatusR/W
0x0B58Module 4 Interrupt Vector 23 - Saturation StatusR/W0x0C58Module 4 Interrupt Steering 23 - Saturation StatusR/W
0x0D50Module 5 Interrupt Vector 21 - Threshold StatusR/W0x0E50Module 5 Interrupt Steering 21 - Threshold StatusR/W
0x0D58Module 5 Interrupt Vector 23 - Saturation StatusR/W0x0E58Module 5 Interrupt Steering 23 - Saturation StatusR/W
0x0F50Module 6 Interrupt Vector 21 - Threshold StatusR/W0x1050Module 6 Interrupt Steering 21 - Threshold StatusR/W
0x0F58Module 6 Interrupt Vector 23 - Saturation StatusR/W0x1058Module 6 Interrupt Steering 23 - Saturation StatusR/W

REVISION HISTORY

Module Manual - AD Threshold and Saturation Programming Revision History
RevisionRevision DateDescription
C2021-11-30C08896; Transition manual to docbuilder format - no technical information change.
C12022-03-16C09163, pg.15-17, changed "AD4-AD4" to "AD4-AD6".
C22023-01-24ECO C010010, pg.8-9/11, added 24-bit integer mode data ranges.
C32023-06-20ECO C10476, removed all ADG module references from manual.
C42024-04-18ECO C11441, spelling correction ('2's compliment' to '2's complement); no technical info change.

DOCS.NAII REVISIONS

Revision DateDescription
2026-05-18Formatting updates throughout manual (non-technical changes).
NAI Docs Assistant
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