INTRODUCTION
This manual provides information about the North Atlantic Industries, Inc. (NAI) NIU3R System. The NIU3R is a “Nano Interface Unit”; self-contained Multifunction I/O System preconfigured with 8-CH programmable Discrete I/O, 4-CH Discrete Isolated Switching, 10-CH Serial, and 1-CH MIL-STD-1760 functions. The NIU3R boasts a dual ARM ®Cortex®-A53 processor for customer application and I/O and communications management.
For a brief description of the system and complete list of features, click here for the NIU3R data sheet.
SOFTWARE SUPPORT
The ENAIBL Software Support Kit (SSK) is supplied with all system platform based board level products. This platform’s SSK contents include html format help documentation which defines board specific library functions and their respective parameter requirements. A board specific library and its source code is provided (module level ‘C’ and header files) to facilitate function implementation independent of user operating system (O/S). Portability files are provided to identify Board Support Package (BSP) dependent functions and help port code to other common system BSPs. With the use of the provided help documentation, these libraries are easily ported to any 32-bit O/S such as RTOS or Linux.
The latest version of a board specific SSK can be downloaded from our website www.naii.com in the software downloads section. A Quick-Start Software Manual is also available for download where the SSK contents are detailed, Quick-Start Instructions provided and GUI applications are described therein. For other operating system support, contact factory.
CONVENTIONS USED IN THIS MANUAL
Note
An operating procedure, practice, or condition, etc., that is essential to emphasize.
All numbers are expressed in decimal format unless otherwise noted.
Website
GENERAL SAFETY NOTICES
The following general safety notices supplement the specific warnings and cautions appearing elsewhere in the manual. They are recommended precautions that must be understood and applied during operation and maintenance of the instrument covered herein.
Death or serious injury may result if personnel fail to observe safety precautions. Dependent on configuration, some modules (e.g. Synchro / Resolver or AC signal sources) can generate output signals with high voltages. Be careful not to contact high-voltage connections when installing, operating or maintaining this instrument.
The NIU3R is delivered as a standalone system with no accessible or serviceable parts.
Repair
DO NOT ATTEMPT REPAIR. Under no circumstances should repair of this instrument be attempted. All repairs to this chassis must be accomplished at the factory.
High Voltage
HIGH VOLTAGE may be used in the operation of this equipment.
Input Power Always On
Note
The design of the model NIU3R is such that DC input power is continuously supplied to internal circuits when connected to a main power source. To disconnect the NIU3R from external power, the external power source should first be de-energized. The power input cable can then be disconnected.
SYSTEM SPECIFICATIONS & DETAILS
Introduction
The Nano Interface Unit (NIU3R) is an integrated, compact, “nano-sized” subsystem with I/O capability configurations. The NIU3R connects to existing platform Ethernet networks, making data available to any system on the network. Additionally, the NIU3R is delivered with ARM® Cortex®-A53 access support for standalone or other processor related capability. The NIU3R easily adds sensor data acquisition and distribution and communication interfaces to mission computers without expensive chassis and backplane redesign. It has been designed with rugged embedded industrial, military and aerospace applications in mind.
This approach provides unprecedented flexibility for supporting existing or new applications where there are specific interfacing requirements.
Significant application benefits include:
-
Independent (pre-processed) I/O functionality targeted to specific data acquisition/control areas
-
Additional capabilities, technology insertion and sensor interfacing to existing fielded applications
-
Minimal integration risk based on current field-proven, deployed technologies
-
Only ~6.2” x 5.8” x 1.6” @ ~2.5 lbs. (1.13 kg) conduction cooled
-
4x Ethernet
- 10/100/1000Base-T (GbE) (default)
- 1 Gb Fiber Optic 850 nm (option)
Objectives
This manual provides the user with basic hardware implementation and information regarding the operation and interface of the NIU3R. Each NIU3R is fitted with, four embedded module functions, dual-core processor and an integrated motherboard, power supply unit (PSU) and interface connectors.
Scope
This manual covers the basic operation of the NIU3R as a standalone I/O subsystem with pertinent/specific details relating to the operation/communications from/to the NIU3R with the available function module(s) fitted within the NIU3R.
ON BOARD RESOURCES
Memory
DDR4 SDRAM
The NIU3R provides a total of 4 GB of LPDDR4 memory. This memory is organized as 1 1Gb x 16 MT53E1G32D2 device (parts may vary). The Ultrascale+™ has an on chip 64-bit DDR4 memory controller. The controller has full ECC error-correction support, with the ability to detect multi-bit errors and correct single-bit errors within a nibble. Please consult the Micron data sheet for DDR4 device specific details.
NOR Flash
Connected through the local bus, the NIU3R supports 2 x 2 gigabytes of flash. The Flash consists of a stacked (four 512Mb die) Micron® Flash MT25QL02GCBB8E12-0SIT device. Flash features a high-speed SPI-compatible bus interface that utilizes dual QSPI via a two-input logic gate to increase I/O throughput rates four times for each device. The NOR Flash has an erase capacity of 100,000 cycles per sector and typical data retention of 20 years
FRAM
The FM24CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. The ferroelectric random-access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years. The NIU3R FRAM 64K bits are organized as 8,192 x 8 bits random access memory, connected to the Ultrascale+™ CPU through the I2C controller.
SATA
The Ultrascale+™ CPU is directly connected to an onboard Solid-State Drive (SSD). The SSD contains a single level cell NAND Flash together with a controller in a single Multi-Chip package. The Multi-Chip packaged device is soldered directly to the printed circuit board for reliable electrical and mechanical connection.
The SSD has an internal write protect signal SATA_WP. The SATA_WP signal must be connected or switched to ground to enable any write to the SSD. The SATA_WP signal is pulled up on card by a 4.7 KΩ resistor to the internal 3.3 V supply.
The onboard SATA drive conforms to the follow specifications:
- Complies with Serial ATA 2.5 Specification
- Supports speeds: 1.5 Gbps (first-generation SATA), 3 Gbps (second-generation SATA and eSATA)
- Supports advanced technology attachment packet interface (ATAPI) devices
- Contains high-speed descriptor-based DMA controller
- Supports native command queuing (NCQ) commands
The standard ordering code for the NIU3R includes a 32GB SSD drive. Larger devices are available; please consult the factory for availability.
Peripheral I/O
Ethernet
The NIU3R supports four 10/100/1000Base-TX Ethernet connections using one Broadcom BCM54240 Ethernet PHY device and the Xilinx Gigabit Ethernet MACs. The PHY-to-MAC interface employs a Reduced Gigabit Media Independent Interface (RGIII) connection using four data lines at 250 Mbps each for a connection speed of 1 Gbps. The NIU3R contains internal magnetics and can directly drive copper CAT5e or CAT6 twisted pairs.
The NIU3R Ethernet ports support:
- Detection and correction of pair swaps (MDI crossover), and pair polarity
- MAC-side and line-side loopback
- Auto-negotiation
Ethernet Port 1 can be routed as 10/100/1000Base-TX Ethernet as a build option.
Ethernet Port 2 can be routed as 10/100/1000Base-TX Ethernet as a build option.
I/O pin outs can be found in the Pinout Details section of this document.
Serial Port
The NIU3R has a single, asynchronous serial port. The interface uses a two-wire, TXD, RXD interface (system/power GND referenced). The SER-TXD and SER-RXD RS-232 signals are routed to J2 on the NIU3R.
Tamper Detect Interface and Action Circuit
NAI is developing an optional Tamper Detect Interface and Action Circuit for improved Security/Cybersecurity requirements. This circuit will offer FIPS 140-3 Level 3 Design Support, Crypto-Key Storage (with Battery-Backed RAM), Secure Boot and Anti-Tamper/Tamper Detect & Sanitize functions. For further information, please contact NAI.
Software Libraries/Associated Documents
NIU3R BSP Processor Module Library
The NIU3R Processor library package provides function interfaces to the on-module functionality. This package contains Help documentation (in html format) that explains all the functions available in the library. The package also contains the source code (**.h, **.c) files as well as the files needed to build the library using any of the supported operating systems. Example programs are also provided to demonstrate the usage of the libraries in typical applications of the module.
Associated Documents
Check the NAI website or contact factory for the latest downloads and documentation.
SPECIFICATIONS
The NIU3R is designed to meet the following general specifications.
General
| Ethernet Data Transfer: | Data transfers within 1 ms (typical) |
| Input Voltage: | 18 to 36 VDC (28 VDC nominal) |
| Power (Base unit): | ~30 W @ 28 V VDC nominal plus module(s) power (see specific module(s) specifications) I/O Signal GND reference is isolated from main power source return and chassis. |
| Power/Heat Dissipation: | ~30 watts (maximum) when properly mounted to a cold-plate, which must be maintained at a temperature not to exceed 71°C. Note: The total NIU3R power dissipation is dependent on the configuration of the modules fitted in the NIU3R. |
| Temperature, Operating: | -40°C to 71°C (conduction cooled - measured at cold plate interface) |
| Temperature, Storage: | -55°C to 105°C |
| Size: | Height: ~1.6” (41 mm) Depth: ~5.8” (147 mm) Width: ~6.2” (157 mm) |
| Weight: | The approximate weight of a typical fully configured NIU3R (model #) is ~2.5 lbs. (1.13 kg). |
| Environmental MIL-STD-810(F-H) (*1) | ||||||
| No. | Description | Procedure (for ref.) | Cycles (for ref.) | Table (for ref.) | Figure (for ref.) | Comments |
| 514 | Vibration | I | 514.8-I | Method 514.8, 4.4G 10 minutes all axis operational | ||
| 501 | Temp (High) | I | 501.7-I | PHS&T (2 hour soak @ 71C), Non-op, performance check @ end of soak | ||
| 501 | Temp Variation (Diurnal Hot Day) | I | 501.7-I | 3X 24 Hour cycles of 35C>71C>35C NO SUN EXPOSURE REQUIRED, Non-op, performance check @ end of third cycle | ||
| 501 | Temp Variation (Captive Carriage Thermal Soak) | II | 501.7-II | 85C for 2 hours, 95C for 5 minutes operational | ||
| 502 | Temp (Low) | I | 502.7-I | PHS&T (2 hour soak @ -40C), Non-op, performance check @ end of soak | ||
| 502 | Temp (Low – Captive Carriage) | I | 502.7-II | 54C for 2 hours | ||
| 503 | Temp (Shock) | 1-D | 3 | Room>-40C, stabilize>Room, >+49C, stabilize. Chamber switch/Temp change in less than 1 min, Non-op, performance check @ end of soak | ||
| 503 | Temp (Shock – Captive Carriage) | 1-D | 3 | 41C>+66C in less than 5 minutes>Room>-54C in less than 1 minute, operational | ||
| 507 | Humidity | II | 10 | 507.6-II | 10X 24 Hour cycles 100%>95%>100% humidity at room temp, op checks @ end of 5th & 10th Cycles | |
| 500 | Pressure | II | 1 | 500.6-II | n/a | 108,000 Pa (15.7 psia) until stable, operational |
| 513 | Acceleration | II | 1 | 513.8-II | n/a | 30G for 5 seconds, all directions for total of 8 runs |
| 516 | Shock – Ejection | I | 516.8-I | n/a | 18 total SRS shocks, operational | |
| 520 | Combined Environment – Conditioning Cycle | 3 | 520.5 | n/a | 3 cycles of 40k feet @ -54C for 2 hours > 32C @ 90% humidity for 2 hours, op checks @ end of 1st and 3rd cycles | |
| Ingress Protection IEC 60529 (*1) | ||||||
| No. | Description | Procedure | Cycles | Table | Figure | Comments |
| IP54 | Dust Protection | |||||
| IP54 | Water Splashing | |||||
| IP65 | Dust Tight | |||||
| IP65 | Water Jets | |||||
EMC/EMI
| EMC / MIL-STD-461 (*1, *2) | ||
| MIL-STD-461(G) | Method/Curve/Procedure | Comments |
| CE102 | Conducted emissions, Power Leads, 10 kHz to 10 MHz. | |
| CS101 | Conducted Susceptibility Power Leads, 30 Hz to 150 kHz | |
| CS106 | Conducted susceptibility, Power Leads, 30 Hz to 150 kHz. | |
| CS114 | Conducted susceptibility, Bulk Cable Injection, 10 kHz to 200 MHz, Curve 5 | |
| CS115 | Conducted susceptibility, bulk cable injection, Impulse Excitation | |
| CS116 | Conducted susceptibility, Damped Sinusoidal Transients, Cables & Power Leads, 10 kHz to 100 MHz | |
| RE101 | Radiated emissions, magnetic field, 30 Hz to 100 kHz. | |
| RE102 | Radiated emissions, Electric Field 2 MHz to 18 GHz, limit: fixed wing internal <25m | |
| RS101 | Radiated emissions, electric field, 10 kHz to 18 GHz. | |
| RS103 | Radiated, susceptibility, Electric Field External 200 V/M from 2 MHz to 40 GHz | |
| CS118 | Personnel Borne Electrostatic Discharge, 16kV | |
Notes:
*1 - Designed to meet / Generic Test Reports (contact factory for availability).
*2 - Utilizing proper shielded cables and system practices.
Note
Specifications are subject to change without notice.
MTBF
The Mean Time between Failures is configuration, environment, and temperature dependent. Please contact factory regarding calculations based on the specific configuration and program requirements.
UNPACKING & INSPECTION
Figure 1. NIU3R
Unpacking
The NIU3R packing materials were designed specifically for transport protection of the NIU3R. When receiving the shipment container, inspect packaging for any evidence of physical damage. If damage is evident, it is recommended that the carrier agent is present when opening the shipping container. It is further recommended that all packing material is retained in the event the NIU3R needs to be shipped elsewhere.
System/Chassis Identification
An identification label, indicating part number, unique serial number, and Ethernet PHY MACs / default IP address(es) is affixed to the front of the system chassis.
Figure 2. Unit Identification
Inspection
Inspect the chassis and connectors to ensure that they were not damaged during transit.
MECHANICAL INTERFACE
Mechanical Description
The NIU3R is a rugged, aluminum (6061-T6) alloy, conduction-cooled system. It must be mounted to a cold plate. The system thermal management design considerations should ensure that the chassis thermal interface (NIU3R bottom surface) does not exceed 71°C. Mounting holes are provided on the chassis bottom housing flanges (as depicted). See the outline drawing below.
Mounting Requirements
Refer to NIU3R Outline and Installation Drawing (OID) for details on mounting and installing the NIU3R. It is available for download from NAI’s website. The NIU3R is conduction cooled and must be mounted in accordance with the drawing. The OID provides recommended hardware, torque, cold-plate flatness and surface finish specifications, and thermal conductivity requirements.
Figure 3. NIU3R Outline Dimensions/Cold Plate Mounting Pattern (Reference Only)
Note
- For reference only (refer to the product web page for the latest revision NIU3R Outline and Installation Drawing (OID).
- Unless otherwise specified, dimensions are in inches (mm); tolerances are:
2 PL DEC ±0.01; 3 PL DEC ±0.005
FRACT ±1/64 (0.4); ANGLES ±1/2 (12.7)
CONNECTOR DESIGNATION & DESCRIPTION
The Power, I/O Interface and Ethernet connectors are located on the NIU3R front panel housing.
Figure 4. NIU3R (Front Panel Connector Placement)
Table 1. NIU3R Connector Designation and Description
| Connector Designation | Description |
| J1 | I/O Connector, Inboard I/O |
| J2 | 4x GbE, Maintenance, Debug (RS-232, System Reset) & extended processor option signals (RS-232, Hardware SATA Write Protect) |
| J3 | Primary Power Connector, VDC |
Connector Details and Pinout
Generic pinout. See module I/O section or contact factory regarding any special module I/O configuration.
J1, Inboard Functions
The NIU3R is preconfigured with 16-CH programmable Discrete I/O, 4-CH Discrete Isolated Switching, 10-CH Serial, and 1-CH MIL-STD-1760 functions.
Figure 5. J1 I/O Inboard Functions Connector Detail
Parts Identification
Table 2. J1 I/O Inboard Functions Connector Definition
| Chassis (Box-level) | Mating Cable Connector | ||||
| Designation | MIL-DTL Equivalent Reference | Rows / Socket Size | Pin-count | MIL-DTL Equivalent Reference | NAI P/N (for reference) |
| J1 | MK-4C2-100-225-6600 | 4 / 22 | 100 | MM-412-100-161-81UM | 07-0162 |
Pinout
Generic pinout. See module I/O section or contact factory regarding any special module I/O configuration.
Table 3. J1 I/O Inboard Functions Connector Pinout
| J1 Connector Pin | Signal | Notes |
| 1 | TXDHI-CH10/CLKOUT-CH9 | |
| 2 | TXDLO-CH10/CLKOUT-CH9 | |
| 3 | RXDHI-CH10/CLKIN-CH9 | |
| 4 | RXDLO-CH10/CLKIN-CH9 | |
| 5 | GND_D | |
| 6 | TXDHI_CH7 | |
| 7 | TXDLO_CH7 | |
| 8 | RXDHI_CH7 | |
| 9 | RXDLO_CH7 | |
| 10 | GND_D | |
| 11 | STORE_MATED | |
| 12 | GND_D | |
| 13 | TXDHI_CH2 | |
| 14 | TXDLO_CH2 | |
| 15 | RXDLO_CH2 | |
| 16 | RXDHI_CH2 | |
| 17 | SPARE2 | |
| 18 | DT2_CH2_N | |
| 19 | DT2_CH2_P | |
| 20 | DT2_CH1_P | |
| 21 | DT2_CH1_N | |
| 22 | GND_DT | Signal/System Ground |
| 23 | DT1_IN_CH16 | |
| 24 | DT1_IN_CH15 | |
| 25 | DT1_IN_CH14 | |
| 26 | DT1_IN_CH13 | |
| 27 | GND_D | Signal/System Ground |
| 28 | SER0_TXD | |
| 29 | SER0_RXD | |
| 30 | GND_D | Signal/System Ground |
| 31 | GND_D | Signal/System Ground |
| 32 | TXDHI_CH6 | |
| 33 | TXDLO_CH6 | |
| 34 | RXDHI_CH6 | |
| 35 | RXDLO_CH6 | |
| 36 | GND_D | Signal/System Ground |
| 37 | TXDLO_CH4 | |
| 38 | TXDHI_CH4 | |
| 39 | RXDHI_CH4 | |
| 40 | RXDLO_CH4 | |
| 41 | GND_D | Signal/System Ground |
| 42 | DT2_CH4_P | |
| 43 | DT2_CH4_N | |
| 44 | DT2_CH3_P | |
| 45 | DT2_CH3_N | |
| 46 | SPARE1 | |
| 47 | DT1_OUT_CH4 | |
| 48 | DT1_OUT_CH3 | |
| 49 | DT1_OUT_CH2 | |
| 50 | DT1_OUT_CH1 | |
| 51 | VCC1 | |
| 52 | RXDLO_CH9 | |
| 53 | RXDHI_CH9 | |
| 54 | TXDLO_CH9 | |
| 55 | TXDHI_CH9 | |
| 56 | GND_D | Signal/System Ground |
| 57 | RXDLO_CH8 | |
| 58 | RXDHI_CH8 | |
| 59 | TXDLO_CH8 | |
| 60 | TXDHI_CH8 | |
| 61 | GND_D | Signal/System Ground |
| 62 | TXDHI_CH3 | |
| 63 | TXDLO_CH3 | |
| 64 | RXDHI_CH3 | |
| 65 | RXDLO_CH3 | |
| 66 | GND_D | Signal/System Ground |
| 67 | RXDLO_CH1 | |
| 68 | RXDHI_CH1 | |
| 69 | TXDLO_CH1 | |
| 70 | TXDHI_CH1 | |
| 71 | GND_D | Signal/System Ground |
| 72 | DT1_OUT_CH8 | |
| 73 | DT1_OUT_CH7 | |
| 74 | DT1_OUT_CH5 | |
| 75 | DT1_OUT_CH6 | |
| 76 | +3V3 | |
| 77 | GND_D | Signal/System Ground |
| 78 | 1760_BUSB_N | |
| 79 | 1760_BUSB_P | |
| 80 | 1760_BUSA_N | |
| 81 | 1760_BUSA_P | |
| 82 | GND_D | Signal/System Ground |
| 83 | TXDHI_CH5 | |
| 84 | TXDLO_CH5 | |
| 85 | RXDLO_CH5 | |
| 86 | RXDHI_CH5 | |
| 87 | GND_D | Signal/System Ground |
| 88 | CARRIAGE_MATED | |
| 89 | PLATFORM_CLASS | |
| 90 | SAFETY_EN | |
| 91 | GND_D | Signal/System Ground |
| 92 | JTAG_TDI | |
| 93 | JTAG_TMS | |
| 94 | JTAG_TCK | |
| 95 | JTAG_TDO | |
| 96 | GND_D | Signal/System Ground |
| 97 | DT1_IN_CH11 | |
| 98 | DT1_IN_CH9 | |
| 99 | DT1_IN_CH12 | |
| 100 | DT1_IN_CH10 |
J2, Ethernet Communication & Debug
The NIU3R supports up to four 10/100/1000Base-T ports (when appropriately configured) and debug/maintenance signals. The debug/maintenance signals provided are an RS-232 console port and System Reset (for a soft reset/reload). There are also signals provided for Battery-Backed Key Storage and access/changes to the FPGA
Figure 6. J2 Ethernet Communications & Debug Connector Detail
Parts Identification
Table 4. J2 Ethernet Communications & Debug Connector Definition
| Chassis (Box-level) | Mating Cable Connector | ||||
| Designation | MIL-DTL Equivalent Reference | Rows / Socket Size | Pin-count | MIL-DTL Equivalent Reference | NAI P/N + (for reference) |
| J2 | MK-3C2-051-225-2600 | 3 / 22 | 51 | MM-312-051-161-41UM | 07-0161 |
Pinout
Table 5. J2 Ethernet Communications & Debug Connector Pinout
| J2 Connector Pin | Signal | Notes |
| 1 | TAMPER_DET_IN | *6 |
| 2 | SER0_RXD | *2 |
| 3 | SER0_TXD | *2 |
| 4 | "+VBAT_IN" | *7 |
| 5 | GND_D | *4 |
| 6 | ETH3_TP3_N | *5 |
| 7 | ETH3_TP3_P | *5 |
| 8 | ETH3_TP2_N | *5 |
| 9 | ETH3_TP2_P | *5 |
| 10 | ETH3_TP1_N | *5 |
| 11 | ETH3_TP1_P | *5 |
| 12 | ETH3_TP0_P | *5 |
| 13 | ETH3_TP0_N | *5 |
| 14 | SYSRSTN | *1 |
| 15 | PT1_IN | *8 |
| 16 | PT1_OUT | *8 |
| 17 | +3V3 | *8 |
| 18 | GND_D | *4 |
| 19 | ETH4_TP3_N | *5 |
| 20 | ETH4_TP3_P | *5 |
| 21 | ETH4_TP2_N | *5 |
| 22 | ETH4_TP2_P | *5 |
| 23 | ETH4_TP1_N | *5 |
| 24 | ETH4_TP1_P | *5 |
| 25 | ETH4_TP0_N | *5 |
| 26 | ETH4_TP0_P | *5 |
| 27 | GND_D | *4 |
| 28 | ETH1_TP3_P | *5 |
| 29 | ETH1_TP3_N | *5 |
| 30 | ETH1_TP2_N | *5 |
| 31 | ETH1_TP2_P | *5 |
| 32 | ETH1_TP1_P | *5 |
| 33 | ETH1_TP1_N | *5 |
| 34 | ETH1_TP0_N | *5 |
| 35 | ETH1_TP0_P | *5 |
| 36 | SPARE_IO_2 | *9 |
| 37 | SPARE_IO_1 | *9 |
| 38 | NVMRO | *4 |
| 39 | JTAG_TDO | *10 |
| 40 | JTAG_TMS | *10 |
| 41 | JTAG_TDI | *10 |
| 42 | JTAG_TCK | *10 |
| 43 | GND_D | *4 |
| 44 | ETH2_TP3_N | *5 |
| 45 | ETH2_TP3_P | *5 |
| 46 | ETH2_TP2_N | *5 |
| 47 | ETH2_TP2_P | *5 |
| 48 | ETH2_TP1_N | *5 |
| 49 | ETH2_TP1_P | *5 |
| 50 | ETH2_TP0_N | *5 |
| 51 | ETH2_TP0_P | *5 |
Notes
| 1. | SYSRSTn: An active “low” or GND logic level (as referenced to System GND of the NIU3R) assertion of the SYSRST# signal (internally pulled ‘high’) on the NIU3R processor and module card will initiate an NIU3R system reset. |
| 2. | Debug: RS-232 Serial Communications Console port |
| 3. | NVMRO: Used for SATA Flash write enable/disable on the processor of the NIU3R. OPEN for Write Protect, GND for Write Enable. |
| 4. | GND: All the identified GNDs are referenced to the same internal signal GND (System GND). |
| 5. | ETHx-TPyz: Standard NIU3R configuration provides 4x 10/100/1000Base-T Ethernet ports: x = port number; y = twisted par/differential signal number (0/1/2/3); z = differential signal polarity (p = positive(+) and n = negative(-)). |
| 6. | TAMPER DETECT: Key storage for FIPS 140-2 level 3. |
| 7. | VBAT: Battery voltage for Tamper Detect. |
| 8. | PT1: Access to US+ FPGA pins for future custom I/O expansion |
| 9. | SPARE_IO_X: Spare I/O (currently inactive). |
| 10. | JTAG: Allows for reprogramming of the QSPI memory and changes to the FPGA. |
J3, Primary Power Connector
Primary input power is supported on the NIU3R via the J3 connector. Connectors used are as follows:
Figure 7. J3 Primary Power Connector Detail
Parts Identification
Table 6. J3 Primary Power Connector Definition
| Chassis (Box-level) | Mating Cable Connector | ||||
| Designation | MIL-DTL Equivalent Reference | Rows / Socket Size | Pin-count | MIL-DTL Equivalent Reference | NAI P/N + (for reference) |
| J3 | MK-2C2-009-225-2600 | 2 / 22 | 9 | MM-212-009-161-41UM | 07-0160 |
Pinout
Table 7. J3 Primary Power Connector Pinout
| J3 Connector Pin | Signal |
| 1 | 28VDC-IN |
| 2 | 28VDC-IN |
| 3 | 28VDC-IN |
| 4 | 28VDC-IN |
| 5 | 28VDC-RTN |
| 6 | 28VDC-RTN |
| 7 | 28VDC-RTN |
| 8 | 28VDC-RTN |
| 9 | Chassis GND |
OPERATIONAL DESCRIPTION
Basic Operations
Primary SBC/host/mission computer communications interface to the NIU3R is via the Gig-E port(s). Full command/control/register data query is requested and sent as a TCP/IP or UDP type message to the NIU3R via NAI Ethernet protocol structure, i.e. the NIU3R receives a message command and replies accordingly. In addition to direct read/write function module register access, once initialized the protocol can also support multi-register block read/writes as well as generate interrupt driven output messages or timed interval data ‘dump’ messages. For detailed supplement, please visit the NAI web-site specific product page and refer to:
NAI Ethernet Interface for Generation 5 SBC and Embedded IO Boards Software Specification
The Software Support Kit (SSK) supplied with the NIU3R includes a full suite of NAI sample applications that enables the user to interact with the function modules fitted within the NIU3R unit. For additional details on the sample applications, please refer to the ‘Sample Applications’ tab on the NAI website.
REGISTER MEMORY MAP ADDRESSING
The register map address consists of the following:
- cPCI/PCIe BAR or Base Address for the Board
- Module Slot Base Address
- Function Offset Address
Board Base Address
The table below lists the BAR used for access to the motherboard and module registers. The second BAR is used internally for motherboard and module firmware updates. The other cPCI/PCIe BARs not listed are not used.
| NAI Boards | Device ID | Bus | Motherboard and Module Register Access | Motherboard and Module Firmware Updates |
| Slave Boards | ||||
| NIU3R | N/A | N/A | Direct Memory Access | Internal Direct Memory Access |
Module Slot and Function Address
The NIU3R includes (4) basic preconfigured IO functions embedded within the motherboard (onboard functions). These functions are like the standard NAI COSA® smart functions identified as:
- DT1 = 1. DT1 = Support function ID for 8-CH Discrete I/O
- DT2 = Support function ID for 4-CH Discrete Switch
- SC3 = Support function ID for 8-CH Serial Communications (Async only)
- CMJ = Support function ID for 2-CH Serial communications (Async or Sync) & 1-CH MIL-STD-1760
The following depicts the memory structure allocated for the (4) onboard function IDs.
| NIU3R function/module structure/order: | |
| Function #1: | Onboard Function DT1-type (Discrete I/O) |
| Function #2: | Onboard Function DT2-type (Discrete Switch) |
| Function #3: | Onboard Function SC3-type (Serial Comm) |
| Function #4: | Onboard Function CMJ-type (Serial Comm, MIL-STD-1760) |
The “start” address of the function(s) on the CIU3 are factory pre-defined (and read from)) the Module Address register (refer to the figure below).
Figure 8. Register Memory Map Addressing Example for NIU3R
Address Calculation
Motherboard Registers:
Read/Write access to the motherboard registers starts with the base address for the board and then the motherboard base offset address.
For example, to address Module Slot 1 Start Address register (i.e. register address = 0x4000):
- Start with the base address for the board.
- Add the motherboard base register address offset.
| Motherboard Address = | Base Address + | Motherboard Address Offset | = 0x9000 0400 |
| 0x9000 0000 | 0x0400 |
Module Registers:
Read/Write access to the Function module’s registers start with the base address of the board. Add the “content” for the Module Start Address and then, add the specific module function register offset.
For example, to address an appropriate/specific function module with a register offset:
- Start with the base address for the board.
- Add the value (contents) from the module base address offset register (contents/value of Motherboard Memory register for Module 1 (i.e., @ 0x4000) = 0x4000.
- Then add the specific module function Register Offset of interest (i.e., 0x1000)
| (Function Specific) Address = | Base Address + | Module Base Address Offset + | Function Register Offset | = 0x9000 5000 |
| 0x9000 0000 | 0x4000 | 0x1000 |
REGISTER DESCRIPTIONS
Module Information Registers
The Module Slot Address, Module Slot Size and Module Slot ID provide information about the modules detected on the board.
| Module Slot Addressing Ready | |
| Function: | Indicates that the module slots are ready to be addressed. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R |
| Initialized Value: | 0xA5A5A5A5 |
| Operational Settings: | This register will contain the value of 0xA5A5A5A5 when the module addresses have been determined. |
| Module Slot Address | |
| Function: | Specifies the Base Address for the module in the specific slot position. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R |
| Initialized Value: | Based on board's module configuration. |
| Operational Settings: | 0x0000 0000 indicates no Module found. |
| Module Slot Size | |
| Function: | Specifies the Memory Size (in bytes) allocated for the module in the specific slot position. |
| Type: | unsigned binary word (32-bit) |
| Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R |
| Initialized Value: | Assigned by factory for the module. |
| Operational Settings: | 0x0000 0000 indicates no Module found. |
| Module Slot ID | |
| Function: | Specifies the Model ID for the module in the specified slot position. |
| Type: | 4-character ASCII string |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R |
| Initialized Value: | Assigned by factory for the module. |
| Operational Settings: | The Module ID is formatted as four ASCII bytes: three characters followed by a space. A value of 0000 0000 indicates no Module found. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| ASCII Character (ex: 'A' - 0x41) | ASCII Character (ex: 'D' - 0x44) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| ASCII Character (ex: '5' - 0x35) | ASCII Space (' ' - 0x20) | ||||||||||||||
Hardware Information Registers
The registers identified in this section provide information about the board’s hardware.
| Product Serial Number | |
| Function: | Specifies the Board Serial Number. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R |
| Initialized Value: | Serial number assigned by factory for the board. |
| Operational Settings: | N/A |
| Platform | |
| Function: | Specifies the Board Platform Identifier. Values are for the ASCII characters for the NAI valid platforms (Identifiers). |
| Type: | 4-character ASCII string |
| Data Range: | See table below. |
| Read/Write: | R |
| Initialized Value: | ASCII code is for the Platform Identifier of the board |
| Operational Settings: | NAI platform for this board is shown below: |
| NAI Platform | Platform Identifier | 4-character ASCII string |
| NIU | 00 | 0x0000 0000 |
| Model | |
| Function: | Specifies the Board Model Identifier. Values are for the ASCII characters for the NAI valid models. |
| Type: | 4-character ASCII string |
| Data Range: | See table below. |
| Read/Write: | R |
| Initialized Value: | ASCII code is for the Model Identifier of the board |
| Operational Settings: | NAI model for this board is shown below: |
| NAI Model | 4-character ASCII string |
| NIU | 0x0055 494E |
| Generation | |
| Function: | Specifies the Board Generation. Identifier values are for the ASCII characters for the NAI valid generation identifiers. |
| Type: | 4-character ASCII string |
| Data Range: | See table below. |
| Read/Write: | R |
| Initialized Value: | ASCII code is for the Generation Identifier of the board |
| Operational Settings: | NAI generation for this board is shown below: |
| NAI Generation | 4-character ASCII string |
| 3R | 0x0000 5233 |
| Processor Count/Ethernet Interface Count | |
| Function: | Specifies the Processor Count and Ethernet Interface Count |
| Type: | unsigned binary word (32-bit) |
| Data Range: | See table below. |
| Read/Write: | R |
| Operational Settings: | Processor Count - Indicates the number of unique processor types on the motherboard = 1 Ethernet Interface Count - Indicates the number of Ethernet interfaces on the product motherboard. For NIU3R, the Ethernet Interface Count is set for Dual Ethernet = 2. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Processor Count (0x0001) | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Ethernet Interface Count (0x0002) | |||||||||||||||
| Maximum Module Slot Count/ARM Platform Type | |
| Function: | Specifies the Maximum Module Slot Count and ARM Platform Type. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | See table below. |
| Read/Write: | R |
| Operational Settings: | Maximum Module Slot Count = 4 ARM Platform Type - UltraScale+ = 3 |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Maximum Module Slot = 0x0004 | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| ARM Platform Type = 0x0003 (UltraScale) | |||||||||||||||
Processor Operating System Registers
The registers in this section provide information about the Operating System that is running on the host processor on the motherboard. For boards that have more than one processor (ex. 75PPC1, 75INT2, 68PPC2, etc), the host processor would be the Power-PC or Intel processor.
| ARM Processor Platform | |
| Function: | Specifies the ARM Processor on the motherboard. Values are for the ASCII characters for the NAI host processor platforms specified by the Operating System. |
| Type: | 8-character ASCII string - Two (2) unsigned binary word (32-bit) |
| Data Range: | N/A |
| Read/Write: | R |
| Initialized Value: | ASCII code is for the Host Platform Identifier of the board |
| Operational Settings: | Valid NAI platforms based on Operating System loaded to host processor. |
| Processor Platform (Note: 8-character ASCII string) (“aarch64”) | |||||||||||||||
| Word 1 (0x6372 6161 = “craa”) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 'c' (0x63) | 'r' (0x72) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 'a' (0x61) | 'a' (0x61) | ||||||||||||||
| Word 2 (0x0034 3668 = “ 46h”) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| null (0x00) | '4' (0x34) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| '6' (0x36) | 'h' (0x68) | ||||||||||||||
| Processor Operating System | |
| Function: | Specifies the Operating System installed for the host processor. Values are for the ASCII characters for the NAI supported operating systems. |
| Type: | 12-character ASCII string - Three (3) unsigned binary word (32-bit) |
| Data Range: | N/A |
| Read/Write: | R |
| Operational Settings: | ASCII, 12 characters; ('Linux', 'VxWorks', 'RTOS', ...) |
| Processor Platform (Note: 12-character ASCII string) (“Linux”) | |||||||||||||||
| Word 1 (0x756E 694C = “uniL”) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 'u' (0x75) | 'n' (0x6E) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 'i' (0x69) | 'L' (0x4C) | ||||||||||||||
| Word 2 (0x0000 0078 = “ x”) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| null (0x00) | null (0x00) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| null (0x00) | 'x' (0x78) | ||||||||||||||
| Word 3 (0x0000 0000 = “ ”) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| null (0x00) | null (0x00) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| null (0x00) | null (0x00) | ||||||||||||||
Motherboard Firmware Information Registers
The registers in this section provide information on the revision of the firmware installed on the motherboard.
| Motherboard Core Firmware Version | |
| Function: | Specifies the Version of the NAI factory provided Motherboard Core Application installed on the board. |
| Type: | Two (2) unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R |
| Operational Settings: | The motherboard firmware version consists of four components: Major, Minor, Minor 2 and Minor 3. |
| Motherboard Core Firmware Version (Note: little-endian order in register) (ex. 4.50.0.0) | |||||||||||||||
| Word 1 (Ex. 0050 0004 = 4.50 (Major.Minor) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Minor (ex: 0x0050 = 50) | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Major (ex: 0x0004 = 4) | |||||||||||||||
| Word 2 (Ex. 0x0000 0000 = 0000 = 0.0 (Minor2.Minor3)) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Minor 3 (ex: 0x000 = 0) | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Minor 2 (ex: 0x000 = 0) | |||||||||||||||
| Motherboard Firmware Build Date/Time | |
| Function: | Specifies the Build Date/Time of the NAI factory provided Motherboard Core Application installed on the board. |
| Type: | Two (2) unsigned binary word (32-bit) |
| Data Range: | N/A |
| Read/Write: | R |
| Operational Settings: | The motherboard firmware time consists of the Build Date and Build Time. |
| Motherboard Firmware Build Time (Note: little-endian order in register) | |||||||||||||||
| Word 1 - Build Date (ex. 0x1006 07E5 = 2021-6-16) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Day (ex: 0x10 = 1624) | Month (ex: 0x06 = 6) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Year (ex: 0x07E5 = 2021) | |||||||||||||||
| Word 2 - Build Time (ex. 0x001A 1A10 = 16:26:26) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| null (0x00) | Seconds (ex: 0x1A = 26) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Minutes (ex: 0x1A = 26) | Hours (ex: 0x10 = 16) | ||||||||||||||
| Motherboard FPGA Firmware Version | |
| Function: | Specifies the Version of the NAI factory provided Motherboard FPGA installed on the board. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R |
| Operational Settings: | The motherboard FPGA firmware version consists of two components: Major, Minor |
| Motherboard FPGA Firmware Version (ex. 0x0005 0009 = 5.9) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Major (ex: 0x0005 = 5) | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Minor (ex: 0x0009 = 9) | |||||||||||||||
| Motherboard FPGA Firmware Compile Date/Time | |
| Function: | Specifies the Compile Date/Time of the NAI factory provided Motherboard FPGA installed on the board. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | N/A |
| Read/Write: | R |
| Operational Settings: | The motherboard firmware time consists of the Build Date and Time in the following format: |
| Motherboard FPGA Compile Time (ex. 0xC32B 2923 = 06/24/21 18:36:35) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Day (D31:D27) | Month (D26:D23) | Year (D22:D17) | |||||||||||||
| ex. 0xC | ex. 0x3 | 0x2 | 0xB | ||||||||||||
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 10 |
| Day = 0x18 = 24 | Month = 0x6 = 6 | Year = 0x15 = 21 | |||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Hour (D16:D12) | Minutes (D11:D6) | Seconds (D5:D0) | |||||||||||||
| ex. 0x2 | ex. 0x9 | ex. 0x2B | ex. 0x3 | ||||||||||||
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 |
| Hour = 0x12 = 18 | Minutes = 0x24 = 36 | Seconds = 0x23 = 35 | |||||||||||||
Motherboard Monitoring Registers
The registers in this provide motherboard temperature measurement information.
Temperature Readings Register
The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) for the processor and PCB for the UltraScale processor.
These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).
| Temperature Readings Register | |
| Function: | Specifies the Measured Temperatures on Motherboard. |
| Type: | signed byte (8-bits) for each temperature reading - Six (6) 32-bit words |
| Data Range: | 0x0000 0000 to 0xFFFF 0000 |
| Read/Write: | R |
| Initialized Value: | Value corresponding to the measured temperatures based on the table below. |
| Operational Settings: | The 8-bit temperature readings are signed bytes. For example, if the following register contains the value 0x0000 2B2B: |
Example:
| Word 1 (Current UltraScale Temperatures) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| UltraScale Core Temperature | UltraScale PCB Temperature | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0x00 | 0x00 | ||||||||||||||
The values would represent the following temperatures:
| Temperature Measurements | Data Bits | Value | Temperature (Celsius) |
| UltraScale Core Temperature | D31:D24 | 0x2B | +43° |
| UltraScale PCB Temperature | D23:D16 | 0x2B | +43° |
| Temperature Readings | |||||||||||||||
| Word 1 (Current UltraScale Temperatures) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| UltraScale Core Temperature | UltraScale PCB Temperature | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0x00 | 0x00 | ||||||||||||||
| Word 2 (Reserved) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0x00 | 0x00 | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0x00 | 0x00 | ||||||||||||||
| Word 3 (Max UltraScale Temperatures) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Max UltraScale Core Temperature | Max UltraScale PCB Temperature | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0x00 | 0x00 | ||||||||||||||
| Word 4 (Reserved) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0x00 | 0x00 | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Word 5 (Min UltraScale Temperatures) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Min UltraScale Core Temperature | Min UltraScale PCB Temperature | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Word 6 (Reserved) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0x00 | 0x00 | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Higher Precision Temperature Readings Registers
These registers provide higher precision readings of the current UltraScale Core and PCB temperatures.
| Higher Precision UltraScale Core Temperature | |
| Function: | Specifies the Higher Precision Measured UltraScale Core temperature on Motherboard Board. |
| Type: | signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R |
| Initialized Value: | Measured UltraScale Core temperature on Motherboard Board |
| Operational Settings: | The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 02FF, this represents UltraScale Core Temperature = 43.767° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Signed Integer Part of Temperature | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Fractional Part of Temperature | |||||||||||||||
| Higher Precision Motherboard PCB Temperature | |
| Function: | Specifies the Higher Precision Measured Motherboard PCB temperature. |
| Type: | signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R |
| Initialized Value: | Measured Motherboard PCB temperature |
| Operational Settings: | The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 02FF, this represents Interface PCB Temperature = 43.767° Celsius, and value 0xFFE8 036B represents -24.875° Celsius. |
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Signed Integer Part of Temperature | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Fractional Part of Temperature | |||||||||||||||
Motherboard Health Monitoring Registers
The registers in this section provide a summary of motherboard temperature sensors and their corresponding bits. Additionally, this section provides an overview of the registers allocated to those sensors, which are used to monitor current/minimum/maximum temperature readings, upper & lower critical/warning temperature thresholds, and whether or not a programmed temperature threshold has been exceeded.
These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).
| Motherboard Sensor Summary Alarm | |
| Function: | The corresponding sensor bit is set if the sensor has crossed any of its thresholds. |
| Type: | unsigned binary word (32-bits) |
| Data Range: | See table below |
| Read/Write: | R |
| Initialized Value: | 0 |
| Operational Settings: | This register provides a summary for motherboard sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event. |
| Bit(s) | Sensor |
| D31:D5 | Reserved |
| D4 | Motherboard PCB Temperature |
| D3 | US+ Core Temperature |
| D2:D0 | Reserved |
Motherboard Sensor Registers
The registers listed in this section apply to each module sensor listed for the Motherboard Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring motherboard temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Zynq Core Temperature sensor as an example.
| Sensor Threshold Status | |
| Function: | Reflects which threshold has been crossed |
| Type: | unsigned binary word (32-bits) |
| Data Range: | See table below |
| Read/Write: | R |
| Initialized Value: | 0 |
| Operational Settings: | The associated bit is set when the sensor reading exceed the corresponding threshold settings. |
| Bit(s) | Description |
| D31:D4 | Reserved |
| D3 | Exceeded Upper Critical Threshold |
| D2 | Exceeded Upper Warning Threshold |
| D1 | Exceeded Lower Critical Threshold |
| D0 | Exceeded Lower Warning Threshold |
| Sensor Current Reading | |
| Function: | Reflects current reading of temperature sensor |
| Type: | Single Precision Floating Point Value (IEEE-754) |
| Data Range: | Single Precision Floating Point Value (IEEE-754) |
| Read/Write: | R |
| Initialized Value: | N/A |
| Operational Settings: | The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius. |
| Sensor Minimum Reading | |
| Function: | Reflects minimum value of temperature sensor since power up |
| Type: | Single Precision Floating Point Value (IEEE-754) |
| Data Range: | Single Precision Floating Point Value (IEEE-754) |
| Read/Write: | R |
| Initialized Value: | N/A |
| Operational Settings: | The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius. |
| Sensor Maximum Reading | |
| Function: | Reflects maximum value of temperature/voltage/current sensor since power up |
| Type: | Single Precision Floating Point Value (IEEE-754) |
| Data Range: | Single Precision Floating Point Value (IEEE-754) |
| Read/Write: | R |
| Initialized Value: | N/A |
| Operational Settings: | The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius. |
| Sensor Lower Warning Threshold | |
| Function: | Reflects lower warning threshold of temperature sensor |
| Type: | Single Precision Floating Point Value (IEEE-754) |
| Data Range: | Single Precision Floating Point Value (IEEE-754) |
| Read/Write: | R/W |
| Initialized Value: | Default lower warning threshold (value dependent on specific sensor) |
| Operational Settings: | The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius. |
| Sensor Lower Critical Threshold | |
| Function: | Reflects lower critical threshold of temperature sensor |
| Type: | Single Precision Floating Point Value (IEEE-754) |
| Data Range: | Single Precision Floating Point Value (IEEE-754) |
| Read/Write: | R/W |
| Initialized Value: | Default lower critical threshold (value dependent on specific sensor) |
| Operational Settings: | The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius. |
| Sensor Upper Warning Threshold | |
| Function: | Reflects upper warning threshold of temperature sensor |
| Type: | Single Precision Floating Point Value (IEEE-754) |
| Data Range: | Single Precision Floating Point Value (IEEE-754) |
| Read/Write: | R/W |
| Initialized Value: | Default upper warning threshold (value dependent on specific sensor) |
| Operational Settings: | The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius. |
| Sensor Upper Critical Threshold | |
| Function: | Reflects upper critical threshold of temperature sensor |
| Type: | Single Precision Floating Point Value (IEEE-754) |
| Data Range: | Single Precision Floating Point Value (IEEE-754) |
| Read/Write: | R/W |
| Initialized Value: | Default upper critical threshold (value dependent on specific sensor) |
| Operational Settings: | The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius. |
Ethernet Configuration Registers
The registers in this section provide information about the Ethernet Configuration for the two ports on the board.
Important
Regardless if the board is configured for one or two Ethernet ports, the second IP address cannot be on the same Subnet as the First IP Address. The table below provides examples of valid and invalid IP Addresses and Subnet Mask Addresses.
| First Port (A) IP Address | First Port (A) Subnet Mask | Second Port (B) IP Address | Second Port (B) Subnet Mask | Result |
| 192.168.1.5 | 255.255.255.0 | 192.168.2.5 | 255.255.255.0 | Good |
| 192.168.1.5 | 255.255.0.0 | 192.168.2.5 | 255.255.0.0 | Conflict |
| 192.168.1.5 | 255.255.0.0 | 192.168.2.5 | 255.255.255.0 | Conflict |
| 10.0.0.15 | 255.0.0.0 | 192.168.1.5 | 255.255.255.0 | Good |
| Ethernet MAC Address and Ethernet Settings | |
| Function: | Specifies the Ethernet MAC Address and Ethernet Settings for the Ethernet port. |
| Type: | Two (2) unsigned binary word (32-bit) |
| Data Range: | See table. |
| Read/Write: | R |
| Operational Settings: | The Ethernet MAC Address consists of six octets. The Ethernet Settings are defined in table. |
| Bits | Description | Values |
| D31:D23 | Reserved | 0 |
| D22:D21 | Duplex | 00 = Not Specified 01 = Half Duplex 10 = Full Duplex 11 = Reserved |
| D20:D18 | Speed | 000 = Not Specified 001 = 10 Mbps 010 = 100 Mbps 011 = 1000 Mbps 100 = 2500 Mbps 101 = 10000 Mbps 110 = Reserved + 111 = Reserved |
| D17 | Auto Negotiate | 0 = Enabled 1 = Disabled |
| D16 | Static IP Address | 0 = Enabled 1 = Disabled |
| Ethernet MAC Address and Ethernet Settings (Note: little-endian order in register) | |||||||||||||||
| Word 1 (Ethernet MAC Address (Octets 1-4)) (ex: aa:bb:cc:dd:ee:ff) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| MAC Address Octet 4 (ex: 0xDD) | MAC Address Octet 3 (ex: 0xCC) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| MAC Address Octet 2 (ex: 0xBB) | MAC Address Octet 1 (ex: 0xAA) | ||||||||||||||
| Word 2 (Ethernet MAC Address (Octets 5-6) and Ethernet Settings) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Ethernet Settings (See table) | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| MAC Address Octet 6 (ex: 0xFF) | MAC Address Octet 5 (ex: 0xEE) | ||||||||||||||
| Ethernet Interface Name | |
| Function: | Specifies the Ethernet Interface Name for the Ethernet port. |
| Type: | 8-character ASCII string |
| Data Range: | See table. |
| Read/Write: | R |
| Operational Settings: | The Ethernet Interface Name (eth0, eth1, etc) for the Ethernet port. |
| Ethernet Interface Name (Note: ascii string in register) (ex. “eth0”) | |||||||||||||||
| Word 1 (Bit 0-31) (ex: 0x3068 7465 = “0hte”) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| ASCII Character (ex: '0' - 0x30) | ASCII Character (ex: 'h' - 0x68) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| ASCII Character (ex: 't' - 0x74) | ASCII Character (ex: 'e' - 0x65) | ||||||||||||||
| Word 2 (Bit 32-63) (ex: 0x0000 0000) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| ASCII Character (ex: null - 0x00) | ASCII Character (ex: null - 0x00) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| ASCII Character (ex: null - 0x00) | ASCII Character (ex: null - 0x00) | ||||||||||||||
| Ethernet IPv4 Address | |
| Function: | Specifies the Ethernet IPv4 Address for the Ethernet port. |
| Type: | Three (3) unsigned binary word (32-bit) |
| Data Range: | See table. |
| Read/Write: | R |
| Operational Settings: | The Ethernet IPv4 Address consists of three parts: IPv4 Address, IPv4 Subnet Mask and IPv4 Gateway. |
| Ethernet IPv4 Address (Note: little-endian order in register) | |||||||||||||||
| Word 1 (Ethernet IPv4 Address) (ex: 0x1001 A8C0 = 192.168.1.16) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| IPv4 Address Octet 4 (ex: 0x10 = 16) | IPv4 Address Octet 3 (ex: 0x01 = 1) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| IPv4 Address Octet 2 (ex: 0xA8 = 168) | IPv4 Address Octet 1 (ex: 0xC0 = 192) | ||||||||||||||
| Word 2 (Ethernet IPv4 Subnet) (ex: 0x00FF FFFF = 255.255.255.0) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| IPv4 Subnet Octet 4 (ex: 0x00 = 0) | IPv4 Subnet Octet 3 (ex: 0xFF = 255) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| IPv4 Subnet Octet 2 (ex: 0xFF = 255) | IPv4 Subnet Octet 1 (ex: 0xFF = 255) | ||||||||||||||
| Word 3 (Ethernet IPv4 Gateway) (ex: 0x0101 A8C0 = 192.168.1.1) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| IPv4 Gateway Octet 4 (ex: 0x01 = 1) | IPv4 Gateway Octet 3 (ex: 0x01 = 1) | ||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| IPv4 Gateway Octet 2 (ex: 0xA8 = 168) | IPv4 Gateway Octet 1 (ex: 0xC0 = 192) | ||||||||||||||
| Ethernet IPv6 Address | |
| Function: | Specifies the Ethernet IPv6 Address for the Ethernet port. |
| Type: | Five (5) unsigned binary word (32-bit) |
| Data Range: | See table. |
| Read/Write: | R |
| Operational Settings: | The IPv6 Prefix length indicates the network portion of an IPv6 address using the following format: |
- IPv6 address/prefix length
- Prefix length can range from 0 to 128
- Typical prefix length is 64
The following is an illustration of IPv6 addressing with IPv6 Prefix length of 64.
| 64 bits | 64 bits | ||||||
| Prefix | Interface ID | ||||||
| Prefix 1 | Prefix 2 | Prefix 3 | Subnet ID | Interface ID 1 | Interface ID 2 | Interface ID 3 | Interface ID 4 |
| Example: 2002:c0a8:101:0:7c99:d118:9058:1235/64 | |||||||
| 2002 | C0A8 | 0101 | 0000 | 7C99 | D118 | 9058 | 1235 |
| Ethernet IPv6 Address (Note: little-endian order within 32-bit and 16-bit words in register) (ex. IPv6 Address: 2002:c0a8:201:0:7c99:d118:9058:1235 IPv6 Prefix: 64) | |||||||||||||||
| Word 1 (Ethernet IPv6 Address (Prefix 1-2)) (ex:0xA8C0 0220 = 2002 C0A8) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Prefix 2 (ex: 0xA8C0 = C0A8) | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Prefix 1 (ex: 0x0220 = 2002) | |||||||||||||||
| Word 2 (Ethernet IPv6 Address (Prefix 3/Subnet ID)) (ex:0x000 0201 = 0201 0000) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Subnet ID (ex: 0x0000 = 0000) | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Prefix 3 (ex: 0x0201 = 0201) | |||||||||||||||
| Word 3 (Ethernet IPv6 Address (Interface ID 1-2)) (ex: 0x18D1 997C = 7C99 D118) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Interface ID 2 (ex: 0x18D1 = D118) | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Interface ID 1 (ex: 0x997C = 7C99) | |||||||||||||||
| Word 4 (Ethernet IPv6 Address (Interface ID 3-4)) (ex: 0x3512 5890 = 9058 1235) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| Interface ID 4 (ex: 0x3512 = 1235) | |||||||||||||||
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Interface ID 3 (ex: 0x5890 = 9058) | |||||||||||||||
| Word 5 (Ethernet IPv6 Prefix Length) (ex:0x0000 0040) | |||||||||||||||
| D31 | D30 | D29 | D28 | D27 | D26 | D25 | D24 | D23 | D22 | D21 | D20 | D19 | D18 | D17 | D16 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Prefix Length (ex: 0x0040 = 64) | |||||||||||||||
Interrupt Vector and Steering
When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.
Note
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).
| Interrupt Vector | |
| Function: | Set an identifier for the interrupt. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | When an interrupt occurs, this value is reported as part of the interrupt mechanism. |
| Interrupt Steering | |
| Function: | Sets where to direct the interrupt. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | See table |
| Read/Write: | R/W |
| Initialized Value: | 0 |
| Operational Settings: | When an interrupt occurs, the interrupt is sent as specified: |
| Direct Interrupt to VME | 1 |
| Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App) | 2 |
| Direct Interrupt to PCIe Bus | 5 |
| Direct Interrupt to cPCI Bus | 6 |
Modules Health Monitoring Registers
| Module BIT Status | |
| Function: | Provides the ability to monitor the individual Module BIT Status. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R |
| Operational Settings: | The Module BIT Status registers provide the ability to monitor individual Module BIT results as Latched and current value. A 1 is any bit field indicates BIT failure for the Module in that slot. |
| Bit(s) | Description |
| D31:D21 | Reserved |
| D20 | Module Slot 4 BIT Failure (current value) |
| D19 | Module Slot 3 BIT Failure (current value) |
| D18 | Module Slot 2 BIT Failure (current value) |
| D17 | Module Slot 1 BIT Failure (current value) |
| D16 | MB |
| D15:D5 | Reserved |
| D4 | Module Slot 4 BIT Failure - Latched |
| D3 | Module Slot 3 BIT Failure - Latched |
| D2 | Module Slot 2 BIT Failure - Latched |
| D1 | Module Slot 1 BIT Failure - Latched |
| D0 | MB BIT |
| Scratchpad Area | |
| Function: | Registers reserved as scratch pad for customer use. Note, this area is also used to copy results from FRAM so that data can be read via the PCIe bus. |
| Type: | unsigned binary word (32-bit) |
| Data Range: | 0x0000 0000 to 0xFFFF FFFF |
| Read/Write: | R/W |
| Operational Settings: | This area in memory is reserved for customer use or POST FRAM results. |
MOTHERBOARD FUNCTION REGISTER MAP
KEY
| Configuration/Control |
| Measurement/Status/Board Information |
| MODULE INFORMATION REGISTERS | |||||
| OFFSET | REGISTER NAME | ACCESS | OFFSET | REGISTER NAME | ACCESS |
| 0x03FC | Module Slot Addressing Ready | R | |||
| 0x0400 | Module Slot 1 Address | R | 0x0430 | Module Slot 1 Size | R |
| 0x0404 | Module Slot 2 Address | R | 0x0434 | Module Slot 2 Size | R |
| 0x0408 | Module Slot 3 Address | R | 0x0438 | Module Slot 3 Size | R |
| 0x040C | Module Slot 4 Address | R | 0x043C | Module Slot 4 Size | R |
| 0x0460 | Module Slot 1 ID | R | |||
| 0x0464 | Module Slot 2 ID | R | |||
| 0x0468 | Module Slot 3 ID | R | |||
| 0x046C | Module Slot 4 ID | R | |||
| HARDWARE INFORMATION REGISTERS | |||||
| OFFSET | REGISTER NAME | ACCESS | OFFSET | REGISTER NAME | ACCESS |
| 0x0020 | Product Serial Number | R | |||
| 0x0024 | Platform | R | 0x0030 | Processor Count/Ethernet Count | R |
| 0x0028 | Model | R | 0x0034 | Maximum Module Slot Count/ARM Platform Type | R |
| 0x002C | Generation | R | |||
| 0x0038 | Processor Platform (Bit 0-31) | R | 0x0040 | Processor Operating System (Bit 0-31) | R |
| 0x003C | Processor Platform (Bit 32-63) | R | 0x0044 | Processor Operating System (Bit 32-63) | R |
| 0x0048 | Processor Operating System (Bit 64-95) | R | |||
| 0x004C | Processor Operating System Version (Bit 0-31) | R | |||
| 0x0050 | Processor Operating System Version (Bit 32-63) | R | |||
| MOTHERBOARD FIRMWARE INFORMATION REGISTERS | |||||
| OFFSET | REGISTER NAME | ACCESS | OFFSET | REGISTER NAME | ACCESS |
| Motherboard Core Information | Motherboard FPGA Information | ||||
| 0x0100 | MB Core Major/Minor Version | R | 0x0270 | MB FPGA Revision | R |
| 0x0104 | MB Core Minor 2/3 Version | R | 0x0274 | MB FPGA Compile Date/Time | R |
| 0x0108 | MB Core Build Date (Bit 0-31) | R | |||
| 0x010C | MB Core Build Date (Bit 32-63) | R | |||
| MOTHERBOARD MONITORING REGISTERS | |||||
| OFFSET | REGISTER NAME | ACCESS | OFFSET | REGISTER NAME | ACCESS |
| Temperature Readings | High Precision Temperature Readings | ||||
| 0x0200 | Current UltraScale Temperatures | R | 0x0230 | Current UltraScale Core Temperature | R |
| 0x0204 | Reserved | R | 0x0234 | Current UltraScale PCB Temperature | R |
| 0x0208 | Max UltraScale Temp | R | |||
| 0x020C | Reserved | R | |||
| 0x0210 | Min UltraScale Temperatures | R | |||
| 0x0214 | Reserved | R | |||
| MOTHERBOARD HEALTH MONITORING REGISTERS | |||||
| OFFSET | REGISTER NAME | ACCESS | OFFSET | REGISTER NAME | ACCESS |
| 0x20F8 | Motherboard Sensor Summary Status | R | |||
| ETHERNET CONFIGURATION REGISTERS | |||||
| OFFSET | REGISTER NAME | ACCESS | OFFSET | REGISTER NAME | ACCESS |
| Ethernet A | Ethernet B | ||||
| 0x0070 | Ethernet A MAC (Octets 1-4) | R | 0x00A0 | Ethernet B MAC (Octets 1-4) | R |
| 0x0074 | Ethernet A MAC (Octets 5-6)/Misc Settings | R | 0x00A4 | Ethernet B MAC (Octets 5-6)/Misc Settings | R |
| 0x0078 | Ethernet A Interface Name (Bit 0-31) | R | 0x00A8 | Ethernet B Interface Name (Bit 0-31) | R |
| 0x007C | Ethernet A Interface Name (Bit 32-63) | R | 0x00AC | Ethernet B Interface Name (Bit 32-63) | R |
| 0x0080 | Ethernet A IPv4 Address | R | 0x00B0 | Ethernet B IPv4 Address | R |
| 0x0084 | Ethernet A IPv4 Subnet Mask | R | 0x00B4 | Ethernet B IPv4 Subnet Mask | R |
| 0x0088 | Ethernet A IPv4 Gateway | R | 0x00B8 | Ethernet B IPv4 Gateway | R |
| 0x008C | Ethernet A IPv6 Address (Prefix 1-2) | R | 0x00BC | Ethernet B IPv6 Address (Prefix 1-2) | R |
| 0x0090 | Ethernet A IPv6 Address (Prefix 3/Subnet ID) | R | 0x00C0 | Ethernet B IPv6 Address (Prefix 3/Subnet ID) | R |
| 0x0094 | Ethernet A IPv6 Address (Interface ID 1-2) | R | 0x00C4 | Ethernet B IPv6 Address (Interface ID 1-2) | R |
| 0x0098 | Ethernet A IPv6 Address (Interface ID 3-4) | R | 0x00C8 | Ethernet B IPv6 Address (Interface ID 3-4) | R |
| 0x009C | Ethernet A IPv6 Prefix Length | R | 0x00CC | Ethernet B IPv6 Prefix Length | R |
| INTERRUPT REGISTERS | |||||
| OFFSET | REGISTER NAME | ACCESS | OFFSET | REGISTER NAME | ACCESS |
| 0x0500 - 0x057C | Module 1 Interrupt Vector 1 - 32 | R/W | 0x0600 - 0x067C | Module 1 Interrupt Steering 1 - 32 | R/W |
| 0x0700 - 0x077C | Module 2 Interrupt Vector 1 - 32 | R/W | 0x0800 - 0x087C | Module 2 Interrupt Steering 1 - 32 | R/W |
| 0x0900 - 0x097C | Module 3 Interrupt Vector 1 - 32 | R/W | 0x0A00 - 0x0A7C | Module 3 Interrupt Steering 1 - 32 | R/W |
| 0x0B00 - 0x0B7C | Module 4 Interrupt Vector 1 - 32 | R/W | 0x0B00 - 0x0B7C | Module 4 Interrupt Steering 1 - 32 | R/W |
| MODULES HEALTH MONITORING REGISTERS | |||||
| OFFSET | REGISTER NAME | ACCESS | OFFSET | REGISTER NAME | ACCESS |
| 0x0128 | Module BIT Status (current and latched) | R | |||
| SCRATCHPAD REGISTERS | |||||
| OFFSET | REGISTER NAME | ACCESS | OFFSET | REGISTER NAME | ACCESS |
| 0x3800 - 0x3BFF | Scratchpad Registers | R/W | |||
ETHERNET
(For detailed supplement, please visit the NAI web-site specific product page and refer to: Ethernet Interface for Generation 5 SBC and Embedded IO Boards Specification)
Note
For products capable of 10/100/1000Base-KX functionality - the product Ethernet PHY supports 1000BASE-X. Product interoperability with 10/100/1000BASE-KX is supported with 1000BASE-X (provided that auto-negotiation is disabled).
The Ethernet Interface Option allows communications and control access to all function modules either via the system BUS or Ethernet ports 1 or 2.
| Ethernet 1 | Ethernet 2 | Ethernet 3* | Ethernet 4* | |
| (REF PORT A) | (REF PORT B) | (REF PORT C) | (REF PORT D) | |
| The default IP address: | 192.168.1.16 | 192.168.2.16 | 192.168.3.16 | 192.168.4.16 |
| The default subnet: | 255.255.255.0 | 255.255.255.0 | 255.255.255.0 | 255.255.255.0 |
| The default gateway: | 192.168.1.1 | 192.168.2.1 | 192.168.3.1 | 192.168.4.1 |
*see Part Number Designation for applicability.
Note
Actual “as shipped” card Ethernet default IP addresses may vary based upon final ATP configuration(s).
The NAI interface supports IPv4 and IPv6 and both the TCP and UDP protocols. The Ethernet Operation Mode Command Listener application running on the motherboard host processor implements the operation interface. The listener is operational on startup through the nai_MBStartup process and listen on specific ports for commands to process. The default ports are listed below:
- TCP1 - Port 52801
- TCP2 - Port 52802
- UDP1 - Port 52801
- UDP2 - Port 52802
While the listener is active, note that interrupts from the motherboard do not trigger. The listener can be disabled by turning off the nai_MBStartup process through the Motherboard EEPROM. To turn off nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 1 in the console, either by serial port or telnet to the motherboard, and then reboot the system. To turn on the nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 0 in the console, either by serial port or telnet to the motherboard, and then reboot the system.
Ethernet Message Framework
The interface uses a specific message framework for all commands and responses. All messages begin with a Preamble code and end with a Postamble code. The message framework is shown below.
| Preamble 2 bytes Always 0xD30F | SequenceNo 2 bytes | Type Code 2 byte | Message Length (2 bytes) | Payload (0..1414 bytes) | Postamble 2 bytes Always 0xF03D |
Message Elements
| Preamble | The Preamble is used to delineate the beginning of a message frame. The Preamble is always 0xD30F. |
| SequenceNo | The SequenceNo is used to associate Commands with Responses. |
| Type Code | Type Codes are used to define the type of Command or Response the message contains. |
| Message Length | The Message Length is the number of bytes in the complete message frame starting with and including the Preamble and ending with and including the Postamble. |
| Payload | The Payload contains the unique data that makes up the command or response. Payloads vary based on command type. |
| Postamble | The Postamble is use to delineate the end of a message frame. The Postamble is always 0xF03D. |
Notes
- The messaging protocol applies only to card products.
- Messaging is managed by the connected (client) computer. The client computer will send a single message and wait for a reply from the card. Multiple cards may be managed from a single computer, subject to channel and computer capacity.
Board Addressing
The interface provides two main addressing areas: Onboard and Off-board.
Onboard addressing refers to accessing resources located on the board that is implementing the operation interface (including its modules).
Off-board addressing refers to accessing resources located on another board reachable via VME, PCI, or other bus. Off-board addressing requires a Master/Slave configuration.
The user must always specify if a particular address is Onboard or Off-board. See the command descriptions for the onboard and off-board flags.
Within a particular board (Onboard or Off-board), the address space is broken up into two areas: Motherboard Common Address Space and Module Address Space. All addresses are 32-bit.
Motherboard Common Address Space starts at 0x00000000 and ends at 0x00004000. This is a 4Kx32-bit address space (16 kbytes).
Module Address Space starts at 0x00004000. Module addressing is dynamically configured at startup. NAI boards support between 1 and 6 modules. The minimum module address space size is 4Kx32 (16 kbytes) and module sizes are always a multiple of 4Kx32.
Module addressing is dynamic and cumulative. The first detected module (starting with Slot 1) is given an address of 0x00004000. The 2nd detected Module is given an address of:
First_Detected_Module_Address + First_Detected_Module_Size
Note
Slots do not define addresses.
If no module is detected in a module slot, that slot is not given an address. Therefore, if the first detected Module is in Slot 2, then that module address will be 0x00004000. If the next detected module is in Slot 4, then the address of that Module will be:
Second_Detected_Module_Address = First_Detected_Module_Address + First_Detected_Module_Size
If a 3rd Module is detected in Slot 6, then the address of that Module will be:
Third_Detected_Module_Address = Second_Detected_Module_Address + Second_Detected_Module_Size
Note
Module addresses are calculated at each board startup when the modules are detected. Therefore, if a module should fail to be detected due to malfunction or because it was removed from the motherboard, the addresses of the modules that follow it in the slot sequence will be altered. This is important to note when programming to this interface.
Users can always retrieve the Module Addresses, Module Sizes and Module IDs from the fixed Motherboard Common address area. This data is set upon each board startup. While the Module Addressing is dynamic, the address where these addresses are stored is fixed. For example, to find the startup address of the module location in Slot 3, refer to the MB Common Address 0x00000408 from the Motherboard Common Addresses table that follows.
Ethernet Wiring Convention
| RJ-45 Pin | T568A Color | T568B Color | 10/100Base-T | 1000BASE-T | NAI wiring convention |
| 1 | white/green stripe | white/orange stripe | TX+ | DA+ | ETH-TP0+ |
| 2 | green | orange | TX- | DA- | ETH-TP0- |
| 3 | white/orange stripe | white/green stripe | RX+ | DB+ | ETH-TP1+ |
| 4 | blue | blue | DC+ | ETH-TP2+ | |
| 5 | white/blue stripe | white/blue stripe | DC- | ETH-TP2- | |
| 6 | orange | green | RX- | DB- | ETH-TP1- |
| 7 | white/brown stripe | white/brown stripe | DD+ | ETH-TP3+ | |
| 8 | brown | brown | DD- | ETH-TP3- |
DOCS.NAII REVISIONS
| Revision Date | Description |
|---|---|
| 2026-06-24 | Initial publication of NIU3R manual. |
NAI Cares
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