CIU3 Manual

CIU3 DATA SHEET

Click here for the CIU3 Data Sheet

INTRODUCTION

This manual provides information about the North Atlantic Industries, Inc. (NAI) CIU3 System. The CIU3 is a “COSA® Integration Unit”; self-contained Multifunction I/O System preconfigured with 12-CH programmable Discrete I/O, 4-CH ARINC 429/575, 4-CH A/D, 4-CH Serial, 2-CH CANBus, and 1-CH MIL-STD-1553 functions. The CIU3 can also be configured with up to three additional smart Configurable Open Systems Architecture™ (COSA®) function modules. The CIU3 boasts a dual ARM ®Cortex®-A53 processor for customer application and I/O and communications management.

SOFTWARE SUPPORT

The ENAIBL Software Support Kit (SSK) is supplied with all system platform based board level products. This platform’s SSK contents include html format help documentation which defines board specific library functions and their respective parameter requirements. A board specific library and its source code is provided (module level ‘C’ and header files) to facilitate function implementation independent of user operating system (O/S). Portability files are provided to identify Board Support Package (BSP) dependent functions and help port code to other common system BSPs. With the use of the provided help documentation, these libraries are easily ported to any 32-bit O/S such as RTOS or Linux.

The latest version of a board specific SSK can be downloaded from our website www.naii.com in the software downloads section. A Quick-Start Software Manual is also available for download where the SSK contents are detailed, Quick-Start Instructions provided and GUI applications are described therein. For other operating system support, contact factory.

CONVENTIONS USED IN THIS MANUAL

Note

An operating procedure, practice, or condition, etc., that is essential to emphasize.

All numbers are expressed in decimal format unless otherwise noted.

Website

http://www.naii.com/

GENERAL SAFETY NOTICES

The following general safety notices supplement the specific warnings and cautions appearing elsewhere in the manual. They are recommended precautions that must be understood and applied during operation and maintenance of the instrument covered herein.

Death or serious injury may result if personnel fail to observe safety precautions. Dependent on configuration, some modules (e.g. Synchro / Resolver or AC signal sources) can generate output signals with high voltages. Be careful not to contact high-voltage connections when installing, operating or maintaining this instrument.

The CIU3 is delivered as a standalone system with no accessible or serviceable parts.

Repair

DO NOT ATTEMPT REPAIR. Under no circumstances should repair of this instrument be attempted. All repairs to this chassis must be accomplished at the factory.

High Voltage

HIGH VOLTAGE may be used in the operation of this equipment.

Input Power Always On

Note

The design of the model CIU3 is such that DC input power is continuously supplied to internal circuits when connected to a main power source. To disconnect the CIU3 from external power, the external power source should first be de-energized. The power input cable can then be disconnected.

SYSTEM SPECIFICATIONS & DETAILS

Introduction

The COSA® Integration Unit (CIU3) is a versatile, compact, low-power, self-contained multifunction I/O system with unprecedented I/O capability configurations. The CIU3 connects to existing platform Ethernet networks, making data available to any system on the network. Additionally, the CIU3 is delivered with ARM® Cortex®-A53 access support for standalone or other processor related capability. The CIU3 easily adds sensor data acquisition and distribution and communication interfaces to mission computers without expensive chassis and backplane redesign. It has been designed with rugged embedded industrial, military and aerospace applications in mind. Leveraging NAI’s field-proven, unique modular architecture, the CIU3 supports a wide selection of different Intelligent I/O, motion simulation/measurement and communications functions such as:

A/D Converter	D/A Converter	I/O TTL/CMOS	RTD	I/O Discrete
I/O Differential Transceiver	Synchro/Resolver LVDT/RVDT Measurement	Synchro/Resolver LVDT/RVDT Simulation	Strain Gage	Encoder
Dual-Channel Dual Redundant BC/RT/MT MIL-STD-1553	High-Speed Sync/Async RS232/422/423/485	ARINC 429/575	CANBus	I/O Relay
AC Reference	Ethernet Switch	SSD/Flash

This approach provides unprecedented flexibility for supporting existing or new applications where there are specific interfacing requirements.

Significant application benefits include:

• Independent (pre-processed) I/O functionality targeted to specific data acquisition/control areas

• Additional capabilities, technology insertion and sensor interfacing to existing fielded applications

• Minimal integration risk based on current field-proven, deployed technologies

• Only ~9.5” x 8.25” x 1.125” @ ~4.5 lbs. (2.04 kg) conduction cooled

• 2x Ethernet

  • 10/100/1000Base-T (GbE) (default)

Objectives

This manual provides the user with basic hardware implementation and information regarding the operation and interface of the CIU3. Each CIU3 is fitted with one, two or three function modules, six embedded module functions, dual-core processor and an integrated motherboard, power supply unit (PSU) and interface connectors.

Scope

This manual covers the basic operation of the CIU3 as a standalone I/O subsystem with pertinent/specific details relating to the operation/communications from/to the CIU3 with the available function module(s) fitted within the CIU3.

ON BOARD RESOURCES

Memory

DDR4 SDRAM

The CIU3 is equipped with 4 GB of LPDDR4 memory using MT53E1G32D2FW devices. Memory is organized using a 1 Gb x 32 LPDDR4 component. The integrated 64-bit memory controller within the UltraScale+™ supports full error correction capabilities, detecting multi-bit faults and correcting single-bit errors within a nibble. For device-specific, please refer to the Micron data sheet.

QSPI Flash

The CIU3 supports two Micron MT25QL02GCBB8E12-0SIT 256 MBb, Quad-SPI (QSPI) flash devices. These devices are used for nonvolatile storage of the ARM boot code, user data, and program. These devices connect to the APU dedicated interface. The device interface may contain a secondary boot code. These devices supports the Common Flash Interface (CFI). This 4-bit data memory interface can sustain burst read operations.

FRAM

The FM24CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. The ferroelectric random-access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years. The CIU3 FRAM 64K bits are organized as 8,192 x 8 bits random access memory, connected to the Ultrascale+™ CPU through the I²C controller.

SATA

The Ultrascale+™ CPU is directly connected to an onboard Solid-State Drive (SSD). The SSD contains a single level cell NAND Flash together with a controller in a single Multi-Chip package. The Multi-Chip packaged device is soldered directly to the printed circuit board for reliable electrical and mechanical connection.

The SSD has an internal write protect signal SATA_WP. The SATA_WP signal must be connected or switched to ground to enable any write to the SSD. The SATA_WP signal is pulled up on card by a 4.7 KΩ resistor to the internal 3.3 V supply.

The onboard SATA drive conforms to the follow specifications:

• Complies with Serial ATA 2.5 Specification
• Supports speeds: 1.5 Gbps (first-generation SATA), 3 Gbps (second-generation SATA and eSATA)
• Supports advanced technology attachment packet interface (ATAPI) devices
• Contains high-speed descriptor-based DMA controller
• Supports native command queuing (NCQ) commands

The standard ordering code for the CIU3 includes a 32GB SSD drive. Larger devices are available; please consult the factory for availability.

Peripheral I/O

Ethernet

The CIU3 supports two 10/100/1000Base-TX Ethernet connections using two Marvell Alaska 88E1512 Ethernet PHY devices and the Xilinx Gigabit Ethernet MACs. The PHY-to-MAC interface employs a Reduced Gigabit Media Independent Interface (RGIII) connection using four data lines at 250 Mbps each for a connection speed of 1 Gbps. The CIU3 contains internal magnetics and can directly drive copper CAT5e or CAT6 twisted pairs.

The CIU3 Ethernet ports support:

• Detection and correction of pair swaps (MDI crossover), and pair polarity
• MAC-side and line-side loopback
• Auto-negotiation

Ethernet Port 1 can be routed as 10/100/1000Base-TX Ethernet as a build option.

Ethernet Port 2 can be routed as 10/100/1000Base-TX Ethernet as a build option.

I/O pin outs can be found in the Pinout Details section of this document.

USB

The CIU3 supports one USB 2.0 port. Contact factory for availability.

USB0 is available on the CIU3, on connector J2. The USB port can operate as a standalone host.

• Compatible with USB specification, Rev. 2.0
• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
• Supports operation as a standalone USB host controller
• Supports USB root hub with one downstream-facing port
• Enhanced host controller interface (EHCI)-compatible
• One controller supports operation as a standalone USB device
• Supports one upstream-facing port
• Supports six programmable USB endpoints

I²C

I²C is a two-wire, bidirectional single ended serial bus that provides an efficient method of exchanging data between a master and slave device. The CIU3 has one I²C device for communicating with onboard devices, as shown in the table below.

Assignment	I2C addresses	Device
Onboard Devices	0x50 + 0x56	EEPROM
	0x53	FRAM

Serial Port

The CIU3 has a single, asynchronous serial port. The interface uses a two-wire, TXD, RXD interface (system/power GND referenced). The SER-TXD and SER-RXD RS-232 signals are routed to J2 on the CIU3.

Software Libraries/Associated Documents

CIU3 BSP Processor Module Library

The CIU3 Processor library package provides function interfaces to the on-module functionality. This package contains Help documentation (in html format) that explains all the functions available in the library. The package also contains the source code (**.h, **.c) files as well as the files needed to build the library using any of the supported operating systems. Example programs are also provided to demonstrate the usage of the libraries in typical applications of the module.

Associated Documents

Check the NAI website or contact factory for the latest downloads and documentation.

SPECIFICATIONS

The CIU3 is designed to meet the following general specifications.

General Specifications
Ethernet Data Transfer:	Data transfers within 1 ms (typical)
Input Voltage	18 to 36 VDC (28 VDC nominal)
Power (Base unit):	0.6 A (~17 W) @ 28 VDC nominal plus module(s) power (see specific module(s) specifications) I/O Signal GND reference is isolated from main power source return and chassis.
Power/Heat Dissipation:	~30 watts (maximum) when properly mounted, with the thermal transfer mounting surface maintained at a temperature not to exceed 71°C. Note: The total CIU3 power dissipation is dependent on the configuration of the modules fitted in the CIU3.
Temperature, Operating:	-40°C to 71°C (conduction cooled - measured at primary thermal interface)
Temperature, Storage:	-55°C to 105°C
Size:	Depth: ~8.25" (209.6 mm) Height: ~1.125" (28.6 mm) Width: ~9.5” (241.3 mm)
Weight:	The weight of an CIU3 system is dependent on the configuration. The approximate weight of the CIU3 is based on the selection of the functional module(s). The approximate weight of a typical fully configured CIU3 (model #) is ~4.5 lbs. (2.04 kg).

Environmental

Please contact factory regarding Environmental testing based on the specific configuration and program requirements.

EMC/EMI

Please contact factory regarding EMC/EMI testing based on the specific configuration and program requirements.

UNPACKING & INSPECTION

Figure 1. CIU3

Unpacking

The CIU3 packing materials were designed specifically for transport protection of the CIU3. When receiving the shipment container, inspect packaging for any evidence of physical damage. If damage is evident, it is recommended that the carrier agent is present when opening the shipping container. It is further recommended that all packing material is retained in the event the CIU3 needs to be shipped elsewhere.

System/Chassis Identification

An identification label, indicating part number, unique serial number, and Ethernet PHY MACs / default IP address(es) is affixed to the side of the system chassis.

Figure 2. Unit Identification

Inspection

Inspect the chassis and connectors to ensure that they were not damaged during transit.

MECHANICAL INTERFACE

Mechanical Description

The CIU3 is a rugged, aluminum, conduction-cooled system. It must be mounted to a cold plate. The system thermal management design considerations should ensure that the chassis thermal interface (CIU3 bottom surface) does not exceed 71°C. Mounting holes are provided on the chassis bottom housing flanges (as depicted). See the outline drawing below.

Mounting Requirements

The CIU3 is conduction cooled and must be mounted in accordance with the drawing. The OID provides recommended hardware, torque, cold-plate flatness and surface finish specifications, and thermal conductivity requirements.

Figure 3. CIU3 Outline Dimensions/Cold Plate Mounting Pattern (Reference Only)

Notes:

1. Unless otherwise specified, dimensions are in inches (mm); tolerances are:

• 2 PL DEC ±0.01; 3 PL DEC ±0.005
• FRACT ±1/64 (0.4); ANGLES ±1/2 (12.7)

Chassis (Earth) GND

Chassis ground point threaded insert location is on the connector side of the CIU3 as shown. IMAGE PENDING

Figure 4. CIU3 Outline Dimensions/Chassis GND Location

Note

Chassis GND braid or equivalent to be secured by 6-32 screw/studs (with a depth of 0.3 inches) as end application requires. The CIU3 chassis is provided with 6-32 threaded insert only. The recommended torque for the CIU3 Chassis GND screw is 11 in-lbs. (125 N·cm)

CONNECTOR DESIGNATION & DESCRIPTION

The Power, I/O Interface and Ethernet connectors are located on the CIU3 front panel housing.

Figure 5. CIU3 (Front Panel Connector Placement)

CIU3 Connector Designation and Description

Connector Designation	Description
J1	Primary Power Connector, VDC
J2	Inboard Functions, Ethernet Communication & Debug
J3	I/O, Module-1, Module-2, & Module-3

Connector Details and Pinout

This section details connector and pinout information. See module I/O section or contact factory regarding any special module I/O configuration.

J1, Primary Power Connector

Primary input power is supported on the CIU3 via the J1 connector. Connectors used are as follows:

Figure 6. J1 Primary Power Connector Detail

Parts Identification

J1 Primary Power Connector Definition

	Chassis (Box-level)			Mating Cable Connector
Designation	MIL-DTL Equivalent Reference	Rows / Socket Size	Pin-count	MIL-DTL Equivalent Reference	NAI P/N + (for reference)
J1	MK-2C2-009-225-2600	2 / 22	9	MM-212-009-113-4100	05-0740

Pinout

J1 Primary Power Connector Pinout

J1 Connector Pin	Signal
1	28VDC-IN
2	28VDC-IN
3	28VDC-RTN
4	28VDC-RTN
5	Chassis GND
6	28VDC-IN
7	28VDC-IN
8	28VDC-RTN
9	28VDC-RTN

J2, Inboard Functions, Ethernet Communication & Debug

The J2 connector on the CIU3 supports all inboard module functions (MIL-STD-1553, ARINC 429/575, CAN, A/D, Discrete I/O, Serial Comms), up to two 10/100/1000Base-T ports (when appropriately configured) and debug/maintenance signals. The debug/maintenance signals provided are an RS-232 console port and System Reset (for a soft reset/reload). Additionally, typically for ARM/processor optioned configurations, a USB 2.0 port, Hardware Write Protect (for SATA accessibility) and a Real Time Clock Standby (i.e. auxiliary 3.3V/battery backup for the real time clock) are also provided.

Figure 7. J2 Inboard Functions, Ethernet Communications & Debug Connector Detail

Parts Identification

J2 Inboard Functions, Ethernet Communications & Debug Connector Definition

	Chassis (Box-level)			Mating Cable Connector
Designation	MIL-DTL Equivalent Reference	Rows / Socket Size	Pin-count	MIL-DTL Equivalent Reference	NAI P/N + (for reference)
J2	MK-4C2-100-225-6600	4 / 22	100	MM-412-100-113-8100	05-0738

Pinout

J2 Inboard Functions, Ethernet Communications & Debug Connector Pinout

J2 Connector Pin	Signal	Notes
1	DT-IO-CH01
2	DT-IO-CH12
3	DT-IO-CH06
4	DT-IO-CH07
5	DT-ISO-GND
6	GND	*6
7	TXDLO-CH4
8	TXDHI-CH4
9	RXDHI-CH4
10	TXDLO-CH3
11	TXDHI-CH3
12	RXDHI-CH3
13	GND	*6
14	TXDLO-CH2
15	RXDLO-CH2
16	RXDH1-CH2
17	TXDLO-CH1
18	RXDLO-CH1
19	RXDH1-CH1
20	GND	*6
21	AD0-SYNC-O1-N
22	AD1-SYNC-O2-P
23	AD1-SYNC-O2-N
24	GND-CAN1
25	CAN-CH1-H
26	CAN-CH1-L
27	DT-IO-CH03
28	DT-IO-CH02
29	DT-IO-CH08
30	GND	*6
31	GND	*6
32	ETH0-TP2P	*7
33	ETH0-TP0P	*7
34	RXDLO-CH4
35	ETH1-TP1N	*7
36	ETH1-TP2N	*7
37	RXDLO-CH3
38	SER0-RXD	*2
39	I2C1-SCL	*5
40	TXDHI-CH2
41	GND	*6
42	SYNC-ID3
43	TXDHI-CH1
44	SYNC-ID1
45	GND	*8
46	AD0-SYNC-O1-P
47	AD2-SYNC-I1-N
48	AD3-SYNC-I2-N
49	GND	*6
50	GND-CAN2
51	CAN-CH2-L
52	DT-IO-CH11
53	DT-IO-CH05
54	DT-IO-CH09
55	DT-ISO-GND
56	ETH0-TP2N	*7
57	ETH0-TP0N	*7
58	ETH0-TP1P	*7
59	ETH1-TP1P	*7
60	ETH1-TP2P	*7
61	ETH1-TP0N	*7
62	GND	*6
63	SER0-TXD	*2
64	+5V0-USB05V0	*4
65	I2C1-SDA	*5
66	v31
67	AR429A-CH3
68	SYNC-ID2
69	NVMRO	*3
70	AR429A-CH2
71	AD2-SYNC-I1-P
72	AD3-SYNC-I2-P
73	1553-BUSA-CH1-P
74	GND	*6
75	CAN-CH2-H
76	DT-IO-CH04
77	DT-VCC1
78	DT-IO-CH10
79	DT-VCC2
80	ETH0-TP3N	*7
81	ETH0-TP3P	*7
82	ETH0-TP1N	*7
83	ETH1-TP3P	*7
84	ETH1-TP3N	*7
85	ETH1-TP0P	*7
86	USB0-D-N	*4
87	USB0-D-P	*4
88	GND	*6
89	SYSRSTn	*1
90	GND	*6
91	AR429B-CH3
92	AR429B-CH4
93	AR429A-CH4
94	AR429B-CH2
95	AR429B-CH1
96	AR429A-CH1
97	GND	*6
98	1553-BUSA-CH1-N
99	1553-BUSB-CH1-N
100	1553-BUSB-CH1-P

Notes

1.	SYSRSTn : An active “low” or GND logic level (as referenced to System GND of the CIU3) assertion of the SYSRST# signal (internally pulled ‘high’) on the CIU3 processor and module cards will initiate an CIU3 system reset.
2.	Debug: RS-232 Serial Communications Console port
3.	NVMRO: Used for SATA Flash write enable/disable on the processor of the CIU3. OPEN for Write Protect, GND for Write Enable.
4.	USB: USB 2.0 compatibility - accessible with processor accessible version of the CIU3.(ARM option only).
5.	I2C1-Sxy: The two lines used for I2C communications. SCL (Serial Clock) synchronizes all data transfers over the I2C bus, SDA (Serial Data) carries the data.
6.	GND: All the identified GNDs are referenced to the same internal signal GND (System GND).
7.	ETHx-TPyz: Standard CIU3 configuration provides 2x 10/100/1000Base-T Ethernet ports: x = port number; y = twisted pair/differential signal number (0/1/2/3); z = differential signal polarity (p = positive(+) and n = negative(-)).

J3, I/O, Module-1, Module-2, & Module-3

The J3 I/O connector supports Module-1, Module-2, and Module-3 function I/O.

Figure 8. J3 I/O Module-1/-2/-3 Connector Detail

Parts Identification

J3 I/O Module-1/-2/-3 Connector Definition

	Chassis (Box-level)			Mating Cable Connector
Designation	MIL-DTL Equivalent Reference	Rows / Socket Size	Pin-count	MIL-DTL Equivalent Reference	NAI P/N + (for reference)
J3	MK-4C2-100-225-6600	4 / 22	100	MM-412-100-113-8100	05-0738

Pinout

Generic pinout. See module I/O section or contact factory regarding any special module I/O configuration.

J3 I/O Module-1/-2/-3 Connector Pinout

J3 Connector Pin	Signal + (CIU3)	Signal + (CIU3P)	Notes
1	GND	GND	Signal/System Ground
2	MOD1-DATIO03	MOD1-ETH1-TP2P	*
3	MOD1-DATIO02	MOD1-ETH1-TP0N	*
4	MOD1-DATIO01	MOD1-ETH1-TP0P	*
5	MOD1-DATIO11	MOD1-ETH2-TP3P	*
6	MOD1-DATIO23	MOD1-ETH4-TP3P	*
7	MOD1-DATIO24	MOD1-ETH4-TP3N	*
8	MOD1-DATIO31	MOD1-ETH4-TP1P	*
9	MOD2-DATIO30	MOD2-DATIO30	*
10	MOD2-DATIO29	MOD2-DATIO29	*
11	MOD2-DATIO20	MOD2-DATIO20	*
12	MOD2-DATIO17	MOD2-DATIO17	*
13	MOD2-DATIO18	MOD2-DATIO18	*
14	MOD2-DATIO01	MOD2-DATIO01	*
15	MOD2-DATIO03	MOD2-DATIO03	*
16	MOD2-DATIO04	MOD2-DATIO04	*
17	MOD3-DATIO01	MOD3-DATIO01	*
18	MOD3-DATIO15	MOD3-DATIO15	*
19	MOD3-DATIO16	MOD3-DATIO16	*
20	MOD3-DATIO29	MOD3-DATIO29	*
21	MOD3-DATIO12	MOD3-DATIO12	*
22	MOD3-DATIO11	MOD3-DATIO11	*
23	MOD3-DATIO17	MOD3-DATIO17	*
24	MOD3-DATIO19	MOD3-DATIO19	*
25	MOD3-DATIO20	MOD3-DATIO20	*
26	N/C	N/C	*1
27	MOD1-DATIO14	MOD1-ETH3-TP0N	*
28	MOD1-DATIO04	MOD1-ETH1-TP2N	*
29	MOD1-DATIO28	MOD1-ETH2-TP1N	*
30	MOD1-DATIO16	MOD1-ETH3-TP2N	*
31	MOD1-DATIO12	MOD1-ETH2-TP3N	*
32	MOD1-DATIO29	MOD1-ETH3-TP1P	*
33	MOD1-DATIO21	MOD1-ETH4-TP2P	*
34	MOD1-DATIO32	MOD1-ETH4-TP1N	*
35	MOD2-DATIO16	MOD2-DATIO16	*
36	MOD2-DATIO13	MOD2-DATIO13	*
37	MOD2-DATIO19	MOD2-DATIO19	*
38	MOD2-DATIO12	MOD2-DATIO12	*
39	MOD2-DATIO27	MOD2-DATIO27	*
40	MOD2-DATIO02	MOD2-DATIO02	*
41	MOD2-DATIO22	MOD2-DATIO22	*
42	MOD2-DATIO25	MOD2-DATIO25	*
43	MOD3-DATIO02	MOD3-DATIO02	*
44	MOD3-DATIO03	MOD3-DATIO03	*
45	MOD3-DATIO13	MOD3-DATIO13	*
46	MOD3-DATIO30	MOD3-DATIO30	*
47	MOD3-DATIO10	MOD3-DATIO10	*
48	MOD3-DATIO28	MOD3-DATIO28	*
49	MOD3-DATIO18	MOD3-DATIO18	*
50	MOD3-DATIO21	MOD3-DATIO21	*
51	GND	GND	Signal/System Ground
52	MOD1-DATIO25	MOD1-ETH1-TP1P	*
53	MOD1-DATIO13	MOD1-ETH3-TP0P	*
54	MOD1-DATIO27	MOD1-ETH2-TP1P	*
55	MOD1-DATIO07	MOD1-ETH2-TP0P	*
56	MOD1-DATIO15	MOD1-ETH3-TP2P	*
57	MOD1-DATIO30	MOD1-ETH3-TP1N	*
58	MOD1-DATIO18	MOD1-ETH3-TP3N	*
59	MOD1-DATIO22	MOD1-ETH4-TP2N	*
60	MOD2-DATIO15	MOD2-DATIO15	*
61	MOD2-DATIO32	MOD2-DATIO32	*
62	MOD2-DATIO14	MOD2-DATIO14	*
63	MOD2-DATIO11	MOD2-DATIO11	*
64	MOD2-DATIO10	MOD2-DATIO10	*
65	MOD2-DATIO28	MOD2-DATIO28	*
66	MOD2-DATIO21	MOD2-DATIO21	*
67	MOD2-DATIO06	MOD2-DATIO06	*
68	MOD2-DATIO26	MOD2-DATIO26	*
69	MOD3-DATIO04	MOD3-DATIO04	*
70	MOD3-DATIO05	MOD3-DATIO05	*
71	MOD3-DATIO14	MOD3-DATIO14	*
72	MOD3-DATIO09	MOD3-DATIO09	*
73	MOD3-DATIO24	MOD3-DATIO24	*
74	MOD3-DATIO27	MOD3-DATIO27	*
75	MOD3-DATIO22	MOD3-DATIO22	*
76	GND	GND	Signal/System Ground
77	MOD1-DATIO26	MOD1-ETH1-TP1N	*
78	MOD1-DATIO05	MOD1-ETH1-TP3P	*
79	MOD1-DATIO06	MOD1-ETH1-TP3N	*
80	MOD1-DATIO08	MOD1-ETH2-TP0N	*
81	MOD1-DATIO09	MOD1-ETH2-TP2P	*
82	MOD1-DATIO10	MOD1-ETH2-TP2N	*
83	MOD1-DATIO17	MOD1-ETH3-TP3P	*
84	MOD1-DATIO19	MOD1-ETH4-TP0P	*
85	MOD1-DATIO20	MOD1-ETH4-TP0N	*
86	MOD2-DATIO31	MOD2-DATIO31	*
87	MOD2-DATIO24	MOD2-DATIO24	*
88	MOD2-DATIO23	MOD2-DATIO23	*
89	MOD2-DATIO09	MOD2-DATIO09	*
90	MOD2-DATIO08	MOD2-DATIO08	*
91	MOD2-DATIO07	MOD2-DATIO07	*
92	MOD2-DATIO05	MOD2-DATIO05	*
93	MOD3-DATIO25	MOD3-DATIO25	*
94	MOD3-DATIO26	MOD3-DATIO26	*
95	MOD3-DATIO06	MOD3-DATIO06	*
96	MOD3-DATIO07	MOD3-DATIO07	*
97	MOD3-DATIO08	MOD3-DATIO08	*
98	MOD3-DATIO23	MOD3-DATIO23	*
99	MOD3-DATIO31	MOD3-DATIO31	*
100	MOD3-DATIO32	MOD3-DATIO32	*

Notes

*	Module signal type is dependent on module function type fitted to slot. NOTE: MOD1-ETHx-TPyz - Variant CIU3P configuration supports only high-speed PCIe interface modules on module slot 1: x = port number; y = twisted pair/differential signal number (0/1/2/3); z = differential signal polarity (p = positive(`) and n = negative(-)).
1.	N/C: Signals are undefined in the standard CIU3 configurations. These signals are considered no-connects (N/C).

POWER-UP & OPERATIONAL DESCRIPTION

Panel LEDs & Functions

Front Panel LEDs indications.

Figure 9. CIU3 Status LEDs Location

CIU3 Status LEDs Function

LED	ILLUMINATED	EXTINGUISHED
GRN:	Blinking: Initializing Steady On: Power-On / Ready	Power-off
YEL:	Blinking: Unit Access (GbE activity)	No Unit Access or Activity
RED:	Module BIT (Attention required)	No Module BIT Attention required

REGISTER MEMORY MAP ADDRESSING

The register map address consists of the following:

• cPCI/PCIe BAR or Base Address for the Board
• Module Slot Base Address
• Function Offset Address

Board Base Address

The table below lists the BAR used for access to the motherboard and module registers. The second BAR is used internally for motherboard and module firmware updates. The other cPCI/PCIe BARs not listed are not used.

NAI Boards	Device ID	Bus	Motherboard and Module Register Access	Motherboard and Module Firmware Updates
Slave Boards
CIU3	N/A	N/A	Direct Memory Access	Internal Direct Memory Access

Module Slot and Function Address

The CIU3 includes (6) basic preconfigured IO functions embedded within the motherboard (onboard functions). These functions are like the standard NAI COSA® smart functions identified as:

1. IF2 = Support function ID; for 1 channels MIL-STD-1553 (A/B redundant) & 4 Channels ARINC 429/575 (combination functions)
2. IF1 = Support function ID; for 2 channels CAN Bus & 4 channels A/D (± 10V) (combination functions)
3. IF3 = Support function ID; for 12-CH programmable Discrete I/O (Enhanced capability) & 4 channels Serial Comms (RS-232/422/485) (combination function)

Additionally, the CIU3 can be fitted with three additional function modules.

The following depicts the memory structure allocated for the (3) onboard function IDs and (3) configured functions

CIU3 function/module structure/order:
Function #1:	Expansion Module 1
Function #2:	Expansion Module 2
Function #3:	Expansion Module 3
Function #4:	Onboard Function IF2-type (MIL-STD-1553, ARINC 429)
Function #5:	Onboard Function IF1-type (CAN Bus, A/D)
Function #6:	Onboard Function IF3-tpe (Discrete I/O, Serial Comms)

The “start” address of the function(s) on the CIU3 are factory pre-defined (and read from)) the Module Address register (refer to the figure below).

Figure 10. Register Memory Map Addressing Example for CIU3

Address Calculation

Motherboard Registers:

Read/Write access to the motherboard registers starts with the base address for the board and then the motherboard base offset address.

For example, to address Module Slot 1 Start Address register (i.e. register address = 0x4000):

1. Start with the base address for the board.
2. Add the motherboard base register address offset.

Motherboard Address =	Base Address Motherboard Address Offset	= 0x9000 4000
	0x9000 0000 + 0x4000

Module Registers:

Read/Write access to the Function module’s registers start with the base address of the board. Add the “content” for the Module Start Address and then, add the specific module function register offset.

For example, to address an appropriate/specific function module with a register offset:

1. Start with the base address for the board.
2. Add the value (contents) from the module base address offset register (contents/value of Motherboard Memory register for Module 1 (i.e., @ 0x4000) = 0x4000.
3. Then add the specific module function Register Offset of interest (i.e., 0x1000)

(Function Specific) Address =	Base Address +	Module Base Address Offset +	Function Register Offset	= 0x9000 5000
	0x9000 0000	0x4000	0x1000

REGISTER DESCRIPTIONS

Module Information Registers

The Module Slot Address, Module Slot Size and Module Slot ID provide information about the modules detected on the board.

Module Slot Addressing Ready
Function:	Indicates that the module slots are ready to be addressed.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	0xA5A5A5A5
Operational Settings:	This register will contain the value of 0xA5A5A5A5 when the module addresses have been determined.

Module Slot Address
Function:	Specifies the Base Address for the module in the specific slot position.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Based on board's module configuration.
Operational Settings:	0x0000 0000 indicates no Module found.

Module Slot Size
Function:	Specifies the Memory Size (in bytes) allocated for the module in the specific slot position.
Type:	unsigned binary word (32-bit)
Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Assigned by factory for the module.
Operational Settings:	0x0000 0000 indicates no Module found.

Module Slot ID
Function:	Specifies the Model ID for the module in the specified slot position.
Type:	4-character ASCII string
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Assigned by factory for the module.
Operational Settings:	The Module ID is formatted as four ASCII bytes: three characters followed by a space. A value of 0000 0000 indicates no Module found.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

ASCII Character (ex: 'A' - 0x41)

ASCII Character (ex: 'D' - 0x44)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ASCII Character (ex: '5' - 0x35)

ASCII Space (' ' - 0x20)

Hardware Information Registers

The registers identified in this section provide information about the board’s hardware.

Product Serial Number
Function:	Specifies the Board Serial Number.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Serial number assigned by factory for the board.
Operational Settings:	N/A

Platform
Function:	Specifies the Board Platform Identifier. Values are for the ASCII characters for the NAI valid platforms (Identifiers).
Type:	4-character ASCII string
Data Range:	See table below.
Read/Write:	R
Initialized Value:	ASCII code is for the Platform Identifier of the board
Operational Settings:	NAI platform for this board is shown below:

NAI Platform	Platform Identifier	4-character ASCII string
CIU	00	0x0000 3030

Model
Function:	Specifies the Board Model Identifier. Values are for the ASCII characters for the NAI valid models.
Type:	4-character ASCII string
Data Range:	See table below.
Read/Write:	R
Initialized Value:	ASCII code is for the Model Identifier of the board
Operational Settings:	NAI model for this board is shown below:

NAI Model	4-character ASCII string
CIU	0x0055 4943

Generation
Function:	Specifies the Board Generation. Identifier values are for the ASCII characters for the NAI valid generation identifiers.
Type:	4-character ASCII string
Data Range:	See table below.
Read/Write:	R
Initialized Value:	ASCII code is for the Generation Identifier of the board
Operational Settings:	NAI generation for this board is shown below:

NAI Generation	4-character ASCII string
3	0x0000 0033

Processor Count/Ethernet Interface Count
Function:	Specifies the Processor Count and Ethernet Interface Count
Type:	unsigned binary word (32-bit)
Data Range:	See table below.
Read/Write:	R
Operational Settings:	Processor Count - Indicates the number of unique processor types on the motherboard = 1 Ethernet Interface Count - Indicates the number of Ethernet interfaces on the product motherboard. For CIU3, the Ethernet Interface Count is set for Dual Ethernet = 2.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Processor Count (0x0001)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Ethernet Interface Count (0x0002)

Maximum Module Slot Count/ARM Platform Type
Function:	Specifies the Maximum Module Slot Count and ARM Platform Type.
Type:	unsigned binary word (32-bit)
Data Range:	See table below.
Read/Write:	R
Operational Settings:	Maximum Module Slot Count = 6 ARM Platform Type - UltraScale+ = 4

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Maximum Module Slot = 0x0006

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ARM Platform Type = 0x0004 (UltraScale)

Processor Operating System Registers

The registers in this section provide information about the Operating System that is running on the host processor on the motherboard. For boards that have more than one processor (ex. 75PPC1, 75INT2, 68PPC2, etc), the host processor would be the Power-PC or Intel processor.

ARM Processor Platform
Function:	Specifies the ARM Processor on the motherboard. Values are for the ASCII characters for the NAI host processor platforms specified by the Operating System.
Type:	8-character ASCII string - Two (2) unsigned binary word (32-bit)
Data Range:	N/A
Read/Write:	R
Initialized Value:	ASCII code is for the Host Platform Identifier of the board
Operational Settings:	Valid NAI platforms based on Operating System loaded to host processor.

Processor Platform (Note: 8-character ASCII string) (“aarch64”)

Word 1 (0x6372 6161 = “craa”)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

'c' (0x63)

'r' (0x72)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

'a' (0x61)

'a' (0x61)

Word 2 (0x0034 3668 = “ 46h”)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

null (0x00)

'4' (0x34)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

'6' (0x36)

'h' (0x68)

Processor Operating System
Function:	Specifies the Operating System installed for the host processor. Values are for the ASCII characters for the NAI supported operating systems.
Type:	12-character ASCII string - Three (3) unsigned binary word (32-bit)
Data Range:	N/A
Read/Write:	R
Operational Settings:	ASCII, 12 characters; ('Linux', 'VxWorks', 'RTOS', ...)

Processor Platform (Note: 12-character ASCII string) (“Linux”)

Word 1 (0x756E 694C = “uniL”)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

'u' (0x75)

'n' (0x6E)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

'i' (0x69)

'L' (0x4C)

Word 2 (0x0000 0078 = “ x”)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

null (0x00)

null (0x00)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

null (0x00)

'x' (0x78)

Word 3 (0x0000 0000 = “ ”)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

null (0x00)

null (0x00)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

null (0x00)

null (0x00)

Motherboard Firmware Information Registers

The registers in this section provide information on the revision of the firmware installed on the motherboard.

Motherboard Core Firmware Version
Function:	Specifies the Version of the NAI factory provided Motherboard Core Application installed on the board.
Type:	Two (2) unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Operational Settings:	The motherboard firmware version consists of four components: Major, Minor, Minor 2 and Minor 3.

Motherboard Core Firmware Version (Note: little-endian order in register) (ex. 4.50.0.0)

Word 1 (Ex. 0050 0004 = 4.50 (Major.Minor)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Minor (ex: 0x0050 = 50)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Major (ex: 0x0004 = 4)

Word 2 (Ex. 0x0000 0000 = 0000 = 0.0 (Minor2.Minor3))

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Minor 3 (ex: 0x000 = 0)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Minor 2 (ex: 0x000 = 0)

Motherboard Firmware Build Date/Time
Function:	Specifies the Build Date/Time of the NAI factory provided Motherboard Core Application installed on the board.
Type:	Two (2) unsigned binary word (32-bit)
Data Range:	N/A
Read/Write:	R
Operational Settings:	The motherboard firmware time consists of the Build Date and Build Time.

Motherboard Firmware Build Time (Note: little-endian order in register)

Word 1 - Build Date (ex. 0x1006 07E5 = 2021-6-16)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Day (ex: 0x10 = 1624)

Month (ex: 0x06 = 6)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Year (ex: 0x07E5 = 2021)

Word 2 - Build Time (ex. 0x001A 1A10 = 16:26:26)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

null (0x00)

Seconds (ex: 0x1A = 26)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Minutes (ex: 0x1A = 26)

Hours (ex: 0x10 = 16)

Motherboard FPGA Firmware Version
Function:	Specifies the Version of the NAI factory provided Motherboard FPGA installed on the board.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Operational Settings:	The motherboard FPGA firmware version consists of two components: Major, Minor

Motherboard FPGA Firmware Version (ex. 0x0005 0009 = 5.9)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Major (ex: 0x0005 = 5)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Minor (ex: 0x0009 = 9)

Motherboard FPGA Firmware Compile Date/Time
Function:	Specifies the Compile Date/Time of the NAI factory provided Motherboard FPGA installed on the board.
Type:	unsigned binary word (32-bit)
Data Range:	N/A
Read/Write:	R
Operational Settings:	The motherboard firmware time consists of the Build Date and Time in the following format:

Motherboard FPGA Compile Time (ex. 0xC32B 2923 = 06/24/21 18:36:35)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Day (D31:D27)

Month (D26:D23)

Year (D22:D17)

ex. 0xC

ex. 0x3

0x2

0xB

1

1

0

0

0

0

1

1

0

0

1

0

1

0

1

10

Day = 0x18 = 24

Month = 0x6 = 6

Year = 0x15 = 21

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Hour (D16:D12)

Minutes (D11:D6)

Seconds (D5:D0)

ex. 0x2

ex. 0x9

ex. 0x2B

ex. 0x3

0

0

1

0

1

0

0

1

0

0

1

0

0

0

1

1

Hour = 0x12 = 18

Minutes = 0x24 = 36

Seconds = 0x23 = 35

Motherboard Monitoring Registers

The registers in this provide motherboard temperature measurement information.

Temperature Readings Register

The temperature registers provide the current, maximum (from power-up) and minimum (from power-up) for the processor and PCB for the UltraScale processor.

These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).

Temperature Readings Register
Function:	Specifies the Measured Temperatures on Motherboard.
Type:	signed byte (8-bits) for each temperature reading - Six (6) 32-bit words
Data Range:	0x0000 0000 to 0xFFFF 0000
Read/Write:	R
Initialized Value:	Value corresponding to the measured temperatures based on the table below.
Operational Settings:	The 8-bit temperature readings are signed bytes. For example, if the following register contains the value 0x0000 2B2B:

Example:

Word 1 (Current UltraScale Temperatures)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

UltraScale Core Temperature

UltraScale PCB Temperature

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0x00

0x00

The values would represent the following temperatures:

Temperature Measurements	Data Bits	Value	Temperature (Celsius)
UltraScale Core Temperature	D31:D24	0x2B	+43°
UltraScale PCB Temperature	D23:D16	0x2B	+43°

Temperature Readings

Word 1 (Current UltraScale Temperatures)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

UltraScale Core Temperature

UltraScale PCB Temperature

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0x00

0x00

Word 2 (Reserved)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0x00

0x00

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0x00

0x00

Word 3 (Max UltraScale Temperatures)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Max UltraScale Core Temperature

Max UltraScale PCB Temperature

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0x00

0x00

Word 4 (Reserved)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0x00

0x00

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Word 5 (Min UltraScale Temperatures)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Min UltraScale Core Temperature

Min UltraScale PCB Temperature

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Word 6 (Reserved)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0x00

0x00

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Higher Precision Temperature Readings Registers

These registers provide higher precision readings of the current UltraScale Core and PCB temperatures.

Higher Precision UltraScale Core Temperature
Function:	Specifies the Higher Precision Measured UltraScale Core temperature on Motherboard Board.
Type:	signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Measured UltraScale Core temperature on Motherboard Board
Operational Settings:	The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 02FF, this represents UltraScale Core Temperature = 43.767° Celsius, and value 0xFFF6 0177 represents -10.375° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Fractional Part of Temperature

Higher Precision Motherboard PCB Temperature
Function:	Specifies the Higher Precision Measured Motherboard PCB temperature.
Type:	signed word (16-bits) for integer part and unsigned word (16-bits) for fractional part
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	Measured Motherboard PCB temperature
Operational Settings:	The upper 16-bits represent the signed integer part of the temperature and the lower 16-bits represent the fractional part of the temperature with the resolution of 1/1000 of degree Celsius. For example, if the register contains the value 0x002B 02FF, this represents Interface PCB Temperature = 43.767° Celsius, and value 0xFFE8 036B represents -24.875° Celsius.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Signed Integer Part of Temperature

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Fractional Part of Temperature

Motherboard Health Monitoring Registers

The registers in this section provide a summary of motherboard temperature sensors and their corresponding bits. Additionally, this section provides an overview of the registers allocated to those sensors, which are used to monitor current/minimum/maximum temperature readings, upper & lower critical/warning temperature thresholds, and whether or not a programmed temperature threshold has been exceeded.

These registers are only available on Xilinx Generation 5 platforms, and are periodically populated by the motherboard core application, which only runs in Petalinux and BareMetal. For other operating systems, refer to the naibrd Software Support Kit (SSK) naibsp_system_Monitor_Temperature_Get() routine to manually retrieve the temperature (NOTE: this feature is typically utilized for development/factory use only; contact the factory for additional details on potential use, if required).

Motherboard Sensor Summary Alarm
Function:	The corresponding sensor bit is set if the sensor has crossed any of its thresholds.
Type:	unsigned binary word (32-bits)
Data Range:	See table below
Read/Write:	R
Initialized Value:	0
Operational Settings:	This register provides a summary for motherboard sensors. When the corresponding sensor bit is set, the Sensor Threshold Status register for that sensor will indicate the threshold condition that triggered the event.

Bit(s)	Sensor
D31:D5	Reserved
D4	Motherboard PCB Temperature
D3	US Core Temperature
D2:D0	Reserved

Motherboard Sensor Registers

The registers listed in this section apply to each module sensor listed for the Motherboard Sensor Summary Status register. Each individual sensor register provides a group of registers for monitoring motherboard temperatures readings. From these registers, a user can read the current temperature of the sensor in addition to the minimum and maximum temperature readings since power-up. Upper and lower critical/warning temperature thresholds can be set and monitored from these registers. When a programmed temperature threshold is crossed, the Sensor Threshold Status register will set the corresponding bit for that threshold. The figure below shows the functionality of this group of registers when accessing the Zynq Core Temperature sensor as an example.

Sensor Threshold Status
Function:	Reflects which threshold has been crossed
Type:	unsigned binary word (32-bits)
Data Range:	See table below
Read/Write:	R
Initialized Value:	0
Operational Settings:	The associated bit is set when the sensor reading exceed the corresponding threshold settings.

Bit(s)	Description
D31:D4	Reserved
D3	Exceeded Upper Critical Threshold
D2	Exceeded Upper Warning Threshold
D1	Exceeded Lower Critical Threshold
D0	Exceeded Lower Warning Threshold

Sensor Current Reading
Function:	Reflects current reading of temperature sensor
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	The register represents current sensor reading as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Minimum Reading
Function:	Reflects minimum value of temperature sensor since power up
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	The register represents minimum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Maximum Reading
Function:	Reflects maximum value of temperature/voltage/current sensor since power up
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	The register represents maximum sensor value as a single precision floating point value. For example, for a temperature sensor, register value 0x41C6 0000 represents temperature = 24.75° Celsius.

Sensor Lower Warning Threshold
Function:	Reflects lower warning threshold of temperature sensor
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	Default lower warning threshold (value dependent on specific sensor)
Operational Settings:	The register represents sensor lower warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC220 0000 represents temperature = -40.0° Celsius.

Sensor Lower Critical Threshold
Function:	Reflects lower critical threshold of temperature sensor
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	Default lower critical threshold (value dependent on specific sensor)
Operational Settings:	The register represents sensor lower critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0xC25C 0000 represents temperature = -55.0° Celsius.

Sensor Upper Warning Threshold
Function:	Reflects upper warning threshold of temperature sensor
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	Default upper warning threshold (value dependent on specific sensor)
Operational Settings:	The register represents sensor upper warning threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42AA 0000 represents temperature = 85.0° Celsius.

Sensor Upper Critical Threshold
Function:	Reflects upper critical threshold of temperature sensor
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	Default upper critical threshold (value dependent on specific sensor)
Operational Settings:	The register represents sensor upper critical threshold as a single precision floating point value. For example, for a temperature sensor, register value 0x42FA 0000 represents temperature = 125.0° Celsius.

Ethernet Configuration Registers

The registers in this section provide information about the Ethernet Configuration for the two ports on the board.

Important

Regardless if the board is configured for one or two Ethernet ports, the second IP address cannot be on the same Subnet as the First IP Address. The table below provides examples of valid and invalid IP Addresses and Subnet Mask Addresses.

First Port (A) IP Address	First Port (A) Subnet Mask	Second Port (B) IP Address	Second Port (B) Subnet Mask	Result
192.168.1.5	255.255.255.0	192.168.2.5	255.255.255.0	Good
192.168.1.5	255.255.0.0	192.168.2.5	255.255.0.0	Conflict
192.168.1.5	255.255.0.0	192.168.2.5	255.255.255.0	Conflict
10.0.0.15	255.0.0.0	192.168.1.5	255.255.255.0	Good

Ethernet MAC Address and Ethernet Settings
Function:	Specifies the Ethernet MAC Address and Ethernet Settings for the Ethernet port.
Type:	Two (2) unsigned binary word (32-bit)
Data Range:	See table.
Read/Write:	R
Operational Settings:	The Ethernet MAC Address consists of six octets. The Ethernet Settings are defined in table.

Bits	Description	Values
D31:D23	Reserved	0
D22:D21	Duplex	00 = Not Specified ` 01 = Half Duplex ` 10 = Full Duplex + 11 = Reserved
D20:D18	Speed	000 = Not Specified ` 001 = 10 Mbps ` 010 = 100 Mbps ` 011 = 1000 Mbps ` 100 = 2500 Mbps ` 101 = 10000 Mbps ` 110 = Reserved + 111 = Reserved
D17	Auto Negotiate	0 = Enabled + 1 = Disabled
D16	Static IP Address	0 = Enabled + 1 = Disabled

Ethernet MAC Address and Ethernet Settings (Note: little-endian order in register)

Word 1 (Ethernet MAC Address (Octets 1-4)) (ex: aa:bb:cc:dd:ee:ff)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

MAC Address Octet 4 (ex: 0xDD)

MAC Address Octet 3 (ex: 0xCC)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

MAC Address Octet 2 (ex: 0xBB)

MAC Address Octet 1 (ex: 0xAA)

Word 2 (Ethernet MAC Address (Octets 5-6) and Ethernet Settings)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Ethernet Settings (See table)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

MAC Address Octet 6 (ex: 0xFF)

MAC Address Octet 5 (ex: 0xEE)

Ethernet Interface Name
Function:	Specifies the Ethernet Interface Name for the Ethernet port.
Type:	8-character ASCII string
Data Range:	See table.
Read/Write:	R
Operational Settings:	The Ethernet Interface Name (eth0, eth1, etc) for the Ethernet port.

Ethernet Interface Name (Note: ascii string in register) (ex. “eth0”)

Word 1 (Bit 0-31) (ex: 0x3068 7465 = “0hte”)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

ASCII Character (ex: '0' - 0x30)

ASCII Character (ex: 'h' - 0x68)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ASCII Character (ex: 't' - 0x74)

ASCII Character (ex: 'e' - 0x65)

Word 2 (Bit 32-63) (ex: 0x0000 0000)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

ASCII Character (ex: null - 0x00)

ASCII Character (ex: null - 0x00)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ASCII Character (ex: null - 0x00)

ASCII Character (ex: null - 0x00)

Ethernet IPv4 Address
Function:	Specifies the Ethernet IPv4 Address for the Ethernet port.
Type:	Three (3) unsigned binary word (32-bit)
Data Range:	See table.
Read/Write:	R
Operational Settings:	The Ethernet IPv4 Address consists of three parts: IPv4 Address, IPv4 Subnet Mask and IPv4 Gateway.

Ethernet IPv4 Address (Note: little-endian order in register)

Word 1 (Ethernet IPv4 Address) (ex: 0x1001 A8C0 = 192.168.1.16)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

IPv4 Address Octet 4 (ex: 0x10 = 16)

IPv4 Address Octet 3 (ex: 0x01 = 1)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

IPv4 Address Octet 2 (ex: 0xA8 = 168)

IPv4 Address Octet 1 (ex: 0xC0 = 192)

Word 2 (Ethernet IPv4 Subnet) (ex: 0x00FF FFFF = 255.255.255.0)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

IPv4 Subnet Octet 4 (ex: 0x00 = 0)

IPv4 Subnet Octet 3 (ex: 0xFF = 255)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

IPv4 Subnet Octet 2 (ex: 0xFF = 255)

IPv4 Subnet Octet 1 (ex: 0xFF = 255)

Word 3 (Ethernet IPv4 Gateway) (ex: 0x0101 A8C0 = 192.168.1.1)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

IPv4 Gateway Octet 4 (ex: 0x01 = 1)

IPv4 Gateway Octet 3 (ex: 0x01 = 1)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

IPv4 Gateway Octet 2 (ex: 0xA8 = 168)

IPv4 Gateway Octet 1 (ex: 0xC0 = 192)

Ethernet IPv6 Address
Function:	Specifies the Ethernet IPv6 Address for the Ethernet port.
Type:	Five (5) unsigned binary word (32-bit)
Data Range:	See table.
Read/Write:	R
Operational Settings:	The IPv6 Prefix length indicates the network portion of an IPv6 address using the following format:

• IPv6 address/prefix length
• Prefix length can range from 0 to 128
• Typical prefix length is 64

The following is an illustration of IPv6 addressing with IPv6 Prefix length of 64.

64 bits				64 bits
Prefix				Interface ID
Prefix 1	Prefix 2	Prefix 3	Subnet ID	Interface ID 1	Interface ID 2	Interface ID 3	Interface ID 4
Example: 2002:c0a8:101:0:7c99:d118:9058:1235/64
2002	C0A8	0101	0000	7C99	D118	9058	1235

Ethernet IPv6 Address (Note: little-endian order within 32-bit and 16-bit words in register) (ex. IPv6 Address: 2002:c0a8:201:0:7c99:d118:9058:1235 IPv6 Prefix: 64)

Word 1 (Ethernet IPv6 Address (Prefix 1-2)) (ex:0xA8C0 0220 = 2002 C0A8)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Prefix 2 (ex: 0xA8C0 = C0A8)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Prefix 1 (ex: 0x0220 = 2002)

Word 2 (Ethernet IPv6 Address (Prefix 3/Subnet ID)) (ex:0x000 0201 = 0201 0000)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Subnet ID (ex: 0x0000 = 0000)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Prefix 3 (ex: 0x0201 = 0201)

Word 3 (Ethernet IPv6 Address (Interface ID 1-2)) (ex: 0x18D1 997C = 7C99 D118)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Interface ID 2 (ex: 0x18D1 = D118)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Interface ID 1 (ex: 0x997C = 7C99)

Word 4 (Ethernet IPv6 Address (Interface ID 3-4)) (ex: 0x3512 5890 = 9058 1235)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

Interface ID 4 (ex: 0x3512 = 1235)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Interface ID 3 (ex: 0x5890 = 9058)

Word 5 (Ethernet IPv6 Prefix Length) (ex:0x0000 0040)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Prefix Length (ex: 0x0040 = 64)

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed (typically with a unique number/identifier) such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Note

The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Common Memory and these registers are associated with the Module Slot position (refer to Function Register Map).

Interrupt Vector
Function:	Set an identifier for the interrupt.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	When an interrupt occurs, this value is reported as part of the interrupt mechanism.

Interrupt Steering
Function:	Sets where to direct the interrupt.
Type:	unsigned binary word (32-bit)
Data Range:	See table
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	When an interrupt occurs, the interrupt is sent as specified:

Direct Interrupt to VME	1
Direct Interrupt to ARM Processor (via SerDes) (Custom App on ARM or NAI Ethernet Listener App)	2
Direct Interrupt to PCIe Bus	5
Direct Interrupt to cPCI Bus	6

Modules Health Monitoring Registers

Module BIT Status
Function:	Provides the ability to monitor the individual Module BIT Status.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Operational Settings:	The Module BIT Status registers provide the ability to monitor individual Module BIT results as Latched and current value. A 1 is any bit field indicates BIT failure for the Module in that slot.

Bit(s)	Description
D31:D23	Reserved
D22	Module Slot 6 BIT Failure (current value)
D21	Module Slot 5 BIT Failure (current value)
D20	Module Slot 4 BIT Failure (current value)
D19	Module Slot 3 BIT Failure (current value)
D18	Module Slot 2 BIT Failure (current value)
D17	Module Slot 1 BIT Failure (current value)
D16	MB
D15:D7	Reserved
D6	Module Slot 6 BIT Failure - Latched
D5	Module Slot 5 BIT Failure - Latched
D4	Module Slot 4 BIT Failure - Latched
D3	Module Slot 3 BIT Failure - Latched
D2	Module Slot 2 BIT Failure - Latched
D1	Module Slot 1 BIT Failure - Latched
D0	MB BIT

Scratchpad Area
Function:	Registers reserved as scratch pad for customer use. Note, this area is also used to copy results from FRAM so that data can be read via the PCIe bus.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R/W
Operational Settings:	This area in memory is reserved for customer use or POST FRAM results.

MOTHERBOARD FUNCTION REGISTER MAP

KEY

Configuration/Control

Measurement/Status/Board Information

MODULE INFORMATION REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x03FC	Module Slot Addressing Ready	R
0x0400	Module Slot 1 Address	R	0x0430	Module Slot 1 Size	R
0x0404	Module Slot 2 Address	R	0x0434	Module Slot 2 Size	R
0x0408	Module Slot 3 Address	R	0x0438	Module Slot 3 Size	R
0x040C	Module Slot 4 Address	R	0x043C	Module Slot 4 Size	R
0x0410	Module Slot 5 Address	R	0x0440	Module Slot 5 Size	R
0x0414	Module Slot 6 Address	R	0x0444	Module Slot 6 Size	R
0x0460	Module Slot 1 ID	R
0x0464	Module Slot 2 ID	R
0x0468	Module Slot 3 ID	R
0x046C	Module Slot 4 ID	R
0x0470	Module Slot 5 ID	R
0x0474	Module Slot 6 ID	R
HARDWARE INFORMATION REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0020	Product Serial Number	R
0x0024	Platform	R	0x0030	Processor Count/Ethernet Count	R
0x0028	Model	R	0x0034	Maximum Module Slot Count/ARM Platform Type	R
0x002C	Generation	R
0x0038	Processor Platform (Bit 0-31)	R	0x0040	Processor Operating System (Bit 0-31)	R
0x003C	Processor Platform (Bit 32-63)	R	0x0044	Processor Operating System (Bit 32-63)	R
			0x0048	Processor Operating System (Bit 64-95)	R
0x004C	Processor Operating System Version (Bit 0-31)	R
0x0050	Processor Operating System Version (Bit 32-63)	R
MOTHERBOARD FIRMWARE INFORMATION REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
Motherboard Core Information			Motherboard FPGA Information
0x0100	MB Core Major/Minor Version	R	0x0270	MB FPGA Revision	R
0x0104	MB Core Minor 2/3 Version	R	0x0274	MB FPGA Compile Date/Time	R
0x0108	MB Core Build Date (Bit 0-31)	R
0x010C	MB Core Build Date (Bit 32-63)	R
MOTHERBOARD MEASUREMENTS REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
Temperature Readings			High Precision Temperature Readings
0x0200	Current UltraScale Temperatures	R	0x0230	Current UltraScale Core Temperature	R
0x0204	Reserved	R	0x0234	Current UltraScale PCB Temperature	R
0x0208	Max UltraScale Temp	R
0x020C	Reserved	R
0x0210	Min UltraScale Temperatures	R
0x0214	Reserved	R
ETHERNET CONFIGURATION REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
ETHERNET A (LEFT) / ETHERNET B (RIGHT)
0x0070	Ethernet A MAC (Octets 1-4)	R	0x00A0	Ethernet B MAC (Octets 1-4)	R
0x0074	Ethernet A MAC (Octets 5-6)/Misc Settings	R	0x00A4	Ethernet B MAC (Octets 5-6)/Misc Settings	R
0x0078	Ethernet A Interface Name (Bit 0-31)	R	0x00A8	Ethernet B Interface Name (Bit 0-31)	R
0x007C	Ethernet A Interface Name (Bit 32-63)	R	0x00AC	Ethernet B Interface Name (Bit 32-63)	R
0x0080	Ethernet A IPv4 Address	R	0x00B0	Ethernet B IPv4 Address	R
0x0084	Ethernet A IPv4 Subnet Mask	R	0x00B4	Ethernet B IPv4 Subnet Mask	R
0x0088	Ethernet A IPv4 Gateway	R	0x00B8	Ethernet B IPv4 Gateway	R
0x008C	Ethernet A IPv6 Address (Prefix 1-2)	R	0x00BC	Ethernet B IPv6 Address (Prefix 1-2)	R
0x0090	Ethernet A IPv6 Address (Prefix 3/Subnet ID)	R	0x00C0	Ethernet B IPv6 Address (Prefix 3/Subnet ID)	R
0x0094	Ethernet A IPv6 Address (Interface ID 1-2)	R	0x00C4	Ethernet B IPv6 Address (Interface ID 1-2)	R
0x0098	Ethernet A IPv6 Address (Interface ID 3-4)	R	0x00C8	Ethernet B IPv6 Address (Interface ID 3-4)	R
0x009C	Ethernet A IPv6 Prefix Length	R	0x00CC	Ethernet B IPv6 Prefix Length	R
INTERRUPT REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0500 - 0x057C	Module 1 Interrupt Vector 1 - 32	R/W	0x0600 - 0x067C	Module 1 Interrupt Steering 1 - 32	R/W
0x0700 - 0x077C	Module 2 Interrupt Vector 1 - 32	R/W	0x0800 - 0x087C	Module 2 Interrupt Steering 1 - 32	R/W
0x0900 - 0x097C	Module 3 Interrupt Vector 1 - 32	R/W	0x0A00 - 0x0A7C	Module 3 Interrupt Steering 1 - 32	R/W
0x0B00 - 0x0B7C	Module 4 Interrupt Vector 1 - 32	R/W	0x0C00 - 0x0C7C	Module 4 Interrupt Steering 1 - 32	R/W
0x0D00 - 0x0D7C	Module 5 Interrupt Vector 1 - 32	R/W	0x0E00 - 0x0E7C	Module 5 Interrupt Steering 1 - 32	R/W
0x0F00 - 0x0F7C	Module 6 Interrupt Vector 1 - 32	R/W	0x1000 - 0x107C	Module 6 Interrupt Steering 1 - 32	R/W
MOTHERBOARD HEALTH MONITORING REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x20F8	Motherboard Sensor Summary Status	R
MODULES HEALTH MONITORING REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
MODULE BIT STATUS
0x0128	Module BIT Status (current and latched)	R
SCRATCHPAD REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x3800 - 0x3BFF	Scratchpad Registers	R/W

ETHERNET

(For detailed supplement, please visit the NAI web-site specific product page and refer to: Ethernet Interface for Generation 5 SBC and Embedded IO Boards Specification)

Note

For products capable of 10/100/1000Base-KX functionality – the product Ethernet PHY supports 1000BASE-X. Product interoperability with 10/100/1000BASE-KX is supported with 1000BASE-X (provided that auto-negotiation is disabled).

The Ethernet Interface Option allows communications and control access to all function modules either via the system BUS or Ethernet ports 1 or 2.

	Ethernet 1	Ethernet 2	Ethernet 3*	Ethernet 4*
	(REF PORT A)	(REF PORT B)	(REF PORT C)	(REF PORT D)
The default IP address:	192.168.1.16	192.168.2.16	192.168.3.16	192.168.4.16
The default subnet:	255.255.255.0	255.255.255.0	255.255.255.0	255.255.255.0
The default gateway:	192.168.1.1	192.168.2.1	192.168.3.1	192.168.4.1

*see Part Number Designation for applicability.

Note

Actual “as shipped” card Ethernet default IP addresses may vary based upon final ATP configuration(s).

The NAI interface supports IPv4 and IPv6 and both the TCP and UDP protocols. The Ethernet Operation Mode Command Listener application running on the motherboard host processor implements the operation interface. The listener is operational on startup through the nai_MBStartup process and listen on specific ports for commands to process. The default ports are listed below:

• TCP1 - Port 52801
• TCP2 - Port 52802
• UDP1 - Port 52801
• UDP2 - Port 52802

While the listener is active, note that interrupts from the motherboard do not trigger. The listener can be disabled by turning off the nai_MBStartup process through the Motherboard EEPROM. To turn off nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 1 in the console, either by serial port or telnet to the motherboard, and then reboot the system. To turn on the nai_MBStartup use the command mbeeprom_util set MBStartupInitOnlyFlag 0 in the console, either by serial port or telnet to the motherboard, and then reboot the system.

Ethernet Message Framework

The interface uses a specific message framework for all commands and responses. All messages begin with a Preamble code and end with a Postamble code. The message framework is shown below.

Preamble 2 bytes Always 0xD30F
SequenceNo 2 bytes
Type Code 2 byte
Message Length (2 bytes)
Payload (0..1414 bytes)
Postamble 2 bytes Always 0xF03D

Message Elements

Preamble	The Preamble is used to delineate the beginning of a message frame. The Preamble is always 0xD30F.
SequenceNo	The SequenceNo is used to associate Commands with Responses.
Type Code	Type Codes are used to define the type of Command or Response the message contains.
Message Length	The Message Length is the number of bytes in the complete message frame starting with and including the Preamble and ending with and including the Postamble.
Payload	The Payload contains the unique data that makes up the command or response. Payloads vary based on command type.
Postamble	The Postamble is use to delineate the end of a message frame. The Postamble is always 0xF03D.

Notes

1. The messaging protocol applies only to card products.
2. Messaging is managed by the connected (client) computer. The client computer will send a single message and wait for a reply from the card. Multiple cards may be managed from a single computer, subject to channel and computer capacity.

Board Addressing

The interface provides two main addressing areas: Onboard and Off-board.

Onboard addressing refers to accessing resources located on the board that is implementing the operation interface (including its modules).

Off-board addressing refers to accessing resources located on another board reachable via VME, PCI, or other bus. Off-board addressing requires a Master/Slave configuration.

The user must always specify if a particular address is Onboard or Off-board. See the command descriptions for the onboard and off-board flags.

Within a particular board (Onboard or Off-board), the address space is broken up into two areas: Motherboard Common Address Space and Module Address Space. All addresses are 32-bit.

Motherboard Common Address Space starts at 0x00000000 and ends at 0x00004000. This is a 4Kx32-bit address space (16 kbytes).

Module Address Space starts at 0x00004000. Module addressing is dynamically configured at startup. NAI boards support between 1 and 6 modules. The minimum module address space size is 4Kx32 (16 kbytes) and module sizes are always a multiple of 4Kx32.

Module addressing is dynamic and cumulative. The first detected module (starting with Slot 1) is given an address of 0x00004000. The 2nd detected Module is given an address of:

First_Detected_Module_Address + First_Detected_Module_Size

Note

Slots do not define addresses.

If no module is detected in a module slot, that slot is not given an address. Therefore, if the first detected Module is in Slot 2, then that module address will be 0x00004000. If the next detected module is in Slot 4, then the address of that Module will be:

Second_Detected_Module_Address = First_Detected_Module_Address + First_Detected_Module_Size

If a 3rd Module is detected in Slot 6, then the address of that Module will be:

Third_Detected_Module_Address = Second_Detected_Module_Address + Second_Detected_Module_Size

Note

Module addresses are calculated at each board startup when the modules are detected. Therefore, if a module should fail to be detected due to malfunction or because it was removed from the motherboard, the addresses of the modules that follow it in the slot sequence will be altered. This is important to note when programming to this interface.

Users can always retrieve the Module Addresses, Module Sizes and Module IDs from the fixed Motherboard Common address area. This data is set upon each board startup. While the Module Addressing is dynamic, the address where these addresses are stored is fixed. For example, to find the startup address of the module location in Slot 3, refer to the MB Common Address 0x00000408 from the Motherboard Common Addresses table that follows.

Ethernet Wiring Convention

RJ-45 Pin	T568A Color	T568B Color	10/100Base-T	1000BASE-T	NAI wiring convention
1	white/green stripe	white/orange stripe	TX+	DA+	ETH-TP0+
2	green	orange	TX-	DA-	ETH-TP0-
3	white/orange stripe	white/green stripe	RX+	DB+	ETH-TP1+
4	blue	blue		DC+	ETH-TP2+
5	white/blue stripe	white/blue stripe		DC-	ETH-TP2-
6	orange	green	RX-	DB-	ETH-TP1-
7	white/brown stripe	white/brown stripe		DD+	ETH-TP3+
8	brown	brown		DD-	ETH-TP3-

CIU3 I/O MAPPING

CIU3 I/O Mapping (for reference) is shown below, with respect to DATAIO. Additional information on pin-outs can be found in the Module Operational Manuals or by contacting the factory.

MOD1 J3 - I/O	MOD2 J3 - I/O	MOD3 J3 - I/O	Internal Reference Only
4	14	17	MOD-DATIO01
3	40	43	MOD-DATIO02
2	15	44	MOD-DATIO03
28	16	69	MOD-DATIO04
78	92	70	MOD-DATIO05
79	67	95	MOD-DATIO06
55	91	96	MOD-DATIO07
80	90	97	MOD-DATIO08
81	89	72	MOD-DATIO09
82	64	47	MOD-DATIO10
5	63	22	MOD-DATIO11
31	38	21	MOD-DATIO12
53	36	45	MOD-DATIO13
27	62	71	MOD-DATIO14
56	60	18	MOD-DATIO15
30	35	19	MOD-DATIO16
83	12	23	MOD-DATIO17
58	13	49	MOD-DATIO18
84	37	24	MOD-DATIO19
85	11	25	MOD-DATIO20
33	66	50	MOD-DATIO21
59	41	75	MOD-DATIO22
6	88	98	MOD-DATIO23
7	87	73	MOD-DATIO24
52	42	93	MOD-DATIO25
77	68	94	MOD-DATIO26
54	39	74	MOD-DATIO27
29	65	48	MOD-DATIO28
32	10	20	MOD-DATIO29
57	9	46	MOD-DATIO30
8	86	99	MOD-DATIO31
34	61	100	MOD-DATIO32
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
26	26	26	N/C
1	1	1	SYSTEM GND
51	51	51	SYSTEM GND
76	76	76	SYSTEM GND

Key

N/C	Indicates module signal pin not available at Jx I/O Connector.

CIU3 PART NUMBER DESIGNATION

Standard Product CIU3-AAABBBCCCPMIDCOTSH-XX +
Variant Product* CIU3P-AAABBBCCCPMIDCOTSH-XX

PROD ID

M1

M2

M3

P

MEM

OBIO

DTIO

CAN

SW/OS

TEMP

SYNC

HU

(-XX)

Configuration and Option Descriptions

CIU3-

Rugged System, COSA Integration Unit AMD/Xilinx Zynq™ UltraScale+™ MPSoC + 2x 10/100/1000BASE-T Ethernet Inboard I/O Functions & 3x COSA Expansion I/O Function Module Slots

AAA

Function Module Slot 1 (M1) Z00 = No Module

BBB

Function Module Slot 2 (M2) Z00 = No Module

CCC

Function Module Slot 3 (M3) Z00 = No Module

P

Processor Type (Local processing requires OS) ` 1 = Dual-core Arm® Cortex®-A53 MPCore @ 1.2 GHz (default) ` 2 = Quad-core Arm® Cortex®-A53 MPCore @ 1.2 GHz

M

On-board Memory Support (DDR4 SDRAM / SATA SSD) + 1 = 4 GB w/ECC / 32 GB (default)

I

On-board Function I/O All configurations include Base Unit functions: ` 2x 10/100/1000BASE-T RS-232 debug port USB 2.0 (not accessible with RES Processor / OS selection) I2C (not accessible with RES Processor / OS selection) Plus Inboard Functions Configuration: ` 1 = Standard pre-configured (default): IF1 (M5) = 2x CAN bus & 4x A/D (±10V) IF2 (M4) = 1x MIL-STD-1553 (A/B redundant) & 4x ARINC 429/575 IF3 (M6) = 12x Programmable DIO (Enhanced DT4-Type) + & 4x Serial Comms (RS-232/422/485)

D

I/O Connector Type ` 1 - 3 = Reserved ` 4 = Non-Keyed J2 & J3 Connectors (Default) K = Keyed J2 & J3 Connectors

C

CAN bus Type + 1 = CAN 2.0A/B, CAN FD, ARINC 825-4 (CB8-type)

O

Processor / OS ` (OS options other than 0 are applicable w/ ARM processor & embedded software application only) ` 0 = Remote Ethernet Server (RES) - External Ethernet Host only (no local SW processing) ` 1 = PetaLinux 2023.2 (default) ` 2 = BIT / PetaLinux 2023.2 (Pending) ` 6 = BIT / VxWorks 7 (Pending) ` 7 = U-Boot (for VxWorks 7) A = Deos 653 (Pending)

T

Temperature C = 0ᵒC – 50ᵒC H = -40ᵒC – 85ᵒC

S

SYNC Capability (PENDING) + 0 = No SYNC Capability

H

Power Supply Hold-up (HU) + 0 = No HU (Default) H = HU Installed

-XX

Special Code (dash number) Leave blank for standard product.

^*CIU3P: Variant of CIU3 supporting only high-speed PCIe interface modules in MOD-SLT-1; otherwise identical in form, fit, and function.
Note: Definitions and specifications are subject to change without notice.

SYNCHRO/RESOLVER AND LVDT/RVDT SIMULATION MODULE CODE TABLES

Select the Digital-to-Synchro (DSx), Digital-to-Resolver (DRx) or Digital-to-LVDT/RVDT (DLx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. Frequency/voltage band tolerances +/- 10%. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.

• Single Channel module pending availability (contact factory)

Module ID	Format	Channel(s)	Output Voltage VL-L (Vrms)	Reference Voltage (Vrms)	Frequency Range (Hz)	Power / CH maximum (VA)	Notes
DS1	SYN	1*	2 - 28	2 - 115	47 - 1 K	3
DR1	RSL
DL1	LVDT/RVDT
DS2	SYN	1*	2 - 28	2 - 115	1 K - 5 K	3
DR2	RSL
DL2	LVDT/RVDT
DS3	SYN	1*	2 - 28	2 - 115	5 K - 10 K	3
DR3	RSL
DL3	LVDT/RVDT
DS4	SYN	1*	2 - 28	2 - 115	10 K - 20 K	3
DR4	RSL
DL4	LVDT/RVDT
DS5	SYN	1*	28 - 90	2 - 115	47 - 1 K	3
DR5	RSL
DL5	LVDT/RVDT
DSX	SYN	1*	X	X	X	X	X = TBD; special configuration, requires special part number code designation, contact factory
DRX	RSL
DLX	LVDT/RVDT
DSA	SYN	2	2 - 28	2 - 115	47 - 1 K	1.5
DRA	RSL
DLA	LVDT/RVDT
DSB	SYN	2	2 - 28	2 - 115	1 K - 5 K	1.5
DRB	RSL
DLB	LVDT/RVDT
DSC	SYN	2	2 - 28	2 - 115	5 K - 10 K	1.5
DRC	RSL
DLC	LVDT/RVDT
DSD	SYN	2	2 - 28	2 - 115	10 K - 20 K	1.5
DRD	RSL
DLD	LVDT/RVDT
DSE	SYN	2	28 - 90	2 - 115	47 - 1 K	2.2
DRE	RSL
DLE	LVDT/RVDT
DSY	SYN	2	Y	Y	Y	Y	Y = TBD; special configuration, requires special part number code designation, contact factory
DRY	RSL
DLY	LVDT/RVDT
DSJ	SYN	3	2 - 28	2 - 115	47 - 1 K	0.5
DRJ	RSL
DLJ	LVDT/RVDT
DSK	SYN	3	2 - 28	2 - 115	1 K - 5 K	0.5
DRK	RSL
DLK	LVDT/RVDT
DSL	SYN	3	2 - 28	2 - 115	5 K - 10 K	0.5
DRL	RSL
DLL	LVDT/RVDT
DSM	SYN	3	2 - 28	2 - 115	10 K - 20 K	0.5
DRM	RSL
DLM	LVDT/RVDT
DSN	SYN	3	28 - 90	2 - 115	47 - 1 K	0.5
DRN	RSL
DLN	LVDT/RVDT
DSZ	SYN	3	Z	Z	Z	Z	Z = TBD; special configuration, requires special part number code designation, contact factory
DRZ	RSL
DLZ	LVDT/RVDT

SYNCHRO/RESOLVER AND LVDT/RVDT MEASUREMENT MODULE CODE TABLES

SYN/RSL Four-Channel Measurement (Field Programmable SYN/RSL)

Select the Synchro/Resolver-to-Digital (SDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Reference voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.

Frequency/voltage band tolerances +/- 10%.

Module ID	Input Voltage V (Vrms)	Reference Voltage + (Vrms)	Frequency Range + (Hz)	Notes
SD1	2 - 28	2 - 115	47 - 1 K
SD2	2 - 28	2 - 115	1K - 5 K
SD3	2 - 28	2 - 115	5K - 10 K
SD4*	2 - 28	2 - 115	10K - 20 K
SD5	28 - 90	2 - 115	47 - 1 K
SDX*	X	X	X	X = TBD; special configuration, requires special part number code designation, contact factory

*Consult factory for availability

LVDT/RVDT Four-Channel Measurement (Field Programmable 2, 3 or 4-Wire)

Select the LVDT/RVDT-to-Digital (LDx) module ID corresponding to the application operating parameters required from the following code table (where x = the specific module ID designator). Customer should indicate the actual frequency applicable to the design to assure that the correct default band width is set at the factory. All Input and Excitation voltages are auto ranging. For availability and ranges other than those listed contact the factory. Specifications may be subject to change.

Frequency/voltage band tolerances +/- 10%.

Module ID	Input Signal Voltage V + (Vrms)	Excitation Voltage + (Vrms)	Frequency Range + (Hz)	Notes
LD1	2 - 28	2 - 115	47 - 1 K
LD2	2 - 28	2 - 115	1K - 5 K
LD3	2 - 28	2 - 115	5K - 10 K
LD4*	2 - 28	2 - 115	10K - 20 K
LD5	28 - 90	2 - 115	47 - 1 K
LDX*	X	X	X	X = TBD; special configuration, requires special part number code designation, contact factory

*Consult factory for availability

APPENDIX A: INBOARD MODULE FUNCTION

The CIU3 is preconfigured with 4-Ch serial RS-232/422/485 communications, 4-Ch A/D converter, 12-Ch programmable Discrete I/O, 4-Ch ARINC 429/575, 2-Ch CANBus, and 1-Ch MIL-STD-1553 functionality. The following sections describe the principle of operation, register descriptions, and register memory map for each of these specific functions.

Note

All inboard functions are provided by an IFx combination module:
IF1 - CAN & A/D
IF2 - MIL-STD-1553 & ARINC 429/575
IF3 - Discrete I/O & RS-232/422/485

CANBus Function

Principle of Operation

Through an IF1 combination module, the inboard CANBus communications function provides the CAN data link layer protocol as standardized in ISO 11898-1 (2003). It can also provide Flexible Data (FD) communication, which is an extension of that ISO standard. The standard describes the data link layer (composed of the logical link control (LLC) sublayer and the media access control (MAC) sublayer) and some aspects of the physical layer of the OSI reference model. All the other protocol layers are the network designer’s choice.

Each CAN node can send and receive messages, but not simultaneously. A message consists primarily of an ID (identifier), which represents the priority of the message, and up to 8 (64 for CAN FD) data bytes. The devices that are connected by a CAN network are typically sensors,actuators, and other control devices. These devices are not connected directly to the bus, but through a host processor and a CAN controller.

If the bus is idle, which is represented by recessive level (Logical 1), any node may begin to transmit. If two or more nodes begin sending messages at the same time, the message with the more dominant ID (which has more dominant bits, i.e., zeroes) will overwrite other nodes’ less dominant IDs, so that eventually (after this arbitration on the ID) only the dominant message remains and is received by all nodes. This mechanism is referred to as priority-based bus arbitration. Messages with numerically smaller values of IDs have higher priority and are transmitted first.

When utilized, CAN FD communication provides nodes with the capability to send more payload data at faster speeds over a conventional CAN A/B network. The electrical condition/configuration of the CANBus (total number of units connected, length of the CANBus wires, other electromagnetic factors) determine the fastest data transfer rate possible on that CANBus. It also provides better error detection in received CAN messages.

Each node (the CAN module on an appropriate board/system platform is a node) provides:

Host Module Processing

The host (on-module) processor decides what received messages mean and which messages it wants to transmit itself. Sensors, actuators, and control devices can be connected to the host processor.

For the CIU3, 2 channels of CAN-FD are available. Each channel can be viewed as a separate CAN Bus. The BareMetal application that runs on the CIU3 processor not only services the CAN-FD module functionality but also services all other “inboard” module functionality (such as Discrete I/O, ARINC-429, and MIL-STD-1553).

The BareMetal application has a control loop that services each of these inboard modules sequentially in a single thread. Each module has a different amount of functionality to be performed when it is their turn to run. Regarding CAN-FD functionality, for versions of the BareMetal where the Enhanced Last Error Code compatibility bit is not set, the BareMetal application will cycle through all channels checking for incoming commands, in addition to performing any Rx and Tx actions for each channel before it relinquishes processing control. For BareMetal versions that have the Enhanced Last Error Code compatibility bit set, the BareMetal application will only process one (target) channel on any given pass before relinquishing processing control. This ‘target channel to process’ moves to the next channel so during the next CAN-FD run period, a different target channel is processed. The reason for this “round-robin” approach to processing the CAN channels is that CAN-FD processing was determined to be taking longer than was expected due to the processing of both channels before relinquishing control. By processing only an individually selected channel during a run period, the other modules are now processed in a timelier manner, reducing the overall processing loop time.

Another factor impacting the amount of time spent processing CAN-FD is the frequency of messages that need to be sent or received during the CAN-FD processing cycle for the channel(s) being processed. The BareMetal application for CAN-FD measures MAX_WORK_TIME in milliseconds (ms). The ‘non-round-robin’ versions of the BareMetal code contain a default value of 1000ms (approximately 1 second). Users of these versions of the BareMetal can set this MAX_WORK_TIME to any value from 0 to 4,294,967,295 (max unsigned integer 32-bit value). If set to 0, however, the ‘non-round-robin’ versions of the BareMetal will automatically assign the MAX_WORK_TIME to the default value (1000ms). The least amount of time the user can set the MAX_WORK_TIME to be is 1ms.

This logic was changed with the ‘round-robin version’ of the BareMetal. Now, the default MAX_WORK_TIME in milliseconds is 0. This means that when transmitting or receiving CAN-FD messages, the most that will be processed is 1 message before CAN-FD relinquishes processing control. During each CAN-FD processing cycle, the control register is checked for any requested commands to be performed (bit by bit). If any bits return a value of 1, that command’s desired action is performed. When the action is finished, the corresponding control bit is set back to 0 to indicate that the action was completed by the BareMetal functionality. After all the applicable control bits are processed, a check is made to see if transmit for the channel being processed is enabled. If transmit is enabled, the BareMetal will try to transmit data found in the transmit FIFO. After transmitting each full message, a timer is checked to see how much time has been spent in the transmit function. If this time exceeds the MAX_WORK_TIME, the transmit function will exit even if there is still additional data in the transmit FIFO to send. This time limit helps to prevent delaying the other function modules from being serviced.

After the transmit function is finished, the receive function is called, which probes the CAN-FD IP to determine if any messages are available for retrieval. If there are available messages for retrieval, a logic like what is used for the transmit function regarding the MAX_WORK_TIME allowed is performed. Full CAN-FD messages are read from the CAN-FD IP and copied to the receive FIFO. The retrieval of messages will continue if there are messages to be received or until the MAX_WORK_TIME has been exceeded. In either case the receive function will exit and the CAN-FD will relinquish control back to the BareMetal main routine allowing the next function module in the queue to be processed.

CAN Controller: Hardware with a Synchronous Clock

Receiving: the CAN controller stores received bits serially from the bus until an entire message is available and put in the FIFO, which can then be fetched by the host processor (usually after the CAN controller has triggered an interrupt or is polling for messages).

Sending: the host processor stores the transmit messages onto a CAN controller, which transmits the bits serially onto the bus.

Transceiver

Receiving: it adapts signal levels from the bus to levels that the CAN controller expects and has protective circuitry that protects the CAN controller.

Transmitting: it converts the transmit-bit signal received from the CAN controller into a signal that is sent onto the bus. With CAN A/B, bit rates up to 1 Mbit/s are possible at network lengths below 40 m. Decreasing the bit rate allows longer network distances (e.g., 500 m at 125 kbit/s). With CAN FD, bit rates up to 4 Mbit/s are possible at network lengths below 40 m (Note: this is for data payload only; the arbitration bit rate is still limited to 1 Mbit/s for compatibility). Decreasing the bit rate allows longer network distances (e.g., 500 m at 125 kbit/s). CAN FD extends the speed of the data section by a factor of up to 8 (64 bytes) of the arbitration bit rate over what classic CAN provides (8 bytes). The CAN FD frame/message ID uses an Extended ID (29-bit format) version of the classic CAN Standard ID (11-bit) format. CAN FD can also handle Standard ID format messages, as well.

As applications may require many nodes (SG), which are not predetermined, both conventional CAN A/B bus and CAN-FD bus require proper termination (120-ohm resistor at each end of the bus) to operate properly. A new feature to NAI’s CAN-FD module is the ability to assign termination to desired channels in code rather than requiring a physical resistor to be attached.

Continuous Background Built-in Test (BIT)/Diagnostic Capability

BIT is performed in the background continuously within the FPGA. Each channel is checked periodically at 80MHz for correct operation. Any failure triggers an interrupt if enabled, with the results available in the status registers. The testing is transparent to the user and has no effect on the operation of the inboard CANBus function.

Register Descriptions

The register descriptions provide the register name, Register Offset, Type, Data Range, Read or Write information, Default Value, a description of the function and, in most cases, a data table.

Receive Registers

The registers listed are associated with data that is received on the CANBus channels

Receive FIFO Buffer Data
Function:	Stores received messages.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	W-H, R-A + NOTE: 'H' is 'Host; 'A' is 'ARM'
Operational Settings:	N/A
Default:	0

CAN Frame as it is to be read off the FIFO - The FIFO contains 32-bit values where the top 8 bits are reserved for flags. The payload is “packed” where up to 3 x 8-bit values are stuffed into 1 x 32-bit read from the FIFO (upper 8 bits are always reserved for flags)

Description	Bits Read	Meaningful Bits	NOTES
Msg ID - Lower 16	32	Lower 16 (0x0000FFFF)	Lower and Upper make up 29 Bit Identifier
Msg ID - Upper 16	32	Upper 16 (0x0000FFFF)
Timestamp - Lower 16	32	Lower 16 (0x0000FFFF)	Lower and Upper Timestamp
Timestamp - Upper 16	32	Upper 16 (0x0000FFFF)
Msg/Payload Length	32	1 Byte (0x000000FF)	Length of Msg (payload count)
Payload Data is “Packed” - lower 24 bits make up 3 x 8 bits of data. Top 8 bits are reserved for flags.
Data[0], Data[1], Data[2]	32
Data[0]	X	1st Byte (0x000000FF)	1st Byte is Data[0]
Data[1]	X	2nd Byte (0x0000FF00)	2nd Byte is Data[1]
Data[2]	X	3rd Byte (0x00FF0000)	3rd Byte is Data[2]
If msg length indicates more data to read…another 32 bits would be read from the FIFO
Data[3], Data[4], Data[5]	32
Data[3]	X	1st Byte (0x000000FF)	1st Byte is Data[3]
Data[4]	X	2nd Byte (0x0000FF00)	2nd Byte is Data[4]
Data[5]	X	3rd Byte (0x00FF0000)	3rd Byte is Data[5]
This continues until Data[MsgLen -1]

Receive FIFO Word Count
Function:	Contains the number of 32-bit words in the Receive FIFO buffer.
Type:	unsigned integer word
Data Range:	0 to 2048 (0 to 0x0000 0800)
Read/Write:	R
Operational Settings:	N/A
Default:	0

Receive FIFO Frame Count
Function:	Contains the number of frames in the Receive FIFO buffer.
Type:	unsigned integer word
Data Range:	0 to 409 (0 to 0x0000 0199) (Minimum CAN frame will be 5 entries on the FIFO)
Read/Write:	R
Operational Settings:	Each minimum CAN frame is 5; 32-bit words that get placed on the FIFO. Maximum frame count is thus 2048 (0x0000 0800) / 5 = 409 (0x0000 0199).
Default:	0

Transmit Registers

The registers listed are associated with data that is transmitted on the CANBus channels.

Transmit FIFO Buffer Data
Function:	Transmits messages in FIFO
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	W-H, R-A + NOTE: 'H' is 'Host; 'A' is 'ARM'
Operational Settings:	N/A
Default:	0

CAN Frame as it is to be read off the FIFO - The FIFO contains 32-bit values where the top 8 bits are reserved for flags. The payload is “packed” where up to 3 x 8-bit values are stuffed into 1 x 32-bit read from the FIFO (upper 8 bits are always reserved for flags)

Description	Bits Read	Meaningful Bits	NOTES
Protocol	32	0xFF00000F	Valid Protocol values are 0 and 1. Flag for Start of message is 0x80000000
Msg ID - Lower 16	32	Lower 16 (0x0000FFFF)	Lower and Upper make up 29 Bit Identifier
Msg ID - Upper 16	32	Upper 16 (0x0000FFFF)
Extended ID	32	0x0000000F	Mode A = 0 Extended = 1
Msg/Payload Length	32	1 Byte (0x000000FF)	Length of Msg (payload count). If zero payload, the End of Message Flag (0x10000000) will be set
Payload Data is “Packed” - lower 24 bits make up 3 x 8 bits of data. Top 8 bits are reserved for flags.			End of Message Flag (0x10000000) will be set on the last payload data value only.
Data[0], Data[1], Data[2]	32
Data[0]	X	1st Byte (0x000000FF)	1st Byte is Data[0]
Data[1]	X	2nd Byte (0x0000FF00)	2nd Byte is Data[1]
Data[2]	X	3rd Byte (0x00FF0000)	3rd Byte is Data[2]
If msg length indicates more data to read…another 32 bits would be read from the FIFO
Data[3], Data[4], Data[5]	32
Data[3]	X	1st Byte (0x000000FF)	1st Byte is Data[3]
Data[4]	X	2nd Byte (0x0000FF00)	2nd Byte is Data[4]
Data[5]	X	3rd Byte (0x00FF0000)	3rd Byte is Data[5]
This continues until Data[MsgLen -1]

Transmit FIFO Word Count
Function:	Contains the number of 32-bit words in the Transmit FIFO register.
Type:	unsigned integer word
Data Range:	0 to 2048 (0 to 0x0000 0800)
Read/Write:	R
Operational Settings:	N/A
Default:	0

Transmit FIFO Frame Count
Function:	Contains the number of frames in the Transmit FIFO register.
Type:	unsigned integer word
Data Range:	0 to 409 (0 to 0x0000 0199) (Minimum CAN frame will be 5 entries on the FIFO)
Read/Write:	R
Operational Settings:	Each minimum CAN frame is 5; 32-bit words that get placed on the FIFO. Maximum frame count is thus 2048 (0x0000 0800) / 5 = 409 (0x0000 0199).
Default:	0

Command Registers

The registers listed are associated with functionality which enables Tx and Rx FIFO to be dedicated to sending and receiving CAN-FD messages.

BareMetal Capabilities Register
Function:	Determines if the revision of BM can use Command FIFO, response registers and can set the device sample point.
Type:	unsigned integer word
Data Range:	0 to 0x5
Read/Write:	R/W
Operational Settings:	See table below
Default:	0

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	D	0	D

Bit	Description
D0	Cmd FIFO in Use: if set to 1, Cmd FIFO is available and can be used to send parameters to the BareMetal.
D1
D2	Response Registers: If set to 1, the BareMetal is using these registers to return data instead of the Rx FIFO.
D4:D31

Command FIFO Buffer Data
Function:	Transmits BareMetal parameters in FIFO
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0xFFFF FFFF
Read/Write:	W-H, R-A + NOTE: 'H' is 'Host; 'A' is 'ARM'
Operational Settings:	N/A
Default:	0

Command FIFO Word Count
Function:	Contains the number of words in the Command FIFO register.
Type:	unsigned integer word
Data Range:	0 to 1024 (0 to 0x0000 0400)
Read/Write:	R
Operational Settings:	N/A
Default:	0

Control Registers

The register specified in this section provides the ability to control the operation for each CANBus channel.

Control

The control register has been implemented to act solely as a “request for action” register. Bits can be set to a 1 to request various actions or capabilities. When the action or capability is acted upon by the CAN firmware, these request bits will be set back to 0.

Control
Function:	Provides flags for controlling transmit and receive activity.
Type:	binary word (32-bit)
Data Range:	0x0000 0000 to 0x00FF FFFF
Read/Write:	R/W
Operational Settings:	See descriptions that follow.
Default:	0 (disabled)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	0	0	0	0	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	0	D	D	D	D	D	D	D	D	D	D	0	0	D	D

Bit	Description
D0	Request Enable Tx: Enables any messages found in the Tx FIFO to be placed on the bus from the current channel.
D1	Request Disable Tx: Stops any messages currently in the Tx FIFO from being put on the bus from the current channel.
D2
D3
D4:	Request Set Level Dominant: This is for Debug purposes only and forces channel bus signal to a constant dominant value.
D5	Request Set Level Recessive: This is for Debug purposes only and forces channel bus signal to a constant recessive value.
D6	Request Enable Termination: Internal termination will be enabled for the current channel.
D7	Request Disable Termination: Internal termination will be disabled for the current channel.
D8	Request Base Rate Change: Desired base rate enumerated type value needs to be assigned to the lower 16 bits of the datarate-baserate register. Valid values include 0 (1Mb), 1 (500K), 3 (250K), 7 (125K) and 9 (83.33K)
D9	Request Data Rate Change: Desired data rate enumerated type value needs to be assigned to the upper 16 bits of the datarate-baserate register. Valid values include 6 (4Mb), 7 (3Mb), 8 (2Mb) and 9 (1Mb). NOTE: Data rate of 3 Mb is not recommended as it has been found to be unreliable.
D10	Request reset of Tx FIFO: Clears the entire Tx FIFO
D11	Request reset of Rx FIFO: Clears the entire Rx FIFO
D12	Reset Drop Count: Resets the counter that keeps track of how many messages were dropped due to FIFO already being full.
D13	Request reset of Command FIFO: Clears the entire Command FIFO.
D14:
D15	Request Reset Channel. Expected for next release: Reset Channel will reset both the Tx, Rx and Cmd FIFOs, disable Tx enable, Clear any Last Error Code, zero out Tx/Rx error counter and drop count registers and reset entire set of response registers. Reset Channel also retains the configured baud rate so the baud rates that were configured prior to the reset will be reassigned after the reset completes back to the same baud rates.
D16:	Request Config Sequencer: Allows caller to configure a given sequencer (schedule). Configuration data is expected to be placed on the Tx FIFO in the following order: (1) Requested Config Sequencer Cmd ID so we know the data following this is the data needed to configure a new sequencer/schedule. ` (2) Sequencer ID (schedule index): 1 based value of schedule to configure. ` (3) Protocol: 0 (CAN A/B) or 1 (CAN-FD) ` (4) Rate: The number of 125us between two transmissions ` (5) Skew: The number of 125us after the rate event to transmit the message. (Example: If the rate is 80, then the message is transmitted every 10ms. If two messages have the same rate then it may be wise to stagger the messages a little to avoid collision by setting the skew for the 1 message to 0 and the skew for the 2 message to 2 where 2 * 125us = 250us. ` (6) MsgID (low): place lowest 16 bits of MsgID onto FIFO. ` (7) MsgID (high): place highest 13 bits of MsgID onto FIFO (zeros if CAN A/B). ` (8) Extended ID: 0 (Not Extended 11bit identifier), 1 (Extended 29bit identifier) ` (9) Msg (payload) Length: value between 0 and 64 if CAN-FD or 0 and 8 if CAN A/B + (10) Msg payload starts..should have Msg Length number of values in the FIFO waiting to be read into a buffer.
D17	Request Start Sequencer/Scheduler: This will start all configured sequencers/schedules
D18	Request Stop Sequencer/Scheduler: This will stop all configured sequencers/schedules
D19	Set Sample Point: Provides flexibility to assign various sample point values (75% or 80%) to the CAN FD core since it is important that all CAN FD devices use the same sample point to detect bit rate switching (BRS).
D20	Request Enable Filters: Enables all filters configured for the current channel.
D21	Request Disable Filters: Disables all filters configured for the current channel.
D22	Request Set Filter: Allows caller to configure a filter (A total of 8 filters can be configured indexed from 0 - 7). Filter configuration data is expected to be placed on the Cmd FIFO in the following order: (1) Set Filter Cmd ID: so we know the data following this is the data needed to configure a new filter. ` (2) Filter Index: A value between 0 and 7 (filter slot to configure). ` (3) CAN ID (low): low 16 bits of CAN ID. ` (4) CAN ID (high): the highest 16 bits of CAN ID (pushed to the lower 16 bits of this FIFO value). ` (5) Extended ID: 1 to only allow extended ID messages, 0 normal CAN A/B messages ` (6) First Byte of Payload to filter on (8 bits) ` (7) 2 Byte of Payload to filter on (8 bits)
D23	Request Get Filter: Retrieves desired filter data. The following is expected to be on the Cmd FIFO when this control bit value is detected being set: (1) Get Filter Cmd ID: so we know the data following this is the data needed to get desired filter information. + (2) Filter Index: A value between 0 and 7 of which to fetch filter configuration data. NOTE: The response data will be made available in the set of response registers for the
D24	Request Set Filter Mask: The following data is expected to be on the Cmd FIFO in order to configure the desired Filter Mask. The Filter Mask is used on incoming messages that are received and on the corresponding Filter configuration data that was set where Filter Index = Mask Index. After applying the mask to both, the corresponding bits are compared and if both sides match, the data is received else it is rejected. (1) Set Filter Mask Cmd ID: so we know the data following this is the data needed to configure a new filter mask. ` (2) Mask Index: A value between 0 and 7 (mask slot to configure). NOTE: Mask index is meant to align with desired Filter Index from Set Filter. ` (3) CAN ID (low): low 16 bits of CAN ID. ` (4) CAN ID (high): the highest 16 bits of CAN ID (pushed to the lower 16 bits of this FIFO value). ` (5) Extended ID: 1 to only allow extended ID messages, 0 normal CAN A/B messages ` (6) First Byte of Payload to filter on (8 bits) ` (7) 2 Byte of Payload to filter on (8 bits)
D25	Request Get Filter Mask: Retrieves desired filter mask configuration data. The following is expected to be on the Cmd FIFO when this control bit value is detected being set: (1) Get Filter Mask Cmd ID: so we know the data following this is the data needed to get desired filter mask information. + (2) Mask Index: A value between 0 and 7 of which to fetch mask configuration data. NOTE: The response data will be made available in the set of response registers for the given channel.
D26	Request Remove Filter: Removes desired filter from the filter configuration. The following is expected to be on the FIFO when this control bit is detected being set: (1) Remove Filter Cmd ID: so we know the data following this is the data needed to remove desired filter information. + (2) Filter Index: A value between 0 and 7 (filter slot to remove filter configuration)
D27
D28
D29
D30
D31	Config edit flag when set to a 1 it indicates end-user is currently editing the control register and we should not yet act upon set values. If 0, all bits in the control register will be evaluated and acted upon.

Data Rate/Base Rate
Function:	Indicates the current rate (speed) at which data is being transmitted on the CAN network. User applications should always specifically configure the Baud Rates for each active channel and not rely on the default values set within the BareMetal.
Type:	unsigned binary word (32-bit)
Data Range:	Lower 16 bits range is 0 - 3...Upper 16 bits range is from 6 - 9.
Read/Write:	R/W
Operational Settings:	Upper 16 bits dedicated to data rate enumerated type value; Lower 16 bits dedicated to base rate enumerated type value. + NOTE: Data Rate is applicable only when the protocol is set to CAN-FD; Base Rate is utilized by both CAN A/B and CAN FD.
Default:	0 for Base Rate; + 8 for Data Rate

Data Rate (CAN FD only)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

Base Rate

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

Valid values for Base Rate currently include:
0:	1Mb (1000K) Base Baud
1:	500K Base Baud
3:	250K Base Baud
7:	125K Base Baud
9:	83.33 Base Baud
Valid values for Data Rate currently include:
6:	4Mb (4000K) Data Baud
7:	3Mb (3000K) Data Baud
8:	2Mb (2000K) Data Baud
9:	1Mb (1000K) Data Baud

Note

Data rate of 3 Mb is not recommended as it has been found to be unreliable.

Sample Point
Function:	Indicates the sample point.to be used. Different 3rd party vendor equipment may use different sample points. This register provides some flexibility to the NAI CAN-FD functionality.
Type:	unsigned binary word (32-bit)
Data Range:	0 (75%) to 0x0000 0001 (80%)
Read/Write:	R/W
Operational Settings:	The sample point can be set to 75% or 80% depending on which value works best for the CAN-FD operational environment
Default:	0x0000 0001 (80%)

RxMaxWorkTimeMS
Function:	Defines length of time user will wait to perform receiving of CAN-FD messages before processing control is returned to all other processing. + NOTE: A value of zero forces the default value of 1000ms to be used if the Enhanced Last Error Code capabilities bit is not set in the Baremetal Capabilities register. If it is desired to spend as little time as possible, this value should be set to 0x00000001. If the Enhanced Last Error Code capabilities bit is set, the default value of 0 ms is used and is the recommended value to spend as little time as possible.
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0xFFFF FFFF
Read/Write:	R/W
Operational Settings:	1000ms / 0ms
Default:	1000ms (if Enhanced Last Error Code capabilities bit is 0); + 0ms (if Enhanced Last Error Code capabilities bit is 1)

TxMaxWorkTimeMS
Function:	Defines length of time user will wait to perform transmitting of CAN-FD messages before processing control is returned to all other processing. + NOTE: A value of zero forces the default value of 1000ms to be used if the Enhanced Last Error Code capabilities bit is not set in the Baremetal Capabilities register. If it is desired to spend as little time as possible, this value should be set to 0x00000001. If the Enhanced Last Error Code capabilities bit is set, the default value of 0 ms is used and is the recommended value to spend as little time as possible.
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0xFFFF FFFF
Read/Write:	R/W
Operational Settings:	1000ms
Default:	1000ms (if Enhanced Last Error Code capabilities bit is 0); + 0ms (if Enhanced Last Error Code capabilities bit is 1)

Transmit Enable State
Function:	Reflects the state of Transmit Enable.
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0x1
Read/Write:	R/W
Operational Settings:	See below.
Default:	0

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Bit	Description
D0	Tx Enabled when bit reflects a 1

Message Status/Monitoring Registers

The registers specified in this section provide status and monitoring information on about the CANBus messages.

FIFO Status
Function:	Describes current FIFO Status.
Type:	unsigned binary word (32-bit)
Data Range:	NA
Read/Write:	R
Operational Settings:	See table below.
Default: 0

Bit	Description	Configurable?
D0	Rx FIFO EMPTY: When set to 1: Rx FIFO is empty.	No
D1	Rx FIFO ALMOST EMPTY: When set to 1: Rx FIFO is at 20% capacity.	No
D2	Rx FIFO ALMOST FULL: When set to 1: Rx FIFO is at 80% capacity.	No
D3	Rx FIFO FULL: When set to 1: Rx FIFO is full.	No
D4	Tx FIFO EMPTY: When set to 1: Tx FIFO is empty.	No
D5	Tx FIFO ALMOST EMPTY: When set to 1: Tx FIFO is at 20% capacity.	No
D6	Tx FIFO ALMOST FULL: When set to 1: Tx FIFO is at 80% capacity.	No
D7	Tx FIFO FULL: When set to 1: Tx FIFO is full.	No

Last Error Code (LEC)
Function:	Stores the value of the last detected error. + NOTE: this is a single value so if multiple errors occur prior to this register being read, only the last error value will be present.
Type:	signed binary word (32-bit) if compatibility bit D3 from BareMetal Compatibilities Registers is 0 (Non-Enhanced Error Code) + unsigned binary word (32-bit) if compatibility bit D3 from BareMetal Compatibilities Register is 1 (Enhanced Error Code)
Data Range:	0 = success; negative value = failure
Read/Write:	R/W (to allow register to be cleared)
Operational Settings:	The last error code to be received on a channel.
Default:	0

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Common Error Values (when Non-Enhanced Error Code):
-50:	INVALID_DEVICE_NUMBER
-65:	INVALID PARAMETER
-1009:	MESSAGE NOT DETECTED

Full List of Error Values when Enhanced Error Code:
(HEX)	Error Description
0x0001	NAI_BUS ERROR Bus Errors can happen for multiple reasons. Most often are Baud Rate mismatches. Check all devices on the bus to make sure they are all running the same baud rates (both config and data for CAN-FD or only config for CAN A/B). Bus Error can also take place if the bus is not properly terminated. Check the termination and/or configure the FPGA termination via the NAI SSK library functionality. Bus Errors can also happen if there is only 1 device on the bus. CAN-FD needs at least 2 devices on the bus in order to function appropriately.
0x0002	NAI_SEQUENCER_START_ERROR This error is reported if there is a problem enabling the sequencer. Sequencer can additionally be thought of as a schedule and can be configured to TX data at a desired frequency.
0x0003	NAI_SEQUENCER_STOP_ERROR This error is reported if there is a problem stopping (or disabling) the sequencer.
0x0004	NAI_SEQUENCER_INDEX_ERROR Sequencer index errors may occur if a sequence index that is out-of-range is attempted to be configured. Valid index range is from 1 - 31 inclusive.
0x0005	NAI_SET_DEVICE_MODE_ERROR The BareMetal logic for CAN-FD will force the CAN-FD IP to be in different modes under certain circumstances (like monitor mode or normal mode). If the IP fails to enter these modes when requested, this error will be raised.
0x0006	NAI_BAUD_RATE_CHANGE_ERROR If the CAN-FD IP fails to enter the baud rate being requested, this error will be raised.
0x0007	NAI_ENABLE_FILTERS_ERROR This error is reported if the CAN-FD IP fails to enable the filters when a request is made.
0x0008	NAI_DISABLE_FILTERS_ERROR This error is reported if the CAN-FD IP fails to disable the filters when a request is made.
0x0009	NAI_MISSING_END_OF_MSG_ERROR This error is reported if when reading a CAN message off the TX FIFO, the end of message delimiter is not found.
0x000A	NAI_INSUFFICIENT_DATA_ERROR This error is reported when a given command (control register bit set to a 1) requires additional information, and that additional information was not found to be included. Older versions of the BareMetal code used the TX FIFO as the transfer mechanism from the user application to the BareMetal. Newer versions of the BareMetal have a separate Command FIFO that is used. In either case, if the BareMetal does not see all the information it expects on the FIFO being used, this error will be raised.
0x000B	NAI_EXPECTED_CMD_NOT_FOUND_ERROR As discussed in the prior error regarding NAI_INSUFFICIENT_DATA_ERROR, when a control register bit is set to a 1 and the command associated with that bit requires additional information, a FIFO is used as the transport mechanism from the user application to the BareMetal application. The first piece of information the BareMetal looks for is the Command ID to make sure the data being passed on the FIFO matches the command we are looking to get additional information about. If the Command ID read off the FIFO does not match the command associated with the control register bit that we are currently processing, this error is raised.
0x000C	NAI_INIT_DEVICE_ERROR This error is reported if the CAN-FD IP fails to initialize the given CAN-FD device. (Each channel of the CAN-FD will have its own device ID)
0x000D	NAI_OPEN_DEVICE_ERROR This error is reported if the CAN-FD IP fails to open the given CAN-FD device. (Each channel of the CAN-FD will have its own device ID)
0x000E	NAI_NO_ROOM_ON_RX_FIFO_ERROR This error is raised if when receiving a CAN message, it is determined that there is not enough room to put the entire message on the Rx FIFO. This can happen if the Rx FIFO fills up. The BareMetal will not put a partial message on the Rx FIFO. If the entire message won't fit, the BareMetal will report this error and stop attempting to receive more CAN messages.
0x0010	NAI_FILTER_INDEX_ERROR This error is raised if the filter index on the BareMetal side is found to be > 7. The BareMetal application expects filter index to be in the range of 0 to 7 inclusive (Max of 8 Filter Indexes).
0x0011	NAI_SET_FILTER_ERROR This error is raised if the CAN-FD IP fails to set the filter information for the specified filter index.
0x0012	NAI_GET_FILTER_ERROR This error is raised if the CAN-FD IP fails to get the filter information for the specified filter index.
0x0013	NAI_SET_FILTER_MASK_ERROR This error is raised if the CAN-FD IP fails to set the filter mask information for the specified filter mask index.
0x0014	NAI_GET_FILTER_MASK_ERROR This error is raised if the CAN-FD IP fails to get the filter mask information for the specified filter mask index.
0x0015	NAI_REMOVE_FILTER_ERROR This error is raised if the CAN-FD IP fails to remove the filter information associated with the specified filter index.
0x0020	NAI_IP_GENERAL_API_ERROR The NAI_IP_GENERAL_API_ERROR is a general error that will be raised when internal calls into the CAN-FD IP are made and return an IP failure status.
0x0021	NAI_IP_TX_FIFO_FULL This error is raised if the CAN-FD IP signals that its own Tx FIFO within the IP is full.
0x0022	NAI_IP_RX_FIFO_FULL This error is raised if the CAN-FD IP signals that its own Rx FIFO within the IP is full.

Drop Count
Function:	Every time a received message is unable to be placed onto the Rx FIFO because the FIFO is full, the message will be dropped, and this register's value will be incremented by 1. This Drop count can be reset by sending the request to reset the drop count command via the control register (see data bit 12 (D12) of the control register description).
Type:	unsigned binary word (32-bit)
Data Range:	0 - 0xFFFF FFFF
Read/Write:	R/W
Operational Settings:	Drop Count
Default:	0

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Tx/Rx Error Counter
Function:	This register exposes the Tx Errors and Rx Errors reported by the CAN IP (intellectual property). The Tx Error Count is shifted up 16 bits starting at bit D16 and the Rx Error Count starts at bit D0. Both the Tx and Rx Error Counts have a max value of 255.
Type:	unsigned binary word (32-bit)
Data Range:	0 - 0x00FF 00FF
Read/Write:	R/W
Operational Settings:	Tx/Rx Error Counter
Default:	0

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D

Status and Interrupt Registers

The registers may be set for any or all channels and will latch if a transition is detected on a channel or channels. Each channel(s) will remain latched until the channel is cleared. Multiple channels may be cleared simultaneously, if desired. Each channel bit in the register is polled for a read status. Any subsequent channel(s) transition, if detected, will propagate through to be read (rolling-latch).

Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel) location (bit-mapped per channel), will “clear” the bit (set the bit to 0) if the actual interruptible event condition has cleared. If the interruptible condition “event” is still persistent while clearing, this may retrigger the interrupt.

There is a corresponding Interrupt Enable and vector associated with each “Latched” Status. Each status type may be “polled” (at any time) or is “interruptible” when interrupts are enabled and the associated Interrupt Service Routine (ISR) vectors are programmed accordingly. When programmed for “interruptible” status, interrupts are typically generated and flagged with the programmed vector available as data. The host or single board computer (SBC) typically services the interrupt by a general or specific ISR, which reads the (typically) unique programmed vector (identifier of which status generated the interrupt), reads the associated status register to determine which channel in the status register was “flagged” and then “clears” the status register. This essentially resets the interrupt mechanism, which is now ready to be triggered by the next status register detected event “flag”. “Latched Status” will trigger on either “sense on edge” or “sense on level” based on the settings of the associated Set Edge/Level Interrupt register. Sense on “edge” requires a change from low to high state to trigger the status detection, while sense on “level” is independent of the previous state. Unless otherwise specified, all status or fault indications are bit set per channel.

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt

Note

BIT Status is a shared register between the CAN and AD functions. Bits D1:D0 are dedicated to the CAN function, and bits D19:D16 are dedicated to the AD function.

BIT Dynamic Status

BIT Latched Status

BIT Interrupt Enable

BIT Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

AD Ch4

AD Ch3

AD Ch2

AD Ch1

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CAN Ch2

CAN Ch1

BIT Dynamic Status
Function:	Indicates current condition of Built-In Test (BIT).
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0x000F 0003
Read/Write:	R
Operational Settings:	NA
Default:	0
BIT Latched Status
Function:	Sets and maintains the status of running Built-In Test (BIT), until cleared.
Type:	unsigned binary word (32-bit)
Read/Write:	R/W
Operational Settings:	Write 1 to clear register.
Default:	0
BIT Interrupt Enable
Function:	Sets the corresponding channel to enable an interrupt for whenever BIT fails for that channel.
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0x000F 0003
Read/Write:	R/W
Operational Settings:	When enabled, an interrupt will be generated whenever BIT fails for the channel. Each channel may be set for a different condition.
Default:	0
BIT Set Edge/Level Interrupt
Function:	Determines whether Interrupt Enable register will generate an interrupt for “sense on edge” or “sense on level” event detection.
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0x000F 0003
Read/Write:	R/W
Operational Settings:	Write a 1 to sense on level and a 0 to sense on edge.
Default:	Sense on edge (0)

New Data Available Status

There are four registers associated with the New Data Available Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

New Data Available Dynamic Status
New Data Available Latched Status
New Data Available Interrupt Enable
New Data Available Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	Ch2	Ch1

New Data Available Dynamic Status
Function:	Indicates current condition of received data in Receive FIFO register.
Type:	binary word (32-bit)
Data Range:	0 to 0x0003
Read/Write:	R
Operational Settings:	NA
Default:	0
New Data Available Latched Status
Function:	Sets and maintains the status of received data in Receive FIFO register, until cleared.
Type:	binary word (32-bit)
Data Range:	0 to 0x0003
Read/Write:	R/W
Operational Settings:	Write 1 to clear register.
Default:	0
New Data Available Interrupt Enable
Function:	Sets the corresponding channel to enable an interrupt for when CAN data is received.
Type:	binary word (32-bit)
Data Range:	0 to 0x0003
Read/Write:	R/W
Operational Settings:	When enabled, an interrupt will be generated for each time CAN data is received in the receive FIFO. Only one interrupt vector exists for all channels. Caller must interrogate the interrupt status register to determine which channel caused the interrupt.
Default:	0
New Data Available Set Edge/Level Interrupt
Function:	Determines whether Interrupt Enable register will generate an interrupt for “sense on edge” or “sense on level” event detection.
Type:	binary word (32-bit)
Data Range:	0 to 0x0003
Read/Write:	R/W
Operational Settings:	Write a 1 to sense on level and a 0 to sense on edge.
Default:	Sense on edge (0)

FIFO Status

There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

FIFO Dynamic Status

FIFO Latched Status

FIFO Interrupt Enable

FIFO Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

D

D

D

D

D

D

D

D

Bit	Description	Configurable?
D0	Rx FIFO EMPTY: When set to 1: Rx FIFO is empty.	No
D1	Rx FIFO ALMOST EMPTY: When set to 1: Rx FIFO is at 20% capacity.	No
D2	Rx FIFO ALMOST FULL: When set to 1: Rx FIFO is at 80% capacity.	No
D3	Rx FIFO FULL: When set to 1: Rx FIFO is full.	No
D4	Tx FIFO EMPTY: When set to 1: Tx FIFO is empty.	No
D5	Tx FIFO ALMOST EMPTY: When set to 1: Tx FIFO is at 20% capacity.	No
D6	Tx FIFO ALMOST FULL: When set to 1: Tx FIFO is at 80% capacity.	No
D7	Tx FIFO FULL: When set to 1: Tx FIFO is full.	No

FIFO Dynamic Status
Function:	Checks the corresponding bit for a channel's FIFO Status. The FIFO Dynamic Status register indicates the current condition of the FIFO buffer.
Type:	binary word (32-bit)
Data Range:	0 to 0x0000 003F
Read/Write:	R
Initialized Value:	0
Operational Settings:	D0-D7 is used to show the different conditions of the buffer.
FIFO Latched Status
Function:	Checks the corresponding bit for a channel's FIFO Status. The FIFO Latched Status register maintains the last condition of the FIFO buffer, until cleared.
Type:	binary word (32-bit)
Data Range:	0 to 0x0000 003F
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	D0-D7 is used to show the different conditions of the buffer. Write a 1 to this register to clear status.
FIFO Interrupt Enable
Function:	Interrupts may be enabled based on D0-D7 FIFO Status.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 003F
Read/Write:	R/W
Initialized Value:	0 (Not Enabled)

Notes:

• Shown below is an example of interrupts generated for the High Watermark. As shown, the interrupt is generated as the FIFO Word Count crosses the High Watermark. The interrupt will not be generated a second time until the count goes below the watermark and then above it again.

FIFO Set Edge/Level Interrupt
Function:	When the FIFO Status Interrupt Enable register is enabled, this register determines whether the interrupt will be generated for either “sense on edge” or “sense on level” event detection.
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Write a 1 to sense on level and a 0 to sense on edge.

Function Register Map

KEY

Input

Output

RECEIVE REGISTERS
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1004	Receive FIFO Buffer Data Ch 1	R-H, W-A	0x1008	Receive FIFO Word Count Ch 1	R
0x1084	Receive FIFO Buffer Data Ch 2	R-H, W-A	0x1088	Receive FIFO Word Count Ch 2	R
NOTE: For Receive FIFO Buffer Data, 'H' is 'Host; 'A' is 'ARM'.
0x100C	Receive FIFO Frame Count Ch 1	R
0x108C	Receive FIFO Frame Count Ch 2	R
TRANSMIT REGISTERS
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1010	Transmit FIFO Buffer Data Ch 1	W-H, R-A	0x1014	Transmit FIFO Word Count Ch 1	R
0x1090	Transmit FIFO Buffer Data Ch 2	W-H, R-A	0x1094	Transmit FIFO Word Count Ch 2	R
NOTE: For Transmit FIFO Buffer Data, 'H' is 'Host; 'A' is 'ARM'.
0x1018	Transmit FIFO Frame Count Ch 1	R
0x1098	Transmit FIFO Frame Count Ch 2	R
COMMAND REGISTERS
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1200	BM Capabilities Register	R/W
0x1028	Command FIFO Buffer Data Ch 1	W-H, R-A	0x102C	Command FIFO Word Count Ch 1	R
0x10A8	Command FIFO Buffer Data Ch 2	W-H, R-A	0x10AC	Command FIFO Word Count Ch 2	R
NOTE: For Command FIFO Buffer Data, 'H' is 'Host; 'A' is 'ARM'.
CONTROL REGISTERS
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1000	Control Ch 1	R/W	0x101C	Data Rate/Base Rate Ch 1	R/W
0x1080	Control Ch 2	R/W	0x109C	Data Rate/Base Rate Ch 2	R/W
0x1020	Sample Point Ch 1	R/W	0x1060	RxMaxWorkMS Ch 1	R/W
0x10A0	Sample Point Ch 2	R/W	0x10E0	RxMaxWorkMS Ch 2	R/W
0x1064	TxMaxWorkMS Ch 1	R/W	0x1068	Tx Enable State Ch 1	R
0x10E4	TxMaxWorkMS Ch 2	R/W	0x10E8	Tx Enable State Ch 2	R
MESSAGE STATUS/MONITOR REGISTERS
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x104C	FIFO Status Ch 1	R
0x10CC	FIFO Status Ch 2	R
0x1024	Last Error Code Ch 1	R/W	0x1050	Drop Count Ch 1	R/W
0x10A4	Last Error Code Ch 2	R/W	0x10D0	Drop Count Ch 2	R/W
0x1030	Tx/Rx Error Counter Ch 1	R/W
0x10B0	Tx/Rx Error Counter Ch 2	R/W
BIT REGISTER
NOTE: Base Address - 0x9010 4000
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a '1' to a bit set to '1' will set the bit to '0').
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0800	BIT Dynamic Status	R
0x0804	BIT Latched Status*	R/W
0x0808	BIT Interrupt Enable	R/W
0x080C	BIT Set Edge/Level Interrupt	R/W
FIFO STATUS REGISTERS
NOTE: Base Address - 0x9010 4000
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a '1' to a bit set to '1' will set the bit to '0').
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0810	Dynamic Status Ch 1	R	0x0820	Dynamic Status Ch 2	R
0x0814	Latched Status Ch 1*	R/W	0x0824	Latched Status Ch 2*	R/W
0x0818	Interrupt Enable Ch 1	R/W	0x0828	Interrupt Enable Ch 2	R/W
0x081C	Set Edge/Level Interrupt Ch 1	R/W	0x082C	Set Edge/Level Interrupt Ch 2	R/W
NEW DATA AVAILABLE REGISTER
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0830	Dynamic Status Ch 1-2	R
0x0834	Latched Status Ch 1-2*	R/W
0x0838	Interrupt Enable Ch 1-2	R/W
0x083C	Set Edge/Level Interrupt Ch 1-2	R/W
RESPONSE REGISTERS
When data other than CAN messages needs to be returned from the CAN module, the data to be returned is placed in a series of Response Registers. Each channel has its own series of Response Registers that can be used. The BareMetal logic will fill these registers and update the Response Count so the consumer can determine how many of the Response Registers need to be read.
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1300	#Response Count Ch 1	R
0x1304	Response Data Ch 1	R
0x1308	Response Data Ch 1	R
0x130C	Response Data Ch 1	R
	...
0x137C	Response Data Ch 1	R
0x1380	Response Count Ch 2	R
0x1384	Response Data Ch 2	R
0x1388	Response Data Ch 2	R
0x138C	Response Data Ch 2	R
	...
0x13FC	Response Data Ch 2	R

Analog-to-Digital Function

Principle of Operation

Through an IF1 combination module, the inboard Analog-to-Digital function is a 4-channel, A/D converter. This function contains 4 Successive Approximation Register (SAR) A/D converters, simultaneous sampling. It provides up to 4 differential A/D channels. Inputs may be bipolar or unipolar voltages. Ranges for the inboard function is shown below. The inboard Analog-to-Digital function will sense and report unconnected inputs.

Module	AD Function
Full Scale Range Inputs*	5.0V Unipolar
	10.0V Unipolar
	5.0V Bipolar
	10.0V Bipolar

*Programmable, per channel, as Full Scale (FS) range inputs, where range is -FS to +FS or 0 to FS VDC. The ability to set lower voltages for FS assures the utilization of the maximum resolution.

The sample rate is programmable up to 312.5 kHz. Each differential channel includes an anti-aliasing filter followed by a digital second order IIR Butterworth low-pass filter with a programmable breakpoint that enables user to field-adjust the filtering for each channel. The input range is field programmable for each channel. The ability to set lower voltages for Full Scale Input assures maximum resolution. The “Latch” feature holds the A/D reading for the channel being sampled until it is unlatched by the user.

The module provides bipolar outputs in two-s complement with a range from 0xFF80 0000 (maximum negative) to 0x007F FFFF (maximum positive). Unipolar output range is from 0x0000 0000 to 0x00FF FFFF (FS).

Built-In Test (BIT)/Diagnostic Capability

The onboard AD function supports two types of built-in tests: Power-On and Initiated. The results of these tests are logically OR’d together and stored in the BIT Dynamic Status and BIT Latched Status registers.

Power-On Self-Test (POST)/Power-On BIT (PBIT)/Start-Up BIT (SBIT)

The power-on self-test is performed on each channel automatically when power is applied and report the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.

Initiated Built-In Test

The inboard AD function supports two off-line Initiated Built-in Test: User Initiated BIT (UBIT) (“D0”) and Initiated BIT (IBIT) (“D3”).

UBIT test is used to check the card and interface. This test disconnects all A/D channels from the I/O and connects them across an internal D/A. Test voltage is controlled by the user by setting the desired voltage in the UBIT Test Data register. While UBIT test is enabled, the A/D Reading register will reflect the value entered for the test voltage. Note the units of the A/D Reading may represent voltage or engineering units depending on the mode specified by setting the Enable Floating Point Mode register.

IBIT test starts an initiated BIT test that disconnects all A/D’s from the I/O and then connects them across an internal stimulus. Each channel will be checked to a test accuracy of 0.2% FS and monitored for open inputs. The IBIT test cycle is completed within 20 seconds (depending on the sample rate) and results can be read from the BIT Status registers after the IBIT bit changes from 1 to 0 indicating that the IBIT test is complete. The test can be enabled or disabled at any time by writing to the appropriate register.

A/D FIFO Buffering

The inboard AD function includes A/D FIFO Buffering for greater control of the incoming signal (data) for analysis and display. When initialized and triggered, the A/D buffer will accept/store the data based on the same Sample Rate register combined with the number of active channels, or at a lower rate when utilizing the FIFO Skip Count feature. Programmable buffer sample thresholds can be utilized for data flow control.

Threshold and Saturation Programming

The inboard AD function provides registers that support threshold and saturation detection. Refer to “Analog-to-Digital Threshold and Saturation Programming Module Manual” for the Principle of Operation description.

Status and Interrupts

The inboard AD function provides registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

Module Common Registers

The inboard AD function includes module common registers that provide access to module-level bare metal/FPGA revisions & compile times, unique serial number information, and temperature/voltage/current monitoring. Refer to “Module Common Registers Module Manual” for the detailed information.

Engineering Scaling Conversions

The A/D Module Threshold, Saturation and Measurement registers can be programmed to be utilized as single precision floating point values (IEEE-754) or as 32-bit integer values.

It is very often necessary to convert a voltage reading into a more useful value such as PSI (Pounds per Square Inch), GPM (Gallons per Minute), LBS (pounds), etc. For example, when measuring force, it would be more beneficial to read the data as LBS (pounds) instead of volts. Other examples would be reading the data as PSI for pressure or GPM for flow. When the Enable Floating Point Mode register is set to 1, the values entered for the Floating Point Scale register and Floating Point Offset register will be used to convert the voltage measurement (i.e., A/D Reading and FIFO Buffer Data registers) to the associated engineering unit as follows:

AD Data in Engineering Units (Floating Point) =
                    (AD Value (Volts) * Floating Point Scale) + Floating Point Offset

The purpose for providing this feature is to offload the processing that is normally performed by the mission processor to convert the integer values to engineering unit values.

When the Enable Floating Point Mode register is set to 1 (Floating Point Mode) the following registers are formatted as Single Precision Floating Point Value (IEEE-754):

• A/D Reading
• FIFO Buffer Data
• Threshold Detect Level*
• Upper and Lower Saturation*

*When the Enable Floating Point Mode register is set to 1, it is important that these registers are updated with the Single Precision Floating Point (IEEE-754) representation of the value for proper operation of the channel. Conversely, when the Enable Floating Point Mode register is set to 0, these registers must be updated with the Integer 32-bit representation of the value.

Note

when changing the Enable Floating Point Mode from Integer Mode to Floating Point Mode or vice versa, the following steps are followed to avoid faults from falsely being generated:

1. Set the Enable Floating Point Mode register to the desired mode (Integer or Floating Point).

2. The application waits for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values nd internal values is complete. Data registers will be converted to the units specified and can be read in that specified format.

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

A/D Measurement Registers

The A/D readings are normally in terms of voltage. When the Enable Floating Point Mode is enabled, the register value formatted as Single Precision Floating Point Value (IEEE-754), in addition the Floating Point Scale and Floating Point Offset will be applied to convert the voltage engineering units.

A/D Reading
Function:	The value represents voltage or engineering units depending on mode.
Type:	signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Values are dependent on Polarity and Range settings for the channel Enable Floating Point Mode: 0 (Integer Mode)       Unipolar: 0x0000 0000 to 0x00FF FFFF       Bipolar (2's complement. 24-bit value sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode)      Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

A/D Control Registers

The A/D control registers provide the ability to specify the polarity and range, the sample rate and the filter break frequency. The A/D Latch control register provides the ability to latch any of the A/D channels to the current sample capture.

Polarity & Range
Function:	Sets input format for polarity and range for each channel. NOTE: if the Enable Floating Point Mode register is set to 1, the Floating Point Scale register must be set to the Range.
Type:	unsigned binary word (32-bit)
Data Range:	See table below.
Read/Write:	R/W
Initialized Value:	0x0000 0010 (± 10 V)
Operational Settings:	For bipolar/unipolar selection, program D4 bit as 0 for unipolar and 1 for bipolar as shown in table below.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	Polarity	0	0	Range

	Range
Reg Value	AD
0x01	0 - 5 V
0x00	0 - 10 V
0x11	± 5 V
0x10	± 10 V

Channel Sample Rate
Function:	Displays the current sample rate.
Type:	unsigned binary word (32-bit)
Data Range:	2441 - 312500 (0x0000 0989 to 0x0004 C4B4)
Read/Write:	R
Initialized Value:	0
Operational Settings:	LSB is 1Hz. Sample rate applies to all channels.

Sample Rate Divider
Function:	Used to divide the sample rate by a power of 2.
Type:	unsigned binary word (32-bit)
Data Range:	2441 - 312500 (0x0000 0989 to 0x0004 C4B4)
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	7 = max integer value for the sample rate divider, and corresponds to a sample rate of 2441.

Sample Rate Register Value	Sample Rate + (SPS)
0x0	312500
0x1	156250
0x2	78125
0x3	39062.5
0x4	19531.25
0x5	9765.625
0x6	4882.8125
0x7	2441.40625

Filter Break Frequency
Function:	The break frequency is the 3 dB point of a digital, second-order, IIR low-pass filter.
Type:	unsigned binary word (32-bit)
Data Range:	0 Hz to 90 kHz (0x0000 0000 to 0x0001 5F90)
Read/Write:	R/W
Initialized Value:	20 kHz (0x0000 4E20)
Operational Settings:	LSB is 1 Hz. The break frequency must not be less than 1% of the clock rate frequency. (Example: For a clock rate frequency of 2 kHz, the Filter Break Frequency should be no less than 20 Hz). Set to 0 to disables filter.

Acquisition Time & Conversion Time
Acquisition Time & Conversion Time:	total time required to obtain digital result. It consists of acquisition, decimator group delay when engaged and IIR filter.

Acquisition & Conversion time will vary depending on the programmed sample rates. Expect a total delay of 5.5µs when sampling at 200kHz (max). Refer to the following chart for lower sample rates:

Latch All A/D Channels
Function:	Latches all A/D channels.
Type:	unsigned binary word (32-bit)
Data Range:	0 to 1
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set 1 to latch all A/D channels and 0 to unlatch all A/D channels.

Note

The channel’s A/D Reading register will maintain the same reading while the Latch A/D bit is set to 1. Sampling for the channel will resume for that channel only when the bit is set to 0.

A/D Test Registers

Two off-line (UBIT, IBIT), can be selected. External reference voltage is not required for any of these tests.

Test Enabled
Function:	Sets bit to enable the associated Built-In Self-Test (BIST): IBIT and UBIT.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 000F
Read/Write:	R/W
Initialized Value:	0x4 (IBIT Test Enabled)
Operational Settings:	BIT tests includes two off-line (IBIT) tests. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggers when the BIT testing detects failures.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	IBIT Enabled	0	0	UBIT Enabled

UBIT Test Data
Function:	Specifies voltage to be applied for the A/D UBIT off-line test.
Type:	signed binary word (32-bit)
Data Range:	Voltage values are dependent on Polarity and Range settings for the channel       Unipolar: 0x0000 0000 to 0x00FF FFFF       Bipolar (2's complement. 24-bit value sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	LSB is dependent on the Range setting. Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

UBIT Polarity
Function:	Specifies polarity of the test generator going into all channels.
Type:	binary word (32-bit)
Data Range:	0x0000 0000 or 0x0000 0010
Read/Write:	R/W
Initialized Value:	0x0000 0000
Operational Settings:	Write 0 to D4 of register to set channels for unipolar. Write 1 to set all channels for bipolar.
Default:	Unipolar.

FIFO Registers

The FIFO registers are configurable for each channel.

FIFO Buffer Data
Function:	Available data in the FIFO buffer can be retrieved, one word at a time. (LSB for 24-bit word resolution is dependent on the Polarity and Range setting).
Type:	Voltage: signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode) Timestamp (sample counter): unsigned binary word (32-bit)
Data Range:	Enable Floating Point Mode: 0 (Integer Mode)      Unipolar: 0x0000 0000 to 0x00FF FFFF      Bipolar (2's complement. 24-bit value sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode)      Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

FIFO Word Count
Function:	This is a counter that reports the number of 24-bit words stored in the FIFO buffer.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x000F FFFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	Every time a read operation is made from the A/D Data memory address, its corresponding Words in FIFO counter will be decremented by one. The maximum number of words that can be stored in the FIFO is 1 mega words.

FIFO Thresholds

The FIFO Almost Empty, FIFO Low Watermark, FIFO High Watermark, FIFO Almost Full and FIFO Buffer Size sets the threshold limits that are used to set the bits in the FIFO Status register.

FIFO Almost Empty
Function:	The FIFO Almost Empty is used to set the limits for the “almost empty" status.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x000F FFFF
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	When the Words in FIFO counter is greater than or equal to the value stored in the FIFO Almost Empty register, the “almost empty" bit (D1) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the register, the “almost empty" bit (D1) of the FIFO Status register will be reset.

FIFO Low Watermark
Function:	The FIFO Low Watermark (low-threshold level) is used to set the limits for the “low watermark" status.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x000F FFFF
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	When the Words in FIFO counter is less than or equal to the value stored in the FIFO Low Watermark register, the “low watermark" bit (D2) of the FIFO Status register will be set. When the Words in FIFO counter is greater than the value stored in the register, the “low watermark" bit (D2) of the FIFO Status register will be reset.

FIFO High Watermark
Function:	The FIFO High Watermark (high-threshold level) is used to set the limits for the “high watermark" status.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x000F FFFF
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	When the Words in FIFO counter is greater than or equal to the value stored in the FIFO High Watermark register, the “high watermark" bit (D3) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the high threshold, the “high watermark" bit (D3) of the FIFO Status register will be reset.

FIFO Almost Full
Function:	The FIFO Almost Full is used to set the limits for the “almost full" status.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x000F FFFF
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	When the Words in FIFO counter is greater than or equal to the value stored in the FIFO Almost Full register, the “almost full" bit (D4) of the FIFO Status register will be set. When the Words in FIFO counter is less than the value stored in the register, the “almost full" bit (D4) of the FIFO Status register will be reset.

FIFO Buffer Size
Function:	Sets the number of samples to be taken and placed into the FIFO when a trigger occurs.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x001F FFFF
Read/Write:	R/W
Initialized Value:	0x001F FFFF
Operational Settings:	The size of each sample (number of words written to the FIFO per sample) is determined by the sample format described by the FIFO Buffer Control register. When the Words in FIFO counter reaches the FIFO Buffer Size, the “sample done" bit (D6) is set and no additional samples will be placed in the FIFO. When Words in FIFO counter is less than FIFO Buffer Size, the “sample done" bit (D6) will be reset.

Data Control
Function:	Sets the format of the samples to be stored in the FIFO buffer which is determined by the bitmapped table.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0014
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	The Time Stamp data format (D4) requires one word of storage space from the FIFO buffer. For example, if (D4) is set to 0 and the FIFO Buffer Size register is set to 1, a FIFO write will put one word of data in the FIFO memory space per sample and discard the timestamp (sample counter). Since the maximum physical size of FIFO is 1M words for each channel, the value in the FIFO Buffer Size and Data Control registers could cause an overflow to the FIFO buffer. When an overflow condition occurs, any data that is not placed in the FIFO will be lost.

D31:D5	Reserved. Set to 0
D4	Time Stamp. An integer counter that counts from 0 to 65,535 and wraps around when it overflows.
D3	Reserved. Set to 0
D2	Data Type. 0 = Raw (unfiltered); 1 = Filtered (post-programmable IIR).
D1:D0	Reserved. Set to 0

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	D	0	D	0	0

FIFO Sample Delay
Function:	Sets the number of delay samples before the actual FIFO data collection begins.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	The data collected during the delay period will be discarded.

FIFO Skip Count
Function:	Sets how many samples to skip over when storing data in FIFO.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0 (No Skip Count (FIFO stores every sample))
Operational Settings:	If the sample rate for a channel is 10 kHz, there would be a new sample every 100µs. By setting the FIFO skip count to 1, the FIFO will store a new sample every 200 µs, or at a 5 kHz rate.

Clear FIFO
Function:	Clears FIFO by resetting the Words in FIFO count.
Type:	unsigned binary word (32-bit)
Data Range:	0 or 1
Read/Write:	W
Initialized Value:	0x0
Operational Settings:	This resets the Words in FIFO to zero; Clear FIFO register does not clear data in the buffer. A read to the buffer data will give “aged" data. Write a 1 to reset the Words in FIFO for the channel.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

FIFO Trigger Control
Function:	Starts/triggers FIFO. FIFO can be started/triggered by different sources.
Type:	unsigned binary word (32-bit)
Data Range:	0x0 to 0x1FF
Read/Write:	R/W
Initialized Value:	0 (Disable Trigger)
Operational Settings:	For the current implementation, triggering of FIFO is by Software Trigger only. Hardware triggering will be implemented in a future release. Hardware triggering will be platform dependent based on pin-outs and I/O availability. See the tables that follow for the current and pending settings.

D8	Trigger Enable
0	Not Enabled / Stop Trigger
1	Enable Trigger

D[6..4]	Trigger Edge
0	RESERVED for Hardware Trigger (Positive Edge)
1	RESERVED for Hardware Trigger (Negative Edge)
2	RESERVED for Hardware Trigger (Either Edge)
3	Software Trigger
4	Threshold 1
5	Threshold 2
6	Threshold 1 or 2

D0	Trigger Type
0	Continuous
1	Single Sample

D[15..0]	Summary Description
0x0100	Store continuously once there is a positive edge on the Hardware Trigger (pending).
0x0101	Store single sample once there is a positive edge on the Hardware Trigger (pending).
0x0110	Store continuously once there is a negative edge on the Hardware Trigger (pending).
0x0111	Store single sample once there is a negative edge on the Hardware Trigger (pending).
0x0120	Store continuously once there is a negative or positive edge on the Hardware Trigger (pending).
0x0121	Store single sample once there is a negative or positive edge on the Hardware Trigger (pending).
0x0130	Store continuously once there is a Software Trigger.
0x0131	Store single sample once there is a Software Trigger
0x1140	Store continuously once threshold 1 for channel 2 occurs
0xE161	Store single sample once either threshold 1 or 2 for channel 15 occurs
0x0000	Disable Trigger (will stop FIFO from storing data if continuously running

D[15..12]	Threshold Channel Select
0	Channel 1
1	Channel 2
2	Channel 3
3	Channel 4

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

FIFO Software Trigger
Function:	Software trigger is used to start the FIFO buffer and the collection of data.
Type:	unsigned binary word (32-bit)
Data Range:	0 or 1
Read/Write:	W
Initialized Value:	0 (Not Triggered)
Operational Settings:	To use this operation, the FIFO Trigger Control register must be set up as described in the FIFO Trigger Control register. Write a 1 to trigger FIFO collection for all channels.

D31:D1	Reserved. Set to 0
D0	Set to 1 to start the FIFO data collection.

Threshold Detect Programming Registers

The Analog-to-Digital Modules provide registers that support threshold detection. Refer to “Analog-to-Digital Threshold and Saturation Programming Module Manual” for the register descriptions.

Saturation Programming Registers

The Analog-to-Digital Modules provide registers that support saturation detection. Refer to “Analog-to-Digital Threshold and Saturation Programming Module Manual” for the register descriptions.

Engineering Scaling Conversions Registers

The Analog-to-Digital Module Threshold, Saturation, and Measurement registers can be programmed to be utilized as a Single Precision Floating Point Value (IEEE-754) or as a 32-bit integer value.

Enable Floating Point Mode
Function:	Sets all channels for floating point mode or integer module.
Type:	unsigned binary word (32-bit)
Data Range:	0 or 1
Read/Write:	R/W
Initialized Value:	0 (Integer mode)
Operational Settings:	Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode. Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Floating Point Offset
Function:	This register sets the floating point offset to add to AD data.
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	N/A
Read/Write:	R/W
Initialized Value:	0.0
Operational Settings:	Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Floating Point Scale
Function:	This register sets the floating point scale to multiply the AD data.
Type:	Single Precision Floating Point Value (IEEE-754)
Data Range:	N/A
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Refer to section Appendix A: Integer/Floating Point Mode Programming for Integer and Floating Point Mode examples.

Floating Point State
Function:	Indicates whether the module's internal processing is converting the register values and internal values to the binary representation of the mode selected (Integer or Floating Point).
Type:	unsigned binary word (32-bit)
Data Range:	0 to 1
Read/Write:	R
Initialized Value:	0
Operational Settings:	Indicates the whether the module registers are in Integer (0) or Floating Point Mode (1). When the Enable Floating Point Mode is modified, the application must wait until this register's value matches the requested mode before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Module Common Registers

Refer to “Module Common Registers Module Manual” for the register descriptions.

Status and Interrupt Registers

The AD modules provide status registers for BIT, FIFO, Overcurrent, Open, External Power Loss, Threshold Detect, Saturation, Inter-FPGA Failure and Summary.

Channel Status Enable
Function:	Determines whether to update the status for the channels. This feature can be used to “mask" status bits of unused channels in status registers that are bitmapped by channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 000F (Channel Status)
Read/Write:	R/W
Initialized Value:	0x0000 000F
Operational Settings:	When the bit corresponding to a given channel in the Channel Status Enable register is not enabled (0) the status will be masked and report '0' or “no failure". This applies to all statuses that are bitmapped by channel (BIT Status, Overcurrent Status and Summary Status).

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. The BIT Status register will indicate an error when the voltage read is not within the error of the set value.

BIT Status
Function:	Sets the corresponding bit associated with the channel's BIT error.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x000F 0003
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Note

BIT Status is a shared register between the CAN and AD functions. Bits D1:D0 are dedicated to the CAN function, and bits D19:D16 are dedicated to the AD function.

BIT Dynamic Status

BIT Latched Status

BIT Interrupt Enable

BIT Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

AD Ch4

AD Ch3

AD Ch2

AD Ch1

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CAN Ch2

CAN Ch1

FIFO Status

There are four registers associated with the FIFO Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. D0-D6 is used to show the different conditions of the buffer.

Function:	Sets the corresponding bit associated with the FIFO status type; there is a separate register for each channel.
Type:	binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 007F
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Note

Shown below is an example of interrupts generated for the High Watermark. As shown, the interrupt is generated as the FIFO count crosses the High Watermark. The interrupt will not be generated a second time until the count goes below the watermark and then above it again.

FIFO Dynamic Status

FIFO Latched Status

FIFO Interrupt Enable

FIFO Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

D

D

D

D

D

D

D

Bit	Description	Configurable?
D0	Empty; 1 when FIFO Count = 0	No
D1	Almost Empty; 1 when FIFO Count <= “FIFO Almost Empty" register	Yes
D2	Low Watermark; 1 when FIFO Count <= “FIFO Low Watermark" register	Yes
D3	High Watermark; 1 when FIFO Count >= “FIFO High Watermark" register	Yes
D4	Almost Full; 1 when FIFO Count >= “FIFO Almost Full" register	Yes
D5	Full; 1 when FIFO Count = 1 Mega Words (0x000F FFFF)	No
D6	Sample Done; 1 when FIFO Count "FIFO Buffer Size" register	Yes

Threshold Detect Status

The Analog-to-Digital function provide registers that support threshold detection. Refer to “Threshold and Saturation Capability” for the register descriptions.

Saturation Status

The Analog-to-Digital function provide registers that support saturation detection. Refer to “Threshold and Saturation Capability” for the register descriptions.

Summary Status

There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Function:	Sets the corresponding bit if any fault (BIT, Overcurrent, Open, External Power Loss, or Inter-FPGA Failure) occurs on that channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x000F 0000
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Summary Dynamic Status
Summary Latched Status
Summary Interrupt Enable
Summary Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Function Register Map

KEY

Configuration/Control

State/Measurement/Status

A/D MEASUREMENT REGISTERS
**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).
NOTE: Base Address - 0x9010 8000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1000	A/D Reading Ch 1**	R
0x1004	A/D Reading Ch 2**	R
0x1008	A/D Reading Ch 3**	R
0x100C	A/D Reading Ch 4**	R
A/D CONTROL REGISTER
NOTE: Base Address - 0x9010 8000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1080	Polarity & Range Ch 1	R/W	0x1100	Filter Break Frequency Ch 1	R/W
0x1084	Polarity & Range Ch 2	R/W	0x1104	Filter Break Frequency Ch 2	R/W
0x1088	Polarity & Range Ch 3	R/W	0x1108	Filter Break Frequency Ch 3	R/W
0x108C	Polarity & Range Ch 4	R/W	0x110C	Filter Break Frequency Ch 4	R/W
0x188C	Sample Rate	R/W	0x1880	Latch All A/D Channels	R/W
FIFO REGISTERS
**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).
NOTE: Base Address - 0x9010 8000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1180	FIFO Buffer Data Ch 1**	R	0x1200	FIFO Word Count Ch 1	R
0x1184	FIFO Buffer Data Ch 2**	R	0x1204	FIFO Word Count Ch 2	R
0x1188	FIFO Buffer Data Ch 3**	R	0x1208	FIFO Word Count Ch 3	R
0x118C	FIFO Buffer Data Ch 4**	R	0x120C	FIFO Word Count Ch 4	R
0x1480	FIFO Sample Delay Ch 1	R/W	0x1580	FIFO Skip Count Ch 1	R/W
0x1484	FIFO Sample Delay Ch 2	R/W	0x1584	FIFO Skip Count Ch 2	R/W
0x1488	FIFO Sample Delay Ch 3	R/W	0x1588	FIFO Skip Count Ch 3	R/W
0x148C	FIFO Sample Delay Ch 4	R/W	0x158C	FIFO Skip Count Ch 4	R/W
0x1600	Clear FIFO Ch 1	W	0x1680	Data Control Ch 1	R/W
0x1604	Clear FIFO Ch 2	W	0x1684	Data Control Ch 2	R/W
0x1608	Clear FIFO Ch 3	W	0x1688	Data Control Ch 3	R/W
0x160C	Clear FIFO Ch 4	W	0x168C	Data Control Ch 4	R/W
0x1884	FIFO Trigger Control	R/W	0x1888	FIFO Software Trigger	W
FIFO THRESHOLDS
NOTE: Base Address - 0x9010 8000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1280	FIFO Almost Empty Ch 1	R/W	0x1380	FIFO Low Watermark Ch 1	R/W
0x1284	FIFO Almost Empty Ch 2	R/W	0x1384	FIFO Low Watermark Ch 2	R/W
0x1288	FIFO Almost Empty Ch 3	R/W	0x1388	FIFO Low Watermark Ch 3	R/W
0x128C	FIFO Almost Empty Ch 4	R/W	0x138C	FIFO Low Watermark Ch 4	R/W
0x1300	FIFO Almost Full Ch 1	R/W	0x1400	FIFO High Watermark Ch 1	R/W
0x1304	FIFO Almost Full Ch 2	R/W	0x1404	FIFO High Watermark Ch 2	R/W
0x1308	FIFO Almost Full Ch 3	R/W	0x1408	FIFO High Watermark Ch 3	R/W
0x130C	FIFO Almost Full Ch 4	R/W	0x140C	FIFO High Watermark Ch 4	R/W
0x1500	FIFO Buffer Size Ch 1	R/W
0x1504	FIFO Buffer Size Ch 2	R/W
0x1508	FIFO Buffer Size Ch 3	R/W
0x150C	FIFO Buffer Size Ch 4	R/W
THRESHOLD DETECT PROGRAMMING REGISTERS
The Analog-to-Digital function provide registers that support threshold detection. Refer to “Appendix D: Threshold and Saturation Capability" for the Threshold Detect Programming Function Register Map.
SATURATION PROGRAMMING REGISTERS
The Analog-to-Digital function provide registers that support saturation. Refer to “Appendix D: Threshold and Saturation Capability" for the Saturation Programming Function Register Map.
ENGINEERING SCALING CONVERSIONS REGISTERS
**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).
~ Data is always in Floating Point.
NOTE: Base Address - 0x9010 8000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x02B4	Enable Floating Point	R/W	0x0264	Floating Point State	R
0x1700	Floating Point Offset Ch 1~	R/W	0x1780	Floating Point Scale Ch 1~	R/W
0x1704	Floating Point Offset Ch 2~	R/W	0x1784	Floating Point Scale Ch 2~	R/W
0x1708	Floating Point Offset Ch 3~	R/W	0x1788	Floating Point Scale Ch 3~	R/W
0x170C	Floating Point Offset Ch 4~	R/W	0x178C	Floating Point Scale Ch 4~	R/W
STATUS REGISTERS
NOTE: Base Address - 0x9010 8000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x02B0	Channel Status Enable	R/W
BIT REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0800	Dynamic Status	R
0x0804	Latched Status*	R/W
0x0808	Interrupt Enable	R/W
0x080C	Set Edge/Level Interrupt	R/W
NOTE: Base Address - 0x9010 8000
0x0248	Test Enabled	R/W	0x0294	UBIT Polarity	R/W
0x0298	UBIT Test Data	R/W
0x02AC	Power-on BIT Complete++	R
++After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.
STATUS REGISTERS
NOTE: Base Address - 0x9010 4000
THRESHOLD DETECT STATUS — The Analog-to-Digital function provide status registers for threshold detection. Refer to “Appendix D: Threshold and Saturation Capability" for the Threshold Status Function Register Map.
SATURATION PROGRAMMING REGISTERS — The Analog-to-Digital function provide status registers for saturation. Refer to “Appendix D:Threshold and Saturation Capability" for the Saturation Status Function Register Map.
SUMMARY STATUS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x09A0	Dynamic Status	R
0x09A4	Latched Status*	R/W
0x09A8	Interrupt Enable	R/W
0x09AC	Set Edge/Level Interrupt	R/W
FIFO STATUS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0900	Dynamic Status Ch 1	R	0x0910	Dynamic Status Ch 2	R
0x0904	Latched Status Ch 1*	R/W	0x0914	Latched Status Ch 2*	R/W
0x0908	Interrupt Enable Ch 1	R/W	0x0918	Interrupt Enable Ch 2	R/W
0x090C	Set Edge/Level Interrupt Ch 1	R/W	0x091C	Set Edge/Level Interrupt Ch 2	R/W
0x0920	Dynamic Status Ch 3	R	0x0930	Dynamic Status Ch 4	R
0x0924	Latched Status Ch 3*	R/W	0x0934	Latched Status Ch 4*	R/W
0x0928	Interrupt Enable Ch 3	R/W	0x0938	Interrupt Enable Ch 4	R/W
0x092C	Set Edge/Level Interrupt Ch 3	R/W	0x093C	Set Edge/Level Interrupt Ch 4	R/W

Appendix: Integer/Floating Point Mode Programming

Integer Mode Programming

When in Integer Mode, the values in the following registers are dependent on the Polarity and Range settings:

• A/D Reading and FIFO Buffer Data

• UBIT Test Data

• Threshold Level and Threshold Hysteresis

• Low and High Saturation

A/D Reading and FIFO Buffer Data

The LSB for the 24-bit word resolution for the A/D Reading register and the FIFO Buffer Data register is dependent on the Polarity and Range setting. The 32-bit binary value in these registers use the two’s complement form to represent the positive and negative values.

For example:

• Polarity & Range Register = 0x10 (Polarity = Bipolar & Range = 10.0 V)

  LSB = 10.0 / 0x007F FFFF = 10.0 / 2<sup>23</sup> = **10.0 / 8388608**
  
  If the register value is 3774873 (binary equivalent for this value is **0x0039 9999**), conversion to the voltage value is 3774873 * (10.0 /
  

8388608. = 4.50 V.

  If the register value is -100000 (binary equivalent for this value is 0xFFFE 7960), conversion to the voltage value is -100000 * (10.0 /

8388608. = -0.0119 V.

• Polarity & Range Register = 0x00 (Polarity = Unipolar & Range = 10.0 V)

  LSB = 10.0 / 0x00FF FFFF = 10.0 / 2<sup>24</sup> = **10.0 / 16777216**
  
  If the register value is 3774873 (binary equivalent for this value is **0x0039 9999**), conversion to the voltage value is 14745 * (10.0 / 1677216) = **2.25 V**.
  

UBIT Test Programming

The value to set in the UBIT Test Data register is dependent on the Polarity and Range setting. In the Integer mode, the A/D Reading register will represent the voltage measured as the result of setting the UBIT test value.

For example:

• Polarity & Range Register = 0x10 (Polarity = Bipolar & Range = 10.0 V)

  LSB = 10.0 / 0x007F FFFF = 10.0 / 2<sup>23</sup> = **10.0 / 838860**
  

UBIT Test Value		Example of A/D Reading
Test Value (volts)	Binary Value	Reading (volts)	Binary Value
3.0	3.0 * (8388608/10.0) = 2516582 = 0x0026 6666	2.96	2.96 * (8388608/10.0) = 2483027 = 0x0025 E353
-3.0	-3.0 * (8388608/10.0) = -2516582 = 0xFFD9 999A	-2.96	-2.96 * (8388608/10.0) = -2483027 = 0xFFDA 1CAD

• Polarity & Range Register = 0x00 (Polarity = Unipolar & Range = 10.0 V)

  LSB = 10.0 / 0x00FF FFFF = 10.0 / 2<sup>24</sup> = **10.0 / 16777216**
  

UBIT Test Value		Example of A/D Reading
Test Value (volts)	Binary Value	Reading (volts)	Binary Value
3.0	3.0 * (16777216/10.0) = 5033164 = 0x004C CCCC	2.96	2.96 * (65536/10.0) = 4966055 = 0x004B C6A7

Threshold Programming

The LSB for the 24-bit word resolution for the Threshold Detect Level and Threshold Detect Hysteresis registers is dependent on the Polarity and Range setting. The 32-bit binary value in these registers use the two’s complement form to represent the positive and negative values.

For example:

• Polarity & Range Register = 0x10 (Polarity = Bipolar & Range = 10.0 V)

  LSB = 10.0 / 0x007F FFFF = 10.0 / 2<sup>23</sup> = **10.0 / 8388608**
  

Threshold Detect Level Value (volts)		Threshold Detect Hysteresis Value (volts) (must be positive)
Level Value	Binary Value	Hysteresis	Binary Value
7.5	7.5 * (8388608/10.0) = 6291456= 0x0060 0000	0.25	0.25 * (8388608/10.0) = 209715= 0x0003 3333
-7.5	-7.5 * (8388608/10.0) = -6291456 = 0xFFA0 0000	-0.15	0.15 * (8388608/10.0) = 125829= 0x0001 EB85

• Polarity & Range Register = 0x00 (Polarity = Unipolar & Range = 10.0 V)

  LSB = 10.0 / 0x00FF FFFF = 10.0 / 2<sup>24</sup> = **10.0 / 16777216**
  

Threshold Detect Level Value (volts)		Threshold Detect Hysteresis Value (volts) (must be positive)
Level Value	Binary Value	Hysteresis	Binary Value
7.5	7.5 * (16777216/10.0) = 12582912= 0x00C0 0000	0.25	0.25 * (16777216/10.0) = 419430= 0x0006 6666

Saturation Programming

The LSB for the 24-bit word resolution for the Low and High Saturation registers is dependent on the Polarity and Range setting. The 32-bit binary value in these registers use the two’s complement form to represent the positive and negative values.

For example:

• Polarity & Range Register = 0x10 (Polarity = Bipolar & Range = 10.0 V)

  LSB = 10.0 / 0x007F FFFF = 10.0 / 2<sup>23</sup> = **10.0 / 8388608**
  

Low Saturation Value (volts)		High Saturation Value (volts)
Value	Binary Value	Value	Binary Value
-7.5	-7.5 * (8388608/10.0) = -6291456= 0xFFA0 0000	7.5	7.5 * (8388608/10.0) = 6291456= 0x0060 0000

• Polarity & Range Register = 0x00 (Polarity = Unipolar & Range = 10.0 V)

  LSB = 10.0 / 0x00FF FFFF = 10.0 / 2<sup>24</sup> = **10.0 / 16777216**
  

Low Saturation Value (volts)		High Saturation Value (volts)
Value	Binary Value	Value	Binary Value
1.5	1.5 * (16777216/10.0) = 9830 = 0x0000 2666	7.5	7.5 * (16777216/10.0) = 49152 0x0000 C000

Floating Point Mode Voltage Programming

When in Floating Point Mode, the registers listed in the Integer Mode Programming section are still dependent on the Polarity and Range settings, however, the module handles the conversion of the 32-bit binary value to to Single Precision Floating Point Value (IEEE-754) format. The values in the Floating Point Scale register and Floating Point Offset register are used in the conversion. For results to be represent voltage:

• Set Floating Point Scale register to Range

• Set Floating Point Offset register to 0

A/D Reading and FIFO Buffer Data

For example:

• Polarity & Range Register = 0x10 (Polarity = Bipolar & Range = 10.0 V)

  Floating Point Scale = **10.0** = **10.0 V**  
  
  Floating Point Offset = **0**
  

Example of Internal A/D Reading Value	Applying Floating PointScale and Offset (volts)	Single Precision Floating Point Value (IEEE-754)
3774873/ 8388608= 0.45 (0x0039 9999/0x007F FFFF)	(0.45 * 10.0) + 0.0 = 4.50	0x4090 0000
-25585 / 8388608= -0.00305 (0xFFFF 9C0F/0x007F FFFF)	(-0.00305 * 10.0) + 0.0 =-0.0305	0xBCF9 DB23

• Polarity & Range Register = 0x00 (Polarity = Unipolar & Range = 10.0 V)

  Floating Point Scale = **10.0** = **10.0 V**
  
  Floating Point Offset = **0**
  

Example of Internal A/D Reading Value	Applying Floating PointScale and Offset (volts)	Single Precision Floating Point Value (IEEE-754)
3774873/ 16777216= 0.225 0x0039 9999/0x00FF FFFF)	(0.225 * 10.0) + 0.0 = 2.25	0x4010 0000

UBIT Test Programming

The value to set in the UBIT Test Data register is dependent on the Polarity and Range settings and these settings will determine the 32-bit value to set in this register. In the Floating Point mode, the A/D Reading register will represent the voltage measured as the result of setting the UBIT test value.

For example:

• Polarity & Range Register = 0x10 (Polarity = Bipolar & Range = 10.0 V)

  LSB = 10.0 / 0x007F FFFF = 10.0 / 2<sup>23</sup> = **10.0 / 8388608**
  
  Floating Point Scale = **10.0** = **10.0 V**
  
  Floating Point Offset = **0**
  

UBIT Test Value		Example of A/D Reading
Test Value(volts)	Binary Value	Internal A/D Reading Value	Reading (Volts)	Single Precision Floating Point Value (IEEE-754)
3.0	3.0 * (8388608/10.0) = 2516582= 0x0026 6666	2482944/ 8388608= 0.296 (0x0025 E300/0x007F FFFF)	(0.296 * 10.0) + 0.0 = 2.96	0x403D 70A4
-3.0	-3.0 * (8388608/10.0) =-2516582= 0xFFD9 999A	-2482944 / 8388608= -0.296 (0xFFDA 1D00/0x007F FFFF)	(-0.296 * 10.0) + 0.0 =-2.96	0xC03D 70A4

• Polarity & Range Register = 0x00 (Polarity = Unipolar & Range = 10.0 V)

  LSB = 10.0 / 0x00FF FFFF = 10.0 / 2<sup>24</sup> = **10.0 / 16777216**
  
  Floating Point Scale = **10.0** = **10.0 V**
  
  Floating Point Offset = **0**
  

UBIT Test Value		Example of A/D Reading
Test Value(volts)	Binary Value	Internal A/D Reading Value	Reading (Volts)	Single Precision Floating Point Value (IEEE-754)
3.0	3.0 * (16777216/10.0) = 5033164= 0x004C CCCC	4966144/ 16777216= 0.296 (0x004B C700/0x00FF FFFF)	(0.296 * 10.0) + 0.0 = 2.96	0x403D 70A4

Threshold Programming

In Floating Point mode, the Threshold Detect Level and Threshold Detect Hysteresis values should be entered in Single Precision Floating Point Value (IEEE-754) format.

For example:

• Polarity & Range Register = 0x10 (Polarity = Bipolar & Range = 10.0 V)

OR

  Polarity & Range Register = **0x00** (Polarity = **Unipolar** & Range = **10.0V**)

  Floating Point Scale = **10.0 = 10.0 V**

  Floating Point Offset = **0**

Threshold Detect Level Value (volts)		Threshold Detect Hysteresis Value (volts) (must be positive)
Level Value	Single Precision Floating Point Value (IEEE-754)	Hysteresis	Single Precision Floating Point Value (IEEE-754)
7.5	0x40F0 0000	0.25	0x3E80 0000
-7.5	0xC0F0 0000	0.15	0x3E19 999A

Saturation Programming

In Floating Point mode, the Low and High Saturation values should be entered in Single Precision Floating Point Value (IEEE-754) format.

For example:

• Polarity & Range Register = 0x10 (Polarity = Bipolar & Range = 10.0 V)

OR

  Polarity & Range Register = **0x00** (Polarity = **Unipolar** & Range = **10.0V**)

  Floating Point Scale = **10.0 = 10.0 V**

  Floating Point Offset = **0**

Low Saturation Value (volts)		High Saturation Value (volts)
Value	Single Precision Floating Point Value (IEEE-754)	Values	Single Precision Floating Point Value (IEEE-754)
-7.5	0xC0F0 0000	7.5	0xC0F0 0000

Floating Point Mode Engineering Units Programming

When in Floating Point Mode, the registers listed in the Integer Mode Programming section are still dependent on the Polarity and Range settings, however, the module handles the conversion of the 32-bit binary value to Single Precision Floating Point Value (IEEE 754) format. The values in the Floating Point Scale register and Floating Point Offset register are used in the conversion. For results to be represent engineering units:

• Set Floating Point Scale register to *Range ** Engineering Unit Conversion

• Set Floating Point Offset register to Engineering Unit Conversion Bias

A/D Readings

The following calculation is used to convert A/D Reading to engineering units:

AD Data in Engineering Units (Floating Point) =
                    (AD Value (Volts) * Floating Point Scale) + Floating Point Offset

For example:

• A signal of -10V to 10V indicate a displacement from -38.5mm to 38.5 mm respectively.

  Polarity & Range Register = **0x10** (Polarity = **Bipolar** & Range = **10.0 V**)
  
  Floating Point Scale = **Range ** Scale Conversion* = **10.0 ** 3.85 = 38.5*
  
  Floating Point Offset = **0.0**
  

Voltage (volts)	Example of Internal A/D Reading Value	Applying Floating Point Scale and Offset (mm)	Single Precision Floating Point Value (IEEE-754)
10.0	8388608/ 8388608= 1.0 (0x007F FFFF/0x007F FFFF)	(1.0 * 38.5) + 0.0 = 38.5	0x421A 0000
5.0	4194304 / 8388608= 0.5 (0x0040 0000/0x007F FFFF)	(0.5 * 38.5) + 0.0 = 19.25	0x419A 0000
4.5	3774720/ 8388608= 0.45 (0x0039 9900/0x007F FFFF)	(0.45 * 38.5) + 0.0 = 17.325	0x418A 999A
0.0	0 /8388608= 0.0 (0x0000 0000/0x007F FFFF)	(0.0 * 38.5) + 0.0 = 0.0	0x0000 0000
-0.0305	-25600 / 8388608= -0.00305 (0xFFFF 9C00/0x007F FFFF)	(-0.00305 * 38.5) + 0.0 = 0.117425	0x3DF0 7C85
-5.0	-4194304 / 8388608= -0.5 (0xFFC0 00000/0x007F FFFF)	(-0.5 * 38.5) + 0.0 = -19.25	0xC19A 0000
-10.0	-8388608 / 8388608= -1.0 (0xFF80 0000/0x007F FFFF)	(-1.0 * 38.5) + 0.0 = -38.5	0xC21A 0000

• A pressure sensor is used to measure 0-500 PSI where the voltage reading are 1-5 volts.

  Polarity & Range Register = **0x00** (Polarity = **Unipolar** & Range = **10.0 V**)
  
  Floating Point Scale = **Range ** Scale Conversion* = **10 ** 125 = 1250*
  
  Floating Point Offset = **-125**
  

Note

Set Low Saturation Value to the equivalent of 1 volt and High Saturation Value to the equivalent to 5 volts.

Voltage (volts)	Example of Internal A/D Reading Value	Applying Floating Point Scale and Offset (mm)	Single Precision Floating Point Value (IEEE-754)
5.0	8388608/ 16777216= 0.5 (0x0080 0000/0x00FF FFFF)	(0.5 * 1250) + (-125) = 500	0x43FA 0000
4.0	6710784/ 16777216= 0.4 (0x0066 6600/0x00FF FFFF)	(0.4 * 1250) + (-125) = 375.0	0x43BB 8000
3.0	5033216/ 16777216= 0.3 (0x004C CD00/0x00FF FFFF)	(0.3 * 1250) + (-125) = 250.0	0x437A 0000
2.5	4194304/ 16777216= 0.25 (0x0040 0000/0x00FF FFFF)	(0.25 * 1250) + (-125) = 187.5	0x433B 8000
2.0	3355392/ 16777216= 0.2 (0x0033 3300/0x00FF FFFF)	(0.2 * 1250) + (-125) = 125.0	0x42FA 0000
1.0	1677824/ 16777216= 0.1 (0x0019 9A00/0x00FF FFFF)	(0.1 * 1250) + (-125) = 0.0	0x0000 0000

UBIT Test Programming

The value to set in the UBIT Test Data register is dependent on the Polarity and Range settings and these settings will determine the 32-bit value to set in this register. In the Floating Point mode, the A/D Reading register will represent the voltage measured and converted to engineering units as the result of setting the UBIT test value.

For example:

• A signal of -10V to 10V indicate a displacement from -38.5mm to 38.5 mm respectively.

  Polarity & Range Register = **0x10** (Polarity = **Bipolar** & Range = **10.0 V**)
  
  Floating Point Scale = **Range ** Scale Conversion* = **10.0 ** 3.85 = 38.5*
  
  Floating Point Offset = **0.0**
  

UBIT Test Value		Example of A/D Reading
Test Value(volts)	Binary Value	Internal A/D Reading Value	Reading (mm)	Single Precision Floating Point Value (IEEE-754)
3.0	3.0 * (8388608/10.0) = 2516582 = 0x0026 6666	2482944/ 8388608 = 0.296 (0x0025 E300/0x007F FFFF)	(0.296 * 38.5) + 0.0 = 11.396	0x4136 5604
-3.0	-3.0 * (8388608/10.0) = -2516582 = 0xFFD9 999A	-2482944/ 8388608 = -0.296(0xFFDA 1D00/0x007F FFFF)	(-0.296 * 38.5) + 0.0 = -11.396	0xC136 0xC136

• A pressure sensor is used to measure 0-500 PSI where the voltage reading are 1-5 volts.

  Polarity & Range Register = **0x00** (Polarity = **Unipolar** & Range = **10.0 V**)
  
  Floating Point Scale = **Range ** Scale Conversion* = **10 ** 125 = 1250*
  
  Floating Point Offset = **-125**
  

UBIT Test Value		Example of A/D Reading
Test Value(volts)	Binary Value	Internal A/D Reading Value	Reading (PSI)	Single Precision Floating Point Value (IEEE-754)
3.0	3.0 * (16777216/10.0) = 5033164 = 0x004C CCCC	4966144/ 16777216 = 0.296 (0x004B C700/0x00FF FFFF)	(0.296 * 1250) + 0.0 = 370.0	0x43B9 0000

Threshold Programming

In Floating Point mode, the Threshold Detect Level and Threshold Detect Hysteresis values should be entered in Single Precision Floating Point Value (IEEE-754) format in terms of engineering units.

For example:

• A signal of -10V to 10V indicate a displacement from -38.5mm to 38.5 mm respectively.

  Polarity & Range Register = **0x10** (Polarity = **Bipolar** & Range = **10.0 V**)
  
  Floating Point Scale = **Range ** Scale Conversion* = **10.0 ** 3.85 = 38.5*
  
  Floating Point Offset = **0.0**
  

Threshold Detect Level Value			Threshold Detect Hysteresis Value (volts) (must be positive)
Level Value(volts)	Binary Value	Applying Floating Point Scale and Offset (mm)	Hysteresis (volts)	Binary Value	Applying Floating Point Scale and Offset (mm)
7.5	6291456/ 8388608 = 0.75 (0x0060 0000/0x007F FFFF)	(0.75 * 38.5) + 0 = 28.875 0x41E7 0000	0.25	209664/ 8388608 = 0.025 (0x0003 3300/0x0000 7FFF) (0.025 * 38.5) + 0 = 0.9625 0x3F76 6666	-7.5
-6291456/ 8388608 = -0.75 (0xFFA0 0000/0x007F FFFF	(-0.75 * 38.5) + 0 = -28.875 0xC1E7 0000	0.15	125952/ 8388608 = 0.015 (0x0001 EC00/0x0000 7FFF)	(0.015 * 38.5) + 0 = 0.5775 0x3F13 D70A

• A pressure sensor is used to measure 0-500 PSI where the voltage reading are 1-5 volts.

  Polarity & Range Register = **0x00** (Polarity = **Unipolar** & Range = **10.0 V**)
  
  Floating Point Scale = **Range ** Scale Conversion* = **10 ** 125 = 1250*
  
  Floating Point Offset = **-125**
  

Note

Set Low Saturation Value to the equivalent of 1 volt and High Saturation Value to the equivalent to 5 volts

Threshold Detect Level Value			Threshold Detect Hysteresis Value (volts) (must be positive)
Level Value (volts)	Binary Value	Applying Floating Point Scale and Offset (mm)	Hysteresis (volts)	Binary Value	Applying Floating Point Scale and Offset (mm)
7.5	12582912/ 16777216 = 0.75 (0x00C0 0000/0x00FF FFFF)	(0.75 * 38.5) + 0 = 28.875 0x41E7 0000	0.25	419328/ 16777216= 0.025 (0x0006 6600/ 0x00FF FFFF)	(0.025 * 38.5) + 0 = 0.9625 0x3F76 666
-7.5	12582912/ 16777216 = -0.75 (0xFF40 0000/0x00FF FFFF)	(-0.75 * 38.5) + 0 = -28.875 0xC1E7 0000	0.15	251648/ 16777216 = 0.015 (0x0003 D700/ 0x00FF FFFF)	(0.015 * 38.5) + 0 = 0.5775 0x3F13 D70A

Saturation Programming

In Floating Point mode, the Low and High Saturation values should be entered in Single Precision Floating Point Value (IEEE-754) format.

For example:

• A signal of -10V to 10V indicate a displacement from -38.5mm to 38.5 mm respectively.

  Polarity & Range Register = **0x10** (Polarity = **Bipolar** & Range = **10.0 V**)
  
  Floating Point Scale = **Range ** Scale Conversion* = **10.0 ** 3.85 = 38.5*
  
  Floating Point Offset = **0.0**
  

Low Saturation Value			High Saturation Value
Level Value (volts)	Binary Value	Applying Floating Point Scale and Offset (mm)	Hysteresis (volts)	Binary Value	Applying Floating Point Scale and Offset (mm)
9.5	-7969280/ 8388608 = -0.95 (0xFF86 600/ 0x007F FFFF)	(-0.95 * 38.5) + 0 = -36.575 0xC212 4CCD	9.5	7969280/ 8388608 = 0.95 (0x0079 9A00/0x007F FFFF)	(0.95 * 38.5) + 0 = 36.575 0x4212 4CCD

• A pressure sensor is used to measure 0-500 PSI where the voltage reading are 1-5 volts.

  Polarity & Range Register = **0x00** (Polarity = **Unipolar** & Range = **10.0 V**)
  
  Floating Point Scale = **Range ** Scale Conversion* = **10 ** 125 = 1250*
  
  Floating Point Offset = **-125**
  

Note

Set Low Saturation Value to the equivalent of 1 volt and High Saturation Value to the equivalent to 5 volts.

Low Saturation Value			High Saturation Value
Level Value (volts)	Binary Value	Applying Floating Point Scale and Offset (mm)	Hysteresis (volts)	Binary Value	Applying Floating Point Scale and Offset (mm)
1.0	1677721/ 16777216 = 0.1 (0x0019 9999/ 0x00FF FFFF)	(0.1 * 1250) + (-125) = 0.0 0x0000 0000	5.0	8388608/ 16777216 = 0.5 (0x0008 0000/ 0x00FF FFFF)	(0.5 * 1250) + (-125) = 500.0 0x43FA 0000

MIL-STD-1553 Function

Principle of Operation

Through an IF2 combination module, the inboard MIL-STD-1553B communications function provides (1) channel of a dual-redundant MIL-STD1553B communication bus (FTA module-type). MIL-STD-1553 is a military standard that defines the characteristic for a Digital Time Division Command/Response Multiplexed Data Bus. The 1553 data bus is a dual-redundant, bi-directional, Manchester II encoded data bus with a high bit error reliability. It is used commonly for both military and civilian applications in avionics, aircraft, and spacecraft data handling.

The following table provides a summary of the MIL-STD-1553 characteristics.

Summary of MIL-STD-1553 Characteristics

Terminal Types	Bus Controller Remote Terminal Bus Monitor
Number of Remote Terminals	Maximum of 31
Transmission Technique	Half-duplex
Operation	Asynchronous
Encoding	Manchester II bi-phase level
Fault Tolerance	Typically, Dual Redundant Bus, which means there are two independent bus networks (one bus is called the Primary or “A” bus and the other is the Secondary or “B” bus). 1553 messages are usually only transmitted on either the A or B bus network at a time, but it does not usually matter which bus is used for the message transfer - devices on the 1553 network are supposed to handle messages on either the A or B bus with equal priority.
Coupling	Transformer
Data Rate	1 MHz
Word Length	20 bits
Data Bits/Word	16 bits
Message Length	Maximum of 32 Data Words
Protocol	Command/response
Message Formats	Bus Controller to Remote Terminal (BC-RT message) Remote Terminal to Bus Controller (RT-BC message) Remote Terminal to Remote Terminal (RT-RT message) Broadcast System control (Tx and Rx Mode codes)

The MIL-STD-1553 Data Bus is defined as a twisted shielded pair transmission line consisting of the main bus and several stubs. There is one stub for each remote terminal connected to the bus. The main bus is terminated at each end with a resistance equal to the cable’s characteristic impedance (± 2%). This termination makes the data bus behave electrically like an infinite transmission line. Stubs, which are added to the main bus to connect the terminals, provide “local” loads, and produce impedance mismatch where added. This mismatch, if not properly controlled, produces electrical reflections and degrades the performance of the main bus. The following table provides a summary of the MIL-STD-1553 Transmission Media characteristics.

Summary of MIL-STD-1553 Transmission Media Characteristics

Cable Type	Twisted Shielded Pair
Capacitance	30.0 pF/ft max, wire to wire
Characteristic Impedance	70.0 to 85.0 ohms at 1 MHz
Cable Attenuation	1.5 dB/100 ft. max, at 1 MHz
Cable Twists	4 Twists per ft., minimum
Shield Coverage	90% minimum
Cable Termination	Cable impedance (± 2%)
Direct Coupled Stub Length	Maximum of 1 foot
XFMR Coupled Stub Length	Maximum of 20 feet

Each 1553 channel on the FTA-FTF module employs a Sital Technology BRM1553D core, which is based on Sital’s proven 1553 IP cores, with DDC® Enhanced Mini-Ace® compatible interface. The core may operate in Bus Controller (BC), Remote Terminal (RT), Bus Monitor (BM) or RT/BM combined mode.

Bus Controller

The Bus Controller (BC) provides data flow control for all transmissions on the bus. In addition to initiating all data transfers, the BC must transmit, receive, and coordinate the transfer of information on the data bus. All information is communicated in command/response mode - the BC sends a command to the RTs, which reply with a response.

Remote Terminal

The Remote Terminal (RT) is a device designed to interface various subsystems with the 1553 data bus. The RT receives and decodes commands from the BC, detects any errors and reacts to those errors. The RT must be able to properly handle both protocol errors (missing data, extra words, etc.) and electrical errors (waveform distortion, rise time violations, etc.). RT characteristics include:

• Up to 31 Remote Terminals can be connected to the data bus
• Each Remote Terminal can have 31 Sub addresses
• No Remote Terminal shall speak unless spoken to first by the Bus Controller and specifically commanded to transmit.

Bus Monitor

The Bus Monitor (BM) listens to all messages on the data bus and records selected activities. The BM is a passive device that collects data for real-time or post capture analysis. The BM can store all or portions of traffic on the bus, including electrical and protocol errors. BMs are primarily used for instrumentation and data bus testing.

MIL-STD-1553 Protocol

MIL-STD-1553 data bus system consists of a Bus Controller (BC) controlling multiple Remote Terminals (RT) all connected by a data bus providing a single data path between the Bus Controller and all the associated Remote Terminals. There may also be one or more Bus Monitors (BM); however, Bus Monitors are specifically not allowed to take part in data transfers and are only used to capture or record data for analysis.

Message Formats

The following transactions are allowed between the BC and a specific RT:

1. BC to RT Transfer - The Bus Controller sends one 16-bit receive command word, immediately followed by 1 to 32 16-bit data words. The selected Remote Terminal then sends a single 16-bit Status word.
2. RT to BC Transfer - The Bus Controller sends one transmit command word to a Remote Terminal. The Remote Terminal then sends a single Status word, immediately followed by 1 to 32 data words.
3. Mode Command Without Data Word (Transmit) - The Bus Controller sends one command word with a Sub-address of 0 or 31 signifying a Mode Code type command. The Remote Terminal responds with a Status word.
4. Mode Command with Data Word (Transmit) - The Bus Controller sends one command word with a Sub-address of 0 or 31 signifying a Mode Code type command. The Remote Terminal responds with a Status word immediately followed by a single Data word.
5. Mode Command with Data Word (Receive) - The Bus Controller sends one command word with a Sub-address of 0 or 31 signifying a Mode Code type command immediately followed by a single data word. The Remote Terminal responds with a Status word.

The following transaction is allowed between the BC and a pair of RTs:

1. RT to RT Transfers - The Bus Controller sends out one receive command word immediately followed by one transmit command word. The transmitting Remote Terminal sends a Status word to the BC, immediately followed by 1 to 32 data words to the receiving RT. The receiving Terminal then sends its Status word to the BC.

The following are broadcast transactions that are allowed between the BC and all capable RTs:

1. BC to RT(s) Transfers - The Bus Controller sends one receive command word with a Terminal address of 31 signifying a broadcast type command, immediately followed by 0 to 32 data words. All Remote Terminals will accept the data but will not respond back to the BC.
2. RT to RT(s) Transfers - The Bus Controller sends out one receive command word with a Terminal address of 31 signifying a broadcast type command, immediately followed by one transmit command. The transmitting Remote Terminal sends a Status word immediately followed by 1 to 32 data words. All Remote Terminals will accept the data but will not respond back to the BC.
3. Mode Code without Data Word (Broadcast) - The Bus Controller sends one command word with a Terminal address of 31 signifying a broadcast type command and a sub-address of 0 or 31 signifying a Mode Code type command. No Remote Terminals will respond back to the BC.
4. Mode Code with Data Word (Broadcast) - The Bus Controller sends one command word with a Terminal address of 31 signifying a broadcast type command and a sub-address of 0 or 31 signifying a Mode Code type command, immediately followed by one Data word, if it is an Rx Mode code. No Remote Terminals will respond.

Message Components

The following are three components that make up the 1553 messages:

• Command Word
• Data Word
• Status Word

Each word type is 20 bits in length. The first 3 bits are used as a synchronization field, thereby allowing the decode clock to re-sync at the beginning of each new word. The next 16 bits are the information field. The last bit is the parity bit. Parity is based on odd parity for the single word.

Command Word

The Command Word specifies the function that the Remote Terminal is to perform.

The RT Address field states which unique remote terminal the command is intended for (no two terminals may have the same address). Note the address of 0x00 (00000b) is a valid address, and the address 0x1F (11111b) is always reserved as a broadcast address. The maximum number of terminals the data bus can support is 31.

The Transmit/Receive bit defines the direction of information flow and is always from the point of view of the Remote Terminal. A transmit command (logic 1) indicates that the Remote Terminal is to transmit data, while a receive command (logic 0) indicates that the Remote Terminal is going to receive data

The Sub-Address/Mode Code and Word Count/Mode Code fields are defined as follows:

Sub-Address/Mode Code and Word Count/Mode Code

Sub-Address/Mode Command Field	Word Count/Mode Code Field
0x00 (00000b) or 0x1F (11111b) indicates	Mode Code Command Mode Code number to be performed
0x01 (00001b) to 0x1E (11110b) indicates the Sub-Address 1 to Sub-Address 30	Word Count - note 0x00 (00000b) is decoded as 32 data words

Data Word

The Data Word contains the actual information that is being transferred within a message. Data Words can be transmitted by either a Remote Terminal (Transmit command) or a Bus Controller (Receive command).

Status Word

When the Remote Terminal receives a valid message, it will respond with a Status Word. The Status Word is used to convey to the Bus Controller whether a message was properly received or to convey the state of the Remote Terminal (i.e., service request, busy, etc.).

The RT Address in the Status Word should match the RT Address within the Command Word that the Remote Terminal received. With a RT-RT Transfer message, the RT address within either Status Word received (Rx or Tx), should match the RT address within the corresponding Command word sent (Rx or Tx).

Status Word

Status Bit	Description
Message Error (Bit 9)	This bit is set by the Remote Terminal upon detection of an error in the message or upon detection of an invalid message (i.e. Illegal Command). The error may occur in any of the Data Words within the message. When the terminal detects an error and sets this bit, none of the data received within the message is used.
Instrumentation (Bit 10)	This bit is always set to logic 0.
Service Request (Bit 11)	This bit is set to a logic 1 by the subsystem if servicing is needed. This bit is typically used when the Bus Controller is “polling” terminals to determine if they require processing.
Broadcast Command Received (Bit 15)	This bit indicates that the Remote Terminal received a valid broadcast command. On receiving a valid broadcast command, the Remote Terminal sets this bit to logic 1 and suppresses the transmission of its Status Word. The Bus Controller may issue a Transmit Status Word or Transmit Last Command Word Mode Code to determine if the Remote Terminal received the message properly.
Busy (Bit 16)	This bit indicates to the Bus Controller that the Remote Terminal is unable to move data between the Remote Terminal and the Sub-system in compliance to a command from the Bus Controller. In the earlier days of 1553, the Busy bit was required because many subsystem interfaces (analog, synchros, etc.) were much slower compared to the speed of the multiplex data bus. So instead of losing data, a terminal was able to set the Busy bit indicating to the Bus Controller to try again later. As new systems have been developed, the need for the busy bit has been reduced.
Subsystem Flag (Bit 17)	This bit provides “health” data regarding the subsystems to which the Remote Terminal is connected. Multiple subsystems may logically “OR” their bits together to form a composite health indicator.
Dynamic Bus Control Acceptance Bit (Bit 19)	This bit informs the Bus Controller that the Remote Terminal has received the Dynamic Bus Control Mode Code and has accepted control of the bus. The Remote Terminal, on transmitting its status word, becomes the Bus Controller. The Bus Controller, on receiving the status word from the Remote Terminal with this bit set, ceases to function as the Bus Controller and may become a Remote Terminal or Bus Monitor.
Terminal Flag (Bit 20)	This bit informs the Bus Controller of a fault or failure within the Remote Terminal. A logic 1 indicates a fault condition.

Assisted Mode (AM)

The FTA-FTF 1553 modules have been improved to include the “Assisted Mode (AM)” feature.

In the legacy FT1-FT6 modules, the 1553 messages are fetched from the 1553 device by accessing device registers directly from the host application as shown in Figure 13. The dotted lines indicate read/write access over the bus interface. The bus interface in some cases may be relatively “slow” (ex. Ethernet interface). In this design, four bus accesses are required from the host to fetch one new 1553 message. The number of accesses increases proportionately with the number of 1553 messages to fetch from the 1553 device.

Legacy FT1-FT6 Message Fetch Processing

The FTA-FTF 1553 modules utilize the secondary (ARM) processor built into the module that is dedicated for the purpose of “assisting” the movement of 1553 messages from the 1553 device to the host interface. This is made possible through a system of FIFOs that carry command and response messages to and from the host CPU to a bare metal application running on the secondary processor (refer to Diagram B in figure below). In addition, these modules have the option of funneling all 1553 messages (per channel) to a 4k byte Message FIFO (refer to Diagram A in the figure below) that is accessible from the host.

AM FIFO and Bus Access

In the next figure, the dotted lines indicate slower bus read/write accesses (PCI, Ethernet) whereas the solid lines indicate fast bus accesses. When the Message FIFO is utilized (Diagram A), the Message FIFO is filled as new 1553 messages arrive. Moving the 1553 messages from the Message FIFO to the Host Processor requires 2 “slower” bus accesses to fetch all the new 1553 messages that are in the Message FIFO.

If the Message FIFO is not utilized (Diagram B only), for example to fully support DDC API compatibility, 2 writes and at least 2 reads via the “slower” bus is required to fetch one new 1553 message. The write access to the Command FIFO initiates the transfer of 1553 messages from the device to the Response FIFO and when the transfer is complete, the host can read the Response FIFO. In DDC API compatibility mode, the benefits of the “assisted” design provide significantly improved response times compared to the legacy FT module(s), especially with bulk 1553 transfers.

Both the figure and table below depict the latent time (time required for 1553 message(s) transfer from 1553 device to host memory when initiated by the host CPU) as a function of the number of 1553 messages being transferred. The three candidates for comparison are (1) Assisted Module running in Message FIFO Mode, (2) Assisted Module running in Standard Mode and (3) the Non-Assisted (Legacy) FT Module.

AM Transfer Comparisons

Average and Worst-Case Latent Times in microseconds

1553 Msgs	Assisted Message FIFO		Assisted Standard		Non-Assisted
	Average	Worst-Case	Average	Worst-Case	Average	Worst-Case
1	163.630	182.445	1169.992	1193.958	695.578	705.235
12	239.0805	261.298	1698.532	1735.622	4286.303	5574.973
30	366.4155	399.722	3179.139	3198.554	9566.732	9610.468

The benefits of this approach include:

1. Reduced number of host CPU reads and writes to the device.
2. Reduced host memory footprint (less application memory required on the host).
3. Lower latency from 1553 bus to host memory.

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Assisted Mode Registers

The Assisted Mode registers are comprised of registers that support the AM Command and AM 1553 Message FIFOs.

AM Commands Registers

The registers associated with the AM Commands are divided into the following:

• Command FIFO Management (FIFO Buffer, FIFO Count, FIFO Update)
• Response FIFO Management (FIFO Buffer, FIFO Count)

The Command FIFO registers are used by the host to send commands to the AM processor to configure and operate the 1553 IP core. For every command sent from the host processor to the AM processor, the AM processor responds with a message that is sent to the host processor via the Response FIFO Buffer. The content of the response message will vary depending on the command and may contain configuration information, status information or 1553 data.

AM Command FIFO Buffer
Function:	Used to communicate with the 1553 core via the AM (secondary) processor.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	W
Initialized Value:	0
Operational Settings:	The host writes a command message to the AM Command FIFO Buffer and it is read out by the secondary processor. The secondary processor acts on the 1553 core based on the command that was read out. The AM processor will be unaware any new command messages in the AM Command FIFO Buffer until an update is performed by writing a 1 to the AM Command FIFO Update register.

AM Command FIFO Count
Function:	This register contains the value representing the number of 32-bit words that are currently loaded in the AM Command FIFO Buffer.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	When the host writes a command message to the AM Command FIFO Buffer, the value of the AM Command FIFO Count represents the number of 32-bit words contained in the command message. Once the message is fully read out by the AM processor, the AM Command FIFO Count goes to zero.

AM Command FIFO Update
Function:	This register is used to update the AM Command FIFO count as it is presented to the AM processor. The purpose of this register is to ensure that the AM Command FIFO Buffer does not present incomplete command messages to the AM processor.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0001
Read/Write:	W
Initialized Value:	0
Operational Settings:	The user should write a 1 to this register to update the AM Command FIFO count as it is seen from the AM processor. The proper way to handle sending commands to the AM processor is to write a full command message to the AM Command FIFO Buffer, then update the count by writing a 1 to the AM Command FIFO Update register.

AM Response FIFO Buffer
Function:	Used by the AM (secondary) processor to send response messages to the host.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	After the host writes a valid command message to the AM Command FIFO Buffer and it is read out by the AM processor, the AM processor acts on the 1553 core based on the command type. Once the action is completed, the AM processor sends a response to the host processor via the AM Response FIFO Buffer.

AM Response FIFO Count
Function:	This register contains the value that represents the number of 32-bit words that are present in the AM Response FIFO Buffer.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	When a command is sent from the host to the AM processor and it completes the commanded task, it loads the AM Response FIFO with a response message and the AM Response FIFO Count is updated with the number of 32-bit words that are contained in the response message. Once the host reads out the full response message from the AM Response FIFO Buffer, the AM Response FIFO Count will read zero.

AM 1553 Message FIFO Registers

The Message FIFO Management registers consists of the FIFO Buffer, FIFO Count, FIFO Clear command, and the FIFO Threshold which specify threshold associated with for the “1553 Message FIFO Almost Full” status bits in the Channel Status register.

AM 1553 Message FIFO Buffer
Function:	When the channel is operating in Message FIFO mode, 1553 messages are stored in the 1553 Message FIFO Buffer.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	When the channel is configured for Message FIFO mode, new 1553 messages (comprising 1553 data words, 1553 status words, timestamp and message status information) are stored in the 1553 Message FIFO Buffer and the host can perform a block read on this register to read out a chain of 1553 messages in a single transaction. The number of 32-bit words to read out of the 1553 Message FIFO Buffer is reported in the 1553 Message FIFO Count register. Refer to Appendix - 1553 Receive Message FIFO Format to decode the single 1553 message or a chain of 1553 messages read from this buffer.

AM 1553 Message FIFO Count
Function:	While the channel is operating in Message FIFO mode, the number of 32-bit words in the 1553 Message FIFO Buffer is reported in this register.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	When the channel is configured for Message FIFO mode, new 1553 messages (comprising 1553 data words, 1553 status words, timestamp, and message status information) are stored in the 1553 Message FIFO Buffer. The 32-bit count of a 1553 message can vary depending on the 1553 message type and 1553 data payload size. This register provides the count of 32-bit words that are currently present in the 1553 Message FIFO Buffer instead of providing the count of 1553 messages. When retrieving data from the 1553 Message FIFO Buffer, use the 1553 Message FIFO Count to obtain all 1553 messages and refer to Appendix - 1553 Receive Message FIFO Format to decode 1553 messages.

AM 1553 Message FIFO Clear
Function:	When the channel is operating in Message FIFO mode, this register is used to clear the 1553 Message FIFO Buffer.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	W
Initialized Value:	0
Operational Settings:	Write a 1 to this register to clear the 1553 Message FIFO Buffer. Once the buffer is cleared, the 1553 Message FIFO Count register should read zero.

AM 1553 Message FIFO Threshold
Function:	Set the “1553 Message FIFO Almost Full” status threshold value.
Type:	unsigned binary word (32-bit)
Data Range:	1 to 1002
Read/Write:	R/W
Initialized Value:	512
Operational Settings:	This register sets the “1553 Message FIFO Almost Full” threshold such that when the number of 32-bit words reach or surpass the threshold value, the 1553 Message FIFO Almost Full status bit will report a 1. If interrupts are enabled for this status bit, an interrupt will be generated when the number of 32-bit words reach or surpass the threshold value.

Auxiliary Registers

Reset
Function:	A write to this register causes a reset of the channel/core.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0001
Read/Write:	W (Reset)
Initialized Value:	0
Operational Settings:	Reset - Write a 1 to reset the core.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

RT Address from Backplane
Function:	Provides the Remote Terminal address and the parity.
Type:	unsigned binary word (32-bit)
Data Range:	See table
Read/Write:	R
Initialized Value:	0
Operational Settings:	The RT values are set at the backplane and read from this register.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	D	D	D	D	D	D

Bit	Description
D31:D6	Reserved
D5	RT Parity Bit: 1=Even Parity, 0=Odd Parity
D4:D0	RT Address of the channel.

Miscellaneous Bits
Function:	Provides various control and configuration functions as well as status.
Type:	unsigned binary word (32-bit)
Data Range:	See table
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Refer to table for definitions.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Bit	Description
D31:D16	Reserved
D15	If set, overrides external BC_DISABLE (Bus Controller Mode) with the value from bit 14
D14	BC_DISABLE override value
D13	If set, overrides external M1760 hardware input (Standard) with the value from bit 12
D12	M1760 override value
D11	Reserved
D10	Mode value from backplane (Read Only)
D9	Standard value from backplane (Read Only) Default
D8	Terminate RS-422: 0=No termination, 1=termination
D7	Transceiver Type: 0=Sital, 1=COTS (Read Only)
D6	BC_DISABLE setting at the core (Read Only)
D5	SSFLAG: RT Mode Only - Sets the Sub System flag (bit 2) high in the status word
D4	RTAD_SW_EN: ` 0=No software change of RT address available ` 1=Enables software change of RT Address by configuration reg #6
D3	RT_ADR_LAT: ` 0=RT Address and parity are used as-is, Rising edge=Last RT Address and parity are sampled and stored in the core. Changes to the values are ignored ` 1=RT Address and parity can be latched by writing to configuration reg #5
D2	M1760 Setting at the core (Read Only)
D1	Tx_inhB: ` 0=Enable core transmission on bus B ` 1=inhibit core transmission on bus B
D0	Tx_inhA: ` 0=Enable core transmission on bus A ` 1=inhibit core transmission on bus A

Status and Interrupt Registers

The registers may be set for any or all channels and will latch if a transition is detected on a channel or channels. Each channel(s) will remain latched until the channel is cleared. Multiple channels may be cleared simultaneously, if desired. Each channel bit in the register is polled for a read status. Any subsequent channel(s) transition, if detected, will propagate through to be read (rolling-latch).

Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel) location (bit mapped per channel), will “clear” the bit (set the bit to 0) if the actual interruptible event condition has cleared. If the interruptible condition “event” is still persistent while clearing, this may retrigger the interrupt.

There is a corresponding Interrupt Enable and vector associated with each “Latched” Status. Each status type may be “polled” (at any time) or is “interruptible” when interrupts are enabled and the associated Interrupt Service Routine (ISR) vectors are programmed accordingly. When programmed for “interruptible” status, interrupts are typically generated and flagged with the programmed vector available as data. The host or single board computer (SBC) typically services the interrupt by a general or specific ISR, which reads the (typically) unique programmed vector (identifier of which status generated the interrupt), reads the associated status register to determine which channel in the status register was “flagged” and then “clears” the status register. This essentially resets the interrupt mechanism, which is now ready to be triggered by the next status register detected event “flag”. “Latched Status” will trigger on either “sense on edge” or “sense on level” based on the settings of the associated Set Edge/Level Interrupt register. Sense on “edge” requires a change from low to high state to trigger the status detection, while sense on “level” is independent of the previous state. Unless otherwise specified, all status or fault indications are bit set per channel.

Channel Status

There are four registers associated with the Channel Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Use this register to read current or real-time status.

Channel Status
Function:	Sets the corresponding bit associated with the event type. There are separate registers for each channel.
Type:	unsigned binary word (32-bit)
Range:	0 to 0x0000 0001
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	N/A

Channel Dynamic Status
Channel Latched Status
Channel Interrupt Enable
Channel Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Bit	Description	Notes
D0	1553 Core Interrupt	An interrupt has been signaled from the 1553 core. The specific interrupt signaling event(s) can be identified by reading the core status registers.
D31:D1	Reserved

Summary Status

There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Summary Status
Function:	Sets the corresponding bit if any fault occurs on that channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0001
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Summary Status Dynamic Status
Summary Status Latched Status
Summary Status Interrupt Enable
Summary Status Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Ch1

Function Register Map

KEY

Configuration/Control

Measurement/Status

MODULE COMMON REGISTERS
Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.
AM COMMANDS REGISTERS
NOTE: Base Address - 0x9000 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x10B0	AM Command FIFO Buffer Ch 1	W	0x10B4	AM Command FIFO Count Ch 1	R
0x10B8	AM Command FIFO Update Ch 1	W
0x10C0	AM Response FIFO Buffer Ch 1	R	0x10C4	AM Response FIFO Count Ch 1	R
AM 1553 MESSAGE FIFO REGISTERS
NOTE: Base Address - 0x9000 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x10D0	AM 1553 Message FIFO Buffer Ch 1	R	0x10D4	AM Message FIFO Count Ch 1	R
0x10D8	AM Message FIFO Clear Ch 1	W	0x10DC	AM Message FIFO Threshold Ch 1	R/W
AUXILIARY REGISTERS
NOTE: Base Address - 0x9000 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1080	RT Address from Backplane Ch 1	R	0x1080	Reset Ch 1	W
0x1084	Miscellaneous Bits Ch 1	R/W
1553 CHANNEL STATUS REGISTER
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0”).
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0810	Channel Dynamic Status Ch 1	R
0x0814	Channel Latched Status Ch 1*	R/W
0x0818	Channel Interrupt Enable Ch 1	R/W
0x081C	Channel Set Edge/Level Interrupt Ch 1	R/W
1553 SUMMARY STATUS REGISTER
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0”).
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0820	Summary Dynamic Status Ch 1	R
0x0824	Summary Latched Status Ch 1*	R/W
0x0828	Summary Interrupt Enable Ch 1	R/W
0x082C	Summary Set Edge/Level Interrupt Ch 1	R/W

ARINC 429/575 Function

Principle of Operation

Through an IF2 combination module, the inboard ARINC 429/575 communications function provides up to 4 programmable ARINC-429 channels (AR1 module-type). Each channel is software selectable for transmit and/or receive, high or low speed, and odd or no parity. Therefore, AR1 can support multiple ARINC 429 and 575 channels simultaneously.

Receive Operation

Serial BRZ data is decoded for logic states: one, zero or null. Once Word Gap is detected (4 null states) the receiver waits for either a zero or one state to start the serial-to-parallel shift function. If a waveform timing fault is detected before the serial/parallel function is complete, operation is terminated, and the receiver returns to waiting for Word Gap detection. The serial-to-parallel output data is validated for odd parity, Label and Serial-to-Digital Interface (SDI).

If message validation (filtering) is enabled, the module compares the SDI/Label of incoming ARINC messages to a list of desired SDI/Labels in validation (match) memory and only stores messages with an SDI/Label in the list. The message is stored in the receive FIFO or mailbox, depending if the channel is in FIFO receive mode or mailbox receive mode. In FIFO Receive Mode, received ARINC messages / words are stored with an associated status word and an optional time-stamp value in the channel’s receive FIFO. Additionally, the Rx FIFO can be set for either bounded or circular mode, which determines FIFO behavior when it is full. In bounded mode, newly received ARINC messages are discarded if the FIFO is full whereas in circular mode, new ARINC messages overwrite the oldest messages in the FIFO. In mailbox mode, received ARINC words are stored in mailboxes or records in RAM that are indexed by the SDI/Label of the ARINC word. Each mailbox contains a status word associated with the message, the ARINC message / word, and an optional 32-bit timestamp value. The status word indicates parity error and new message status.

Transmit Operation

Transmitters are tri-stated when TX is not enabled. Transmit operates in one of three modes: Immediate FIFO, Triggered FIFO, and Scheduled. In immediate mode, ARINC data is sent as soon as data is written to the transmit FIFO. In Triggered FIFO mode, a write to the Transmit Trigger register is needed to start transmission of the transmit FIFO contents. Transmission continues until the FIFO is empty. To transmit more data after the FIFO empties out, issue a new trigger after filling the transmit FIFO with new data.

For either FIFO mode, a transmit FIFO Rate register is provided to control rate of transmission. The contents of this register specify the gap time between transmitted words from the FIFO. The default is the minimum ARINC gap time of 4-bit times.

Schedule mode transmits ARINC data words according to a prebuilt schedule table in Transmit Schedule RAM. In the Schedule table, various commands define what messages are sent and the duration of gaps between each message. Note that a Gap (Gap or Fixed Gap) command must be explicitly added in between each Message command otherwise a gap will not be inserted between messages. The ARINC data words and gap times are stored in the Transmit Message RAM and can be updated on the fly as the schedule executes. A write to the Transmit Trigger register initiates the schedule and commands are executed starting from the first command (address 0x0) in the Schedule RAM. While a schedule is running, an ARINC word can be transmitted asynchronously by writing the async data word to the Async Transmit Data register. After it has transmitted, the Async Data Available bit will be cleared from the Channel Status register and the Async Data Sent Interrupt will be set if enabled. The Async Data Available bit in Channel Status also gets cleared by a Stop Cmd in a schedule or if a Transmit Stop command is issued from the Transmit Stop register. Use the Fixed Gap command instead of the Gap command to disable async transmissions during the schedule gap time. Gap and Fixed Gap commands can both be used when building the transmit schedule.

Schedule Transmit Commands

ARINC 429/575 scheduling is controlled by commands that are written to the Transmit Schedule RAM. The available commands are:

Schedule Transit Command

Command Name	Description
Message	This command takes a parameter that specifies the location in Transmit Message memory containing the ARINC data word to be sent. The word is transmitted when the Message command is executed. This ARINC word can be modified in Tx Message memory while the schedule is running.
Gap	This command takes a parameter that specifies the location in Transmit Message memory containing a 20-bit gap time value. Values less than 4 are invalid. If the previous command was a Message, then that message is transmitted and then the transmitter waits out the specified gap time transmitting nulls. An exception to this is if there is an async data word available. If the gap time is greater or equal to 40-bit times (4-bit gap time plus one ARINC word plus another 4-bit gap time) an async data word, if available, will be transmitted during this time. If a new async data word is made available and the remaining gap time is large enough to accommodate another async data word transmission, then the new async data word will be transmitted after a 4-bit gap time. Multiple async data word transmissions can thus occur if the remaining gap time is large enough to accommodate a message and the required minimum 4-bit gap time. Otherwise, the transmitter waits out the remaining gap time before executing the next command.
Fixed Gap	This command takes a parameter that specifies the location in Transmit Message memory containing a 20-bit gap time value. Values less than 4 are invalid. If the previous command was a Message, then that message is transmitted with the specified gap time appended. If the previous command was not a Message, then the transmitter waits for the specified gap time before executing the next command. The difference between the Fixed Gap and Gap command is that Fixed Gap will prevent the transmission of async data words during the gap time. Use Fixed Gap to only allow nulls to be transmitted during the gap time.
Pause	This command causes the transmitter to pause execution of the schedule after transmitting the current word. Either a Transmit Trigger command is issued to resume execution, or a Transmit Stop command is issued to halt execution.
Interrupt	This command causes the Schedule Interrupt to be set if Schedule Interrupt is enabled. An unlatched version of this flag is also visible in the channel status register.
Jump	Jumps to the 9-bit address in Schedule memory pointed to by this command and resumes execution there.
Stop	This command causes the transmitter to stop execution of the schedule after transmitting the current word.

ARINC 429/575 Built-in Test

The AR1 module supports three types of built-in tests: Power-On, Continuous Background and Initiated. The results of these tests are logically ORed together and stored in the BIT Dynamic Status and BIT Latched Status registers.

Power-On Self-Test (POST) / Power-on BIT (PBIT) / Start-up BIT(SBIT)

The power-on self-test is performed on each channel automatically when power is applied and reports the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.

Continuous Background Built-In Test

The background Built-In-Test or Continuous BIT (CBIT) runs in the background for each enabled channel. In Transmit operations, internal transmit data is compared to loop-back data received by the ARINC receivers. When the channel is configured for Receive operation, receive data is continuously monitored via a secondary parallel path circuit and compared to the primary input receive data. If the data does not match, the technique used by the automatic background BIT test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state. Results of the Continuous BIT are stored in the BIT Dynamic Status and BIT Latched Status register.

Initiated Built-In Test

The Initiated Built-In-Test (IBIT) is an internal loopback available for each channel of the AR1 module. The test is initiated by setting the bit for the associated channel in the Test Enabled register to a 1. Once enabled, they must wait at least 3 msec before checking to see if the bit for the associated channel in the Test Enabled register reads a 0. When the AR1 clears the bit, it means that the test has completed, and its results can be checked. The results of the IBIT is stored in the BIT Dynamic Status and BIT Latched Status registers, a 0 indicates that the channel has passed and a 1 indicates that it failed.

Loop-Back Operation

Transmit and receive operation of an AR1 channel can be verified internally by enabling both Tx and Rx on the same channel. Tx Scheduling is not supported when the channel is placed in this mode.

Transient Protection

The module is normally configured for transient protection but can be specified without if protection is implemented externally.

Status and Interrupts

The AR1 Module provide registers that indicate faults or events. Refer to ‘Appendix B: Status and Interrupts’ for the Principle of Operation description.

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Receive Registers

The registers listed are associated with data that is received on the AR1 channels. Two modes of message storage are supported: Receive FIFO and Receive Mailbox.

Receive FIFO Mode Registers

The Receive FIFO Mode Registers contain information about ARINC messages that are received via the Receive FIFO buffer on the AR1 channel. The registers associated with this feature are:

• Receive FIFO Message Buffer
• Receive FIFO Message Count
• Receive FIFO Almost Full Threshold
• Receive FIFO Size

Receive FIFO Message Buffer
Function:	In FIFO receive mode, the received ARINC messages are stored in this buffer.
Type:	unsigned binary word (32-bit)
Range:	0 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	NA
Operational Settings:	Perform two reads from this register to retrieve the Status word and the ARINC data word, respectively. If Time Stamping is enabled, perform one more read to retrieve the timestamp.

Message Status Word

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

N

PE

Data Word

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

*Timestamp Word (if enabled)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

PE = Parity Error 1 Calculated parity does not match the received parity bit
N = New message 1 Message has not been read yet

Receive FIFO Message Count
Function:	Contains the number of ARINC messages in the receive FIFO in Receive FIFO mode.
Type:	unsigned binary word (32-bit)
Range:	0 to 255 (0x00FF)
Read/Write:	R
Initialized Value:	0
Operational Settings:	A received message consists of the message status word and the ARINC data word. If time stamping is enabled, a 32-bit timestamp is also included in the message. For example, if this register reads 1, indicating one message is loaded in the receive FIFO, perform two reads from the Receive FIFO Message Buffer register to retrieve the full message (status word and ARINC data word) if time stamping is disabled or perform three reads from the Receive FIFO Message Buffer register to retrieve the full message (status word, ARINC data word and timestamp word) if time stamping is enabled.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D

Receive FIFO Almost Full Threshold
Function:	Specifies the level of the receive FIFO buffer, equal or above, at which the Rx FIFO Almost Full Status bit D1 in the Channel Status register, is flagged (High True).
Type:	unsigned binary word (32-bit)
Range:	0 to 255 (0x00FF)
Read/Write:	R/W
Initialized Value:	128 (0x0080)
Operational Settings:	If the Interrupt Enable register interrupt is enabled, a SYSTEM interrupt will be generated when the receive FIFO level increases and reaches the threshold level. This register does NOT get reset by a channel reset.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D

Receive FIFO Size
Function:	Specifies the size of the Rx FIFO buffer. The default size is 255 messages.
Type:	unsigned binary word (32-bit)
Range:	1 to 255 (0x00FF)
Read/Write:	R/W
Initialized Value:	255 (0x00FF)
Operational Settings:	This setting affects the Rx FIFO size when the Rx FIFO is configured in either Rx FIFO Bounded or Circular mode.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D

Receive Mailbox Mode Registers

The Receive Mailbox Mode Registers contain information about ARINC messages that are received via mailboxes on the AR1 channel. The registers associated with this feature are:

• Receive FIFO SDI/Label Buffer
• Receive FIFO SDI/Label Count
• Receive FIFO Almost Full Threshold
• Receive FIFO Size
• Mailbox Status Data
• Mailbox Message Data
• Mailbox Timestamp Data

Receive FIFO SDI/Label Buffer
Function:	In Mailbox receive mode, SDI/Label of received messages are stored in this buffer.
Type:	unsigned binary word (32-bit)
Range:	0 to 0x0000 03FF
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	In Mailbox receive mode, this FIFO contains the 10-bit SDI/Label of newly received messages. This provides a list to the user showing which mailboxes contain new messages since the last time this FIFO was read.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	A10	A9	A8	A7	A6	A5	A4	A3	A2	A1

A8-A1 = Label (A8 is MSB and A1 is LSB)
A10-A9 = SDI

Receive FIFO SDI/Label Count
Function:	Contains the number of newly received SDI/Labels in the receive FIFO in Receive Mailbox mode.
Type:	unsigned binary word (32-bit)
Range:	0 to 255 (0x00FF)
Read/Write:	R
Initialized Value:	0
Operational Settings:	In Mailbox receive mode, this register contains the number of newly received SDI/Labels in the receive FIFO. The user may perform this number of reads on the Receive FIFO SDI/Label Buffer register to retrieve all SDI/Labels.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D

Receive FIFO Almost Full Threshold
Function:	Specifies the level of the receive FIFO buffer, equal or above, at which the Rx FIFO Almost Full Status bit D1 in the Channel Status register, is flagged (High True).
Type:	unsigned binary word (32-bit)
Range:	0 to 255 (0x00FF)
Read/Write:	R/W
Initialized Value:	128 (0x0080)
Operational Settings:	If the Interrupt Enable register interrupt is enabled, a SYSTEM interrupt will be generated when the receive FIFO level increases and reaches the threshold level. This register does NOT get reset by a channel reset.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D

Receive FIFO Size
Function:	Specifies the size of the Rx FIFO buffer. The default size is 255 SDI/Labels.
Type:	unsigned binary word (32-bit)
Range:	1 to 255 (0x00FF)
Read/Write:	R/W
Initialized Value:	255 (0x00FF)
Operational Settings:	This setting affects the Rx FIFO size when the Rx FIFO is configured in either Rx FIFO Bounded or Circular mode.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D

Mailbox Status Data
Function:	Stores ARINC Status data word.
Type:	unsigned binary word (32-bit)
Range:	0 to 0x0000 0003
Read/Write:	R
Initialized Value:	0
Operational Settings:	This is a 32-bit value that contains status information associated with the received ARINC word. D1 of 1 indicates that the received ARINC word is a new message. D0 of 1 indicates a parity error is present in the ARINC message. There are 1024 Mailbox Status Data registers, one for each SDI/Label. The user can determine which Mailbox Status Data registers contain new data based on newly received SDI/Labels in the receive FIFO.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	N	PE

PE = Parity Error 1 Calculated parity does not match the received parity bit
N = New message 1 This is a new ARINC message

Mailbox Message Data
Function:	Stores ARINC Message data word.
Type:	unsigned binary word (32-bit)
Range:	0 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	This is the 32-bit ARINC data word. There are 1024 Mailbox Message Data registers, one for each SDI/Label. The user can determine which Mailbox Message Data registers contain new data based on newly received SDI/Labels in the receive FIFO.

Mailbox Timestamp Data
Function:	Stores ARINC Timestamp data word.
Type:	unsigned binary word (32-bit)
Range:	0 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	This is the 32-bit timestamp associated with the received ARINC word. There are 1024 Mailbox Timestamp Data registers, one for each SDI/Label. The user can determine which Mailbox Timestamp Data registers contain new data based on newly received SDI/Labels in the receive FIFO.

Timestamp Registers

Timestamp Control
Function:	Determines the resolution of the timestamp counter.
Type:	unsigned binary word (32-bit)
Range:	0 to 0x0000 0007
Read/Write:	R/W
Initialized Value:	0 (1 µsec)
Operational Settings:	The LSB can have one of four time values. Set bit D2 to zero out the timestamp counter.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	Z	D	D

Timestamp Control Register
Bit(s)	Name	Description
D31:D3	Reserved	Set Reserved bits to 0.
D2	Zero Timestamp	Set the bit to zero out the timestamp counter
D1:D0	Resolution (R/W)	The following sets the Resolution: (0:0) 1 µs ` (0:1) 10 µs ` (1:0) 100 µs + (1:1) 1 ms

Timestamp Value
Function:	Reads the current 32-bit timestamp.
Type:	unsigned binary word (32-bit)
Range:	0 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	The time value of each LSB is determined by the resolution set in the Timestamp Control register.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Message Validation Registers

If message validation (filtering) is enabled, the module compares the SDI/Label of incoming ARINC messages to a list of desired SDI/Labels in validation (match) memory and only stores messages with an SDI/Label in the list.

Match Enable
Function:	Enables or disables reception of ARINC words containing the associated SDI/Label.
Type:	unsigned binary word (32-bit)
Range:	0 to 1
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	D0 set to 1 enables reception of ARINC words containing the SDI/Label that is associated with this register. This register only takes effect if the MATCH ENABLE bit is set to 1 in the Channel Control Register. There are 1024 Match Enable Data Registers, and each register is indexed by the SDI/Label. Note that bit D1 is a reserved bit, and it is fixed to 1.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	D

Transmit Registers

The registers listed are associated with data that is to be transmitted from the AR1 channels. Two modes of message storage are supported: Transmit FIFO and Transmit Scheduling.

Transmit FIFO Registers

The Transmit FIFO Mode Registers contain information about ARINC messages that are to be transmitted via the Transmit FIFO buffer on the AR1 channel. The registers associated with this feature are:

• Transmit FIFO Message Buffer
• Transmit FIFO Message Count
• Transmit FIFO Almost Empty Threshold
• Transmit FIFO Rate

Transmit FIFO Message Buffer
Function:	In immediate or triggered FIFO modes, ARINC messages are placed here prior to transmission.
Type:	unsigned binary word (32-bit)
Range:	0 to 0xFFFF FFFF
Read/Write:	W
Initialized Value:	0
Operational Settings:	ARINC data words are 32-bits. This memory is shared with the Tx Message memory and is only available in Tx FIFO modes.

Transmit FIFO Message Count
Function:	Contains the number of ARINC 32-bit words in the transmit FIFO.
Type:	unsigned binary word (32-bit)
Range:	0 to 255 (0x00FF)
Read/Write:	R
Initialized Value:	0
Operational Settings:	Used only in the FIFO transmit modes.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D

Transmit FIFO Almost Empty Threshold
Function:	Specifies the level of the transmit buffer, equal or below, at which the Tx FIFO Almost Empty Status bit D5 in the Channel Status register, is flagged (High True).
Type:	unsigned binary word (32-bit)
Range:	0 to 255 (0x00FF)
Read/Write:	R/W
Initialized Value:	32 decimal (0x0020)
Operational Settings:	If the Interrupt Enable register interrupt is enabled, a SYSTEM interrupt will be generated when the receive FIFO level increases and reaches the threshold level. This register does NOT get reset by a channel reset.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D

Transmit FIFO Rate
Function:	Determines the Gap time between transmitted ARINC messages in FIFO transmit modes.
Type:	unsigned binary word (32-bit)
Range:	0-0x000F FFFF
Read/Write:	R/W
Initialized Value:	4
Mode:	FIFO
Operational Settings:	Each LSB is 1-bit time. Rates less than 4 are not valid. This register does NOT get reset by a channel reset.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Transmit Scheduling Registers

The Transmit Scheduling Registers are utilized when the channel is set up to run a Transmit Schedule. The memories/registers associated with this feature are:

• Transmit Schedule RAM
• Transmit Message RAM
• Async Transmit Data Register

Transmit Schedule RAM Command Format
Function:	The Transmit Schedule RAM consists of 256 32-bit words that are used to set up a self-running transmit schedule. These are the valid command formats for the Transmit Schedule RAM.
Type:	unsigned binary word (32-bit)
Range:	0 to 0x0000 FFFF
Read/Write:	R/W
Initialized Value:	N/A
Operational Settings:	Only bits 0 to 15 are utilized for schedule commands. Bits 12 to 15 specify the command type and bits 0 to 7 or 8 specify the command parameter. Only the Message, Gap, Fixed Gap and Jump commands utilize a command parameter. When the schedule starts, commands are executed sequentially starting from schedule RAM address 0x0.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16	FUNCTION
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0	FUNCTION
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	STOP CMD
0	0	0	1	0	0	0	0	MA7	MA6	MA5	MA4	MA3	MA2	MA1	MA0	MESSAGE CMD
0	0	1	0	0	0	0	0	MA7	MA6	MA5	MA4	MA3	MA2	MA1	MA0	GAP CMD
0	0	1	1	0	0	0	0	MA7	MA6	MA5	MA4	MA3	MA2	MA1	MA0	FIXED GAP CMD
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	PAUSE CMD
0	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	SCH INTERRUPT CMD
0	1	1	0	0	0	0	SA8	SA7	SA6	SA5	SA4	SA3	SA2	SA1	SA0	JUMP CMD
0	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	RESERVED
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	RESERVED

1. **MA7-MA0** = Address of Tx Message memory organized as 256x32. 2. **SA8-SA0** = Address of next command in Tx Schedule memory organized as 256x32.

Transmit Message RAM Data Format
Function:	The Transmit Message RAM consists of 256 32-bit words that are used by the transmit schedule for ARINC message and gap time word storage.
Type:	unsigned binary word (32-bit)
Range:	0 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	N/A
Operational Settings:	Words that are stored in Transmit Message RAM are utilized by Message, Gap, and Fixed Gap commands in the Transmit Schedule. In the case of Message commands, the command parameter specifies an address in Transmit Message RAM that contains the 32-bit ARINC message to transmit. In the case of Gap or Fixed Gap commands, the command parameter specifies an address in Transmit Message RAM that contains the gap time value.

Async Transmit Data
Function:	This memory location is the transmit async buffer.
Type:	unsigned binary word (32-bit)
Range:	0 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	While a schedule is running, a single 32-bit ARINC message that is intended to be transmitted asynchronously must be written to this register. When an async data word is written to this register, the Async Data Available status bit will get set until the async data word is transmitted. If a gap (not fixed gap) time is greater or equal to 40 bit times (4-bit gap time plus one ARINC word plus another 4-bit gap time) the async data word, if available, will be transmitted during this time.

Transmit Control Registers

Control of the transmission of ARINC messages includes the ability to start/resume, pause and stop the transmission of the message.

Transmit Trigger
Function:	Sends a trigger command to the transmitter and is used to start transmission in Triggered FIFO or Scheduled Transmit modes.
Type:	unsigned binary word (32-bit)
Range:	0 to 0x0000 000F
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set bit to 1 for the channel to resume transmission after a scheduled pause or Transmit pause command.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Transmit Pause
Function:	Sends a command to pause the transmitter after the current word and gap time has finished transmitting.
Type:	unsigned binary word (32-bit)
Range:	0 to 0x0000 000F
Read/Write:	R/W
Initialized Value:	0
Modes Affected:	Triggered FIFO and Schedule Transmit
Operational Settings:	Set bit to 1 for the channel to pause transmission in Triggered FIFO or Scheduled Transmit modes. Issue a Transmit Trigger command to resume transmission or issue a Transmit Stop command to halt transmission.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Transmit Stop
Function:	Sends a command to stop the transmitter after the current word and gap time has been transmitted.
Type:	unsigned binary word (32-bit)
Range:	0 to 0x0000 000F
Read/Write:	R/W
Initialized Value:	0
Modes Affected:	All Transmit modes
Operational Settings:	Set bit to 1 for the channel to stop transmission.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Control Registers

The AR1 control registers provide the ability to reset all the channels in the AR1 module and configuring and controlling individual AR1 channels

Channel Control
Function:	Used to configure and control the channels.
Type:	unsigned binary word (32-bit)
Range:	See table
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	When writing to this register, the configuration bits must be maintained when setting the control bits.

Bit(s)	CONTROL FUNCTIONS	Description
D31:D22	RESERVED	Set RESERVED bits to 0.
D21	SCHEDULE INTERRUPT CLEAR	When the SCHEDULE INTERRUPT CLEAR bit is set to 1 by the user, the Schedule Interrupt bit (D10) in the Channel Status register can be cleared.
D20	RESERVED	Set RESERVED bits to 0.
D19	CHANNEL RESET	When the CHANNEL RESET bit is set to 1 by the user, the channel is held in reset until the user sets the bit to 0. The channel reset causes Tx and Rx FIFO buffers to clear out, but channel configuration settings remain unchanged.
D18	MATCH MEMORY CLEAR	When the MATCH MEMORY CLEAR bit is set to 1 by the user and if MATCH ENABLE bit is set to 1, all 1024 SDI/Labels will be disabled in Rx Match Memory, which means all received ARINC messages will be filtered out and discarded. This is a self-clearing bit. After setting the bit, allow 100 us to complete.
D17	RECEIVE FIFO CLEAR	When the RECEIVE FIFO CLEAR bit is set to 1 then set to 0 by the user, the Rx FIFO buffer is cleared out and the Rx FIFO count goes to zero.
D16	TRANSMIT FIFO CLEAR	When the TRANSMIT FIFO CLEAR bit is set to 1 then set to 0 by the user, the Tx FIFO buffer is cleared out and the Tx FIFO count goes to zero.
Bit(s)	CONFIGURATION FUNCTIONS	Description/Values
D15:D11	RESERVED	Set RESERVED bits to 0.
D10	STORE ON ERROR DISABLE	If the STORE ON ERROR DISABLE bit is cleared (0) and odd parity is enabled, received words that contain a parity error will be stored in the receive buffer or mailbox. When the STORE ON ERROR DISABLE bit is set (1) and odd parity is enabled, received words that contain a parity error will NOT be stored in the receive buffer or mailbox.
D9	RESERVED	Set RESERVED bit to 0.
D8	TIMESTAMP ENABLE	When TIMESTAMP ENABLE bit is set to 1, the receiver will store a 32-bit time stamp value along with the received ARINC word. There is one-time stamp counter per module and it is used across all 12 channels. It has 4 selectable resolutions and can be reset via the Time Stamp Control register. It is recommended to clear the Receive FIFOs whenever the Receive mode or Time Stamp Enable mode is changed to ensure that extraneous data is not leftover from a previous receive operation.
D7	MATCH ENABLE	When the MATCH ENABLE bit is set to 1, the receiver will only store ARINC words which match the SDI/Labels enabled in Rx Match memory.
D6	PARITY DISABLE	The PARITY DISABLE bit when set to 0, causes ARINC bit 32 to be treated as an odd parity bit. The transmitter calculates the ARINC odd parity bit and transmits it as bit 32. The receiver will check the received ARINC word for odd parity and will flag an error if is not. When the PARITY DISABLE bit is set to 1, parity generation and checking will be disabled, and both the transmitter and receiver will treat ARINC bit 32 as data and pass it on unchanged.
D5	HIGH SPEED	The HIGH SPEED bit is used to select the data rate. 12.5 kHz = 0 + 100 kHz = 1
D4:D3	TRANSMIT MODE	The TRANSMIT MODE bits are used to select the Transmit Mode. (0:0) = Immediate FIFO mode ` (0:1) = Schedule mode ` (1:0) = Triggered FIFO mode + (1:1) = Invalid mode
D2	TRANSMIT ENABLE	The TRANSMIT ENABLE bit should be set after all transmit parameters have been set up. This is especially important in Immediate FIFO Transmit mode since this mode will start transmitting as soon as data is put into the Tx FIFO.
D1	RECEIVE MODE	The RECEIVE MODE bit is used to select the storage mode (FIFO or Mailbox) of received messages. FIFO = 0 MBOX = 1
D0	RECEIVER ENABLE	The RECEIVER ENABLE bit should be set after all receive parameters and filters have been set up. After setting this bit, the module will look for a minimum 4-bit gap time before decoding any ARINC bits to prevent it from receiving a partial ARINC word.

Module Reset
Function:	Sends a command to reset the entire 12-channel module to power up conditions.
Type:	unsigned binary word (32-bit)
Range:	0 or 1
Read/Write:	W
Initialized Value:	0
Operational Settings:	All FIFOs are cleared. However, it does not clear out any memories. Set D0 to 1 to reset the module then set to 0 to bring it out of reset.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1

Background BIT Threshold Programming Registers

The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The Reset BIT register provides the ability to reset the BIT counter used in CBIT.

Background BIT Threshold
Function:	Sets background BIT Threshold value to use for all channels for BIT failure indication.
Data Range:	1 to 65,535
Read/Write:	R/W
Initialized Value:	5
Operational Settings:	This value represents the background BIT error “count” that, when surpassed, will cause the BIT status to indicate failure.

BIT Count Clear
Function:	Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0x0000 000F
Read/Write:	W
Initialized Value:	0
Operational Settings:	Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Status and Interrupt Registers

The AR1 Module provides status registers for BIT, Channel and Summary

Channel Status Enable
Function:	Determines whether to update the status for the channels. Does NOT prevent BIT from executing; only prevents the update of results to the status registers. This feature can be used to “mask” status bit updates of unused channels in status registers that are bitmapped by channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 000F (Channel Status)
Read/Write:	R/W
Initialized Value:	0x0000 000F
Operational Settings:	When the bit corresponding to a given channel in the Channel Status Enable register is not enabled (0) the status update will be masked. This applies to all statuses that are bitmapped by channel (BIT Status and Summary Status).

Note

Background BIT will continue to run even if the Channel Status Enable is set to 0.

Note

If latched status has been set for any channel bit, disabling the channel status update will NOT clear the latched status bit. To clear latched bits and disable their status updates, follow these steps:

1. Disable channels in Channel Status Enable register.
2. Read the Latched Status register.
3. Clear the Latched Status register with the value read from step 2.
4. Read the Latched Status register; should not read any errors (0) on channels that have been disabled.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

BIT Status
Function:	Sets the corresponding bit associated with the channel's BIT register.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x000F 0000
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

BIT Dynamic Status
BIT Latched Status
BIT Interrupt Enable
BIT Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	AR Ch4	AR Ch3	AR Ch2	AR Ch1
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Channel Status

There are four registers associated with the Channel Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Use this register to read current or real-time status. The Built-In-Test Error bit is latched and will stay set once an error is detected. It can be cleared by reading the BIT Status register. The Schedule Interrupt bit can be cleared by reading the Interrupt Status register when enabled or it can be cleared via the Channel Control register. See specific registers for function description and programming.

The Rx Data Available bit is set when the receive FIFO is not empty. The Rx FIFO Overflow bit will set whenever the receiver must discard data because the receive FIFO was full and new data was received. The Async Data Available bit in Channel Status also gets cleared by a Stop Cmd in a schedule or if a Transmit Stop command is issued from the Transmit Stop register. The Tx Run bit is set whenever the transmitter is executing a schedule or actively transmitting the contents of the transmit FIFO. The Tx Pause bit is set whenever the transmitter has been paused in schedule mode. Some events are NOT latched. They are dynamic.

Channel Status
Function:	Sets the corresponding bit associated with the event type. There are separate registers for each channel.
Type:	unsigned binary word (32-bit)
Range:	0 to 0x0000 3FFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	N/A

Channel Dynamic Status

Channel Latched Status

Channel Interrupt Enable

Channel Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

Bit	Description	Configurable?	Configuration Register
D0	Rx Data Available	No
D1	Rx FIFO Almost Full	Yes	Receive FIFO Almost Full Threshold
D2	Rx FIFO Full	Yes	Receive FIFO Size
D3	Rx FIFO Overflow	Yes	Receive FIFO Size
D4	Tx FIFO Empty	No
D5	Tx FIFO Almost Empty	Yes	Transmit FIFO Almost Empty Threshold
D6	Tx FIFO Full	No
D7	Parity Error	No
D8	Receive Error	No
D9	Built-in-Test Error	No
D10	Schedule Interrupt	No
D11	Async Data Available	No
D12	Tx Run	No
D13	Tx Pause	No

Summary Status

Summary Status
Function:	Sets the corresponding bit associated with the channel that has data available to receive in its Receive FIFO Mode or Receive Mailbox Mode registers.
Type:	unsigned binary word (32-bits)
Data Range:	0x0000 0000 to 0x0000 000F
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value:	0

Summary Dynamic Status
Summary Latched Status
Summary Interrupt Enable
Summary Set Edge/Level Interrupt
D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Function Register Map

KEY

Configuration/Control

Status

Incoming Data

Outgoing Data

RECEIVE FIFO MODE REGISTERS
NOTE: Base Address - 0x9006 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1104	Receive FIFO Message Buffer Ch 1	R	0x1110	Receive FIFO Message Count Ch 1	R
0x1204	Receive FIFO Message Buffer Ch 2	R	0x1210	Receive FIFO Message Count Ch 2	R
0x1304	Receive FIFO Message Buffer Ch 3	R	0x1310	Receive FIFO Message Count Ch 3	R
0x1404	Receive FIFO Message Buffer Ch 4	R	0x1410	Receive FIFO Message Count Ch 4	R
0x1108	Receive FIFO Almost Full Threshold Ch 1	R/W	0x1124	Receive FIFO Size Ch 1	R/W
0x1208	Receive FIFO Almost Full Threshold Ch 2	R/W	0x1224	Receive FIFO Size Ch 2	R/W
0x1308	Receive FIFO Almost Full Threshold Ch 3	R/W	0x1324	Receive FIFO Size Ch 3	R/W
0x1408	Receive FIFO Almost Full Threshold Ch 4	R/W	0x1424	Receive FIFO Size Ch 4	R/W
RECEIVE MAILBOX MODE REGISTERS
NOTE: Base Address - 0x9006 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1104	Receive FIFO SDI/Label Buffer Ch 1	R	0x1110	Receive FIFO SDI/Label Count Ch 1	R
0x1204	Receive FIFO SDI/Label Buffer Ch 2	R	0x1210	Receive FIFO SDI/Label Count Ch 2	R
0x1304	Receive FIFO SDI/Label Buffer Ch 3	R	0x1310	Receive FIFO SDI/Label Count Ch 3	R
0x1404	Receive FIFO SDI/Label Buffer Ch 4	R	0x1410	Receive FIFO SDI/Label Count Ch 4	R
0x1108	Receive FIFO Almost Full Threshold Ch 1	R/W	0x1124	Receive FIFO Size Ch 1	R/W
0x1208	Receive FIFO Almost Full Threshold Ch 2	R/W	0x1224	Receive FIFO Size Ch 2	R/W
0x1308	Receive FIFO Almost Full Threshold Ch 3	R/W	0x1324	Receive FIFO Size Ch 3	R/W
0x1408	Receive FIFO Almost Full Threshold Ch 4	R/W	0x1424	Receive FIFO Size Ch 4	R/W
TIMESTAMP REGISTERS
NOTE: Base Address - 0x9006 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x100C	Timestamp Control	R/W	0x1010	Timestamp Value	R
MESSAGE VALIDATION REGISTERS
TRANSMIT FIFO REGISTERS
NOTE: Base Address - 0x9006 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1100	Transmit FIFO Message Buffer Ch 1	W	0x1114	Transmit FIFO Message Count Ch 1	R
0x1200	Transmit FIFO Message Buffer Ch 2	W	0x1214	Transmit FIFO Message Count Ch 2	R
0x1300	Transmit FIFO Message Buffer Ch 3	W	0x1314	Transmit FIFO Message Count Ch 3	R
0x1400	Transmit FIFO Message Buffer Ch 4	W	0x1414	Transmit FIFO Message Count Ch 4	R
0x110C	Transmit FIFO Almost Empty Threshold Ch 1	R/W	0x111C	Transmit FIFO Rate Ch 1	R/W
0x120C	Transmit FIFO Almost Empty Threshold Ch 2	R/W	0x121C	Transmit FIFO Rate Ch 2	R/W
0x130C	Transmit FIFO Almost Empty Threshold Ch 3	R/W	0x131C	Transmit FIFO Rate Ch 3	R/W
0x140C	Transmit FIFO Almost Empty Threshold Ch 4	R/W	0x141C	Transmit FIFO Rate Ch 4	R/W
TRANSMIT SCHEDULING REGISTERS
NOTE: Base Address - 0x9006 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1120	Async Transmit Data Ch 1	R/W
0x1220	Async Transmit Data Ch 2	R/W
0x1320	Async Transmit Data Ch 3	R/W
0x1420	Async Transmit Data Ch 4	R/W
TRANSMIT CONTROL REGISTERS
NOTE: Base Address - 0x9006 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1000	Tx Trigger	R/W	0x1004	Tx Pause	R/W
0x1008	Tx Stop	R/W
CONTROL REGISTERS
NOTE: Base Address - 0x9006 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1118	Channel Control Ch 1	R/W	0x1014	Module Reset	W
0x1218	Channel Control Ch 2	R/W
0x1318	Channel Control Ch 3	R/W
0x1418	Channel Control Ch 4	R/W
BIT REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a '1' back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x9000 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0800	Dynamic Status	R
0x0804	Latched Status*	R/W
0x0808	Interrupt Enable	R/W
0x080C	Set Edge/Level Interrupt	R/W
NOTE: Base Address - 0x9006 4000
0x02B8	Background BIT Threshold	R/W	0x02BC	BIT Count Clear	W
CHANNEL STATUS REGISTERS
NOTE: Base Address - 0x9006 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x02B0	Channel Status Enable	R/W
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a '1' back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x9000 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0830	Dynamic Status Ch 1	R	0x0840	Dynamic Status Ch 2	R
0x0834	Latched Status Ch 1*	R/W	0x0844	Latched Status Ch 2*	R/W
0x0838	Interrupt Enable Ch 1	R/W	0x0848	Interrupt Enable Ch 2	R/W
0x083C	Set Edge/Level Interrupt Ch 1	R/W	0x084C	Set Edge/Level Interrupt Ch 2	R/W
0x0850	Dynamic Status Ch 3	R	0x0860	Dynamic Status Ch 4	R
0x0854	Latched Status Ch 3*	R/W	0x0864	Latched Status Ch 4*	R/W
0x0858	Interrupt Enable Ch 3	R/W	0x0868	Interrupt Enable Ch 4	R/W
0x085C	Set Edge/Level Interrupt Ch 3	R/W	0x086C	Set Edge/Level Interrupt Ch 4	R/W
SUMMARY STATUS REGISTER
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a '1' back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x9000 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0870	Dynamic Status	R
0x0874	Latched Status*	R/W
0x0878	Interrupt Enable	R/W
0x087C	Set Edge/Level Interrupt	R/W

Discrete Input/Output Function

Principle of Operation

Through an IF3 combination module, the inboard Discrete Input/Output communications function provides up to 12 individual digital I/O channels with BIT fault detection (Enhanced DT4 module-type), which enables flagging of non-compliant outputs or inconsistent input readings between dual input measurements.

When channels are programmed as inputs, they can be used for either voltage or contact sensing. Channels set for contact sensing (e.g. sensing a relay contact position; OPEN-CLOSED) can be configured with a programmable “pull-up” or “pull-down” (current source or sink) which effectively provides the proper voltage level change to sense the open state of the contact. This unique design eliminates the need for external resistors or mechanical jumpers. Instead, this design offers a current source/sink (in banks of 6 channels) that the user programs to a desired current (0-5 mA) level.

When programmed as outputs, each channel can be set for high-side (current-source), low-side (current-sink) or push-pull (current-source-sink) operation. The load impedance determines the delivered switched output current drive - up to 500 mA per channel. Diode clamping is provided (useful for inductive loads, such as relays) and thermal protection.

Overcurrent protection is implemented using current sensing technology. When the current exceeds a programmed threshold of 650 mA steady-state, or a higher short duration, the overcurrent/short-circuit protection is triggered, shutting down the output drivers for safety. The overcurrent fault status will be indicated for the affected channels and will require a reset operation to restore output. To reset this condition, a reset command needs to be issued to the Overcurrent Reset register, which will restore drive output and allow the latched status to be reset. This is separate from the reset for the Overcurrent Interrupt Enable register on this module. It is recommended that a reset command is done whenever status is cleared to avoid a non-apparent output reset condition.

The 12 channels are configured as 2 banks of 6 channels. Each bank is provided with a separate external input VCC and a ground return (GND) pin. The GND pins are common within the module but are isolated from system (power) GND.

Operational requirements/assumptions:

• An external source VCC supply must be wired for proper:
  • Output operation as a current source
  • Input operation when requiring a programmed pull-up current (i.e. programmed “pull-up” for input contact sense; OPEN/GND detect/state change).
• An external source Ground/Return must be wired for all I/O configurations. The Ground/Return must be the input signal or the load current sink ground/reference.

Input/Output Interface

Each channel can be configured as an input or one of three types of outputs.

Output

When configured as an output, the interface can act as a “High-Side”, “Low-Side” or “Push-Pull” drive, providing up to 500 mA per channel or 1 A when two channels are connected in parallel. The total output per module is 4 A (2 A per bank).

Note

Maximum source current ‘rules’ for rear I/O connectors still apply - see specifications.

Input

When configured as an input, output drivers are disabled. The I/O interface can act as a constant current source, current sink or voltage sensing circuit. For contact sensing, each channel may be set for pull-up or pull-down using the Select Pull Up or Pull Down register and by entering the appropriate current level in the Pull-Up/Down Current register. Contact closure and hysteresis may be defined using the Upper Voltage and Lower Voltage Threshold registers. No additional resistors or hardware are required to provide for current flow. A current value of zero disables the current source/sink circuits and configures the module for voltage sensing. Default is voltage sensing. Level or contact sensing can be mixed within a channel bank if the contact sensing channels are externally pulled up or pulled down.

Note

If this module supplies the current for the contact sensing, then level and contact sensing cannot be mixed within a channel bank. All four threshold levels must be programmed in monotonic, increasing order of: Minimum Low, Lower, Upper and Maximum High. For input and output, threshold levels define logic state. For output, threshold levels are used in BIT test (wrap-around) signal monitoring. A pair of drive FETs and current circuits are provided at each I/O pin. See the functional representation of the drivers in the I/O Circuits interface diagram below.

Input/Output Circuits

Discrete I/O Threshold Programming

Four threshold levels: Max High Voltage Threshold, Upper Voltage Threshold, Lower Voltage Threshold, and Min Low Voltage Threshold offer maximum user flexibility. All four threshold levels must be programmed. For input or output, the threshold levels will define the logic states. For proper operation, the threshold values should be programmed such that:

Max High Voltage Threshold > Upper Voltage Threshold > Lower Voltage Threshold > Min Low Voltage Threshold

Program Upper and Lower Voltage Thresholds, keeping the 0.25 V min. differential in mind, and then add debounce time as required. When the input signal exceeds the Upper Voltage Threshold, a logic high 1 is maintained until the input signal falls below the Lower Voltage Threshold. Conversely, when the input signal falls below the Lower Voltage Threshold, a logic low 0.

Debounce Programming

The Debounce register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Once a signal level is a logic voltage level period longer than the Debounce Time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed Debounce Time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state.

Automatic Background Built-In Test (BIT)/Diagnostic Capability

The inboard Discrete Input/Output function supports automatic background BIT testing that verifies channel processing. The testing is totally transparent to the user, requires no external programming and has no effect on the operation of the module. This capability is accomplished by an additional test comparator that is incorporated into each module. The test comparator checks each channel and is compared against the operational channel. Depending upon the configuration, the Input data read, or Output logic written of the operational channel and test comparator must agree or a fault is indicated with the results available in the associated status register. The results of the tests are stored in the BIT Dynamic Status and BIT Latched Status registers.

The technique used by the continuous background BIT (CBIT) test consists of an “add-2, subtract-1” counting scheme. The BIT counter is incremented by 2 when a BIT-fault is detected and decremented by 1 when there is no BIT fault detected and the BIT counter is greater than 0. When the BIT counter exceeds the (programmed) Background BIT Threshold value, the specific channel’s fault bit in the BIT status register will be set. Note, the interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module. The “add-2, subtract-1” counting scheme effectively filters momentary or intermittent anomalies by allowing them to “come and go“ before a BIT fault status or indication is flagged (e.g. BIT faults would register when sustained; i.e. at a ten second interval, not a 10-millisecond interval). This prevents spurious faults from registering valid such as those caused by EMI and/or dirty power causing false BIT faults. Putting more “weight” on errors (“add-2”) and less “weight” on subsequent passing results (subtract-1) will result in a BIT failure indication even if a channel “oscillates” between a pass and fail state.

In addition to BIT, the inboard Discrete Input/Output function tests for overcurrent conditions and provides Above Max High Voltage, Below Min Low Voltage, and Mid-Range Voltage statuses for threshold signal transitioning.

Status and Interrupts

The inboard Discrete Input/Output provide registers that indicate faults or events. Refer to ‘Appendix B: Inboard Module Status and Interrupts’ for the Principle of Operation description.

Unit Conversions

The Discrete I/O Threshold and Measurement registers can be programmed to be utilized as a single precision floating point value (IEEE-754) or as a 32-bit integer value. The purpose for providing this feature is to offload the processing that is normally performed by the mission processor to convert the integer values to floating-point values.

When the Enable Floating Point Mode register is set to 1 (Floating Point Mode) the following registers are formatted as Single Precision Floating Point Value (IEEE-754):

• Voltage Reading (Volts)
• Current Reading (mA)
• VCC Voltage Reading (Volts)
• Max High Voltage Threshold (Volts)*
• Upper Voltage Threshold (Volts)*
• Lower Voltage Threshold (Volts)*
• Min Low Voltage Threshold (Volts)*
• Pull-Up/Down Current (mA)*

*When the Enable Floating Point Mode register is set to 1, it is important that these registers are updated with the Single Precision Floating Point (IEEE-754) representation of the value for proper operation of the channel. Conversely, when the Enable Floating Point Mode register is set to 0, these registers must be updated with the Integer 32-bit representation of the value.

Note

when changing the Enable Floating Point Mode from Integer Mode to Floating Point Mode or vice versa, the following step should be followed to avoid faults from falsely being generated because data registers (such as Thresholds) or internal registers may have the incorrect binary representation of the values:

1. Set the Enable Floating Point Mode register to the desired mode (Integer = 0 or Floating Point = 1).
2. Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module’s conversion of the register values and internal values is complete. Data registers will be converted to the units specified and can be read in that specified format.

User Watchdog Timer Capability

The inboard Discrete Input/Output Option provide registers that support User Watchdog Timer capability. Refer to ‘Appendix C: Inboard Discrete I/O User Watchdog Timer Functionality’ for the Principle of Operation description.

Enhanced Functionality

The inboard Discrete Input/Output function offers enhanced input and output mode functionality. For incoming signals (inputs), the enhanced modes include Pulse Measurements, Transition Timestamps, Transition Counters, Period Measurement and Frequency Measurement. For outputs, the enhanced modes include PWM (Pulse Width Modulation) Outputs and Pattern Generator Outputs.

Refer to ‘Appendix E: Inboard Discrete I/O Enhanced Input/Output Functionality’ for the Principle of Operation description.

Register Descriptions

The register descriptions provide the Register Name, Type, Data Range, Read or Write information, power on default initialized values, a description of the function and a data table where applicable.

Discrete Input/Output Registers

Each channel can be configured as an input or one of three types of outputs. The I/O Format (Ch1-12) registers are used to set each channel’s Input/Output configuration. The Write Outputs register controls the output channels to either a High (1) or Low (0) state, and the Read I/O register contains the discrete channel’s state (High (1) or Low (0)) as specified by the channel’s threshold configurations.

I/O Format Ch1-12
Function:	Sets channels 1-12 as inputs or outputs.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x00FF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Write integer 0 for input; 1, 2, or 3 for specific output format.

Integer	DH	DL	(2 bits per channel)
0	0	0	Input
1	0	1	Output, Low-side switched, with/without current pull up
2	1	0	Output, High-side switched, with/without current pull down
3	1	1	Output, push-pull

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

Ch12

Ch11

Ch10

Ch9

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Write Outputs
Function:	Drives output channels High 1 or Low 0
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Write 1 to drive output high. Write 0 to drive output low.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

Input/Output State
Function:	Reads High 1 or Low 0 inputs or outputs as defined by internal channel threshold values.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	Bit-mapped per channel.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

Discrete Input/Output Threshold Programming Registers

Four threshold levels: Max High Threshold, Upper Threshold, Lower Threshold, and Min Low Threshold are programmable for each Discrete channel in the module.

Max High Voltage Threshold (Enable Floating Point Mode: Integer Mode)

Upper Voltage Threshold (Enable Floating Point Mode: Integer Mode)

Lower Voltage Threshold (Enable Floating Point Mode: Integer Mode)

Min Low Voltage Threshold (Enable Floating Point Mode: Integer Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

D

D

D

D

D

D

D

D

D

D

D

D

D

Max High Voltage Threshold (Enable Floating Point Mode: Floating Point Mode)

Upper Voltage Threshold (Enable Floating Point Mode: Floating Point Mode)

Lower Voltage Threshold (Enable Floating Point Mode: Floating Point Mode)

Min Low Voltage Threshold (Enable Floating Point Mode: Floating Point Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

Max High Voltage Threshold
Function:	Sets the maximum high voltage threshold value. Programmable per channel from + 0 VDC to 60 VDC.
Type:	unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Enable Floating Point Mode: 0 (Integer Mode) `      0x0000 0000 to 0x0000 0258 Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	0x32
Operational Settings:	Assumes that the programmed level is the minimum voltage used to indicate a Max High Voltage Threshold. If a signal is greater than the Max High Threshold value, a flag is set in the Max High Voltage Threshold Status register. The Max High Voltage Threshold register may be used to monitor any type of high signal voltage condition or threshold such as a “Short to V” as it applies to input measurement as well as contact sensing applications. Integer Mode: LSB is 0.1 VDC. For example: to program 5.0 VDC, 5.0 / 0.1 = 50 (binary equivalent for 50 is 0x0000 0032). Floating Point Mode: Set Max High Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 5.0 V, enter 5.0 as a single precision floating point value (IEEE-754) (binary equivalent 5.0 is 0x40A0 0000).

Upper Voltage Threshold
Function:	Sets the upper voltage threshold value. Programmable per channel from + 0 VDC to 60 VDC.
Type:	unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Enable Floating Point Mode: 0 (Integer Mode) `      0x0000 0000 to 0x0000 0258 Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	0x28
Operational Settings:	A signal is considered logic High 1 when its value exceeds the Upper Voltage Threshold and does not consequently fall below the Upper Voltage Threshold in less than the programmed Debounce Time. Integer Mode: LSB is 0.1 VDC. For example: to program 3.5 VDC, 3.5 / 0.1 = 35 (binary equivalent for 35 is 0x0000 0023). Floating Point Mode: Set Upper Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 3.5 V, enter 3.5 as a single precision floating point value (IEEE-754) (binary equivalent 3.5 is 0x4060 0000).

Lower Voltage Threshold
Function:	Sets the lower voltage threshold value. Programmable per channel from + 0 VDC to 60 VDC.
Type:	unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Enable Floating Point Mode: 0 (Integer Mode) `      0x0000 0000 to 0x0000 0258 Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	0x10
Operational Settings:	A signal is considered logic Low 0 when its value falls below the Lower Voltage Threshold and does not consequently rise above the Lower Voltage Threshold in less than the programmed Debounce Time. Integer Mode: LSB is 0.1 VDC. For example: to program 1.5 VDC, 1.5 / 0.1 = 15 (binary equivalent for 15 is 0x0000 000F). Floating Point Mode: Set Lower Voltage Threshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 1.5 V, enter 1.5 as a single precision floating point value (IEEE-754) (binary equivalent 1.5 is 0x3FC0 0000).

Min Low Voltage Threshold
Function:	Sets the minimum low voltage threshold. Programmable per channel + 0 VDC to 60 VDC.
Type:	unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Enable Floating Point Mode: 0 (Integer Mode) `      0x0000 0000 to 0x0000 0258 Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	0xA
Operational Settings:	Assumes that the programmed level is the voltage used to indicate a minimum low threshold. If a signal is less than the Min Low Voltage Threshold value, a flag is set in the Min Low Voltage Threshold Status register. The Min Low VoltageThreshold register may be used to monitor any type of low signal voltage condition or threshold such as a “Short to Ground” as it applies to input measurement as well as contact sensing applications. Integer Mode: LSB is 0.1 VDC. For example: to program 0.5 VDC, 0.5 / 0.1 = 5 (binary equivalent for 5 is 0x0000 0005). Floating Point Mode: Set Min Low VoltageThreshold value as a Single Precision Floating Point Value (IEEE-754). For example, to program 0.5 V, enter 0.5 as a single precision floating point value (IEEE-754) (binary equivalent 0.5 is 0x3F00 0000).

Discrete Input/Output Measurement Registers

The measured voltage at the I/O pin for each channel can be read from the Voltage Reading register.

Voltage Reading
Function:	Reads actual voltage at I/O pin per individual channel.
Type:	unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Enable Floating Point Mode: 0 (Integer Mode) `      0x0000 0000 to 0x0000 0258 Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	Integer Mode: LSB is 0.1 VDC. If the register value is 261 (binary equivalent for 261 is 0x0000 0105), conversion to the voltage value is 261 * 0.1 = 26.1 V. Floating Point Mode: Read as a Single Precision Floating Point Value (IEEE-754). For example, if the register value is 0x41D0 CCCD, this is equivalent to is 26.1, which represent 26.1 V.

Voltage Reading (Enable Floating Point Mode: Integer Mode)``

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

D

D

D

D

D

D

D

D

D

D

D

D

D

Voltage Reading (Enable Floating Point Mode: Floating Point Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

Current Reading

Current Reading
Function:	Reads actual output current through I/O pin per channel.
Type:	signed binary word (32-bit (only lower 16-bit is used)) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Enable Floating Point Mode: 0 (Integer Mode) `      (2's compliment. 16-bit value sign extended to 32 bits) `      0x0000 0000 to 0x0000 00D0 (positive) or 0x0000 FF30 (negative) Enable Floating Point Mode: 1 (Floating Point Mode) +      Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	Integer Mode: LSB is 3.0 mA. Value is signed binary 16-bit word. Read as 2's complement value for positive and negative current readings. For example, if the register value is 50 (binary equivalent for 50 is 0x0000 0032), the conversion to the current value is 50 3.0 = 150 mA. If register value is -50 (binary equivalent for -150 is 0x0000 FFCE), the conversion to the current value is -50 3.0 = -150 mA. Floating Point Mode: Read as a Single Precision Floating Point Value (IEEE-754). The value will represent a positive or negative current reading. For example, if the register value is 0x4316 0000, this is equivalent to 150, which represent 150 mA. If the register value is 0xC316 0000, this is equivalent to -150, which represents -150 mA.

Current Reading (Enable Floating Point Mode: Integer Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

Current Reading (Enable Floating Point Mode: Floating Point Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

VCC Bank Registers

There are two VCC banks where each bank controls 6 discrete channels. Configuration for each bank involves specifying if the bank is configured for pull-up or pull-down and the current for source/sink. The measured voltage for VCC can be read from the VCC Voltage Reading register.

Select Pull-Up or Pull-Down
Function:	Configures Pull-up or Pull-down configuration per 6-channel bank
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0x0000 0003
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set bit to 1 to configure channel bank to Pull-up. Set bit to 0 to configure channel bank to Pull-down. Each data bit configures entire bank of 6 channels.

Note

For contact (switch closure) applications, a current supply (Vcc) is required for internal pull-up.

Bit(s)	Name	Description
D31:D2	Reserved	Set Reserved bits to 0.
D1	Configure Bank 2 (Ch 07-12)	1=Pull-Up, 0=Pull-Down
D0	Configure Bank 1 (Ch 01-06)	1=Pull-Up, 0=Pull-Down

Pull-Up/Down Current
Function:	Sets current for source/sink per 6-channel bank. Programmable from 0 to 5 mA.
Type:	unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Enable Floating Point Mode: 0 (Integer Mode) `      0x0000 0000 to 0x0000 0032 Enable Floating Point Mode: 1 (Floating Point Mode) `      Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	0 (Voltage Sensing)
Operational Settings:	A current of zero disables the current source/sink circuits and configures for voltage sensing (refer to Input in Input/Output Interface section). Integer Mode: LSB is 0.1 mA. For example: to program 5 mA, 5 / 0.1 = 50 (binary equivalent for 50 is 0x0000 0032). Floating Point Mode: Set the current for source/sink as a Single Precision Floating Point Value (IEEE-754). For example, to program 5 mA, enter 5.0 as a Single Precision Floating Point Value (IEEE-754) (binary equivalent for 5.0 is 0x40A0 0000).

Pull-Up/Down Current (Enable Floating Point Mode: Integer Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

0

0

D

D

D

D

D

D

Pull-Up/Down Current (Enable Floating Point Mode: Floating Point Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

VCC Voltage Reading
Function:	Read the VCC bank voltage.
Type:	unsigned binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Enable Floating Point Mode: 0 (Integer Mode) `      0x0000 0000 to 0x0000 0258 Enable Floating Point Mode: 1 (Floating Point Mode) `      Single Precision Floating Point Value (IEEE-754)
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	Integer Mode: LSB is 0.1 VDC. If the register value is 260 (binary equivalent for this value is 0x0000 0104), conversion to the voltage value is 260 * 0.1 = 26.0 V. Floating Point Mode: Read as a Single Precision Floating Point Value (IEEE-754). For example, the binary equivalent for 0x41D0 0000 is 26.0 which represent 26.0 V.

VCC Voltage Reading (Enable Floating Point Mode: Integer Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

D

D

D

D

D

D

D

D

D

D

D

D

D

VCC Voltage Reading (Enable Floating Point Mode: Floating Point Mode)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

Discrete Input/Output Control Registers

Control of the Discrete I/O channels include specifying the Debounce time for each input channel and resetting the I/O channel on an overcurrent condition.

Debounce Time
Function:	When set for inputs, the input signal will have the debounce filtering applied based on this programmed value. This is selectable for each channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	The Debounce Time register, when programmed for a non-zero value, is used with channels programmed as input to “filter” or “ignore” expected application spurious initial transitions. Enter required Debounce Time into appropriate channel registers. LSB weight is 10 µs/bit (register may be programmed from 0x0000 0000 (debounce filter inactive) through a maximum of 0xFFFF FFFF (2^32 * 10µs). (full scale w/ 10 µs resolution). Once a signal level is a logic voltage level period longer than the debounce time (Logic High and Logic Low), a logic transition is validated. Signal pulse widths less than programmed Debounce Time are filtered. Once valid, the transition status register flag is set for the channel and the output logic changes state. Enter a value of 0 to disable debounce filtering.

Overcurrent Reset
Function:	Resets disabled channels in Overcurrent Latched Status register following an overcurrent condition as measured by the Current Reading register.
Type:	unsigned binary word (32-bit)
Data Range:	0 or 1
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	1 is written to reset disabled channels. Processor will write a 0 back to the Overcurrent Reset register when reset process is complete.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Test Registers

One on-line (CBIT) test can be selected.

Test Enabled
Function:	Sets bit to enable the associated CBIT (“D2”). NOTE: CBIT cannot be disabled
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0004
Read/Write:	R/W
Initialized Value:	0x4 (CBIT Test Enabled)
Operational Settings:	BIT test includes an on-line CBIT test. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects failures.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	CBIT + Test 1	0	0

Unit Conversion Programming Registers

The Enable Floating Point register provides the ability to set the Threshold values as floating-point values and read the Voltage Reading registers as floating-point values. The purpose for this feature is to offload the processing that is normally performed by the mission processor to convert the integer values to floating-point values.

Enable Floating Point Mode
Function:	Sets all channels for floating point mode or integer module.
Type:	unsigned binary word (32-bit)
Data Range:	0 to 1
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set bit to 1 to enable Floating Point Mode and 0 for Integer Mode. Wait for the Floating Point State register to match the value for the requested Floating Point Mode (Integer = 0, Floating Point = 1); this indicates that the module's conversion of the register values and internal values is complete before changing the values of the configuration and control registers with the values in the units specified (Integer or Floating Point).

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D

Background BIT Threshold Programming Registers

The Background BIT Threshold register provides the ability to specify the minimum time before the BIT fault is reported in the BIT Status registers. The Reset BIT register provides the ability to reset the BIT counter used in CBIT.

Background BIT Threshold
Function:	Sets BIT Threshold value (in milliseconds) to use for all channels for BIT failure indication.
Type:	unsigned binary word (32-bit)
Data Range:	1 ms to 232 ms
Read/Write:	R/W
Initialized Value:	5 (5 ms)
Operational Settings:	The interval at which BIT is performed is dependent and differs between module types. Rather than specifying the BIT Threshold as a “count”, the BIT Threshold is specified as a time in milliseconds. The module will convert the time specified to the BIT Threshold “count” based on the BIT interval for that module.

BIT Count Clear

BIT Count Clear
Function:	Resets the CBIT internal circuitry and count mechanism. Set the bit corresponding to the channel you want to clear.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	W
Initialized Value:	0
Operational Settings:	Set bit to 1 for channel to resets the CBIT mechanisms. Bit is self-clearing.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

User Watchdog Timer Programming Registers

Refer to ‘Appendix C: Inboard Discrete I/O User Watchdog Timer Functionality’ for the Register descriptions.

Status and Interrupt Registers

The Discrete Module provides status registers for BIT, Low-to-High Transition, High-to-Low Transition, Above Max High Voltage, Below Min Low Voltage, and Mid-Range Voltage.

Channel Status Enable
Function:	Determines whether to update the status for the channels. This feature can be used to “mask” status bits of unused channels in status registers that are bitmapped by channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF (Channel Status)
Read/Write:	R/W
Initialized Value:	0x0000 0FFF
Operational Settings:	When the bit corresponding to a given channel in the Channel Status Enable register is not enabled (0) the status will be masked and report “0” or “no failure”. This applies to all statuses that are bitmapped by channel (BIT Status, Low-to-High Transition Status, High-to-Low Transition Status, Overcurrent Status, Above Max High Voltage Status, Below Min Low Voltage Status, Mid-Range Voltage and Summary Status).

Note

Background BIT will continue to run even if the Channel Status Enable is set to 0.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

BIT Status

There are four registers associated with the BIT Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Note

When a BIT fault is detected, reading the Voltage Reading Error and the Driver Error register will provide additional diagnostics on the cause of the BIT fault.

BIT Status
Function:	Sets the corresponding bit associated with the channel's BIT error.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Note

Faults are detected (associated channel(s) bit set to 1) within 10 ms.

Note

BIT Status is a shared register between the DT and SC functions. Bits D0:D11 are dedicated to the DT function, and bits D19:D16 are dedicated to the SC function.

BIT Dynamic Status

BIT Latched Status

BIT Interrupt Enable

BIT Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

SC Ch4

SC Ch3

SC Ch2

SC Ch1

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

DT Ch12

DT Ch11

DT Ch10

DT Ch9

DT Ch8

DT Ch7

DT Ch6

DT Ch5

DT Ch4

DT Ch3

DT Ch2

DT Ch1

Voltage Reading Error
Function:	The Voltage Reading Error register is set when a redundant voltage measurement is inconsistent with the input voltage level detected.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	1 is read when a fault is detected. 0 indicates no fault detected.

Note

Faults are detected (associated channel(s) bit set to 1) within 10 ms.

Note

Clearing the latched BIT status will also clear this error register.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

Driver Error
Function:	The Driver Error register is set when the voltage reading mismatches active driver measurement and is inconsistent with the input driver level detected (Note: requires programming of thresholds).
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	1 is read when a fault is detected. 0 indicates no fault detected.

Note

Faults are detected (associated channel(s) bit set to 1) within 10 ms.

Note

Clearing the latched BIT status will also clear this error register.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

Low-to-High Transition Status

There are four registers associated with the Low-to-High Transition Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Low-to-High Transition Status
Function:	Sets the corresponding bit associated with the channel's Low-to-High Transition event.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Note

Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.

Note

Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.

Note

Transition status follows the value read by the Input/Output State register.

Low-to-High Transition Dynamic Status

Low-to-High Transition Latched Status

Low-to-High Transition Interrupt Enable

Low-to-High Transition Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

High-to-Low Transition Status

There are four registers associated with the High-to-Low Transition Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

High-to-Low Transition Status
Function:	Sets the corresponding bit associated with the channel's High-to-Low Transition event.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Note

Considered “momentary” during the actual event when detected. Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.

Note

Programmable for level or edge sensing, status is indicated (associated channel(s) bit set to 1) within 20 µs.

Note

Transition status follows the value read by the Input/Output State register.

High-to-Low Transition Dynamic Status

High-to-Low Transition Latched Status

High-to-Low Transition Interrupt Enable

High-to-Low Transition Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Overcurrent Status

There are four registers associated with the Overcurrent Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Overcurrent Status
Function:	Sets the corresponding bit associated with the channel's Overcurrent error.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Note

Status is indicated (associated channel(s) bit set to 1) within 80 ms.

Note

Latched Status is indicated (associated channel(s) bit set to 1) within 80 ms.

Note

Channel(s) shut down by overcurrent sensed can be reset by writing to the Overcurrent Clear register.

Overcurrent Dynamic Status

Overcurrent Latched Status

Overcurrent Interrupt Enable

Overcurrent Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Above Max High Voltage Status

There are four registers associated with the Above Max High Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.

Above Max High Voltage Status
Function:	Sets the corresponding bit associated with the channel's Above Max High Voltage event.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Above Max High Voltage Dynamic Status

Above Max High Voltage Latched Status

Above Max High Voltage Interrupt Enable

Above Max High Voltage Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Below Min Low Voltage Status

There are four registers associated with the Below Min Low Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.

Below Min Low Voltage Status
Function:	Sets the corresponding bit associated with the channel's Below Min Low Voltage event.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Below Min Low Voltage Dynamic Status

Below Min Low Voltage Latched Status

Below Min Low Voltage Interrupt Enable

Below Min Low Voltage Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Mid-Range Voltage Status

There are four registers associated with the Mid-Range Voltage Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt. Latched status is indicated (bit is set) within 500 µs. Write a 1 to clear status.

Mid-Range Voltage Status
Function:	Sets the corresponding bit associated with the channel's Mid-Range Voltage event.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Note

Voltage level needs to be between the upper and lower thresholds for the debounce time for this status to assert.

Note

In the event this status is asserted, the Input/Output state will hold its previous state.

Mid-Range Voltage Dynamic Status

Mid-Range Voltage Latched Status

Mid-Range Voltage Interrupt Enable

Mid-Range Voltage Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

User Watchdog Timer Fault Status

The inboard Discrete Input/Output option provide registers that support User Watchdog Timer capability. Refer to ‘Appendix C: Inboard Discrete I/O User Watchdog Timer Functionality’ for the Inboard Discrete I/O User Watchdog Timer Fault Status Register descriptions.

Summary Status

There are four registers associated with the Summary Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Summary Status
Function:	Sets the corresponding bit if any fault (BIT and Overcurrent) occurs on that channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Summary Status Dynamic Status

Summary Status Latched Status

Summary Status Interrupt Enable

Summary Status Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

Ch12

Ch11

Ch10

Ch9

Ch8

Ch7

Ch6

Ch5

Ch4

Ch3

Ch2

Ch1

Enhanced Functionality Registers

Refer to ‘Appendix E: Inboard Discrete I/O Enhanced Input/Output Functionality’ for the Register descriptions.

Function Register Map

KEY

Configuration/Control

Measurement/Status

DISCRETE INPUT/OUTPUT REGISTERS
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1038	I/O Format Ch1-12	R/W	0x1000	I/O State	R
			0x1024	Write Outputs	R/W
DISCRETE INPUT/OUTPUT THRESHOLD PROGRAMMING REGISTERS
NOTE: Base Address - 0x9010 C000
**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x20C0	Max High Voltage Threshold Ch 1**	R/W	0x20C4	Upper Voltage Threshold Ch 1**	R/W
0x2140	Max High Voltage Threshold Ch 2**	R/W	0x2144	Upper Voltage Threshold Ch 2**	R/W
0x21C0	Max High Voltage Threshold Ch 3**	R/W	0x21C4	Upper Voltage Threshold Ch 3**	R/W
0x2240	Max High Voltage Threshold Ch 4**	R/W	0x2244	Upper Voltage Threshold Ch 4**	R/W
0x22C0	Max High Voltage Threshold Ch 5**	R/W	0x22C4	Upper Voltage Threshold Ch 5**	R/W
0x2340	Max High Voltage Threshold Ch 6**	R/W	0x2344	Upper Voltage Threshold Ch 6**	R/W
0x23C0	Max High Voltage Threshold Ch 7**	R/W	0x23C4	Upper Voltage Threshold Ch 7**	R/W
0x2440	Max High Voltage Threshold Ch 8**	R/W	0x2444	Upper Voltage Threshold Ch 8**	R/W
0x24C0	Max High Voltage Threshold Ch 9**	R/W	0x24C4	Upper Voltage Threshold Ch 9**	R/W
0x2540	Max High Voltage Threshold Ch 10**	R/W	0x2544	Upper Voltage Threshold Ch 10**	R/W
0x25C0	Max High Voltage Threshold Ch 11**	R/W	0x25C4	Upper Voltage Threshold Ch 11**	R/W
0x2640	Max High Voltage Threshold Ch 12**	R/W	0x2644	Upper Voltage Threshold Ch 12**	R/W
0x20C8	Lower Voltage Threshold Ch 1**	R/W	0x20CC	Min Low Voltage Threshold Ch 1**	R/W
0x2148	Lower Voltage Threshold Ch 2**	R/W	0x214C	Min Low Voltage Threshold Ch 2**	R/W
0x21C8	Lower Voltage Threshold Ch 3**	R/W	0x21CC	Min Low Voltage Threshold Ch 3**	R/W
0x2248	Lower Voltage Threshold Ch 4**	R/W	0x224C	Min Low Voltage Threshold Ch 4**	R/W
0x22C8	Lower Voltage Threshold Ch 5**	R/W	0x22CC	Min Low Voltage Threshold Ch 5**	R/W
0x2348	Lower Voltage Threshold Ch 6**	R/W	0x234C	Min Low Voltage Threshold Ch 6**	R/W
0x23C8	Lower Voltage Threshold Ch 7**	R/W	0x23CC	Min Low Voltage Threshold Ch 7**	R/W
0x2448	Lower Voltage Threshold Ch 8**	R/W	0x244C	Min Low Voltage Threshold Ch 8**	R/W
0x24C8	Lower Voltage Threshold Ch 9**	R/W	0x24CC	Min Low Voltage Threshold Ch 9**	R/W
0x2548	Lower Voltage Threshold Ch 10**	R/W	0x254C	Min Low Voltage Threshold Ch 10**	R/W
0x25C8	Lower Voltage Threshold Ch 11**	R/W	0x25CC	Min Low Voltage Threshold Ch 11**	R/W
0x2648	Lower Voltage Threshold Ch 12**	R/W	0x264C	Min Low Voltage Threshold Ch 12**	R/W
DISCRETE INPUT/OUTPUT MEASUREMENT REGISTERS
NOTE: Base Address - 0x9010 C000
**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x20E0	Voltage Reading Ch 1**	R	0x20E4	Current Reading Ch 1**	R
0x2160	Voltage Reading Ch 2**	R	0x2164	Current Reading Ch 2**	R
0x21E0	Voltage Reading Ch 3**	R	0x21E4	Current Reading Ch 3**	R
0x2260	Voltage Reading Ch 4**	R	0x2264	Current Reading Ch 4**	R
0x22E0	Voltage Reading Ch 5**	R	0x22E4	Current Reading Ch 5**	R
0x2360	Voltage Reading Ch 6**	R	0x2364	Current Reading Ch 6**	R
0x23E0	Voltage Reading Ch 7**	R	0x23E4	Current Reading Ch 7**	R
0x2460	Voltage Reading Ch 8**	R	0x2464	Current Reading Ch 8**	R
0x24E0	Voltage Reading Ch 9**	R	0x24E4	Current Reading Ch 9**	R
0x2560	Voltage Reading Ch 10**	R	0x2564	Current Reading Ch 10**	R
0x25E0	Voltage Reading Ch 11**	R	0x25E4	Current Reading Ch 11**	R
0x2660	Voltage Reading Ch 12**	R	0x2664	Current Reading Ch 12**	R
VCC BANK REGISTERS
NOTE: Base Address - 0x9010 C000
**Data is represented in Floating Point if Enable Floating Point Mode register is set to Floating Point Mode (1).
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1104	Select Pullup or Pulldown	R/W
0x20D0	Pull-Up/Down Current Bank 1 (Ch1-6)**	R/W	0x20EC	VCC Voltage Reading Bank 1 (Ch 1-6)**	R
0x2150	Pull-Up/Down Current Bank 2 (Ch7-12)**	R/W	0x216C	VCC Voltage Reading Bank 2 (Ch 7-12)**	R
DISCRETE INPUT/OUTPUT CONTROL REGISTERS
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x20D4	Debounce Time Ch 1	R/W
0x2154	Debounce Time Ch 2	R/W
0x21D4	Debounce Time Ch 3	R/W
0x2254	Debounce Time Ch 4	R/W
0x22D4	Debounce Time Ch 5	R/W
0x2354	Debounce Time Ch 6	R/W
0x23D4	Debounce Time Ch 7	R/W
0x2454	Debounce Time Ch 8	R/W
0x24D4	Debounce Time Ch 9	R/W
0x2554	Debounce Time Ch 10	R/W
0x25D4	Debounce Time Ch 11	R/W
0x2654	Debounce Time Ch 12	R/W
0x1100	Overcurrent Reset	W
UNIT CONVERSION PROGRAMMING REGISTERS
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x02B4	Enable Floating Point	R/W
USER WATCHDOG TIMER PROGRAMMING REGISTERS
Refer to 'Appendix C: Inboard User Watchdog Timer Functionality' for the User Watchdog Timer Status Function Register Map.
CHANNEL STATUS REGISTER
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x02B0	Channel Status Enable	R/W
BIT REGISTERs
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0800	Dynamic Status	R
0x0804	Latched Status*	R/W
0x0808	Interrupt Enable	R/W
0x080C	Set Edge/Level Interrupt	R/W
0x1200	Voltage Reading Error Dynamic	R	0x1208	Driver Error Dynamic	R
0x1204	Voltage Reading Error Latched*	R/W	0x120C	Driver Error Latched*	R/W
0x0248	Test Enabled	R/W	0x02AC	Power-on BIT Complete++	R
0x02B8	Background BIT Threshold	R/W	0x02BC	BIT Count Clear	W
++After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.
STATUS REGISTERS
NOTE: Base Address - 0x9010 C000
Low-to-High Transition			High-to-Low Transition
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0810	Dynamic Status	R	0x0820	Dynamic Status	R
0x0814	Latched Status*	R/W	0x0824	Latched Status*	R/W
0x0818	Interrupt Enable	R/W	0x0828	Interrupt Enable	R/W
0x081C	Set Edge/Level Interrupt	R/W	0x082C	Set Edge/Level Interrupt	R/W
Overcurrent			Above Max High Voltage
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0830	Dynamic Status	R	0x0840	Dynamic Status	R
0x0834	Latched Status*	R/W	0x0844	Latched Status*	R/W
0x0838	Interrupt Enable	R/W	0x0848	Interrupt Enable	R/W
0x083C	Set Edge/Level Interrupt	R/W	0x084C	Set Edge/Level Interrupt	R/W
Below Min Low Voltage			Mid-Range Voltage
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0850	Dynamic Status	R	0x0860	Dynamic Status	R
0x0854	Latched Status*	R/W	0x0864	Latched Status*	R/W
0x0858	Interrupt Enable	R/W	0x0868	Interrupt Enable	R/W
0x085C	Set Edge/Level Interrupt	R/W	0x086C	Set Edge/Level Interrupt	R/W
User Watchdog Timer Fault/Inter-FPGA Failure
The Discrete Modules provide registers that support User Watchdog Timer capability. Refer to 'Appendix C: Inboard Discrete I/O User Watchdog Timer Functionality' for the User Watchdog Timer Fault Status Function Register Map.
Summary
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x09A0	Dynamic Status	R
0x09A4	Latched Status*	R/W
0x09A8	Interrupt Enable	R/W
0x09AC	Set Edge/Level Interrupt	R/W
ENHANCED FUNCTIONALITY REGISTERS
Refer to 'Appendix E: Inboard Discrete I/O Enhanced Input/Output Functionality' for the Function Register Map.

Serial Function

Principle of Operation

Through a IF3 combination module, the inboard serial communications function provides up to 4 programmable serial RS-232/422/485 channels (SC3 module-type). Each channel of the module can be individually software configured for RS-232C, RS-422 or RS-485 Asynchronous/Synchronous Serial Communications or GPIO. See table below for more specific pinouts between modes. The architecture avoids latency problems because all data transfer is done in hardware and not in software. Any incoming data, no matter how many channels are active, in whatever mode, can be immediately extracted. FPGA design simplifies programming and usage.

-	RS232	RS232 GPIO	RS232 HW Flow	RS422/485	RS422/485 GPIO	RS422/485 HW Flow	RS422/485 Sync
RxDLo - 1	RXD - 1	GPI2 - 1	RXD - 1	RXDLO - 1	GPI-LO - 1	RXDLO - 1	RXDLO - 1
RxDHi - 1	n/a	GPI1 - 1	CTS - 1	RXDHI - 1	GPI-HI - 1	RXDHI - 1	RXDHI - 1
TxDLo -1	TXD - 1	GPO2 - 1	TXD - 1	TXDLO - 1	GPO-LO - 1	TXDLO - 1	TXDLO - 1
TxDHi - 1	n/a	GPO1 - 1	RTS - 1	TXDHI - 1	GPO-HI - 1	TXDHI - 1	TXDHI - 1
...
RxDLo - 4	RXD - 4	GPI2 - 4	RXD - 4	RXDLO - 4	GPI-LO - 4	CTSLO - 1	CLKINLO - 1
RxDHi - 4	n/a	GPI2 - 4	CTS - 4	RXDHI - 4	GPI-HI - 4	CTSHI - 1	CLKINHI - 1
TxDLo - 4	TXD - 4	GPO2 - 4	TXD - 4	TXDLO - 4	GPO-LO - 4	RTSLO - 1	CLKOUTLO - 1
TxDHi - 4	n/a	GPO5 - 4	RTS - 4	TXDHI - 4	GPO-HI - 4	RTSHI - 1	CLKOUTHI - 1

Configuration

Before the user can write to any configuration register, certain steps must be followed to ensure the module accepts the user specified configuration. The steps are as follows:

1. Write a 0 to the Enable Channel bit of the Tx-Rx Configuration register to tell the hardware that we are about to change the configuration.

2. Wait for the Channel Configured status of the Realtime Channel Status registers to read a 0.

3. Write all desired configuration registers.

4. Set the Enable Channel bit of the Tx-Rx Configuration register to 1 to notify the hardware that it can read all the configuration registers.

5. Wait for the Channel Configured status in the Realtime Channel Status register to read a 1 before proceeding to send/receive data.

Async/Sync Modes

All four channels can be configured in asynchronous mode or the first two channels can be configured for synchronous modes. Mixing asynchronous and synchronous modes is also possible.

Sync Mode Channel Pairs

The user can configure any of the first two channels of the serial function to operate in any of the following synchronous modes: HDLC, Mono-Synchronous or Bi-Synchronous. When any of these channels are configured for a synchronous mode, the channel will need to pair with another channel to make sue of its transmitter and receiver to handle clock input and output signals. Channel pairs are as follows: 1&3, 2&4.

Hardware Flow Control

The user can configure any of the first two channels of the serial function to operate in hardware flow control mode by setting the RTS/CTS Flow Control bit of the Tx-Rx Configuration register to a 1. When a channel is configured in this mode, the channel pair’s transmitter and receiver will be used for the Request to Send (RTS) and Clear to Send (CTS) signals. The channels pairs are the same as in sync mode.

GPIO Mode

The serial function is configured for GPIO mode via the Interface Levels register. Setting the GPIO bit to 1, sets a channel to GPIO mode. It is also necessary to choose either RS-232 or RS-422 to determine the GPIO signal level.

Note

As shown in the table in Principle of Operation, single ended RS-232 provides GPI 1, GPI 2, GPO 1 and GPO 2. RS-422 provides GPI 1 and GPO 1 only.

To set an output (GPO) channel to a high state, set the Channel Control register RTS/GPO 1 or GPO 2 bits, to 1. The default is 0 (low). Inputs (GPI) are monitored by the Dynamic Status register, bits CTS/GPI 1 and GPI 2, which provide real-time status monitoring of the GPI inputs. The Latched Status register, bits CTS/GPI 1 and GPI 2, latch when an input is received and are cleared when a 1 is written to the register. The Interrupt Enable register bits CTS/GPI 1 and GPI 2 when set to a 1, will create an interrupt. To invert the GPI/GPO inputs and outputs, set the Tx-Rx Configuration register bits Invert CTS (GPI) and Invert RTS (GPO), to 1. See the Register Descriptions for more information.

Gap Timeout Status

The Gap Timeout Occurred status gets set when there’s data in a channel’s receive buffer but there’s no activity on a channel’s receiver for approximately three byte-times. To use the Gap Timeout feature, set the Enable Gap Timeout bit in the Tx-Rx Configuration register to a 1. When receiving asynchronous data, monitor the Gap Timeout status bit of the Channel Status register to know if a timeout occurred. The status is cleared after all the data in the receive buffer is read or cleared.

Serial Built-In Test/Diagnostic Capability

The serial module supports two types of built-in tests: Power-On and Initiated. The results of these tests are logically ORed together and stored in the BIT Dynamic Status and BIT Latched Status registers.

Power-on Self-Test (POST)/Power-on BIT (PBIT)/Start-up BIT (SBIT)

The power-on self-test is performed on each channel automatically when power is applied and report the results in the BIT Status register when complete. After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.

Initiated Built-In Test

The Initiated Built-In-Test (IBIT) is an internal loopback available for each channel of the serial function. The test is initiated by setting the bit for the associated channel in the Test Enabled register or (for legacy applications) setting the Initiate BIT bit of the Tx-Rx-Configuration register to a 1. Prior to initiating the test, the user must disable the channel, and its respective pair, by writing a 0 to the Enable Channel bit of the channel’s Tx-Rx Configuration register. BIT will not run if the channel is enabled. After the user disables the channel and initiates BIT, they must wait a minimum of 5 msec then check to see if the bit for the associated channel in the Test Enabled register or (for legacy application) Initiate BIT bit of the Tx-Rx-Configuration register reads a 0. When the SC3 clears the bit, it means that the test has completed, and its results can be checked. If the bit has not cleared after 10ms, the test has timed out and not run. In the event this should occur, the user should verify that the channel, and its pair, has been disabled. The results of the IBIT is stored in the BIT Dynamic Status and BIT Latched Status registers, a 0 indicates that the channel has passed and a 1 indicates that it failed.

Receiver Enable/Disable

A Receiver Enable/Disable function allows the user to turn selected receivers ON/OFF. When a receiver is disabled, no data will be placed in the buffer.

Serial Data Transmit Enhancement

An additional asynchronous mode to support “Immediate Transmit” operation has been incorporated. This mode immediately transmits serial data anytime the transmit buffer is not empty. There is no requirement to set the Tx Initiate bit before each transmission, which simplifies system traffic and overhead, since only the actual data byte being transmitted needs be sent to the transmit buffer. Each channel has its own configurable Transmit and Receive buffer. The upper byte of each received word provides status information for that word.

Multi-Drop Link Mode (RS485)

The transmitter and receivers of up to 32 channels can be tied together in either Half or Full-Duplex mode. While in Multi-Drop Link Mode, the transmit line for each channel will automatically tri-state. When data in the transmit buffer is initiated, the transmitter will be taken out of tri-state and send the data. Once transmission is completed, the transmit line is automatically changed back to tri-state mode. To program the serial channel for Multi-Drop mode, the interface level must be set to RS485, and the Tristate Transmit Line bit in the Channel Control register must be set to a 1.

Communication Module Factory Defaults: Registers and Delays

Address Recognition:	Off
Baud Rate:	2580
CTS/RTS:	Disabled
Protocol:	0, Asynchronous
Interface Levels:	5 (Tri-state mode)
Termination Character:	0x0003
Interrupt Level:	0
Interrupt Vector:	0x00
Mode:	Asynchronous
Number of Data Bits:	8
Parity:	Disabled
Receivers:	Disabled
Transmit Buffer Word Count:	0
Receive Buffer Word Count:	0
Receive Buffer, Almost Full:	0x666
Stop Bits:	1
Transmit Buffer, Almost Empty:	0x019A
Tx-Rx Configuration:	0
Channel Control:	0
Data Configuration:	0x0108
Preamble:	0
Receive Buffer High Watermark:	0x0666
Receive Buffer Low Watermark:	0x019A
XON:	0x0011h
XOFF:	0x0013h
XON/XOFF:	Disabled
Time Out Value:	0x9C40

A write to the following registers takes place immediately:

• Transmit Data

• Channel Control

• Channel Interrupt Enable

• Channel Interrupt Edge/Level

• Summary Interrupt Enable

• Summary Edge/Level

• Interrupt Vector

• Interrupt Steering

For all other registers, channel configuration protocol must be followed.

Status and Interrupts

The Serial Communications Function provides registers that indicate faults or events. Refer to “Status and Interrupts Module Manual” for the Principle of Operation description.

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, a description of the function and, in most cases, a data table.

Receive Registers

Serial data received are placed in the Receive FIFO Buffer register. The Receive FIFO Buffer Word Count provide the count of the number of elements in the Receive FIFO Buffer. The Receive FIFO Buffer Almost Full, Receive FIFO Buffer High Watermark and Receive FIFO Buffer Low Watermark registers provide the ability to specify the thresholds for the associated status in the Channel FIFO Status register.

Receive FIFO Buffer
Function:	Received data is placed in this buffer.
Type:	unsigned binary word (32-bit).
Data Range:	0x 0000 0000 to 0x 0000 FFFF
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	Data is received is based on Protocol.

Note

BOF is defined as the first data message received after a frame opens (dependent on channel configuration).

Note

EOF is defined as the last message received (dependent on channel configuration).

Note

Receive FIFO Buffer is a self-clearing register. Performing a register read of the Receive FIFO marks the current location as ‘read’. This moves the pointer to the next unread location and decrements the Receive FIFO Buffer Word Count register count by one.

Asynchronous/Asynchronous-GPI

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

PE

FE

0

0

0

EOF

P

D

D

D

D

D

D

D

D

D

Bi-Synchronous/Mono-Synchronous

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

EOF

0

D

D

D

D

D

D

D

D

HDLC

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

BOF

0

ER1

ER1

ER0

EOF

0

D

D

D

D

D

D

D

D

Asynchronous/Asynchronous-GPI
PE	= Parity Error	A 1 indicates the calculated parity does not match the received parity bit.
FE	= Framing Error	A 1 indicates a framing error was detected.
EOF	= End of Frame	A 1 indicates an ETx character was received. Termination Character Detection must be turned on.
P	= Parity Bit	This bit carries the parity bit of the last received character.
Bi-Synchronous/Mono-Synchronous
EOF	= End of Frame	A 1 indicates the End of Frame. Useful to identify multiple frames in large buffer.
HDLC
BOF	= Beginning of Frame	A 1 indicates first character of frame. Useful to identify multiple frames in large buffer.
EOF	= End of Frame	A 1 indicates End of Frame. Useful to identify multiple frames in large buffer.
ER2:ER0	= Last Frame Status	000 = Good Frame + 111 = CRC Error

Receive FIFO Buffer Word Count
Function:	Contains the number of words in the Receive FIFO Buffer waiting to be read back.
Type:	unsigned binary word (32-bits)
Data Range:	0 to 0x0000 0800 (Buffer Size)
Read/Write:	R
Initialized Value:	0
Operational Settings:	Reads Integers.

Receive FIFO Buffer Almost Full
Function:	Specifies the maximum size, in bytes, of the receive buffer before the Receive FIFO Almost Full Status bit D0 in the FIFO Status register is flagged (High True).
Type:	unsigned binary word (32-bits)
Data Range:	0 to 0x0000 0800 (Buffer Size)
Read/Write:	R/W
Initialized Value:	1638 (0x0000 0666)
Operational Settings:	If the interrupt is enabled (see Interrupt Enable register), a System interrupt will be generated.

Receive FIFO Buffer High Watermark
Function:	Defines the Receive Buffer High Watermark value.
Type:	unsigned binary word (32-bits)
Data Range:	Low Watermark < High Watermark < 0x666
Read/Write:	R/W
Initialized Value:	1638 (0x666)
Operational Settings:	When Receive FIFO Buffer size equals the High Watermark value, the High Watermark bit in both the FIFO Status and Channel Status registers is set to a 1 and: If XON/XOFF is enabled, XOFF is sent, and/or If RTS/CTS is enabled, RTS goes inactive. The Watermark registers are used for XON/XOFF and/or RTS/CTS flow control. The Receive Buffer High Watermark register value controls when the XOFF character is sent when using software flow control and controls when the RTS signal would be negated when using hardware flow control. For software flow control operation, the XOFF character would be sent once when the number of bytes in the Receive FIFO Buffer equals the value in the Receive Buffer High Watermark register. Once the XOFF has been sent, it cannot be sent again until the XON character has been sent. The valid state transitions to sending the XOFF character can be either no previous XON/XOFF character sent or a previous XON character sent. There is also a High Watermark Reached interrupt enable/disable bit in the Channel Interrupt Enable register and a High Watermark Reached bit in the Channel Interrupt Status Register. When the High Watermark is reached, an interrupt request will be generated, when the interrupt enable/disable bit is enabled.

Receive FIFO Buffer Low Watermark
Function:	Defines the Receive Buffer Low Watermark value.
Type:	unsigned binary word (32-bits)
Data Range:	0 < Low Watermark < High Watermark < 0x666
Read/Write:	R/W
Initialized Value:	410 (0x019A)
Operational Settings:	When Receive Buffer size equals the Low Watermark value, the Low Watermark bit in both the FIFO Status and Channel Status registers is set to a 1 and: If XON/XOFF is enabled, XON is sent, and/or If RTS/CTS is enabled, RTS goes active. The Watermark registers are used for XON/XOFF and/or RTS/CTS flow control. The Receive Buffer Low Watermark register value controls when the XON character is sent when using software flow control and controls when the RTS signal would be asserted when using hardware flow control. For software flow control operation, the XON character would be sent once when the number of bytes in the Receive FIFO Buffer equals the value in the Receive Buffer Low Watermark register AND an XOFF character has been sent prior to this XON character. The valid state transition to sending the XON character can only be from the state of a previous XOFF character that has been sent. There is a Low Watermark Reached interrupt enable/disable bit in the Channel Interrupt Enable register and a Low Watermark Reached bit in the Channel Interrupt Status Register. When the Low Watermark is reached, an interrupt request will be generated, when the interrupt enable/disable bit is enabled.

Transmit Registers

Serial data to be transmitted are placed in the Transmit FIFO Buffer register. The Transmit FIFO Buffer Word Count provides the count of the number of elements in the Transmit FIFO Buffer. The Transmit FIFO Buffer Almost Empty register provide the ability to specify the threshold for the associated status in the Channel FIFO Status register.

Transmit FIFO Buffer
Function:	Data to be transmitted is placed in this buffer prior to transmission.
Type:	unsigned binary word (32-bits)
Data Range:	0x 0000 0000 to 0x 0000 01FF
Read/Write:	W
Initialized Value:	Not Applicable (N/A)
Operational Settings:	Data words are 8-bit and occupy the register's lowest significant bits (LSBs), or low byte.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	D1	D	D	D	D	D	D	D	D

Note ¹: Data only in Asynchronous mode when data bits are set to 9.

Transmit FIFO Buffer Word Count
Function:	Contains the number of words in the Transmit FIFO Buffer waiting to be transmitted.
Type:	unsigned binary word (32-bits)
Data Range:	0 to 0x0000 0800 (Buffer Size)
Read/Write:	R
Initialized Value:	0

Transmit FIFO Buffer Almost Empty
Function:	Specifies the minimum size, in bytes, of the transmit buffer before the Transmit Buffer Almost Empty Status bit D1 in the FIFO Status register is flagged (High True).
Type:	unsigned binary word (32-bits)
Data Range:	0 to 0x0000 0800 (Buffer Size)
Read/Write:	R/W
Initialized Value:	410 (0x19A)
Operational Settings:	If the interrupt is enabled (see Interrupt Enable register), a System interrupt will be generated.

Configuration Registers

SC3 configurations includes setting the Interface Levels, Baud Rate, Protocol, Tx-Rx Configuration and if applicable, the Termination Character registers. Additional registers need to be configured specifically for Async or Sync modes.

Interface Levels
Function:	Configures the interface level (RS-232, RS-422, RS-485, Loopback, Tri-State, FPGA Loop-Back, GPIO) for the associated channel.
Type:	unsigned binary word (32-bits)
Data Range:	See table
Read/Write:	R/W
Initialized Value:	5 (Tri-State)
Operational Settings:	Loopback selection connects the channel's transmit and receive line internally. To implement, user must send data and look at Receive FIFO to verify that the sent data. Loopback is usually used for testing. Notes: Channels are programmed for loop back in pairs. For example, if channel 1 is programmed for loop back, then channel 2 will be also. This includes channels 3 and 4.

Bit(s)	Interface	Description
D31:D15	Reserved	Set Reserved bits to 0.
D14	GPIO	Needs to be ORed with either RS232 or RS422.
D13:D8	Reserved	Set Reserved bits to 0.
D7	Disable termination resistor	Disables termination resistor in-between the differential pairs of the transmitter and the receiver. Useful for RS485 Multi-Drop.
D6:D3	Reserved	Set Reserved bits to 0.
D2:D0	Interface Level	These bits set the interface level: (0:0:0) RS232 ` (0:1:0) RS422 ` (0:1:1) RS485 ` (1:0:0) Loopback ` (1:0:1) Tri-State

Baud Rate
Function:	Sets the baud rate for communications.
Type:	unsigned binary word (32-bits)
Data Range:	300 bps to 10 Mbps Sync (1.5 Mbps Async)
Read/Write:	R/W
Initialized Value:	9600 bps

Protocol
Function:	Configures the associated channel for either asynchronous, mono-synchronous, bi-synchronous, HDLC mode or mixed asynchronous and GPIO modes.
Type:	unsigned binary word (32-bits)
Data Range:	See table
Read/Write:	R/W
Initialized Value:	0 (Asynchronous)
Operational Settings:	See table below.

Bit(s)	Protocol	Description
D31:D6	Reserved	Set Reserved bits to 0.
D5:D0	0x00 - Async ` 0x01 - Mono-Synchronous ` 0x02 - Bi-Synchronous ` 0x03 - HDLC ` 0x10 - Async-GPO + 0x20 - Async-GPI	Async-GPO: This mode can transmit general purpose signals on the channels transmitter while being able to receive async serial data on the receiver. Async-GPI: This mode can transmit async serial data on the channels transmitter while being able to receive general purpose signals on the receiver.

Tx-Rx Configuration
Function:	Sets the transmit/receive configuration for the associated channel.
Type:	unsigned binary word (32-bits)
Data Range:	See table
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	BIT - Set Enable Channel bit, D24 low (0) to clear the selected channel. Set Initiate BIT bit D27 high (1) to initiate BIT. After 5 msec, a 0 should be read, which indicates that the BIT test is complete. The BIT Status register reports the channel status.

Bit(s)	Name	Description
D31:D28	Reserved	Set Reserved bits to 0.
D27	Initiate BIT	Write a 1 to start built-in-test. The channel running BIT needs to be disabled, as well as it's channel pair. For common module functionality see the Test Enabled register.
D26	Invert RTS/GPO	0 = Normal + 1 = Invert.
D25	Invert CTS/GPI	0 = Normal + 1 = Invert.
D24	Enable Channel	0 = Disable + 1 = Enable.
D23	Rx Suppression	0 = Receiver Always On + 1 = Receiver Off During Transmission (RS485 only)
D22	Reserved	Set Reserved bits to 0.
D21	Idle Flag	Idle Flag (0x7E) Transmission
D20	Enable Gap Timeout	0 = Ignore gap timeout + 1 = Set Gap Timeout Occurred status when there is no activity on the receiver's bus for more than 3-byte times.
D19	Append CRC	0 = No CRC + 1 = Append CRC to Tx Data, Expect CRC with Rx data
D18:D17	CRC	(0:0) 16-Bit CRC (Mono/Bi-Sync only) ` (0:1) 32-Bit CRC (HDLC only) ` (1:0) 16-Bit CCITT
D16	CRC Reset Value	0 = Ones + 1 = Zeros
D15	Timeout Detection	Turns on timeout detection
D14	XON/XOFF Char as Data	0 = Stripped + 1 = Keep in data
D13	XON/XOFF Flow Control	Turns on Software Flow Control
D12	Termination Character Detection	0 = Ignore termination character + 1 = Set Rx Complete/ETx Received status bit when termination character is received.
D11	Sync char as data	0 = Stripped + 1 = Keep in data
D10:D8	Reserved	Set Reserved bits to 0.
D7	Address Length	0 = 8 bits + 1 = 16 bits
D6:D4	Address Transmission/Recognition (HLDC only): 0x0 - Addressing Off ` 0x1 - Rx Address Recognition only ` 0x2 - Tx Address Transmission only + 0x4 - Addressing On	Addressing Off: Don't send address, receive data from any address. Rx Address Recognition: Expect address on Rx, but don't send address. Tx Address Transmission: Send address, but don't expect it. Addressing On: Send and expect address.
D3:D1	Reserved	Set Reserved bits to 0.
D0	RTS/CTS Flow Control	Turns on Hardware Flow Control

Termination Character
Function:	Contains the termination character used for termination detection.
Type:	unsigned character (usually a member of the ASCII data set)
Data Range:	0x00 to 0xFF
Read/Write:	R/W
Initialized Value:	0x03
Operational Settings:	When using the Asynchronous or Mono/Bi-Synchronous modes, the receive data stream is monitored for the occurrence of the termination character. When this character is detected, the Rx COMPLETE / ETx RECEIVED bit is set in the Channel Status register, an interrupt is generated, if enabled.

Async Only Configuration

In Async mode, additional configurations include setting the Data Configuration, Time Out Value, XOFF Character and XON Character registers.

Data Configuration
Function:	Channel data configuration.
Type:	unsigned binary word (32-bits)
Data Range:	See table
Read/Write:	R/W
Initialized Value:	0x108
Operational Settings:	Sets up the Serial channel configuration.

Bit(s)	Name	Description
D31:D15	Reserved	Set Reserved bits to 0.
D14:D12	Encoding	The following sets the Data Encoding: (0:0:0) No Encoding (NRZ) ` (1:1:0) Manchester (GE Thomas) ` (1:1:1) Manchester (IEEE 802.3)
D11:D10	Reserved	Set Reserved bits to 0.
D9:D8	Stop Bits	The following sets the number of stop bits: (0:1) 1 Stop bit + (1:0) 2 Stop bits
D7	Reserved	Set Reserved bits to 0.
D6:D4	Parity	The following sets the Parity: (0:0:0) No Parity ` (0:0:1) Space Parity ` (0:1:0) Reserved ` (0:1:1) Odd Parity ` (1:0:0) Reserved ` (1:0:1) Even Parity ` (1:1:1) Mark Parity
D3:D0	Number of Data Bits	Actual number of data bits between 5 and 9. For Asynchronous Protocol only.

Time Out Value
Function:	Determines the timeout period.
Type:	unsigned binary word (32-bits)
Data Range:	0 to 0xFFFF
Read/Write:	R/W
Initialized Value:	0x9C40 (1 second)
Operational Settings:	If there is no receive line activity for the configured period of time, a timeout is indicated in the Interrupt Status register, bit D10. LSB is 25µs. Modes Affected: Async.

XON Character
Function:	Specifies the XON character for asynchronous flow control mode.
Type:	unsigned binary word 32-bits (usually a member of the ASCII dataset)
Data Range:	0x00 to 0xFF
Read/Write:	R/W
Initialized Value:	0x11
Modes Affected:	Async
Operational Settings:	When software flow control is enabled, this value is sent as the XON character.

XOFF Character
Function:	Specifies the XOFF character for asynchronous software flow control mode.
Type:	unsigned binary word 32-bits (usually a member of the ASCII data set)
Data Range:	0x00 to 0xFF
Read/Write:	R/W
Initialized Value:	0x13
Modes Affected:	Async
Operational Settings:	When software flow control is enabled, this value is sent as the XOFF character.

Sync Only Configuration

In Sync mode, additional configurations include setting the Clock Mode, HDLC Rx Address/Sync Character and HDLC Tx Address/Sync Character registers.

Clock Mode

Clock Mode
Function:	Configures clock for internal (driven) or external (received) transmit/receive clocks
Type:	unsigned binary word (32-bits)
Data Range:	See table.
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Applicable only for Mono/bi-synchronous or HDLC as set by Protocol register.
Default:	0

Bit(s)	Name	Description
D31:D8	Reserved	Set Reserved bits to 0.
D7	Invert Rx Clock	Swap receive clock edge.
D6	Invert Tx Clock	Swap transmit clock edge.
D5	Tristate Clock after Tx
D4:D2	Reserved	Set Reserved bits to 0.
D1:D0	Clock Mode 0x0: Internal ` 0x1: External ` 0x2: Tx-Internal, Rx-External + 0x3: Reserved	Internal: Module always drives clock. External: Module always receives clock. Tx-Internal, Rx-External: Module drives clock for Tx, Module receives clock for Rx.

HDLC Rx Address/Sync Character
Function:	Mode dependent for HDLC and Synchronous modes. See Operational Settings.
Type:	unsigned binary word (32-bits)
Data Range:	0x0000 to 0xFFFF
Read/Write:	R/W
Initialized Value:	0xA5
Operational Settings:	HDLC Mode: This value is compared to the address of the received message and if it's equal, the message is stored in the receive buffer. Mono/Bi-Synchronous Mode: this value is considered the “Sync Character” and is used for communication synchronization. The receiver searches incoming data for the Sync Character. Once found, communication is synchronized, and additional data is valid. When in Bi-Synchronous, low byte is sent before high byte.

HDLC

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

8-bit address when Address Length bit in Tx-Rx Configuration register is 0.

16-bit address when Address Length bit in Tx-Rx Configuration register is 1.

Mono-Synchronous

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

8-bit synchronization character

Bi-Synchronous

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Second 8-bit synchronization character

First 8-bit synchronization character

HDLC Tx Address/Sync Character
Function:	Mode dependent for HDLC and Synchronous modes. See Operational Settings.
Type:	unsigned binary word (32-bits)
Data Range:	0x0000 to 0xFFFF
Read/Write:	R/W
Initialized Value:	0xA5
Operational Settings:	If using HDLC Mode: this value is compared to the address of the received message and if it's equal, the message is stored in the receive buffer. Mono/Bi-Synchronous Mode: this value is considered the “Sync Character” and is used for communication synchronization. The receiver searches incoming data for the Sync Character. Once found, communication is synchronized, and additional data is valid. When in Bi-Synchronous, low byte is sent before high byte.

Preamble
Function:	Determines the number of preambles and the preamble pattern sent during a preamble transmission.
Type:	unsigned binary word (32-bits)
Data Range:	0x0000 to 0xF0FF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	In HDLC Mode: zero-bit insertion is disabled during preamble transmission.

Bit(s)	Name	Description
D31:D16	Reserved	Set Reserved bits to 0.
D15:D12	Number of Preambles	The number of Preamble Patterns to be sent.
D11:D8	Reserved	Set Reserved bits to 0.
D7:D0	Preamble Pattern	Actual data byte to be sent.

Control Register

The Channel Control register provides control of the serial channel.

Channel Control
Function:	Channel control configuration.
Type:	unsigned binary word (32-bits)
Data Range:	See table.
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Real time control of the Serial channel.

Bit(s)	Name	Description
D31:D19	Reserved	Set Reserved bits to 0.
D18	Enable Receiver
D17	Tx Always (Async Only)	Transmit data as soon as data is buffered.
D16	Tx Initiate	Transmit data in Tx buffer. (The data bit is cleared when all data from the Tx Buffer is transmitted)
D15	Clear Tx FIFO	Clear all data in the Tx FIFO. The data bit is self-clearing.
D14	Clear Rx FIFO	Clear all data in the Rx FIFO. The data bit is self-clearing.
D13	Reset Channel FIFOs & UART	Clear both FIFOs and reset channel. Bit is not self-clearing.
D12:D11	Reserved	Set Reserved bits to 0.
D10	Set/Release Break	0 = Break not set + 1 = Pull transmitter low
D9	Reserved	Set Reserved bits to 0.
D8	Tristate Transmit Line	Tristate the transmit line after transmitting, for use with RS485 Multi-Drop mode.
D7:D2	Reserved	Set Reserved bits to 0.
D1	GPO 2	General purpose output two control.
D0	RTS/GPO 1*	General purpose output one control.

Note

*RTS/CTS as GPO when RTS/CTS Flow Control disabled.

Serial Test Registers

The inboard serial communications function provides the ability to run an initiated test (IBIT). Writing a 1 to the bit associated with the channel in the Test Enabled register.

Note

This register has the same effect as writing a 1 to the Initiate BIT bit of the Tx-Rx Configuration register for legacy applications.

Test Enabled
Function:	Set the bit corresponding to the channel you want to run Initiated Built-In-Test.
Type:	unsigned binary word (32-bit)
Data Range:	0 to 0x0000 000F
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	Set bit to 1 for channel to run an Initiated BIT test. Failures in the BIT test are reflected in the BIT Status registers for the corresponding channels that fail. In addition, an interrupt (if enabled in the BIT Interrupt Enable register) can be triggered when the BIT testing detects failures. Bit is self-clearing.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	Ch4	Ch3	Ch2	Ch1

Status and Interrupt Registers

The inboard serial communications function provides status registers for BIT, Channel, Summary and Channel FIFO.

BIT Status

There are four registers associated with the BIT Status: Dynamic Status, Latched Status, Interrupt Enable, and Set Edge/Level Interrupt.

BIT Status
Function:	Sets the corresponding bit associated with the channel's BIT error.
Type:	unsigned binary word (32-bits)
Data Range:	0x0000 0000 to 0x0000 000F
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Note

BIT Status is a shared register between the DT and SC functions. Bits D0:D11 are dedicated to the DT function, and bits D19:D16 are dedicated to the SC function.

BIT Dynamic Status

BIT Latched Status

BIT Interrupt Enable

BIT Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

SC Ch4

SC Ch3

SC Ch2

SC Ch1

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

DT Ch12

DT Ch11

DT Ch10

DT Ch9

DT Ch8

DT Ch7

DT Ch6

DT Ch5

DT Ch4

DT Ch3

DT Ch2

DT Ch1

Power-on BIT (PBIT) Complete

After power-on, the Power-on BIT Complete register should be checked to ensure that POST/PBIT/SBIT test is complete before reading the BIT Dynamic Status and BIT Latched Status registers.

Power-on BIT (PBIT) Complete
Function:	Indication if Power-on BIT has completed.
Type:	unsigned binary word (32-bits)
Data Range:	0x0000 0000 to 0x0000 0001
Read/Write:	R
Initialized Value:	0

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	PBIT Complete

Channel Status
Function:	Sets the corresponding bit associated with each event type. There are separate registers for each channel.
Type:	unsigned binary word (32-bits)
Data Range:	See table.
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value:	0

Channel Dynamic Status
Channel Latched Status
Channel Interrupt Enable
Channel Set Edge/Level Interrupt
Bit(s)	Name	Configurable	Description
D31	Channel Configured	No	Module is configured and ready to operate.
D30	Built-in-Self Test Passed	No	Indicates the status of the last ran IBIT test.
D29:D18	Reserved	No	Set Reserved bits to 0.
D17	Gap Timeout Occurred	Yes	Rx FIFO has data in it, but there hasn't been activity on the bus in 3-byte times.
D16	GPI 2	No	Binary value of general-purpose input 2.
D15	CTS/GPI1	No	Binary value of general-purpose input 1 or CTS.
D14	CTS Low Detect (fall)	No	CTS falling edge detected.
D13	CTS High Detect (rise)	No	CTS rising edge detected.
D12	Reserved	No	Set Reserved bits to 0.
D11	Break/Abort	No	Break recognized.
D10	Timeout Occurred	Yes	No receive line activity within timeout value.
D9	Tx Complete	No	While transmitting, Tx FIFO count reaches zero.
D8	Tx FIFO Almost Empty	Yes	Transmit FIFO Almost Empty Threshold reached.
D7	Low Watermark Reached	Yes	Rx Buffer Low Watermark Threshold reached.
D6	High Watermark Reached	Yes	Rx Buffer High Watermark Threshold reached.
D5	Rx Overrun	No	Data was received while the Rx FIFO was full.
D4	Rx Data Available	No	Receive FIFO count is greater than zero.
D3	Rx Complete/ET x Received	No	Async: Termination character received (Only if termination detection is turned on.) ` HDLC: End of frame flag detected. ` Mono/Bi-Sync: Termination character received.
D2	CRC Error (Sync & HDLC)	No	CRC calculation did not match.
D1	Rx FIFO Almost Full	Yes	Receive FIFO Almost Full Threshold
D0	Parity Error	No	Parity bit did not match.

Note

For the Latched Channel Status register, the interrupts are cleared when a 1 is written to the specific bit.

Channel FIFO Status
Function:	Describes current FIFO Status.
Type:	unsigned binary word (32-bits)
Data Range:	See Table
Read/Write:	R
Initialized Value:	0
Operational Settings:	See Rx Almost Full, Tx Almost Empty, Rx High Watermark and Rx Low Watermark specific registers for function description and programming.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	D	D	D	D	D	D

Bit(s)	Name	Configurable?	Description
D5	Tx FIFO Full	No	Tx FIFO has reached maximum buffer size.
D4	Rx FIFO Empty	No	Rx FIFO count is zero.
D3	Low Watermark Reached	Yes	Rx Buffer Low Watermark Threshold reached.
D2	High Watermark Reached	Yes	Rx Buffer High Watermark Threshold reached.
D1	Tx FIFO Almost Empty	Yes	Tx FIFO Almost Empty Threshold reached.
D0	Rx FIFO Almost Full	Yes	Rx FIFO Almost Full Threshold reached

Function Register Map

KEY

Incoming Data

Outgoing Data

Configuration/Control

Status

RECEIVE REGISTERS
NOTE: Base Address - 0x9018 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1004	Receive FIFO Buffer Ch 1	R	0x100C	Receive FIFO Buffer Word Count Ch 1	R
0x1084	Receive FIFO Buffer Ch 2	R	0x108C	Receive FIFO Buffer Word Count Ch 2	R
0x1104	Receive FIFO Buffer Ch 3	R	0x110C	Receive FIFO Buffer Word Count Ch 3	R
0x1184	Receive FIFO Buffer Ch 4	R	0x118C	Receive FIFO Buffer Word Count Ch 4	R
0x1034	Receive FIFO Buffer Almost Full Ch 1	R/W	0x1038	Receive FIFO Buffer High Watermark Ch 1	R/W
0x10B4	Receive FIFO Buffer Almost Full Ch 2	R/W	0x10B8	Receive FIFO Buffer High Watermark Ch 2	R/W
0x1134	Receive FIFO Buffer Almost Full Ch 3	R/W	0x1138	Receive FIFO Buffer High Watermark Ch 3	R/W
0x11B4	Receive FIFO Buffer Almost Full Ch 4	R/W	0x11B8	Receive FIFO Buffer High Watermark Ch 4	R/W
0x103C	Receive FIFO Buffer Low Watermark Ch 1	R/W
0x10BC	Receive FIFO Buffer Low Watermark Ch 2	R/W
0x113C	Receive FIFO Buffer Low Watermark Ch 3	R/W
0x11BC	Receive FIFO Buffer Low Watermark Ch 4	R/W
TRANSMIT REGISTERS
NOTE: Base Address - 0x9018 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1000	Transmit FIFO Buffer Ch 1	W	0x1008	Transmit FIFO Buffer Word Count Ch 1	R
0x1080	Transmit FIFO Buffer Ch 2	W	0x1088	Transmit FIFO Buffer Word Count Ch 2	R
0x1100	Transmit FIFO Buffer Ch 3	W	0x1108	Transmit FIFO Buffer Word Count Ch 3	R
0x1180	Transmit FIFO Buffer Ch 4	W	0x1188	Transmit FIFO Buffer Word Count Ch 4	R
0x1030	Transmit FIFO Buffer Almost Empty Ch 1	R/W
0x10B0	Transmit FIFO Buffer Almost Empty Ch 2	R/W
0x1130	Transmit FIFO Buffer Almost Empty Ch 3	R/W
0x11B0	Transmit FIFO Buffer Almost Empty Ch 4	R/W
CONFIGURATION REGISTERS
NOTE: Base Address - 0x9018 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1018	Interface Levels Ch 1	R/W	0x1028	Baud Rate Ch 1	R/W
0x1098	Interface Levels Ch 2	R/W	0x10A8	Baud Rate Ch 2	R/W
0x1118	Interface Levels Ch 3	R/W	0x1128	Baud Rate Ch 3	R/W
0x1198	Interface Levels Ch 4	R/W	0x11A8	Baud Rate Ch 4	R/W
0x1010	Protocol Ch 1	R/W	0x101C	Tx-Rx Configuration Ch 1	R/W
0x1090	Protocol Ch 2	R/W	0x109C	Tx-Rx Configuration Ch 2	R/W
0x1110	Protocol Ch 3	R/W	0x111C	Tx-Rx Configuration Ch 3	R/W
0x1190	Protocol Ch 4	R/W	0x119C	Tx-Rx Configuration Ch 4	R/W
0x1050	Termination Character Ch 1	R/W
0x10D0	Termination Character Ch 2	R/W
0x1150	Termination Character Ch 3	R/W
0x11D0	Termination Character Ch 4	R/W
ASYNC ONLY CONFIGURATION REGISTERS
NOTE: Base Address - 0x9018 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1024	Data Configuration Ch 1	R/W	0x1054	Time Out Value Ch 1	R/W
0x10A4	Data Configuration Ch 2_	R/W	0x10D4	Time Out Value Ch 2	R/W
0x1124	Data Configuration Ch 3_	R/W	0x1154	Time Out Value Ch 3	R/W
0x11A4	Data Configuration Ch 4_	R/W	0x11D4	Time Out Value Ch 4	R/W
0x1048	XON Character Ch 1	R/W	0x104C	XOFF Character Ch 1	R/W
0x10C8	XON Character Ch 2	R/W	0x10CC	XOFF Character Ch 2	R/W
0x1148	XON Character Ch 3	R/W	0x114C	XOFF Character Ch 3	R/W
0x11C8	XON Character Ch 4	R/W	0x11CC	XOFF Character Ch 4	R/W
SYNC ONLY CONFIGURATION REGISTERS
NOTE: Base Address - 0x9018 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1014	Clock Mode Ch 1	R/W	0x1040	HDLC Rx Address/Sync Character Ch 1	R/W
0x1094	Clock Mode Ch 2	R/W	0x10C0	HDLC Rx Address/Sync Character Ch 2	R/W
0x1114	Clock Mode Ch 3	R/W	0x1140	HDLC Rx Address/Sync Character Ch 3	R/W
0x1194	Clock Mode Ch 4	R/W	0x11C0	HDLC Rx Address/Sync Character Ch 4	R/W
0x1044	HDLC Tx Address/Sync Character Ch 1	R/W	0x102C	Preamble Ch 1	R/W
0x10C4	HDLC Tx Address/Sync Character Ch 2	R/W	0x10AC	Preamble Ch 2	R/W
0x1144	HDLC Tx Address/Sync Character Ch 3	R/W	0x112C	Preamble Ch 3	R/W
0x11C4	HDLC Tx Address/Sync Character Ch 4	R/W	0x11AC	Preamble Ch 4	R/W
CONTROL REGISTERS
NOTE: Base Address - 0x9018 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1020	Channel Control Ch 1	R/W
0x10A0	Channel Control Ch 2	R/W
0x1120	Channel Control Ch 3	R/W
0x11A0	Channel Control Ch 4	R/W
BIT REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0800	Dynamic Status	R
0x0804	Latched Status*	R/W
0x0808	Interrupt Enable	R/W
0x080C	Set Edge/Level Interrupt	R/W
NOTE: Base Address - 0x9018 C000
0x0248	Test Enabled	R/W	0x02AC	Power-on BIT Complete++	R
++After power-on, Power-on BIT Complete should be checked before reading the BIT Latched Status.
CHANNEL STATUS REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0).
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0900	Channel Dynamic Status Ch 1	R	0x0910	Channel Dynamic Status Ch 2	R
0x0904	Channel Latched Status Ch 1*	R/W	0x0914	Channel Latched Status Ch 2*	R/W
0x0908	Channel Interrupt Enable Ch 1	R/W	0x0918	Channel Interrupt Enable Ch 2	R/W
0x090C	Channel Set Edge/Level Interrupt Ch 1	R/W	0x091C	Channel Set Edge/Level Interrupt Ch 2	R/W
0x0920	Channel Dynamic Status Ch 3	R	0x0930	Channel Dynamic Status Ch 4	R
0x0924	Channel Latched Status Ch 3*	R/W	0x0934	Channel Latched Status Ch 4*	R/W
0x0928	Channel Interrupt Enable Ch 3	R/W	0x0938	Channel Interrupt Enable Ch 4	R/W
0x092C	Channel Set Edge/Level Interrupt Ch 3	R/W	0x093C	Channel Set Edge/Level Interrupt Ch 4	R/W
FIFO STATUS REGISTER
NOTE: Base Address - 0x9018 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1058	FIFO Status Ch 1	R
0x10D8	FIFO Status Ch 2	R
0x1158	FIFO Status Ch 3	R
0x11D8	FIFO Status Ch 4	R

APPENDIX B: INBOARD MODULE STATUS AND INTERRUPTS

Status registers indicate the detection of faults or events. The status registers can be channel bit-mapped or event bit-mapped. An example of a channel bit-mapped register is the BIT status register, and an example of an event bit-mapped register is the FIFO status register.

For those status registers that allow interrupts to be generated upon the detection of the fault or the event, there are four registers associated with each status: Dynamic, Latched, Interrupt Enabled, and Set Edge/Level Interrupt.

Dynamic Status: The Dynamic Status register indicates the current condition of the fault or the event. If the fault or the event is momentary, the contents in this register will be clear when the fault or the event goes away. The Dynamic Status register can be polled, however, if the fault or the event is sporadic, it is possible for the indication of the fault or the event to be missed.

Latched Status: The Latched Status register indicates whether the fault or the event has occurred and keeps the state until it is cleared by the user. Reading the Latched Status register is a better alternative to polling the Dynamic Status register because the contents of this register will not clear until the user commands to clear the specific bit(s) associated with the fault or the event in the Latched Status register. Once the status register has been read, the act of writing a 1 back to the applicable status register to any specific bit (channel/event) location will “clear” the bit (set the bit to 0). When clearing the channel/event bits, it is strongly recommended to write back the same bit pattern as read from the Latched Status register. For example, if the channel bit-mapped Latched Status register contains the value 0x0000 0005, which indicates fault/event detection on channel 1 and 3, write the value 0x0000 0005 to the Latched Status register to clear the fault/event status for channel 1 and 3. Writing a “1” to other channels that are not set (example 0x0000 000F) may result in incorrectly “clearing” incoming faults/events for those channels (example, channel 2 and 4).

Interrupt Enable: If interrupts are preferred upon the detection of a fault or an event, enable the specific channel/event interrupt in the Interrupt Enable register. The bits in Interrupt Enable register map to the same bits in the Latched Status register. When a fault or event occurs, an interrupt will be fired. Subsequent interrupts will not trigger until the application acknowledges the fired interrupt by clearing the associated channel/event bit in the Latched Status register. If the interruptible condition is still persistent after clearing the bit, this may retrigger the interrupt depending on the Edge/Level setting.

Set Edge/Level Interrupt: When interrupts are enabled, the condition on retriggering the interrupt after the Latch Register is “cleared” can be specified as “edge” triggered or “level” triggered. Note, the Edge/Level Trigger also affects how the Latched Register value is adjusted after it is “cleared” (see below).

• Edge triggered: An interrupt will be retriggered when the Latched Status register change from low (0) to high (1) state. Uses for edge-triggered interrupts would include transition detections (Low-to-High transitions, High-to-Low transitions) or fault detections. After “clearing” an interrupt, another interrupt will not occur until the next transition or the re-occurrence of the fault again.

• Level triggered: An interrupt will be generated when the Latched Status register remains at the high (1) state. Level-triggered interrupts are used to indicate that something needs attention.

Interrupt Vector and Steering

When interrupts are enabled, the interrupt vector associated with the specific interrupt can be programmed with a unique number/identifier defined by the user such that it can be utilized in the Interrupt Service Routine (ISR) to identify the type of interrupt. When an interrupt occurs, the contents of the Interrupt Vector registers is reported as part of the interrupt mechanism. In addition to specifying the interrupt vector, the interrupt can be directed (“steered”) to the native bus or to the application running on the onboard ARM processor.

Interrupt Trigger Types

In most applications, limiting the number of interrupts generated is preferred as interrupts are costly, thus choosing the correct Edge/Level interrupt trigger to use is important.

Example 1: Fault detection

This example illustrates interrupt considerations when detecting a fault like an “open” on a line. When an “open” is detected, the system will receive an interrupt. If the “open” on the line is persistent and the trigger is set to “edge”, upon “clearing” the interrupt, the system will not regenerate another interrupt. If, instead, the trigger is set to “level”, upon “clearing” the interrupt, the system will re-generate another interrupt. Thus, in this case, it will be better to set the trigger type to “edge”.

Example 2: Threshold detection

This example illustrates interrupt considerations when detecting an event like reaching or exceeding the “high watermark” threshold value. In a communication device, when the number of elements received in the FIFO reaches the high-watermark threshold, an interrupt will be generated. Normally, the application would read the count of the number of elements in the FIFO and read this number of elements from the FIFO. After reading the FIFO data, the application would “clear” the interrupt. If the trigger type is set to “edge”, another interrupt will be generated only if the number of elements in FIFO goes below the “high watermark” after the “clearing” the interrupt and then fills up to reach the “high watermark” threshold value. Since receiving communication data is inherently asynchronous, it is possible that data can continue to fill the FIFO as the application is pulling data off the FIFO. If, at the time the interrupt is “cleared”, the number of elements in the FIFO is at or above the “high watermark”, no interrupts will be generated. In this case, it will be better to set the trigger type to “level”, as the purpose here is to make sure that the FIFO is serviced when the number of elements exceeds the high watermark threshold value. Thus, upon “clearing” the interrupt, if the number of elements in the FIFO is at or above the “high watermark” threshold value, another interrupt will be generated indicating that the FIFO needs to be serviced.

Dynamic and Latched Status Registers Examples

The examples in this section illustrate the differences in behavior of the Dynamic Status and Latched Status registers as well as the differences in behavior of Edge/Level Trigger when the Latched Status register is cleared.

Figure B1. Example of Module’s Channel-Mapped Dynamic and Latched Status States

		No Clearing of Latched Status	Clearing of Latched Status ` (Edge-Triggered) 2`		Clearing of Latched Status + (Level-Triggered)	Time
Dynamic Status	Latched Status	Action	Latched Status	Action	Latched	T0
0x0	0x0	Read Latched Register	0x0	Read Latched Register	0x0	T1
0x1	0x1	Read Latched Register	0x1		0x1
		Write 0x1 to Latched Register		Write 0x1 to Latched Register
			0x0		0x1	T2
0x0	0x1	Read Latched Register	0x0	Read Latched Register	0x1
				Write 0x1 to Latched Register
					0x0	T3
0x2	0x3	Read Latched Register	0x2	Read Latched Register	0x2
		Write 0x2 to Latched Register		Write 0x2 to Latched Register
			0x0		0x2	T4
0x2	0x3	Read Latched Register	0x1	Read Latched Register	0x3
		Write 0x1 to Latched Register		Write 0x3 to Latched Register
			0x0		0x2	T5
0xC	0xF	Read Latched Register	0xC	Read Latched Register	0xE
		Write 0xC to Latched Register		Write 0xE to Latched Register
			0x0		0xC	T6
0xC	0xF	Read Latched Register	0x0	Read Latched	0xC
				Write 0xC to Latched Register
					0xC	T7
0x4	0xF	Read Latched Register	0x0	Read Latched Register	0xC
				Write 0xC to Latched Register
					0x4	T8
0x4	0xF	Read Latched Register	0x0	Read Latched Register	0x4

Interrupt Examples

The examples in this section illustrate the interrupt behavior with Edge/Level Trigger.

Figure B2. Illustration of Latched Status State for Module with 4-Channels with Interrupt Enabled

Time	Latched Status ` (Edge-Triggered - Clear Multi-Channel) 2`		Latched Status ` (Edge-Triggered - Clear Single Channel) 2`	Latched Status + (Level-Triggered - Clear Multi-Channel)	Action	Latched
	Action	Latched	Action	Latched	T1 (Int 1)	Interrupt Generated Read Latched Registers
0x1	Interrupt Generated Read Latched Registers	0x1	Interrupt Generated Read Latched Registers	0x1		Write 0x1 to Latched Register
	Write 0x1 to Latched Register		Write 0x1 to Latched Register
0x0		0x0	Interrupt re-triggers Note, interrupt re-triggers after each clear until T2.	0x1	T3 (Int 2)	Interrupt Generated Read Latched Registers
0x2	Interrupt Generated Read Latched Registers	0x2	Interrupt Generated Read Latched Registers	0x2		Write 0x2 to Latched Register
	Write 0x2 to Latched Register		Write 0x2 to Latched Register
0x0		0x0	Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.	0x2	T4 (Int 3)	Interrupt Generated Read Latched Registers
0x1	Interrupt Generated Read Latched Registers	0x1	Interrupt Generated Read Latched Registers	0x3		Write 0x1 to Latched Register
	Write 0x1 to Latched Register		Write 0x3 to Latched Register	.2+		.2+
0x0 .2+	.2+	0x0	Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x3 is reported in Latched Register until T5.	0x3		Interrupt re-triggers Note, interrupt re-triggers after each clear until T7.
0x2	T6 (Int 4)	Interrupt Generated Read Latched Registers	0xC	Interrupt Generated Read Latched Registers	0xC	Interrupt Generated Read Latched Registers
0xE		Write 0xC to Latched Register		Write 0x4 to Latched Register		Write 0xE to Latched Register
.3+			0x0	Interrupt re-triggers Write 0x8 to Latched Register	0x8	Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xE is reported in Latched Register until T7.
0xE .2+		.2+		0x0	Interrupt re-triggers Note, interrupt re-triggers after each clear and 0xC is reported in Latched Register until T8.	0xC
Interrupt re-triggers Note, interrupt re-triggers after each clear and 0x4 is reported in Latched Register always.		0x4

APPENDIX C: INBOARD DISCRETE I/O USER WATCHDOG TIMER FUNCTIONALITY

Principle of Operation

The User Watchdog Timer is optionally activated by the applications that require the module’s outputs to be disabled as a failsafe in the event of an application failure or crash. The circuit is designed such that a specific periodic write strobe pattern must be executed by the software to maintain operation and prevent the disablement from taking place.

The User Watchdog Timer is inactive until the application sends an initial strobe by writing the value 0x55AA to the UWDT Strobe register. After activating the User Watchdog Timer, the application must continually strobe the timer within the intervals specified with the configurable UWDT Quiet Time and UWDT Window registers. The timing of the strobes must be consistent with the following rules:

• The application must not strobe during the Quiet time.
• The application must strobe within the Window time.
• The application must not strobe more than once in a single window time.

A violation of any of these rules will trigger a User Watchdog Timer fault and result in shutting down any isolated power supplies and/or disabling any active drive outputs, as applicable for the specific module. Upon a User Watchdog Timer event, recovery to the module shutting down will require the module to be reset.

Figures C2 and C3 provide an overview and an example with actual values for the User Watchdog Timer Strobes, Quiet Time and Window. As depicted in the diagrams, there are two processes that run in parallel. The Strobe event starts the timer for the beginning of the “Quiet Time”. The timer for the Previous Strobe event continues to run to ensure that no additional Strobes are received within the “Window” associated with the Previous Strobe.

The optimal target for the user watchdog strobes should be at the interval of [Quiet time + ½ Window time] after the previous strobe, which will place the strobe in the center of the window. This affords the greatest margin of safety against unintended disablement in critical operations.

Figure C1. User Watchdog Timer Overview

Figure C2. User Watchdog Timer Example

Figure C3 illustrates examples of User Watchdog Timer failures.

Figure C3. User Watchdog Timer Failures

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

User Watchdog Timer Registers

The registers associated with the User Watchdog Timer provide the ability to specify the UWDT Quiet Time and the UWDT Window that will be monitored to ensure that EXACTLY ONE User Watchdog Timer (UWDT) Strobe is written within the window.

UWDT Quiet Time
Function:	Sets Quiet Time value (in microseconds) to use for the User Watchdog Timer Frame.
Type:	unsigned binary word (32-bit)
Data Range:	0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	LSB = 1 µsec. The application must NOT write a strobe in the time between the previous strobe and the end of the Quiet time interval. In addition, the application must write in the UWDT Window EXACTLY ONCE.
UWDT Window
Function:	Sets Window value (in microseconds) to use for the User Watchdog Timer Frame.
Type:	unsigned binary word (32-bit)
Data Range:	0 µsec to 2^32 µsec (0x0 to 0xFFFFFFFF)
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	LSB = 1 µsec. The application must write the strobe once within the Window time after the end of the Quiet time interval. The application must write in the UWDT Window EXACTLY ONCE. This setting must be initialized to a non-zero value for operation and should allow sufficient tolerance for strobe timing by the application.
UWDT Strobe
Function:	Writes the strobe value to be use for the User Watchdog Timer Frame.
Type:	unsigned binary word (32-bit)
Data Range:	0x55AA
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	At startup, the user watchdog is disabled. Write the value of 0x55AA to this register to start the user watchdog timer monitoring after initial power on or a reset. To prevent a disablement, the application must periodically write the strobe based on the user watchdog timer rules.
UWDT Reset
Function:	Resets the User Watchdog Timer after a failed state.
Type:	unsigned binary word (32-bit)
Data Range:	0 or 1
Read/Write:	R/W
Initialized Value:	0x0
Operational Settings:	After a failed state, writing a 1 to this register will reset the User Watchdog Timer Frame.

Status and Interrupt

The modules that are capable of User Watchdog Timer support provide status registers for the User Watchdog Timer.

User Watchdog Timer Status

The status register that contains the User Watchdog Timer Fault information is also used to indicate channel Inter-FPGA failures on modules that have communication between FPGA components. There are four registers associated with the User Watchdog Timer Fault/Inter-FPGA Failure Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

Function:	Sets the corresponding bit (D31) associated with the channel's User Watchdog Timer Fault error.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Set Edge/Level Interrupt)
Initialized Value:	0

User Watchdog Timer Fault/Inter-FPGA Failure Dynamic Status
User Watchdog Timer Fault/Inter-FPGA Failure Latched Status
User Watchdog Timer Fault/Inter-FPGA Failure Interrupt Enable
User Watchdog Timer Fault/Inter-FPGA Failure Set Edge/Level Interrupt
Bit(s)	Status	Description
D31	User Watchdog Timer Fault Status	0 = No Fault + 1 = User Watchdog Timer Fault
D30:D0	Reserved for Inter-FPGA Failure Status	Channel bit-mapped indicating channel inter-FPGA communication failure detection.

Function Register Map

KEY

Configuration/Control

Measurement/Status

USER WATCHDOG TIMER REGISTERS
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x01C0	UWDT Quiet Time	R/W
0x01C4	UWDT Window	R/W
0x01C8	UWDT Strobe	R/W
0x01CC	UWDT Reset	R/W
STATUS REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0”).
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x09B0	Dynamic Status	R
0x09B4	Latched Status*	R/W
0x09B8	Interrupt Enable	R/W
0x09BC	Set Edge/Level Interrupt	R/W

APPENDIX D: THRESHOLD AND SATURATION CAPABILITY

Principle of Operation

The inboard AD function provides the ability to monitor the acquired data and set a status when the specific thresholds are reached.

Threshold Detect

There are two thresholds that can be independently programmed on the A/D function. These thresholds are used to monitor the acquired data and set a status when the specified thresholds are reached. A configurable hysteresis may also be set to determine when the Threshold Detect registers are cleared. The threshold detection can be configured as a FIFO trigger to capture data based on a specified event. Refer to Figure D1 and Figure D2 for illustrations for Threshold Detect Programming.

Figure D1. Threshold Programming with Hysteresis

Figure D2. Threshold Programming with No Hysteresis

Saturation Programming

A low and high saturation setting that can be independently programmed on the A/D function. These saturation values are used to monitor the acquired data and set a status when the specified saturation is reached as well as setting the A/D reading to the saturation value. Saturation programming can be used to prevent the A/D reading from exceeding the saturation value. Refer to Figure D3 for illustrations of Saturation Programming

Figure D3. Saturation Programming

Register Descriptions

The register descriptions provide the register name, Type, Data Range, Read or Write information, Initialized Value, and a description of the function.

Threshold Detect Programming Registers

There are two threshold and hysteresis registers that can be independently programmed on the A/D function.

Threshold Detect Level

The Threshold Detect Level registers sets the first and second threshold level values.

Threshold Detect Level 1
Function:	Sets the first threshold level value
Type:	signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Voltage Threshold Level values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x00FF FFFF Bipolar (2's complement. sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	90% of full scale (bipolar)

Threshold Detect Level 2
Function:	Sets the second threshold level value.
Type:	signed binary word (32-bit) (Integer Mode) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Voltage Threshold Level values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x00FF FFFF Bipolar (2's complement. sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	-90% of full scale (bipolar)

Threshold Detect Hysteresis

The Threshold Detect Hysteresis registers sets the first and second threshold hysteresis values.

Note

the hysteresis value must be a positive value.

Threshold Detect Hysteresis 1
Function:	Sets the first threshold hysteresis value. This value must be positive.
Type:	signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Voltage Threshold Hysteresis values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x00FF FFFF Bipolar (2's complement. sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	0

Threshold Detect Hysteresis 2
Function:	Sets the second threshold hysteresis value. This value must be positive.
Type:	signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Voltage Threshold Hysteresis values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x00FF FFFF Bipolar (2's complement. sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	0

Threshold Detect Control
Function:	Sets up detect control for the two thresholds for each channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 00FF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set bit to 0 to detect above the threshold level. Set bit to 1 to detect below the threshold level.

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D1

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

Ch4

Ch3

Ch2

Ch1

T2

T1

T2

T1

T2

T1

T2

T1

D

D

D

D

D

D

D

D

Saturation Programming Registers

A low and high saturation setting that can be independently programmed on the A/D function.

Saturation Value

The Low Saturation Value registers sets value to report as A/D reading and sets the Saturation Status bit when the A/D data is below the low saturation value. The High Saturation Value registers sets value to report as A/D reading and sets the Saturation Status bit when the A/D data is above the high saturation value.

Low Saturation
Function:	Sets the low saturation value.
Type:	signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Saturation Voltage values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x00FF FFFF Bipolar (2's complement. sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	0

High Saturation
Function:	Sets the high saturation value.
Type:	signed binary word (32-bit) or Single Precision Floating Point Value (IEEE-754) (Floating Point Mode)
Data Range:	Saturation Voltage values are dependent on Polarity and Range settings for the channel. Enable Floating Point Mode: 0 (Integer Mode) Unipolar: 0x0000 0000 to 0x00FF FFFF Bipolar (2's complement. sign extended to 32 bits): 0xFF80 0000 to 0x007F FFFF Enable Floating Point Mode: 1 (Floating Point Mode) Single Precision Floating Point Value (IEEE-754)
Read/Write:	R/W
Initialized Value:	0

Saturation Control
Function:	Sets up saturation control for the two saturation levels for each channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 00FF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set bits to 1 to enable Saturation Control. Set bits to 0 to disable Saturation Control. Each channel control consists of two bits: Low Saturation Control ("Even' bits (B0, B2, B4,...)) and High Saturation Control ("Odd' bits (B1, B3, B5,...)).

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D1

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

Ch4

Ch3

Ch2

Ch1

High

Low

High

Low

High

Low

High

Low

D

D

D

D

D

D

D

D

Status and Interrupt

The A/D function provides status registers for Threshold Detect and Saturation.

Threshold Detect Status

There are four registers associated with the Threshold Detect Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

0 = Normal; 1 = Outside of threshold range. The status is created based on the values set in the Threshold Detect 1 and Threshold Detect 2 registers. Bits D0 and D1 represent if channel 1 is outside the threshold for Threshold Detect 1 and Threshold Detect 2 respectively, Bits D2 and D3 represent if channel 2 is outside the threshold for Threshold Detect 1 and Threshold Detect 2 respectively, etc. This pattern continues for all channels.

Function:	Sets the corresponding bit associated with the channel’s Threshold Detect error.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 00FF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Threshold Detect Dynamic Status

Threshold Detect Latched Status

Threshold Detect Interrupt Enable

Threshold Detect Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D1

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

Ch4

Ch3

Ch2

Ch1

T2

T1

T2

T1

T2

T1

T2

T1

D

D

D

D

D

D

D

D

Saturation Status

There are four registers associated with the Saturation Status: Dynamic, Latched, Interrupt Enable, and Set Edge/Level Interrupt.

0 = Normal; 1 = Outside of saturation range. The status is created based on the values set in the Low Saturation and High Saturation registers. Bits D0 and D1 represent if channel 1 is outside the voltage for Low Saturation and High Saturation respectively, Bits D2 and D3 represent if channel 2 is outside the voltage for Low Saturation and High Saturation respectively, etc. This pattern continues for all channels.

Function:	Sets the corresponding bit associated with the channel’s Saturation error.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 00FF
Read/Write:	R (Dynamic), R/W (Latched, Interrupt Enable, Edge/Level Interrupt)
Initialized Value:	0

Saturation Dynamic Status

Saturation Latched Status

Saturation Interrupt Enable

Saturation Set Edge/Level Interrupt

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D15

D14

D13

D12

D1

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

Ch4

Ch3

Ch2

Ch1

High

Low

High

Low

High

Low

High

Low

D

D

D

D

D

D

D

D

Function Register Map

KEY

Configuration/Control

Measurement/Status

THRESHOLD DETECT PROGRAMMING REGISTERS
NOTE: Base Address - 0x9010 8000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1980	Threshold Detect Level 1 Ch 1**	R/W	0x1A00	Threshold Detect Level 1 Hysteresis Ch 1**	R/W
0x1984	Threshold Detect Level 1 Ch 2**	R/W	0x1A04	Threshold Detect Level 1 Hysteresis Ch 2**	R/W
0x1988	Threshold Detect Level 1 Ch 3**	R/W	0x1A08	Threshold Detect Level 1 Hysteresis Ch 3**	R/W
0x198C	Threshold Detect Level 1 Ch 4**	R/W	0x1A0C	Threshold Detect Level 1 Hysteresis Ch 4**	R/W
0x1A80	Threshold Detect Level 2 Ch 1**	R/W	0x1B00	Threshold Detect Level 2 Hysteresis Ch 1**	R/W
0x1A84	Threshold Detect Level 2 Ch 2**	R/W	0x1B04	Threshold Detect Level 2 Hysteresis Ch 2**	R/W
0x1A88	Threshold Detect Level 2 Ch 3**	R/W	0x1B08	Threshold Detect Level 2 Hysteresis Ch 3**	R/W
0x1A8C	Threshold Detect Level 1 Ch 4**	R/W	0x1B0C	Threshold Detect Level 2 Hysteresis Ch 4**	R/W
0x1C80	Threshold Detect Control	R/W
SATURATION PROGRAMMING REGISTERS
NOTE: Base Address - 0x9010 8000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1B80	Low Saturation Value Ch 1**	R/W	0x1C00	High Saturation Value Ch 1	R/W
0x1B84	Low Saturation Value Ch 2**	R/W	0x1C04	High Saturation Value Ch 2**	R/W
0x1B88	Low Saturation Value Ch 3**	R/W	0x1C08	High Saturation Value Ch 3**	R/W
0x1B8C	Low Saturation Value Ch 4**	R/W	0x1C0C	High Saturation Value Ch 4**	R/W
0x1C90	Saturation Control	R/W
STATUS REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e., write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0”).
NOTE: Base Address - 0x9010 4000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
Threshold			Saturation
0x0950	Dynamic Status	R	0x0960	Dynamic Status	R
0x0954	Latched Status*	R/W	0x0964	Latched Status*	R/W
0x0958	Interrupt Enable	R/W	0x0968	Interrupt Enable	R/W
0x095C	Set Edge/Level Interrupt	R/W	0x096C	Set Edge/Level Interrupt	R/W

APPENDIX E: INBOARD DISCRETE I/O ENHANCED INPUT/OUTPUT FUNCTIONALITY

The inboard Discrete I/O function provides optional enhanced input and output mode functionality. For incoming signals (inputs), the enhanced modes include Pulse, Frequency and Period measurements. For outputs, the enhanced modes include PWM (Pulse Width Modulation) and Pattern Generation.

Input Modes

All input modes may be configured with debounce capability. Debounce capability allows configurable filtering of noisy signals and transients. Each channel may be set to an individual debounce time value. When a debounce time is set to a non-zero value, the signal reading after a transition must remain at the same level for the debounce interval before it is propagated through, otherwise it is rejected.

The waveform shown in Figure E1 will be used to illustrate the behavior for each input mode.

Figure E1. Incoming Signal Example Used to Illustrate Input Modes

Pulse Measurements

There are two Pulse Measurements features available - High Time Pulse Measurements and Low Time Pulse Measurements. The Pulse Measurement data is stored in the FIFO Buffer.

High Time Pulse Measurements

In this input mode, the data in the FIFO buffer is the measurement for each rising transition to the next falling one. Timing measurements record the time interval (in 10 µs ticks) from a pair of transitions.

Figure E2. High Time Pulse Measurement Input Mode

For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs):

1. 1500 (0x0000 05DC)
2. 2500 (0x0000 09C4)
3. 1000 (0x0000 03E8)

Time Interval	Calculations	High Time Pulse Measurements
1	1500 counts * 10 µsec = 15000 µsec = 15.0 msec	15.0 msec
2	2500 counts * 10 µsec = 25000 µsec = 25.0 msec	25.0 msec
3	1000 counts * 10 µsec = 10000 µsec = 10.0 msec	10.0 msec

Low Time Pulse Measurements

In this mode, the data in the FIFO buffer is the measurement for each falling edge to the next rising edge. Timing measurements record the time interval (in 10 µs ticks) from a pair of transitions.

Figure E3. Low Time Pulse Measurement Input Mode

For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs):

1. 2000 (0x0000 07D0)
2. 500 (0x0000 01F4)
3. 1500 (0x0000 05DC

Time Interval	Calculations	Low Time Pulse Measurements
1	2000 counts * 10 µsec = 20000 µsec = 20.0 msec	20.0 msec
2	500 counts * 10 µsec = 5000 µsec = 5.0 msec	5.0 msec
3	1500 counts * 10 µsec = 15000 µsec = 15.0 msec	15.0 msec

Transition Timestamps

There are three Transition Timestamp Measurements features available - Transition Timestamp for All Rising Edges, Transition Timestamp for All Falling Edges, and Transition Timestamp for All Edges. The Transition Timestamps Measurement data are store in the FIFO Buffer.

Transition Timestamps of All Rising Edges

In this mode, the data in the FIFO buffer is the Rising Edge Timestamp. The timestamp is a 32-bit counter that is incremented at the rate of 100 kHz (in other words, counter is incremented every 10 µsec). The timestamp is can be reset by the application at any time.

Figure E4. Transition Timestamp of All Rising Edges Input Mode

For this example, the FIFO Word Count register will be set to 4 and the FIFO Buffer Data register will contain the following four values (counts of 10 µs):

1. 1000 (0x0000 03E8)
2. 4500 (0x0000 1194)
3. 7500 (0x0000 1D4C)
4. 10000 (0x000 2710)

This data can be interpreted as follows:

Time Interval	Calculations	Time between rising edges
1 to 2	4500 - 1000 = 3500 counts = 3500 * 10 µsec = 35000 µsec = 35.0 msec	35.0 msec
2 to 3	7500 - 4500 = 3000 counts = 3000 * 10 µsec = 30000 µsec = 30.0 msec	30.0 msec
3 to 4	10000 - 7500 = 2500 counts = 2500 * 10 µsec = 25000 µsec = 25.0 msec	25.0 msec

Transition Timestamps of All Falling Edges

In this mode, the data in the FIFO buffer is the Falling Edge Timestamp. The timestamp is a 32-bit counter that is incremented at the rate of 100 kHz (in other words, counter is incremented every 10 µsec). The timestamp is can be reset by the application at any time.

Figure E5. Transition Timestamp of All Falling Edges Input Mode

For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs):

1. 2500 (0x0000 09C4)
2. 7000 (0x0000 1B58)
3. 8500 (0x0000 2134)

This data can be interpreted as follows:

Time Interval	Calculations	Time between falling edges
1 to 2	7000 - 2500 = 4500 counts = 4500 * 10 µsec = 45000 µsec = 45.0 msec	45.0 msec
2 to 3	8500 - 7000 = 1500 counts = 1500 * 10 µsec = 15000 µsec = 15.0 msec	15.0 msec

Transition Timestamps of All Edges

In this mode, the data in the FIFO buffer is the Rising and Falling Edge Timestamp. The timestamp is a 32-bit counter that is incremented at the rate of 100 kHz (in other words, counter is incremented every 10 µsec). The timestamp is can be reset by the application at any time.

Figure E6. Transition Timestamp for All Edges Input Mode

For this example, the FIFO Word Count register will be set to 7 and the FIFO Buffer Data register will contain the following seven values (counts of 10 µs):

1. 1000 (0x0000 03E8)
2. 2500 (0x0000 09C4)
3. 4500 (0x0000 1194)
4. 7000 (0x0000 1B58)
5. 7500 (0x0000 1D4C)
6. 8500 (0x0000 2134)
7. 10000 (0x000 2710)

This data can be interpreted as follows:

Time Interval	Calculations	Time between edges
1 to 2	2500 - 1000 = 1500 counts = 1500 * 10 µsec = 15000 µsec = 15.0 msec	15.0 msec
2 to 3	4500 - 2500 = 2000 counts = 2000 * 10 µsec = 20000 µsec = 20.0 msec	20.0 msec
3 to 4	7000 - 4500 = 2500 counts = 2500 * 10 µsec = 25000 µsec = 25.0 msec	25.0 msec
4 to 5	7500 - 7000 = 500 counts = 500 * 10 µsec = 5000 µsec = 5.0 msec	5.0 msec
5 to 6	8500 - 7500 = 1000 counts = 1000 * 10 µsec = 10000 µsec = 10.0 msec	10.0 msec
6 to 7	10000 - 8500 = 1500 counts = 1500 * 10 µsec = 15000 µsec = 15.0 msec	15.0 msec

Transition Counter

There are three Transition Counter features available - Rising Edge Transition Counter, Falling Edge Transition Counter and All Edge Transition Counter.

Rising Edges Transition Counter

In this mode, the count of the number of Rising Edges is recorded. The counter is a 32-bit counter. The counter is can be reset by the application at any time.

Figure E7. Rising Edges Transition Counter Input Mode

For this example, the Transition Count register will be set to 4.

Falling Edges Transition Counter

In this mode, the count of the number of Falling Edges is recorded. The counter is a 32-bit counter. The counter is can be reset by the application at any time.

Figure E8. Falling Edges Transition Counter Input Mode

For this example, the Transition Count register will be set to 3.

All Edges Transition Counter

In this mode, the count of the number of Rising and Falling Edges is recorded. The counter is a 32-bit counter. The counter is can be reset by the application at any time.

Figure E9. All Edges Transition Counter Input Mode

For this example, the Transition Count register will be set to 7.

Period Measurement

In this input mode, the data in the FIFO buffer is the measurement for each rising edge transition to the next rising edge transition. Timing measurements record the time interval (in 10 µs ticks).

Figure E10. Period Measurement Input Mode

For this example, the FIFO Word Count register will be set to 4 and the FIFO Buffer Data register will contain the following three values (counts of 10 µs):

1. 2000 (0x0000 07D0)
2. 2000 (0x0000 07D0)
3. 2000 (0x0000 07D0)
4. 2000 (0x0000 07D0)

Time Interval	Calculations	Period Measurements
1	2000 counts * 10 µsec = 20000 µsec = 20.0 msec	20.0 msec
2	2000 counts * 10 µsec = 20000 µsec = 20.0 msec	20.0 msec
3	2000 counts * 10 µsec = 20000 µsec = 20.0 msec	20.0 msec
4	2000 counts * 10 µsec = 20000 µsec = 20.0 msec	20.0 msec

Frequency Measurement

In this input mode, the data in the FIFO buffer is the number of rising edge transitions for the programmable time interval programmed in the Frequency Measurement Period register.

For this example, set the Frequency Measurement Period register = 4000 (4000 * 10 µs = 40000 µs = 40 msec).

Figure E11. Frequency Measurement Input Mode

For this example, the FIFO Word Count register will be set to 3 and the FIFO Buffer Data register will contain the following three values (number of rising edges:

1. 2 (0x0000 0002)
2. 2 (0x0000 0002)
3. 2 (0x0000 0002)

Time Interval	Calculations	Frequency Measurements
1	2 counts/40 msec = 2 counts/0.04 seconds = 50 Hz	50 Hz
2	2 counts/40 msec = 2 counts/0.04 seconds = 50 Hz	50 Hz
3	2 counts/40 msec = 2 counts/0.04 seconds = 50 Hz	50 Hz

Output Modes

There are three Enhanced Output Functionality modes: two PWM outputs and one Pattern Generator Output mode.

PWM Output

There are two PWM output modes, PWM Continuous and PWM Burst. The PWM timing is very precise with low jitter. In PWM Output mode, the Mode Select register is set to either “PWM Continuous or PWM Burst”. The value written to the PWM Period register specifies the period to output the PWM signal, the value written to the PWM Pulse Width register specifies the time for the “ON” state, and the value written to the PWM Output Polarity register specifies the initial edge of the output. For PWM Burst mode, the PWM Number of Cycles register specifies the number of cycles to output the signal. Note, there may be an initial “OFF” state level delay based on the Period time before the initial pulse is output.

PWM Continuous

Figure E12 and Figure E13 illustrate the PWM Continuous Output signal, one configured with PWM Output Polarity = Positive (0) and one configured with PWM Output Polarity = Negative (1). The configured PWM output is enabled and disabled with the Enable Measurements/Outputs register.

Figure E12. PWM Continuous Output (PWM Period = 15 msec, PWM Pulse Width = 10 msec, PWM Output Polarity = Positive (0))

Figure E13. PWM Continuous Output (PWM Period = 15 msec, PWM Pulse Width = 10 msec, PWM Output Polarity = Negative (1))

PWM Burst

Figure E14 and Figure E15 illustrate the PWM Burst Output signal with the PWM Number of Cycles = 5 pulses, one configured with PWM Output Polarity = Positive (0) and one configured with PWM Output Polarity = Negative (1). The configured PWM output is enabled with the Enable Measurements/Outputs register. Once the number of pulses that were requested is outputted, the value in the Enable Measurements/Outputs register will be reset (self-clearing) to allow for the output to be re-enabled.

Figure E14. PWM Burst Output (PWM Period = 15 msec, PWM Pulse Width = 10 msec, PWM Output Polarity = Positive (0), PWM Number of Cycles = 5)

Figure E15. PWM Burst Output (PWM Period = 15 msec, PWM Pulse Width = 10 msec, PWM Output Polarity = Negative (1)), PWM Number of Cycles = 5)

Pattern Generator

For the Pattern Generator mode, there is 64K block of unsigned 32-bit words allocated to specify the data pattern for the output channels. The data in each 32-bit word is bit-mapped per channel. The Pattern RAM Start Address and Pattern RAM End Address registers specify the starting and ending address in the 64K block to use as the data to output for each channel configured for Pattern Generator mode. The Pattern RAM Period register specifies the pattern rate. The Pattern RAM Control and Pattern RAM Number of Cycles control the Pattern Generator output - Continuous, Burst with a specified number of cycles, Pause, or External Trigger from input from Channel 1. Note, when any channel is configured for External Trigger Pattern Generator mode, Channel 1 must be set as an input.

Figure E16 illustrates the output of the 24 channels for the Enhanced Function module all configured in Pattern Generator mode.

Figure E16. Pattern Generator

Enhanced Input/Output Functionality Registers

The inboard Discrete I/O option provides enhanced input and output mode functionality. The Mode Select and Enable Output/Measurement registers are general control registers for the different enhanced input and output modes.

Mode Select

Mode Select
Function:	Configures the Enhanced Functionality Modes to apply to the channel.
Type:	unsigned binary word (32-bit)
Data Range:	See table
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	It is important that the channel is correctly configured to either input or output in the Input/Output Format registers to correspond to the Enhanced Functionality Mode selected. Setting a 0 to this register will configure that channel to normal operation.

Mode Select Value (Decimal)	Mode Select Value (Hexadecimal)	Description
0	0x0000 0000	Enhanced Functionality Disabled
Input Enhanced Functionality Mode
1	0x0000 0001	High Time Pulse Measurements
2	0x0000 0002	Low Time Pulse Measurements
3	0x0000 0003	Transition Timestamp of All Rising Edges
4	0x0000 0004	Transition Timestamp of All Falling Edges
5	0x0000 0005	Transition Timestamp of All Edges
6	0x0000 0006	Rising Edges Transition Counter
7	0x0000 0007	Falling Edges Transition Counter
8	0x0000 0008	All Edges Transition Counter
9	0x0000 0009	Period Measurement
10	0x0000 000A	Frequency Measurement
Output Enhanced Functionality Mode
32	0x0000 0020	PWM Continuous
33	0x0000 0021	PWM Burst
34	0x0000 0022	Pattern Generator

Enable Measurements/Outputs

Enable Measurements/Outputs
Function:	Enables/starts the measurements or outputs based on the Mode Select for the channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Setting the bit for the associated channel to a 1 will start the measurement or output depending on the Mode Select configuration for that channel. Setting the bit for the associated channel to 0 will stop the measurements/outputs.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
Ch16	Ch15	Ch14	Ch13	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

Input Mode Registers

After configuring the Mode Select register, write a 1 to the Reset Timer/Counter register resets the channel’s timestamp and counter used for input modes. Write a 1 to the Enable Measurements/Outputs register to begin the measurement of the input signal. Write a 0 to the Enable Measurements/Outputs register to stop the measurement of the input signal. The data can be read either while the measurements are being made on input signals or after stopping the measurements.

Reset Timer/Counter
Function:	Resets the measurement timestamp and counter for the channel.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	W
Initialized Value:	0
Operational Settings:	Setting the bit for the associated channel to a 1 will: reset the timestamp used for the Pulse Measurements mode (1-2), Transition Timestamp mode (3-5), and Period Measurement mode (9) and Frequency Measurement mode (10) reset the counter used for Transition Counter mode (6-8)

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

FIFO Registers

The FIFO registers are used for the following input modes:

• Pulse Measurements mode (1-2)
• Transition Timestamp mode (3-5)
• Period Measurement mode (9)
• Frequency Measurement mode (10)

FIFO Buffer Data
Function:	The data stored in the FIFO Buffer Data is dependent on the input mode.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	N/A
Operational Settings:	Refer to examples in Input Modes.

FIFO Word Count
Function:	This is a counter that reports the number of 32-bit words stored in the FIFO buffer.
Type:	unsigned binary word (32-bit)
Data Range:	0 - 255 (0x0000 0000 to 0x0000 00FF)
Read/Write:	R
Initialized Value:	0
Operational Settings:	Every time a read operation is made from the FIFO Buffer Data register, the value in the FIFO Word Count register will be decremented by one. The maximum number of words that can be stored in the FIFO is 255.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	D	D	D	D	D	D	D	D

Clear FIFO
Function:	Clears FIFO by resetting the FIFO Word Count register.
Type:	unsigned binary word (32-bit)
Data Range:	0 or 1
Read/Write:	W
Initialized Value:	N/A
Operational Settings:	Write a 1 to associated channel to reset the Words in FIFO to zero; Clear FIFO register does not clear data in the buffer. A read to the buffer data will give “aged” data.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

FIFO Status
Function:	Sets the corresponding bit associated with the FIFO status type; there is a separate register for each channel.
Type:	unsigned binary word (32-bit)
Data Range:	See table
Read/Write:	R
Initialized Value:	0

Bit	Name	Description
D31:D4	Reserved	Set to 0
D3	Empty	Set to 1 when FIFO Word Count = 0
D2	Almost Empty	Set to 1 when FIFO Word Count <= 63 (25%)
D1	Almost Full	Set to 1 when FIFO Word Count >= 191 (75%)
D0	Full	Set to 1 when FIFO Word Count = 255

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

Transition Count Registers

The Transition Count register are used for the following input modes:

Transition Counter mode (6-8)

Transition Count
Function:	Contains the count of the transitions depending on the configuration in the Mode Select register - Rising Edges, Falling Edges or All Edges.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0000 to 0xFFFF FFFF
Read/Write:	R
Initialized Value:	0
Operational Settings:	Refer to examples in Transition Counter.

Frequency Measurement Registers

For the Frequency Measurement mode, the period to perform the frequency measurements must be specified in the Frequency Measurement Period register.

Frequency Measurement Period
Function:	When the Mode Select register is programmed for Frequency Measurement mode (10), the value in the Frequency Measurement Period is used as the time interval for counting the number of rising edge transitions within that interval.
Type:	unsigned binary word (32-bit)
Data Range:	0x0 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set the Frequency Measurement Period (LSB = 10 µs). Refer to examples in Frequency Measurement.

Output Modes Registers

After configuring the Mode Select register, write a 1 to the Enable Measurements/Outputs register to outputting the signal. Write a 0 to the Enable Measurements/Outputs register to stop the output signal.

PWM Registers

The PWM Period, PWM Pulse Width and PWM Output Polarity registers configure the PWM output signal. When the Mode Select register is configured for PWM Burst mode, the PWM Number of Cycles register is used to specify the number of cycles to repeat for the burst.

PWM Period
Function:	When the Mode Select register is programmed for PWM Continuous or PWM Burst mode (32-33), the value in the PWM Period is used as the time interval for outputting the PWM signal.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0001 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set the PWM Period (LSB = 10 µs). The PWM Period must be greater than the value set in the PWM Pulse Width register. Refer to examples in PWM Output.

PWM Pulse Width
Function:	When the Mode Select register is programmed for PWM Continuous or PWM Burst mode (32-33), the value in the PWM Pulse Width is used as the time interval of the “ON” state for outputting the PWM signal.
Type:	unsigned binary word (32-bit)
Data Range:	0x0 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set the PWM Pulse Width (LSB = 10 µs). The PWM Pulse Width must be less than the value set in the PWM Pulse Width register. Refer to examples in PWM Output.

PWM Output Polarity
Function:	When the Mode Select register is programmed for PWM Continuous or PWM Burst mode (32-33), the value in the PWM Output Polarity is used to specify whether the PWM output signal starts with a rising edge (Positive (0)), or a falling edge (Negative (1)).
Type:	unsigned binary word (32-bit)
Data Range:	0x0 to 0x0000 0FFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	The PWM Output Polarity register is used to program the starting edge of the PWM Pulse Period (rising or falling). When the PWM output Polarity is set to Positive (0), the output will start with a rising edge, when it's set to Negative (1), the output will start with a falling edge. The default is Positive (0), which is set when the PWM Polarity bit is 0. Refer to examples in PWM Output.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

PWM Number of Cycles
Function:	When the Mode Select register is programmed for PWM Burst mode (33), the value in the PWM Number of Cycles is used to specify the number of times to repeat the PWM output signal.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0001 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set the number of times to output the PWM signal. Refer to examples in PWM Output.

Pattern Generator Registers

The Pattern RAM registers are a 64K block of unsigned 32-bit words allocated to specify the data pattern for the output channels. The Pattern RAM Start Address, Pattern RAM End Address, Pattern RAM Period and Pattern RAM Control registers configure the Pattern Generator output signals. When the Pattern RAM Control register is configured for Burst, the Pattern RAM Number of Cycles specify the number of cycles to repeat the pattern for the burst.

Pattern RAM
Function:	Pattern Generator Memory Block from 0x40000 to 0x7FFFC.
Type:	unsigned binary word (32-bit)
Address Range:	0x0000 0000 to 0x0000 0FFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	64K block of unsigned 32-bit words. The data in each 32-bit word is bit-mapped per channel.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	Ch12	Ch11	Ch10	Ch9	Ch8	Ch7	Ch6	Ch5	Ch4	Ch3	Ch2	Ch1

Pattern RAM Start Address
Function:	When the Mode Select register is programmed for Pattern Generator mode (34), the Pattern RAM Start Address register specifies the starting address within the Pattern RAM block registers to use for the output.
Type:	unsigned binary word (32-bit)
Data Range:	0x0004 0000 to 0x0007 FFFC
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	The value in the Pattern RAM Start Address must be less than the value in the Pattern RAM End Address.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Pattern RAM End Address
Function:	When the Mode Select register is programmed for Pattern Generator mode (34), the Pattern RAM End Address register specifies the end address within the Pattern RAM block registers to use for the output.
Type:	unsigned binary word (32-bit)
Data Range:	0x40000 to 0x7FFFC
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	The value in the Pattern RAM End Address must be greater than the value in the Pattern RAM Start Address.

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	D	D	D
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D

Pattern RAM Period
Function:	When the Mode Select register is programmed for Pattern Generator mode (34), the value in the Pattern RAM Period is used as the time interval for outputting the Pattern Generator signals.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0001 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set the Pattern RAM Period (LSB = 10 µs).
Pattern RAM Control
Function:	When the Mode Select register is programmed for Pattern Generator mode (34), the value in the Pattern RAM Control is used to control the outputting of the Pattern Generator signals.
Type:	unsigned binary word (32-bit)
Data Range:	See table
Read/Write:	W
Initialized Value:	0
Operational Settings:	Configures the Pattern Generator for Continuous, Burst with a specified number of cycles, Pause, or External Trigger from input from Channel 1. Note, when any channel is configured for External Trigger Pattern Generator mode, Channel 1 must be set as an input.

Bits	Description
D31:D5	Reserved. Set to 0
D4	Falling Edge External Trigger - Channel 1 used as the input for the trigger
D3	Rising Edge External Trigger - Channel 1 used as the input for the trigger
D2	Pause
D1	Burst Mode - value in Pattern RAM Number of Cycles register defines number of cycles to output
D0	Enable Pattern Generator

Values	Description
0x0000	Disable Pattern Generator, Continuous Mode, No External Trigger
0x0001	Enable Pattern Generator, Continuous Mode, No External Trigger
0x0002	Disable Pattern Generator, Burst Mode, No External Trigger
0x0003	Enable Pattern Generator, Burst Mode, No External Trigger
0x0005	Enable Pattern Generator, Continuous Mode, Pause, No External Trigger
0x0007	Enable Pattern Generator, Burst Mode, Pause, No External Trigger
0x0008	Disable Pattern Generator, Continuous Mode, Rising External Trigger
0x0009	Enable Pattern Generator, Continuous Mode, Rising External Trigger
0x000A	Disable Pattern Generator, Burst Mode, Rising External Trigger
0x000B	Enable Pattern Generator, Burst Mode, Rising External Trigger
0x000D	Enable Pattern Generator, Continuous Mode, Pause, Rising External Trigger
0x000F	Enable Pattern Generator, Burst Mode, Pause, Rising External Trigger
0x1000	Disable Pattern Generator, Continuous Mode, Falling External Trigger
0x1001	Enable Pattern Generator, Continuous Mode, Falling External Trigger
0x1002	Disable Pattern Generator, Burst Mode, Falling External Trigger
0x1003	Enable Pattern Generator, Burst Mode, Falling External Trigger
0x1005	Enable Pattern Generator, Continuous Mode, Pause, Falling External Trigger
0x1007	Enable Pattern Generator, Burst Mode, Pause, Falling External Trigger
0x0004, 0x0006, 0x000C, 0x000E, 0x1004, 0x1006, 0x1008-0x100F	Invalid

D31	D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17	D16
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0	0	0	0	0	0	0	0	0	0	0	0	D	D	D	D

Pattern RAM Number of Cycles
Function:	When the Mode Select register is programmed for Pattern Generator mode (34) and the Pattern RAM Control register is set for Burst mode, the value in the Pattern RAM Number of Cycles is used to specify the number of times to repeat the pattern output signal.
Type:	unsigned binary word (32-bit)
Data Range:	0x0000 0001 to 0xFFFF FFFF
Read/Write:	R/W
Initialized Value:	0
Operational Settings:	Set the number of times to output the pattern.

Function Register Map

Key:

Configuration/Control

Status

*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a ‘1’ to a bit set to ‘1’ will set the bit to ‘0’).

MODE SELECT REGISTERS
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x300C	Mode Select Ch 1	R/W
0x308C	Mode Select Ch 2	R/W
0x310C	Mode Select Ch 3	R/W
0x318C	Mode Select Ch 4	R/W
0x320C	Mode Select Ch 5	R/W
0x328C	Mode Select Ch 6	R/W
0x330C	Mode Select Ch 7	R/W
0x338C	Mode Select Ch 8	R/W
0x340C	Mode Select Ch 9	R/W
0x348C	Mode Select Ch 10	R/W
0x350C	Mode Select Ch 11	R/W
0x358C	Mode Select Ch 12	R/W
0x2000	Enable Measurements/Outputs	R/W
INPUT MODES REGISTER
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x2004	Reset Timer/Counter	W
FIFO REGISTERS
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x3000	FIFO Buffer Data Ch 1	R	0x3004	FIFO Word Count Ch 1	R
0x3080	FIFO Buffer Data Ch 2	R	0x3084	FIFO Word Count Ch 2	R
0x3100	FIFO Buffer Data Ch 3	R	0x3104	FIFO Word Count Ch 3	R
0x3180	FIFO Buffer Data Ch 4	R	0x3184	FIFO Word Count Ch 4	R
0x3200	FIFO Buffer Data Ch 5	R	0x3204	FIFO Word Count Ch 5	R
0x3280	FIFO Buffer Data Ch 6	R	0x3284	FIFO Word Count Ch 6	R
0x3300	FIFO Buffer Data Ch 7	R	0x3304	FIFO Word Count Ch 7	R
0x3380	FIFO Buffer Data Ch 8	R	0x3384	FIFO Word Count Ch 8	R
0x3400	FIFO Buffer Data Ch 9	R	0x3404	FIFO Word Count Ch 9	R
0x3480	FIFO Buffer Data Ch 10	R	0x3484	FIFO Word Count Ch 10	R
0x3500	FIFO Buffer Data Ch 11	R	0x3504	FIFO Word Count Ch 11	R
0x3580	FIFO Buffer Data Ch 12	R	0x3584	FIFO Word Count Ch 12	R
0x3008	FIFO Status Ch 1	R
0x3088	FIFO Status Ch 2	R
0x3108	FIFO Status Ch 3	R
0x3188	FIFO Status Ch 4	R
0x3208	FIFO Status Ch 5	R
0x3288	FIFO Status Ch 6	R
0x3308	FIFO Status Ch 7	R
0x3388	FIFO Status Ch 8	R
0x3408	FIFO Status Ch 9	R
0x3488	FIFO Status Ch 10	R
0x3508	FIFO Status Ch 11	R
0x3588	FIFO Status Ch 12	R
0x2008	Reset FIFO	W
TRANSITION COUNT REGISTERS
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x3000	Transition Count Ch 1	R
0x3080	Transition Count Ch 2	R
0x3100	Transition Count Ch 3	R
0x3180	Transition Count Ch 4	R
0x3200	Transition Count Ch 5	R
0x3280	Transition Count Ch 6	R
0x3300	Transition Count Ch 7	R
0x3380	Transition Count Ch 8	R
0x3400	Transition Count Ch 9	R
0x3480	Transition Count Ch 10	R
0x3500	Transition Count Ch 11	R
0x3580	Transition Count Ch 12	R
FREQUENCY MEASUREMENT REGISTERS
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x3014	Frequency Measurement Period Ch 1	R/W
0x3094	Frequency Measurement Period Ch 2	R/W
0x3114	Frequency Measurement Period Ch 3	R/W
0x3194	Frequency Measurement Period Ch 4	R/W
0x3214	Frequency Measurement Period Ch 5	R/W
0x3294	Frequency Measurement Period Ch 6	R/W
0x3314	Frequency Measurement Period Ch 7	R/W
0x3394	Frequency Measurement Period Ch 8	R/W
0x3414	Frequency Measurement Period Ch 9	R/W
0x3494	Frequency Measurement Period Ch 10	R/W
0x3514	Frequency Measurement Period Ch 11	R/W
0x3594	Frequency Measurement Period Ch 12	R/W
PWM REGISTERS
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x3014	PWM Period Ch 1	R/W	0x3010	PWM Pulse Width Ch 1	R/W
0x3094	PWM Period Ch 2	R/W	0x3090	PWM Pulse Width Ch 2	R/W
0x3114	PWM Period Ch 3	R/W	0x3110	PWM Pulse Width Ch 3	R/W
0x3194	PWM Period Ch 4	R/W	0x3190	PWM Pulse Width Ch 4	R/W
0x3214	PWM Period Ch 5	R/W	0x3210	PWM Pulse Width Ch 5	R/W
0x3294	PWM Period Ch 6	R/W	0x3290	PWM Pulse Width Ch 6	R/W
0x3314	PWM Period Ch 7	R/W	0x3310	PWM Pulse Width Ch 7	R/W
0x3394	PWM Period Ch 8	R/W	0x3390	PWM Pulse Width Ch 8	R/W
0x3414	PWM Period Ch 9	R/W	0x3410	PWM Pulse Width Ch 9	R/W
0x3494	PWM Period Ch 10	R/W	0x3490	PWM Pulse Width Ch 10	R/W
0x3514	PWM Period Ch 11	R/W	0x3510	PWM Pulse Width Ch 11	R/W
0x3594	PWM Period Ch 12	R/W	0x3590	PWM Pulse Width Ch 12	R/W
0x3018	PWM Number of Cycles Ch 1	R/W
0x3098	PWM Number of Cycles Ch 2	R/W
0x3118	PWM Number of Cycles Ch 3	R/W
0x3198	PWM Number of Cycles Ch 4	R/W
0x3218	PWM Number of Cycles Ch 5	R/W
0x3298	PWM Number of Cycles Ch 6	R/W
0x3318	PWM Number of Cycles Ch 7	R/W
0x3398	PWM Number of Cycles Ch 8	R/W
0x3418	PWM Number of Cycles Ch 9	R/W
0x3498	PWM Number of Cycles Ch 10	R/W
0x3518	PWM Number of Cycles Ch 11	R/W
0x3598	PWM Number of Cycles Ch 12	R/W
0x200C	PWM Output Polarity	R/W
PATTERN GENERATOR REGISTERS
NOTE: Base Address - 0x9010 C000
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0004_0000 to 0x0007_FFFC	Pattern RAM	R/W
0x2010	Pattern RAM Period	R/W	0x2014	Pattern RAM Start Address	R/W
0x2018	Pattern RAM End Address	R/W	0x201C	Pattern RAM Control	R/W
0x2020	Pattern RAM Number of Cycles	R/W

DOCS.NAII REVISIONS

Revision Date	Description
2026-01-23	Initial posting of CIU3 manual.
2026-02-25	SC section: updated factory defaults table; updated initialized values for Rx Almost Full/Hi Watermark/Lo Watermark; updated initialized values for Tx Almost Empty; updated BIT Status register to show shared register with DT function. DT section: updated BIT Status register to show shared register with SC function.