TL1 Function Register Map Template

FUNCTION REGISTER MAP

KEY

Configuration/Control

Measurement/Status

INPUT/OUTPUT REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1038	I/O Format	R/W
0x1000	Read I/O	R	0x1024	Write Outputs	R/W

VCC BANK REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x1020	Vcc Select	R/W
0x1200	Read Vcc Bank 1	R	0x1208	Read Vcc Bank 3	R
0x1204	Read Vcc Bank 2	R	0x120C	Read Vcc Bank 4	R

INPUT/OUTPUT CONTROL REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x208C	Debounce Time Ch.1	R/W	0x210C	Debounce Time Ch.2	R/W
0x218C	Debounce Time Ch.3	R/W	0x220C	Debounce Time Ch.4	R/W
0x228C	Debounce Time Ch.5	R/W	0x230C	Debounce Time Ch.6	R/W
0x238C	Debounce Time Ch.7	R/W	0x240C	Debounce Time Ch.8	R/W
0x248C	Debounce Time Ch.9	R/W	0x250C	Debounce Time Ch.10	R/W
0x258C	Debounce Time Ch.11	R/W	0x260C	Debounce Time Ch.12	R/W
0x268C	Debounce Time Ch.13	R/W	0x270C	Debounce Time Ch.14	R/W
0x278C	Debounce Time Ch.15	R/W	0x280C	Debounce Time Ch.16	R/W
0x288C	Debounce Time Ch.17	R/W	0x290C	Debounce Time Ch.18	R/W
0x298C	Debounce Time Ch.19	R/W	0x2A0C	Debounce Time Ch.20	R/W
0x2A8C	Debounce Time Ch.21	R/W	0x2B0C	Debounce Time Ch.22	R/W
0x2B8C	Debounce Time Ch.23	R/W	0x2C0C	Debounce Time Ch.24	R/W
0x1100	Overcurrent Clear	R/W

USER WATCHDOG TIMER PROGRAMMING REGISTERS

Refer to “User Watchdog Timer Module Manual” for the User Watchdog Timer Status Function Register Map.

MODULE COMMON REGISTERS

Refer to “Module Common Registers Module Manual” for the Module Common Registers Function Register Map.

GENERAL PURPOSE STATUS REGISTERS
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x101C	BIT Error Interrupt Interval	R/W	0x1014	BIT Count Error Clear	R/W

STATUS REGISTERS
*When an event is detected, the bit associated with the event is set in this register and will remain set until the user clears the event bit. Clearing the bit requires writing a 1 back to the specific bit that was set when read (i.e. write-1-to-clear, writing a “1” to a bit set to “1” will set the bit to “0”).
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
BIT			Low-to-High Transition
0x0800	BIT Dynamic Status	R	0x0810	Low-High Transition Dynamic Status	R
0x0804	BIT Latched Status*	R/W	0x0814	Low-High Transition Latched Status*	R/W
0x0808	BIT Interrupt Enable	R/W	0x0818	Lo-Hi Transition Interrupt Enable	R/W
0x080C	BIT Set Edge/Level Interrupt	R/W	0x081C	Lo-Hi Transition Set Edge/Level Interrupt	R/W
High-to-Low Transition			Overcurrent
0x0820	High-Low Transition Dynamic Status	R	0x0830	Overcurrent Dynamic Status	R
0x0824	High-Low Transition Latched Status*	R/W	0x0834	Overcurrent Latched Status*	R/W
0x0828	Hi-Lo Transition Interrupt Enable	R/W	0x0838	Overcurrent Interrupt Enable	R/W
0x082C	Hi-Lo Transition Set Edge/Level Interrupt	R/W	0x083C	Overcurrent Set Edge/Level Interrupt	R/W

INTERRUPT REGISTERS
The Interrupt Vector and Interrupt Steering registers are mapped to the Motherboard Memory Space and these addresses are absolute based on the module slot position. In other words, do not apply the Module Address offset to these addresses.
OFFSET	REGISTER NAME	ACCESS	OFFSET	REGISTER NAME	ACCESS
0x0500	Module 1 Interrupt Vector 1 - BIT	R/W	0x0600	Module 1 Interrupt Steering 1 - BIT	R/W
0x0504	Module 1 Interrupt Vector 2 - Low-High	R/W	0x0604	Module 1 Interrupt Steering 2 - Low-High	R/W
0x0508	Module 1 Interrupt Vector 3 - High-Low	R/W	0x0608	Module 1 Interrupt Steering 3 - High-Low	R/W
0x050C	Module 1 Interrupt Vector 4 - Overcurrent	R/W	0x060C	Module 1 Interrupt Steering 4 - Overcurrent	R/W
0x0510 to 0x0568	Module 1 Interrupt Vector 5-27 - Reserved	R/W	0x0610 to 0x0668	Module 1 Interrupt Steering 5-27 - Reserved	R/W
0x056C	Module 1 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x066C	Module 1 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x0570 to 0x057C	Module 1 Interrupt Vector 29-32 - Reserved	R/W	0x0670 to 0x067C	Module 1 Interrupt Steering 29-32 - Reserved	R/W
0x0700	Module 2 Interrupt Vector 1 - BIT	R/W	0x0800	Module 2 Interrupt Steering 1 - BIT	R/W
0x0704	Module 2 Interrupt Vector 2 - Low-High	R/W	0x0804	Module 2 Interrupt Steering 2 - Low-High	R/W
0x0708	Module 2 Interrupt Vector 3 - High-Low	R/W	0x0808	Module 2 Interrupt Steering 3 - High-Low	R/W
0x070C	Module 2 Interrupt Vector 4 - Overcurrent	R/W	0x080C	Module 2 Interrupt Steering 4 - Overcurrent	R/W
0x0710 to 0x0768	Module 2 Interrupt Vector 5-27 - Reserved	R/W	0x0810 to 0x0868	Module 2 Interrupt Steering 5-27 - Reserved	R/W
0x076C	Module 2 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x086C	Module 2 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x0770 to 0x077C	Module 2 Interrupt Vector 29-32 - Reserved	R/W	0x0870 to 0x087C	Module 2 Interrupt Steering 29-32 - Reserved	R/W
0x0900	Module 3 Interrupt Vector 1 - BIT	R/W	0x0A00	Module 3 Interrupt Steering 1 - BIT	R/W
0x0904	Module 3 Interrupt Vector 2 - Low-High	R/W	0x0A04	Module 3 Interrupt Steering 2 - Low-High	R/W
0x0908	Module 3 Interrupt Vector 3 - High-Low	R/W	0x0A08	Module 3 Interrupt Steering 3 - High-Low	R/W
0x090C	Module 3 Interrupt Vector 4 - Overcurrent	R/W	0x0A0C	Module 3 Interrupt Steering 4 - Overcurrent	R/W
0x0910 to 0x0968	Module 3 Interrupt Vector 5-27 - Reserved	R/W	0x0A10 to 0x0A68	Module 3 Interrupt Steering 5-27 - Reserved	R/W
0x096C	Module 3 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x0A6C	Module 3 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x0970 to 0x097C	Module 3 Interrupt Vector 29-32 - Reserved	R/W	0x0A70 to 0x0A7C	Module 3 Interrupt Steering 29-32 - Reserved	R/W
0x0B00	Module 4 Interrupt Vector 1 - BIT	R/W	0x0C00	Module 4 Interrupt Steering 1 - BIT	R/W
0x0B04	Module 4 Interrupt Vector 2 - Low-High	R/W	0x0C04	Module 4 Interrupt Steering 2 - Low-High	R/W
0x0B08	Module 4 Interrupt Vector 3 - High-Low	R/W	0x0C08	Module 4 Interrupt Steering 3 - High-Low	R/W
0x0B0C	Module 4 Interrupt Vector 4 - Overcurrent	R/W	0x0C0C	Module 4 Interrupt Steering 4 - Overcurrent	R/W
0x0B10 to 0x0B68	Module 4 Interrupt Vector 5-27 - Reserved	R/W	0x0C10 to 0x0C68	Module 4 Interrupt Steering 5-27 - Reserved	R/W
0x0B6C	Module 4 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x0C6C	Module 4 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x0B70 to 0x0B7C	Module 4 Interrupt Vector 29-32 - Reserved	R/W	0x0C70 to 0x0C7C	Module 4 Interrupt Steering 29-32 - Reserved	R/W
0x0D00	Module 5 Interrupt Vector 1 - BIT	R/W	0x0E00	Module 5 Interrupt Steering 1 - BIT	R/W
0x0D04	Module 5 Interrupt Vector 2 - Low-High	R/W	0x0E04	Module 5 Interrupt Steering 2 - Low-High	R/W
0x0D08	Module 5 Interrupt Vector 3 - High-Low	R/W	0x0E08	Module 5 Interrupt Steering 3 - High-Low	R/W
0x0D0C	Module 5 Interrupt Vector 4 - Overcurrent	R/W	0x0E0C	Module 5 Interrupt Steering 4 - Overcurrent	R/W
0x0D10 to 0x0D68	Module 5 Interrupt Vector 5-27 - Reserved	R/W	0x0E10 to 0x0E68	Module 5 Interrupt Steering 5-27 - Reserved	R/W
0x0D6C	Module 5 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x0E6C	Module 5 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x0D70 to 0x0D7C	Module 5 Interrupt Vector 29-32 - Reserved	R/W	0x0E70 to 0x0E7C	Module 5 Interrupt Steering 29-32 - Reserved	R/W
0x0F00	Module 6 Interrupt Vector 1 - BIT	R/W	0x1000	Module 6 Interrupt Steering 1 - BIT	R/W
0x0F04	Module 6 Interrupt Vector 2 - Low-High	R/W	0x1004	Module 6 Interrupt Steering 2 - Low-High	R/W
0x0F08	Module 6 Interrupt Vector 3 - High-Low	R/W	0x1008	Module 6 Interrupt Steering 3 - High-Low	R/W
0x0F0C	Module 6 Interrupt Vector 4 - Overcurrent	R/W	0x100C	Module 6 Interrupt Steering 4 - Overcurrent	R/W
0x0F10 to 0x0F68	Module 6 Interrupt Vector 5-27 - Reserved	R/W	0x1010 to 0x1068	Module 6 Interrupt Steering 5-27 - Reserved	R/W
0x0F6C	Module 6 Interrupt Vector 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W	0x106C	Module 6 Interrupt Steering 28 - User Watchdog Timer Fault/Inter-FPGA Failure	R/W
0x0F70 to 0x0F7C	Module 6 Interrupt Vector 29-32 - Reserved	R/W	0x1070 to 0x107C	Module 6 Interrupt Steering 29-32 - Reserved	R/W